1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Huawei HiNIC PCI Express Linux driver 4 * Copyright(c) 2017 Huawei Technologies Co., Ltd 5 */ 6 7 #ifndef HINIC_PORT_H 8 #define HINIC_PORT_H 9 10 #include <linux/types.h> 11 #include <linux/etherdevice.h> 12 #include <linux/bitops.h> 13 14 #include "hinic_dev.h" 15 16 #define HINIC_RSS_KEY_SIZE 40 17 #define HINIC_RSS_INDIR_SIZE 256 18 #define HINIC_PORT_STATS_VERSION 0 19 #define HINIC_FW_VERSION_NAME 16 20 #define HINIC_COMPILE_TIME_LEN 20 21 #define HINIC_MGMT_VERSION_MAX_LEN 32 22 23 struct hinic_version_info { 24 u8 status; 25 u8 version; 26 u8 rsvd[6]; 27 28 u8 ver[HINIC_FW_VERSION_NAME]; 29 u8 time[HINIC_COMPILE_TIME_LEN]; 30 }; 31 32 enum hinic_rx_mode { 33 HINIC_RX_MODE_UC = BIT(0), 34 HINIC_RX_MODE_MC = BIT(1), 35 HINIC_RX_MODE_BC = BIT(2), 36 HINIC_RX_MODE_MC_ALL = BIT(3), 37 HINIC_RX_MODE_PROMISC = BIT(4), 38 }; 39 40 enum hinic_port_link_state { 41 HINIC_LINK_STATE_DOWN, 42 HINIC_LINK_STATE_UP, 43 }; 44 45 enum hinic_port_state { 46 HINIC_PORT_DISABLE = 0, 47 HINIC_PORT_ENABLE = 3, 48 }; 49 50 enum hinic_func_port_state { 51 HINIC_FUNC_PORT_DISABLE = 0, 52 HINIC_FUNC_PORT_ENABLE = 2, 53 }; 54 55 enum hinic_autoneg_cap { 56 HINIC_AUTONEG_UNSUPPORTED, 57 HINIC_AUTONEG_SUPPORTED, 58 }; 59 60 enum hinic_autoneg_state { 61 HINIC_AUTONEG_DISABLED, 62 HINIC_AUTONEG_ACTIVE, 63 }; 64 65 enum hinic_duplex { 66 HINIC_DUPLEX_HALF, 67 HINIC_DUPLEX_FULL, 68 }; 69 70 enum hinic_speed { 71 HINIC_SPEED_10MB_LINK = 0, 72 HINIC_SPEED_100MB_LINK, 73 HINIC_SPEED_1000MB_LINK, 74 HINIC_SPEED_10GB_LINK, 75 HINIC_SPEED_25GB_LINK, 76 HINIC_SPEED_40GB_LINK, 77 HINIC_SPEED_100GB_LINK, 78 79 HINIC_SPEED_UNKNOWN = 0xFF, 80 }; 81 82 enum hinic_link_mode { 83 HINIC_10GE_BASE_KR = 0, 84 HINIC_40GE_BASE_KR4 = 1, 85 HINIC_40GE_BASE_CR4 = 2, 86 HINIC_100GE_BASE_KR4 = 3, 87 HINIC_100GE_BASE_CR4 = 4, 88 HINIC_25GE_BASE_KR_S = 5, 89 HINIC_25GE_BASE_CR_S = 6, 90 HINIC_25GE_BASE_KR = 7, 91 HINIC_25GE_BASE_CR = 8, 92 HINIC_GE_BASE_KX = 9, 93 HINIC_LINK_MODE_NUMBERS, 94 95 HINIC_SUPPORTED_UNKNOWN = 0xFFFF, 96 }; 97 98 enum hinic_port_type { 99 HINIC_PORT_TP, /* BASET */ 100 HINIC_PORT_AUI, 101 HINIC_PORT_MII, 102 HINIC_PORT_FIBRE, /* OPTICAL */ 103 HINIC_PORT_BNC, 104 HINIC_PORT_ELEC, 105 HINIC_PORT_COPPER, /* PORT_DA */ 106 HINIC_PORT_AOC, 107 HINIC_PORT_BACKPLANE, 108 HINIC_PORT_NONE = 0xEF, 109 HINIC_PORT_OTHER = 0xFF, 110 }; 111 112 enum hinic_valid_link_settings { 113 HILINK_LINK_SET_SPEED = 0x1, 114 HILINK_LINK_SET_AUTONEG = 0x2, 115 HILINK_LINK_SET_FEC = 0x4, 116 }; 117 118 enum hinic_tso_state { 119 HINIC_TSO_DISABLE = 0, 120 HINIC_TSO_ENABLE = 1, 121 }; 122 123 struct hinic_port_mac_cmd { 124 u8 status; 125 u8 version; 126 u8 rsvd0[6]; 127 128 u16 func_idx; 129 u16 vlan_id; 130 u16 rsvd1; 131 unsigned char mac[ETH_ALEN]; 132 }; 133 134 struct hinic_port_mtu_cmd { 135 u8 status; 136 u8 version; 137 u8 rsvd0[6]; 138 139 u16 func_idx; 140 u16 rsvd1; 141 u32 mtu; 142 }; 143 144 struct hinic_port_vlan_cmd { 145 u8 status; 146 u8 version; 147 u8 rsvd0[6]; 148 149 u16 func_idx; 150 u16 vlan_id; 151 }; 152 153 struct hinic_port_rx_mode_cmd { 154 u8 status; 155 u8 version; 156 u8 rsvd0[6]; 157 158 u16 func_idx; 159 u16 rsvd; 160 u32 rx_mode; 161 }; 162 163 struct hinic_port_link_cmd { 164 u8 status; 165 u8 version; 166 u8 rsvd0[6]; 167 168 u16 func_idx; 169 u8 state; 170 u8 rsvd1; 171 }; 172 173 struct hinic_port_state_cmd { 174 u8 status; 175 u8 version; 176 u8 rsvd0[6]; 177 178 u8 state; 179 u8 rsvd1[3]; 180 }; 181 182 struct hinic_port_link_status { 183 u8 status; 184 u8 version; 185 u8 rsvd0[6]; 186 187 u16 func_id; 188 u8 link; 189 u8 port_id; 190 }; 191 192 struct hinic_port_func_state_cmd { 193 u8 status; 194 u8 version; 195 u8 rsvd0[6]; 196 197 u16 func_idx; 198 u16 rsvd1; 199 u8 state; 200 u8 rsvd2[3]; 201 }; 202 203 struct hinic_port_cap { 204 u8 status; 205 u8 version; 206 u8 rsvd0[6]; 207 208 u16 func_idx; 209 u16 rsvd1; 210 u8 port_type; 211 u8 autoneg_cap; 212 u8 autoneg_state; 213 u8 duplex; 214 u8 speed; 215 u8 rsvd2[3]; 216 }; 217 218 struct hinic_link_mode_cmd { 219 u8 status; 220 u8 version; 221 u8 rsvd0[6]; 222 223 u16 func_id; 224 u16 rsvd1; 225 u16 supported; /* 0xFFFF represents invalid value */ 226 u16 advertised; 227 }; 228 229 struct hinic_speed_cmd { 230 u8 status; 231 u8 version; 232 u8 rsvd0[6]; 233 234 u16 func_id; 235 u16 speed; 236 }; 237 238 struct hinic_set_autoneg_cmd { 239 u8 status; 240 u8 version; 241 u8 rsvd0[6]; 242 243 u16 func_id; 244 u16 enable; /* 1: enable , 0: disable */ 245 }; 246 247 struct hinic_link_ksettings_info { 248 u8 status; 249 u8 version; 250 u8 rsvd0[6]; 251 252 u16 func_id; 253 u16 rsvd1; 254 255 u32 valid_bitmap; 256 u32 speed; /* enum nic_speed_level */ 257 u8 autoneg; /* 0 - off; 1 - on */ 258 u8 fec; /* 0 - RSFEC; 1 - BASEFEC; 2 - NOFEC */ 259 u8 rsvd2[18]; /* reserved for duplex, port, etc. */ 260 }; 261 262 struct hinic_tso_config { 263 u8 status; 264 u8 version; 265 u8 rsvd0[6]; 266 267 u16 func_id; 268 u16 rsvd1; 269 u8 tso_en; 270 u8 resv2[3]; 271 }; 272 273 struct hinic_checksum_offload { 274 u8 status; 275 u8 version; 276 u8 rsvd0[6]; 277 278 u16 func_id; 279 u16 rsvd1; 280 u32 rx_csum_offload; 281 }; 282 283 struct hinic_rq_num { 284 u8 status; 285 u8 version; 286 u8 rsvd0[6]; 287 288 u16 func_id; 289 u16 rsvd1[33]; 290 u32 num_rqs; 291 u32 rq_depth; 292 }; 293 294 struct hinic_lro_config { 295 u8 status; 296 u8 version; 297 u8 rsvd0[6]; 298 299 u16 func_id; 300 u16 rsvd1; 301 u8 lro_ipv4_en; 302 u8 lro_ipv6_en; 303 u8 lro_max_wqe_num; 304 u8 resv2[13]; 305 }; 306 307 struct hinic_lro_timer { 308 u8 status; 309 u8 version; 310 u8 rsvd0[6]; 311 312 u8 type; /* 0: set timer value, 1: get timer value */ 313 u8 enable; /* when set lro time, enable should be 1 */ 314 u16 rsvd1; 315 u32 timer; 316 }; 317 318 struct hinic_vlan_cfg { 319 u8 status; 320 u8 version; 321 u8 rsvd0[6]; 322 323 u16 func_id; 324 u8 vlan_rx_offload; 325 u8 rsvd1[5]; 326 }; 327 328 struct hinic_rss_template_mgmt { 329 u8 status; 330 u8 version; 331 u8 rsvd0[6]; 332 333 u16 func_id; 334 u8 cmd; 335 u8 template_id; 336 u8 rsvd1[4]; 337 }; 338 339 struct hinic_rss_template_key { 340 u8 status; 341 u8 version; 342 u8 rsvd0[6]; 343 344 u16 func_id; 345 u8 template_id; 346 u8 rsvd1; 347 u8 key[HINIC_RSS_KEY_SIZE]; 348 }; 349 350 struct hinic_rss_context_tbl { 351 u32 group_index; 352 u32 offset; 353 u32 size; 354 u32 rsvd; 355 u32 ctx; 356 }; 357 358 struct hinic_rss_context_table { 359 u8 status; 360 u8 version; 361 u8 rsvd0[6]; 362 363 u16 func_id; 364 u8 template_id; 365 u8 rsvd1; 366 u32 context; 367 }; 368 369 struct hinic_rss_indirect_tbl { 370 u32 group_index; 371 u32 offset; 372 u32 size; 373 u32 rsvd; 374 u8 entry[HINIC_RSS_INDIR_SIZE]; 375 }; 376 377 struct hinic_rss_indir_table { 378 u8 status; 379 u8 version; 380 u8 rsvd0[6]; 381 382 u16 func_id; 383 u8 template_id; 384 u8 rsvd1; 385 u8 indir[HINIC_RSS_INDIR_SIZE]; 386 }; 387 388 struct hinic_rss_key { 389 u8 status; 390 u8 version; 391 u8 rsvd0[6]; 392 393 u16 func_id; 394 u8 template_id; 395 u8 rsvd1; 396 u8 key[HINIC_RSS_KEY_SIZE]; 397 }; 398 399 struct hinic_rss_engine_type { 400 u8 status; 401 u8 version; 402 u8 rsvd0[6]; 403 404 u16 func_id; 405 u8 template_id; 406 u8 hash_engine; 407 u8 rsvd1[4]; 408 }; 409 410 struct hinic_rss_config { 411 u8 status; 412 u8 version; 413 u8 rsvd0[6]; 414 415 u16 func_id; 416 u8 rss_en; 417 u8 template_id; 418 u8 rq_priority_number; 419 u8 rsvd1[11]; 420 }; 421 422 struct hinic_stats { 423 char name[ETH_GSTRING_LEN]; 424 u32 size; 425 int offset; 426 }; 427 428 struct hinic_vport_stats { 429 u64 tx_unicast_pkts_vport; 430 u64 tx_unicast_bytes_vport; 431 u64 tx_multicast_pkts_vport; 432 u64 tx_multicast_bytes_vport; 433 u64 tx_broadcast_pkts_vport; 434 u64 tx_broadcast_bytes_vport; 435 436 u64 rx_unicast_pkts_vport; 437 u64 rx_unicast_bytes_vport; 438 u64 rx_multicast_pkts_vport; 439 u64 rx_multicast_bytes_vport; 440 u64 rx_broadcast_pkts_vport; 441 u64 rx_broadcast_bytes_vport; 442 443 u64 tx_discard_vport; 444 u64 rx_discard_vport; 445 u64 tx_err_vport; 446 u64 rx_err_vport; 447 }; 448 449 struct hinic_phy_port_stats { 450 u64 mac_rx_total_pkt_num; 451 u64 mac_rx_total_oct_num; 452 u64 mac_rx_bad_pkt_num; 453 u64 mac_rx_bad_oct_num; 454 u64 mac_rx_good_pkt_num; 455 u64 mac_rx_good_oct_num; 456 u64 mac_rx_uni_pkt_num; 457 u64 mac_rx_multi_pkt_num; 458 u64 mac_rx_broad_pkt_num; 459 460 u64 mac_tx_total_pkt_num; 461 u64 mac_tx_total_oct_num; 462 u64 mac_tx_bad_pkt_num; 463 u64 mac_tx_bad_oct_num; 464 u64 mac_tx_good_pkt_num; 465 u64 mac_tx_good_oct_num; 466 u64 mac_tx_uni_pkt_num; 467 u64 mac_tx_multi_pkt_num; 468 u64 mac_tx_broad_pkt_num; 469 470 u64 mac_rx_fragment_pkt_num; 471 u64 mac_rx_undersize_pkt_num; 472 u64 mac_rx_undermin_pkt_num; 473 u64 mac_rx_64_oct_pkt_num; 474 u64 mac_rx_65_127_oct_pkt_num; 475 u64 mac_rx_128_255_oct_pkt_num; 476 u64 mac_rx_256_511_oct_pkt_num; 477 u64 mac_rx_512_1023_oct_pkt_num; 478 u64 mac_rx_1024_1518_oct_pkt_num; 479 u64 mac_rx_1519_2047_oct_pkt_num; 480 u64 mac_rx_2048_4095_oct_pkt_num; 481 u64 mac_rx_4096_8191_oct_pkt_num; 482 u64 mac_rx_8192_9216_oct_pkt_num; 483 u64 mac_rx_9217_12287_oct_pkt_num; 484 u64 mac_rx_12288_16383_oct_pkt_num; 485 u64 mac_rx_1519_max_bad_pkt_num; 486 u64 mac_rx_1519_max_good_pkt_num; 487 u64 mac_rx_oversize_pkt_num; 488 u64 mac_rx_jabber_pkt_num; 489 490 u64 mac_rx_pause_num; 491 u64 mac_rx_pfc_pkt_num; 492 u64 mac_rx_pfc_pri0_pkt_num; 493 u64 mac_rx_pfc_pri1_pkt_num; 494 u64 mac_rx_pfc_pri2_pkt_num; 495 u64 mac_rx_pfc_pri3_pkt_num; 496 u64 mac_rx_pfc_pri4_pkt_num; 497 u64 mac_rx_pfc_pri5_pkt_num; 498 u64 mac_rx_pfc_pri6_pkt_num; 499 u64 mac_rx_pfc_pri7_pkt_num; 500 u64 mac_rx_control_pkt_num; 501 u64 mac_rx_y1731_pkt_num; 502 u64 mac_rx_sym_err_pkt_num; 503 u64 mac_rx_fcs_err_pkt_num; 504 u64 mac_rx_send_app_good_pkt_num; 505 u64 mac_rx_send_app_bad_pkt_num; 506 507 u64 mac_tx_fragment_pkt_num; 508 u64 mac_tx_undersize_pkt_num; 509 u64 mac_tx_undermin_pkt_num; 510 u64 mac_tx_64_oct_pkt_num; 511 u64 mac_tx_65_127_oct_pkt_num; 512 u64 mac_tx_128_255_oct_pkt_num; 513 u64 mac_tx_256_511_oct_pkt_num; 514 u64 mac_tx_512_1023_oct_pkt_num; 515 u64 mac_tx_1024_1518_oct_pkt_num; 516 u64 mac_tx_1519_2047_oct_pkt_num; 517 u64 mac_tx_2048_4095_oct_pkt_num; 518 u64 mac_tx_4096_8191_oct_pkt_num; 519 u64 mac_tx_8192_9216_oct_pkt_num; 520 u64 mac_tx_9217_12287_oct_pkt_num; 521 u64 mac_tx_12288_16383_oct_pkt_num; 522 u64 mac_tx_1519_max_bad_pkt_num; 523 u64 mac_tx_1519_max_good_pkt_num; 524 u64 mac_tx_oversize_pkt_num; 525 u64 mac_tx_jabber_pkt_num; 526 527 u64 mac_tx_pause_num; 528 u64 mac_tx_pfc_pkt_num; 529 u64 mac_tx_pfc_pri0_pkt_num; 530 u64 mac_tx_pfc_pri1_pkt_num; 531 u64 mac_tx_pfc_pri2_pkt_num; 532 u64 mac_tx_pfc_pri3_pkt_num; 533 u64 mac_tx_pfc_pri4_pkt_num; 534 u64 mac_tx_pfc_pri5_pkt_num; 535 u64 mac_tx_pfc_pri6_pkt_num; 536 u64 mac_tx_pfc_pri7_pkt_num; 537 u64 mac_tx_control_pkt_num; 538 u64 mac_tx_y1731_pkt_num; 539 u64 mac_tx_1588_pkt_num; 540 u64 mac_tx_err_all_pkt_num; 541 u64 mac_tx_from_app_good_pkt_num; 542 u64 mac_tx_from_app_bad_pkt_num; 543 544 u64 mac_rx_higig2_ext_pkt_num; 545 u64 mac_rx_higig2_message_pkt_num; 546 u64 mac_rx_higig2_error_pkt_num; 547 u64 mac_rx_higig2_cpu_ctrl_pkt_num; 548 u64 mac_rx_higig2_unicast_pkt_num; 549 u64 mac_rx_higig2_broadcast_pkt_num; 550 u64 mac_rx_higig2_l2_multicast_pkt_num; 551 u64 mac_rx_higig2_l3_multicast_pkt_num; 552 553 u64 mac_tx_higig2_message_pkt_num; 554 u64 mac_tx_higig2_ext_pkt_num; 555 u64 mac_tx_higig2_cpu_ctrl_pkt_num; 556 u64 mac_tx_higig2_unicast_pkt_num; 557 u64 mac_tx_higig2_broadcast_pkt_num; 558 u64 mac_tx_higig2_l2_multicast_pkt_num; 559 u64 mac_tx_higig2_l3_multicast_pkt_num; 560 }; 561 562 struct hinic_port_stats_info { 563 u8 status; 564 u8 version; 565 u8 rsvd0[6]; 566 567 u16 func_id; 568 u16 rsvd1; 569 u32 stats_version; 570 u32 stats_size; 571 }; 572 573 struct hinic_port_stats { 574 u8 status; 575 u8 version; 576 u8 rsvd[6]; 577 578 struct hinic_phy_port_stats stats; 579 }; 580 581 struct hinic_cmd_vport_stats { 582 u8 status; 583 u8 version; 584 u8 rsvd0[6]; 585 586 struct hinic_vport_stats stats; 587 }; 588 589 struct hinic_tx_rate_cfg_max_min { 590 u8 status; 591 u8 version; 592 u8 rsvd0[6]; 593 594 u16 func_id; 595 u16 rsvd1; 596 u32 min_rate; 597 u32 max_rate; 598 u8 rsvd2[8]; 599 }; 600 601 struct hinic_tx_rate_cfg { 602 u8 status; 603 u8 version; 604 u8 rsvd0[6]; 605 606 u16 func_id; 607 u16 rsvd1; 608 u32 tx_rate; 609 }; 610 611 enum nic_speed_level { 612 LINK_SPEED_10MB = 0, 613 LINK_SPEED_100MB, 614 LINK_SPEED_1GB, 615 LINK_SPEED_10GB, 616 LINK_SPEED_25GB, 617 LINK_SPEED_40GB, 618 LINK_SPEED_100GB, 619 LINK_SPEED_LEVELS, 620 }; 621 622 struct hinic_spoofchk_set { 623 u8 status; 624 u8 version; 625 u8 rsvd0[6]; 626 627 u8 state; 628 u8 rsvd1; 629 u16 func_id; 630 }; 631 632 struct hinic_pause_config { 633 u8 status; 634 u8 version; 635 u8 rsvd0[6]; 636 637 u16 func_id; 638 u16 rsvd1; 639 u32 auto_neg; 640 u32 rx_pause; 641 u32 tx_pause; 642 }; 643 644 struct hinic_set_pfc { 645 u8 status; 646 u8 version; 647 u8 rsvd0[6]; 648 649 u16 func_id; 650 u8 pfc_en; 651 u8 pfc_bitmap; 652 u8 rsvd1[4]; 653 }; 654 655 /* get or set loopback mode, need to modify by base API */ 656 #define HINIC_INTERNAL_LP_MODE 5 657 #define LOOP_MODE_MIN 1 658 #define LOOP_MODE_MAX 6 659 660 struct hinic_port_loopback { 661 u8 status; 662 u8 version; 663 u8 rsvd[6]; 664 665 u32 mode; 666 u32 en; 667 }; 668 669 struct hinic_led_info { 670 u8 status; 671 u8 version; 672 u8 rsvd0[6]; 673 674 u8 port; 675 u8 type; 676 u8 mode; 677 u8 reset; 678 }; 679 680 #define STD_SFP_INFO_MAX_SIZE 640 681 682 struct hinic_cmd_get_light_module_abs { 683 u8 status; 684 u8 version; 685 u8 rsvd0[6]; 686 687 u8 port_id; 688 u8 abs_status; /* 0:present, 1:absent */ 689 u8 rsv[2]; 690 }; 691 692 #define STD_SFP_INFO_MAX_SIZE 640 693 694 struct hinic_cmd_get_std_sfp_info { 695 u8 status; 696 u8 version; 697 u8 rsvd0[6]; 698 699 u8 port_id; 700 u8 wire_type; 701 u16 eeprom_len; 702 u32 rsvd; 703 u8 sfp_info[STD_SFP_INFO_MAX_SIZE]; 704 }; 705 706 struct hinic_cmd_update_fw { 707 u8 status; 708 u8 version; 709 u8 rsvd0[6]; 710 711 struct { 712 u32 SL:1; 713 u32 SF:1; 714 u32 flag:1; 715 u32 reserved:13; 716 u32 fragment_len:16; 717 } ctl_info; 718 719 struct { 720 u32 FW_section_CRC; 721 u32 FW_section_type; 722 } section_info; 723 724 u32 total_len; 725 u32 setion_total_len; 726 u32 fw_section_version; 727 u32 section_offset; 728 u32 data[384]; 729 }; 730 731 int hinic_port_add_mac(struct hinic_dev *nic_dev, const u8 *addr, 732 u16 vlan_id); 733 734 int hinic_port_del_mac(struct hinic_dev *nic_dev, const u8 *addr, 735 u16 vlan_id); 736 737 int hinic_port_get_mac(struct hinic_dev *nic_dev, u8 *addr); 738 739 int hinic_port_set_mtu(struct hinic_dev *nic_dev, int new_mtu); 740 741 int hinic_port_add_vlan(struct hinic_dev *nic_dev, u16 vlan_id); 742 743 int hinic_port_del_vlan(struct hinic_dev *nic_dev, u16 vlan_id); 744 745 int hinic_port_set_rx_mode(struct hinic_dev *nic_dev, u32 rx_mode); 746 747 int hinic_port_link_state(struct hinic_dev *nic_dev, 748 enum hinic_port_link_state *link_state); 749 750 int hinic_port_set_state(struct hinic_dev *nic_dev, 751 enum hinic_port_state state); 752 753 int hinic_port_set_func_state(struct hinic_dev *nic_dev, 754 enum hinic_func_port_state state); 755 756 int hinic_port_get_cap(struct hinic_dev *nic_dev, 757 struct hinic_port_cap *port_cap); 758 759 int hinic_set_max_qnum(struct hinic_dev *nic_dev, u8 num_rqs); 760 761 int hinic_port_set_tso(struct hinic_dev *nic_dev, enum hinic_tso_state state); 762 763 int hinic_set_rx_csum_offload(struct hinic_dev *nic_dev, u32 en); 764 765 int hinic_set_rx_lro_state(struct hinic_dev *nic_dev, u8 lro_en, 766 u32 lro_timer, u32 wqe_num); 767 768 int hinic_set_rss_type(struct hinic_dev *nic_dev, u32 tmpl_idx, 769 struct hinic_rss_type rss_type); 770 771 int hinic_rss_set_indir_tbl(struct hinic_dev *nic_dev, u32 tmpl_idx, 772 const u32 *indir_table); 773 774 int hinic_rss_set_template_tbl(struct hinic_dev *nic_dev, u32 template_id, 775 const u8 *temp); 776 777 int hinic_rss_set_hash_engine(struct hinic_dev *nic_dev, u8 template_id, 778 u8 type); 779 780 int hinic_rss_cfg(struct hinic_dev *nic_dev, u8 rss_en, u8 template_id); 781 782 int hinic_rss_template_alloc(struct hinic_dev *nic_dev, u8 *tmpl_idx); 783 784 int hinic_rss_template_free(struct hinic_dev *nic_dev, u8 tmpl_idx); 785 786 void hinic_set_ethtool_ops(struct net_device *netdev); 787 788 int hinic_get_rss_type(struct hinic_dev *nic_dev, u32 tmpl_idx, 789 struct hinic_rss_type *rss_type); 790 791 int hinic_rss_get_indir_tbl(struct hinic_dev *nic_dev, u32 tmpl_idx, 792 u32 *indir_table); 793 794 int hinic_rss_get_template_tbl(struct hinic_dev *nic_dev, u32 tmpl_idx, 795 u8 *temp); 796 797 int hinic_rss_get_hash_engine(struct hinic_dev *nic_dev, u8 tmpl_idx, 798 u8 *type); 799 800 int hinic_get_phy_port_stats(struct hinic_dev *nic_dev, 801 struct hinic_phy_port_stats *stats); 802 803 int hinic_get_vport_stats(struct hinic_dev *nic_dev, 804 struct hinic_vport_stats *stats); 805 806 int hinic_set_rx_vlan_offload(struct hinic_dev *nic_dev, u8 en); 807 808 int hinic_get_mgmt_version(struct hinic_dev *nic_dev, u8 *mgmt_ver); 809 810 int hinic_set_link_settings(struct hinic_hwdev *hwdev, 811 struct hinic_link_ksettings_info *info); 812 813 int hinic_get_link_mode(struct hinic_hwdev *hwdev, 814 struct hinic_link_mode_cmd *link_mode); 815 816 int hinic_set_autoneg(struct hinic_hwdev *hwdev, bool enable); 817 818 int hinic_set_speed(struct hinic_hwdev *hwdev, enum nic_speed_level speed); 819 820 int hinic_get_hw_pause_info(struct hinic_hwdev *hwdev, 821 struct hinic_pause_config *pause_info); 822 823 int hinic_set_hw_pause_info(struct hinic_hwdev *hwdev, 824 struct hinic_pause_config *pause_info); 825 826 int hinic_dcb_set_pfc(struct hinic_hwdev *hwdev, u8 pfc_en, u8 pfc_bitmap); 827 828 int hinic_set_loopback_mode(struct hinic_hwdev *hwdev, u32 mode, u32 enable); 829 830 enum hinic_led_mode { 831 HINIC_LED_MODE_ON, 832 HINIC_LED_MODE_OFF, 833 HINIC_LED_MODE_FORCE_1HZ, 834 HINIC_LED_MODE_FORCE_2HZ, 835 HINIC_LED_MODE_FORCE_4HZ, 836 HINIC_LED_MODE_1HZ, 837 HINIC_LED_MODE_2HZ, 838 HINIC_LED_MODE_4HZ, 839 HINIC_LED_MODE_INVALID, 840 }; 841 842 enum hinic_led_type { 843 HINIC_LED_TYPE_LINK, 844 HINIC_LED_TYPE_LOW_SPEED, 845 HINIC_LED_TYPE_HIGH_SPEED, 846 HINIC_LED_TYPE_INVALID, 847 }; 848 849 int hinic_reset_led_status(struct hinic_hwdev *hwdev, u8 port); 850 851 int hinic_set_led_status(struct hinic_hwdev *hwdev, u8 port, 852 enum hinic_led_type type, enum hinic_led_mode mode); 853 854 int hinic_get_sfp_type(struct hinic_hwdev *hwdev, u8 *data0, u8 *data1); 855 856 int hinic_get_sfp_eeprom(struct hinic_hwdev *hwdev, u8 *data, u16 *len); 857 858 int hinic_open(struct net_device *netdev); 859 860 int hinic_close(struct net_device *netdev); 861 862 #endif 863