1 /* 2 * Huawei HiNIC PCI Express Linux driver 3 * Copyright(c) 2017 Huawei Technologies Co., Ltd 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * for more details. 13 * 14 */ 15 16 #ifndef HINIC_HW_WQE_H 17 #define HINIC_HW_WQE_H 18 19 #include "hinic_common.h" 20 21 #define HINIC_CMDQ_CTRL_PI_SHIFT 0 22 #define HINIC_CMDQ_CTRL_CMD_SHIFT 16 23 #define HINIC_CMDQ_CTRL_MOD_SHIFT 24 24 #define HINIC_CMDQ_CTRL_ACK_TYPE_SHIFT 29 25 #define HINIC_CMDQ_CTRL_HW_BUSY_BIT_SHIFT 31 26 27 #define HINIC_CMDQ_CTRL_PI_MASK 0xFFFF 28 #define HINIC_CMDQ_CTRL_CMD_MASK 0xFF 29 #define HINIC_CMDQ_CTRL_MOD_MASK 0x1F 30 #define HINIC_CMDQ_CTRL_ACK_TYPE_MASK 0x3 31 #define HINIC_CMDQ_CTRL_HW_BUSY_BIT_MASK 0x1 32 33 #define HINIC_CMDQ_CTRL_SET(val, member) \ 34 (((u32)(val) & HINIC_CMDQ_CTRL_##member##_MASK) \ 35 << HINIC_CMDQ_CTRL_##member##_SHIFT) 36 37 #define HINIC_CMDQ_CTRL_GET(val, member) \ 38 (((val) >> HINIC_CMDQ_CTRL_##member##_SHIFT) \ 39 & HINIC_CMDQ_CTRL_##member##_MASK) 40 41 #define HINIC_CMDQ_WQE_HEADER_BUFDESC_LEN_SHIFT 0 42 #define HINIC_CMDQ_WQE_HEADER_COMPLETE_FMT_SHIFT 15 43 #define HINIC_CMDQ_WQE_HEADER_DATA_FMT_SHIFT 22 44 #define HINIC_CMDQ_WQE_HEADER_COMPLETE_REQ_SHIFT 23 45 #define HINIC_CMDQ_WQE_HEADER_COMPLETE_SECT_LEN_SHIFT 27 46 #define HINIC_CMDQ_WQE_HEADER_CTRL_LEN_SHIFT 29 47 #define HINIC_CMDQ_WQE_HEADER_TOGGLED_WRAPPED_SHIFT 31 48 49 #define HINIC_CMDQ_WQE_HEADER_BUFDESC_LEN_MASK 0xFF 50 #define HINIC_CMDQ_WQE_HEADER_COMPLETE_FMT_MASK 0x1 51 #define HINIC_CMDQ_WQE_HEADER_DATA_FMT_MASK 0x1 52 #define HINIC_CMDQ_WQE_HEADER_COMPLETE_REQ_MASK 0x1 53 #define HINIC_CMDQ_WQE_HEADER_COMPLETE_SECT_LEN_MASK 0x3 54 #define HINIC_CMDQ_WQE_HEADER_CTRL_LEN_MASK 0x3 55 #define HINIC_CMDQ_WQE_HEADER_TOGGLED_WRAPPED_MASK 0x1 56 57 #define HINIC_CMDQ_WQE_HEADER_SET(val, member) \ 58 (((u32)(val) & HINIC_CMDQ_WQE_HEADER_##member##_MASK) \ 59 << HINIC_CMDQ_WQE_HEADER_##member##_SHIFT) 60 61 #define HINIC_CMDQ_WQE_HEADER_GET(val, member) \ 62 (((val) >> HINIC_CMDQ_WQE_HEADER_##member##_SHIFT) \ 63 & HINIC_CMDQ_WQE_HEADER_##member##_MASK) 64 65 #define HINIC_SQ_CTRL_BUFDESC_SECT_LEN_SHIFT 0 66 #define HINIC_SQ_CTRL_TASKSECT_LEN_SHIFT 16 67 #define HINIC_SQ_CTRL_DATA_FORMAT_SHIFT 22 68 #define HINIC_SQ_CTRL_LEN_SHIFT 29 69 70 #define HINIC_SQ_CTRL_BUFDESC_SECT_LEN_MASK 0xFF 71 #define HINIC_SQ_CTRL_TASKSECT_LEN_MASK 0x1F 72 #define HINIC_SQ_CTRL_DATA_FORMAT_MASK 0x1 73 #define HINIC_SQ_CTRL_LEN_MASK 0x3 74 75 #define HINIC_SQ_CTRL_QUEUE_INFO_PLDOFF_SHIFT 2 76 #define HINIC_SQ_CTRL_QUEUE_INFO_UFO_SHIFT 10 77 #define HINIC_SQ_CTRL_QUEUE_INFO_TSO_SHIFT 11 78 #define HINIC_SQ_CTRL_QUEUE_INFO_TCPUDP_CS_SHIFT 12 79 #define HINIC_SQ_CTRL_QUEUE_INFO_MSS_SHIFT 13 80 #define HINIC_SQ_CTRL_QUEUE_INFO_SCTP_SHIFT 27 81 #define HINIC_SQ_CTRL_QUEUE_INFO_UC_SHIFT 28 82 #define HINIC_SQ_CTRL_QUEUE_INFO_PRI_SHIFT 29 83 84 #define HINIC_SQ_CTRL_QUEUE_INFO_PLDOFF_MASK 0xFF 85 #define HINIC_SQ_CTRL_QUEUE_INFO_UFO_MASK 0x1 86 #define HINIC_SQ_CTRL_QUEUE_INFO_TSO_MASK 0x1 87 #define HINIC_SQ_CTRL_QUEUE_INFO_TCPUDP_CS_MASK 0x1 88 #define HINIC_SQ_CTRL_QUEUE_INFO_MSS_MASK 0x3FFF 89 #define HINIC_SQ_CTRL_QUEUE_INFO_SCTP_MASK 0x1 90 #define HINIC_SQ_CTRL_QUEUE_INFO_UC_MASK 0x1 91 #define HINIC_SQ_CTRL_QUEUE_INFO_PRI_MASK 0x7 92 93 #define HINIC_SQ_CTRL_SET(val, member) \ 94 (((u32)(val) & HINIC_SQ_CTRL_##member##_MASK) \ 95 << HINIC_SQ_CTRL_##member##_SHIFT) 96 97 #define HINIC_SQ_CTRL_GET(val, member) \ 98 (((val) >> HINIC_SQ_CTRL_##member##_SHIFT) \ 99 & HINIC_SQ_CTRL_##member##_MASK) 100 101 #define HINIC_SQ_CTRL_CLEAR(val, member) \ 102 ((u32)(val) & (~(HINIC_SQ_CTRL_##member##_MASK \ 103 << HINIC_SQ_CTRL_##member##_SHIFT))) 104 105 #define HINIC_SQ_TASK_INFO0_L2HDR_LEN_SHIFT 0 106 #define HINIC_SQ_TASK_INFO0_L4_OFFLOAD_SHIFT 8 107 #define HINIC_SQ_TASK_INFO0_INNER_L3TYPE_SHIFT 10 108 #define HINIC_SQ_TASK_INFO0_VLAN_OFFLOAD_SHIFT 12 109 #define HINIC_SQ_TASK_INFO0_PARSE_FLAG_SHIFT 13 110 /* 1 bit reserved */ 111 #define HINIC_SQ_TASK_INFO0_TSO_FLAG_SHIFT 15 112 #define HINIC_SQ_TASK_INFO0_VLAN_TAG_SHIFT 16 113 114 #define HINIC_SQ_TASK_INFO0_L2HDR_LEN_MASK 0xFF 115 #define HINIC_SQ_TASK_INFO0_L4_OFFLOAD_MASK 0x3 116 #define HINIC_SQ_TASK_INFO0_INNER_L3TYPE_MASK 0x3 117 #define HINIC_SQ_TASK_INFO0_VLAN_OFFLOAD_MASK 0x1 118 #define HINIC_SQ_TASK_INFO0_PARSE_FLAG_MASK 0x1 119 /* 1 bit reserved */ 120 #define HINIC_SQ_TASK_INFO0_TSO_FLAG_MASK 0x1 121 #define HINIC_SQ_TASK_INFO0_VLAN_TAG_MASK 0xFFFF 122 123 #define HINIC_SQ_TASK_INFO0_SET(val, member) \ 124 (((u32)(val) & HINIC_SQ_TASK_INFO0_##member##_MASK) << \ 125 HINIC_SQ_TASK_INFO0_##member##_SHIFT) 126 127 /* 8 bits reserved */ 128 #define HINIC_SQ_TASK_INFO1_MEDIA_TYPE_SHIFT 8 129 #define HINIC_SQ_TASK_INFO1_INNER_L4LEN_SHIFT 16 130 #define HINIC_SQ_TASK_INFO1_INNER_L3LEN_SHIFT 24 131 132 /* 8 bits reserved */ 133 #define HINIC_SQ_TASK_INFO1_MEDIA_TYPE_MASK 0xFF 134 #define HINIC_SQ_TASK_INFO1_INNER_L4LEN_MASK 0xFF 135 #define HINIC_SQ_TASK_INFO1_INNER_L3LEN_MASK 0xFF 136 137 #define HINIC_SQ_TASK_INFO1_SET(val, member) \ 138 (((u32)(val) & HINIC_SQ_TASK_INFO1_##member##_MASK) << \ 139 HINIC_SQ_TASK_INFO1_##member##_SHIFT) 140 141 #define HINIC_SQ_TASK_INFO2_TUNNEL_L4LEN_SHIFT 0 142 #define HINIC_SQ_TASK_INFO2_OUTER_L3LEN_SHIFT 8 143 #define HINIC_SQ_TASK_INFO2_TUNNEL_L4TYPE_SHIFT 16 144 /* 1 bit reserved */ 145 #define HINIC_SQ_TASK_INFO2_OUTER_L3TYPE_SHIFT 24 146 /* 8 bits reserved */ 147 148 #define HINIC_SQ_TASK_INFO2_TUNNEL_L4LEN_MASK 0xFF 149 #define HINIC_SQ_TASK_INFO2_OUTER_L3LEN_MASK 0xFF 150 #define HINIC_SQ_TASK_INFO2_TUNNEL_L4TYPE_MASK 0x7 151 /* 1 bit reserved */ 152 #define HINIC_SQ_TASK_INFO2_OUTER_L3TYPE_MASK 0x3 153 /* 8 bits reserved */ 154 155 #define HINIC_SQ_TASK_INFO2_SET(val, member) \ 156 (((u32)(val) & HINIC_SQ_TASK_INFO2_##member##_MASK) << \ 157 HINIC_SQ_TASK_INFO2_##member##_SHIFT) 158 159 /* 31 bits reserved */ 160 #define HINIC_SQ_TASK_INFO4_L2TYPE_SHIFT 31 161 162 /* 31 bits reserved */ 163 #define HINIC_SQ_TASK_INFO4_L2TYPE_MASK 0x1 164 165 #define HINIC_SQ_TASK_INFO4_SET(val, member) \ 166 (((u32)(val) & HINIC_SQ_TASK_INFO4_##member##_MASK) << \ 167 HINIC_SQ_TASK_INFO4_##member##_SHIFT) 168 169 #define HINIC_RQ_CQE_STATUS_RXDONE_SHIFT 31 170 171 #define HINIC_RQ_CQE_STATUS_RXDONE_MASK 0x1 172 173 #define HINIC_RQ_CQE_STATUS_GET(val, member) \ 174 (((val) >> HINIC_RQ_CQE_STATUS_##member##_SHIFT) & \ 175 HINIC_RQ_CQE_STATUS_##member##_MASK) 176 177 #define HINIC_RQ_CQE_STATUS_CLEAR(val, member) \ 178 ((val) & (~(HINIC_RQ_CQE_STATUS_##member##_MASK << \ 179 HINIC_RQ_CQE_STATUS_##member##_SHIFT))) 180 181 #define HINIC_RQ_CQE_SGE_LEN_SHIFT 16 182 183 #define HINIC_RQ_CQE_SGE_LEN_MASK 0xFFFF 184 185 #define HINIC_RQ_CQE_SGE_GET(val, member) \ 186 (((val) >> HINIC_RQ_CQE_SGE_##member##_SHIFT) & \ 187 HINIC_RQ_CQE_SGE_##member##_MASK) 188 189 #define HINIC_RQ_CTRL_BUFDESC_SECT_LEN_SHIFT 0 190 #define HINIC_RQ_CTRL_COMPLETE_FORMAT_SHIFT 15 191 #define HINIC_RQ_CTRL_COMPLETE_LEN_SHIFT 27 192 #define HINIC_RQ_CTRL_LEN_SHIFT 29 193 194 #define HINIC_RQ_CTRL_BUFDESC_SECT_LEN_MASK 0xFF 195 #define HINIC_RQ_CTRL_COMPLETE_FORMAT_MASK 0x1 196 #define HINIC_RQ_CTRL_COMPLETE_LEN_MASK 0x3 197 #define HINIC_RQ_CTRL_LEN_MASK 0x3 198 199 #define HINIC_RQ_CTRL_SET(val, member) \ 200 (((u32)(val) & HINIC_RQ_CTRL_##member##_MASK) << \ 201 HINIC_RQ_CTRL_##member##_SHIFT) 202 203 #define HINIC_SQ_WQE_SIZE(nr_sges) \ 204 (sizeof(struct hinic_sq_ctrl) + \ 205 sizeof(struct hinic_sq_task) + \ 206 (nr_sges) * sizeof(struct hinic_sq_bufdesc)) 207 208 #define HINIC_SCMD_DATA_LEN 16 209 210 #define HINIC_MAX_SQ_BUFDESCS 17 211 212 #define HINIC_SQ_WQE_MAX_SIZE 320 213 #define HINIC_RQ_WQE_SIZE 32 214 215 #define HINIC_MSS_DEFAULT 0x3E00 216 #define HINIC_MSS_MIN 0x50 217 218 enum hinic_l4offload_type { 219 HINIC_L4_OFF_DISABLE = 0, 220 HINIC_TCP_OFFLOAD_ENABLE = 1, 221 HINIC_SCTP_OFFLOAD_ENABLE = 2, 222 HINIC_UDP_OFFLOAD_ENABLE = 3, 223 }; 224 225 enum hinic_vlan_offload { 226 HINIC_VLAN_OFF_DISABLE = 0, 227 HINIC_VLAN_OFF_ENABLE = 1, 228 }; 229 230 enum hinic_pkt_parsed { 231 HINIC_PKT_NOT_PARSED = 0, 232 HINIC_PKT_PARSED = 1, 233 }; 234 235 enum hinic_l3_offload_type { 236 L3TYPE_UNKNOWN = 0, 237 IPV6_PKT = 1, 238 IPV4_PKT_NO_CHKSUM_OFFLOAD = 2, 239 IPV4_PKT_WITH_CHKSUM_OFFLOAD = 3, 240 }; 241 242 enum hinic_l4_offload_type { 243 OFFLOAD_DISABLE = 0, 244 TCP_OFFLOAD_ENABLE = 1, 245 SCTP_OFFLOAD_ENABLE = 2, 246 UDP_OFFLOAD_ENABLE = 3, 247 }; 248 249 enum hinic_l4_tunnel_type { 250 NOT_TUNNEL, 251 TUNNEL_UDP_NO_CSUM, 252 TUNNEL_UDP_CSUM, 253 }; 254 255 enum hinic_outer_l3type { 256 HINIC_OUTER_L3TYPE_UNKNOWN = 0, 257 HINIC_OUTER_L3TYPE_IPV6 = 1, 258 HINIC_OUTER_L3TYPE_IPV4_NO_CHKSUM = 2, 259 HINIC_OUTER_L3TYPE_IPV4_CHKSUM = 3, 260 }; 261 262 enum hinic_media_type { 263 HINIC_MEDIA_UNKNOWN = 0, 264 }; 265 266 enum hinic_l2type { 267 HINIC_L2TYPE_ETH = 0, 268 }; 269 270 enum hinc_tunnel_l4type { 271 HINIC_TUNNEL_L4TYPE_UNKNOWN = 0, 272 }; 273 274 struct hinic_cmdq_header { 275 u32 header_info; 276 u32 saved_data; 277 }; 278 279 struct hinic_status { 280 u32 status_info; 281 }; 282 283 struct hinic_ctrl { 284 u32 ctrl_info; 285 }; 286 287 struct hinic_sge_resp { 288 struct hinic_sge sge; 289 u32 rsvd; 290 }; 291 292 struct hinic_cmdq_completion { 293 /* HW Format */ 294 union { 295 struct hinic_sge_resp sge_resp; 296 u64 direct_resp; 297 }; 298 }; 299 300 struct hinic_scmd_bufdesc { 301 u32 buf_len; 302 u32 rsvd; 303 u8 data[HINIC_SCMD_DATA_LEN]; 304 }; 305 306 struct hinic_lcmd_bufdesc { 307 struct hinic_sge sge; 308 u32 rsvd1; 309 u64 rsvd2; 310 u64 rsvd3; 311 }; 312 313 struct hinic_cmdq_wqe_scmd { 314 struct hinic_cmdq_header header; 315 u64 rsvd; 316 struct hinic_status status; 317 struct hinic_ctrl ctrl; 318 struct hinic_cmdq_completion completion; 319 struct hinic_scmd_bufdesc buf_desc; 320 }; 321 322 struct hinic_cmdq_wqe_lcmd { 323 struct hinic_cmdq_header header; 324 struct hinic_status status; 325 struct hinic_ctrl ctrl; 326 struct hinic_cmdq_completion completion; 327 struct hinic_lcmd_bufdesc buf_desc; 328 }; 329 330 struct hinic_cmdq_direct_wqe { 331 struct hinic_cmdq_wqe_scmd wqe_scmd; 332 }; 333 334 struct hinic_cmdq_wqe { 335 /* HW Format */ 336 union { 337 struct hinic_cmdq_direct_wqe direct_wqe; 338 struct hinic_cmdq_wqe_lcmd wqe_lcmd; 339 }; 340 }; 341 342 struct hinic_sq_ctrl { 343 u32 ctrl_info; 344 u32 queue_info; 345 }; 346 347 struct hinic_sq_task { 348 u32 pkt_info0; 349 u32 pkt_info1; 350 u32 pkt_info2; 351 u32 ufo_v6_identify; 352 u32 pkt_info4; 353 u32 zero_pad; 354 }; 355 356 struct hinic_sq_bufdesc { 357 struct hinic_sge sge; 358 u32 rsvd; 359 }; 360 361 struct hinic_sq_wqe { 362 struct hinic_sq_ctrl ctrl; 363 struct hinic_sq_task task; 364 struct hinic_sq_bufdesc buf_descs[HINIC_MAX_SQ_BUFDESCS]; 365 }; 366 367 struct hinic_rq_cqe { 368 u32 status; 369 u32 len; 370 371 u32 rsvd2; 372 u32 rsvd3; 373 u32 rsvd4; 374 u32 rsvd5; 375 u32 rsvd6; 376 u32 rsvd7; 377 }; 378 379 struct hinic_rq_ctrl { 380 u32 ctrl_info; 381 }; 382 383 struct hinic_rq_cqe_sect { 384 struct hinic_sge sge; 385 u32 rsvd; 386 }; 387 388 struct hinic_rq_bufdesc { 389 u32 hi_addr; 390 u32 lo_addr; 391 }; 392 393 struct hinic_rq_wqe { 394 struct hinic_rq_ctrl ctrl; 395 u32 rsvd; 396 struct hinic_rq_cqe_sect cqe_sect; 397 struct hinic_rq_bufdesc buf_desc; 398 }; 399 400 struct hinic_hw_wqe { 401 /* HW Format */ 402 union { 403 struct hinic_cmdq_wqe cmdq_wqe; 404 struct hinic_sq_wqe sq_wqe; 405 struct hinic_rq_wqe rq_wqe; 406 }; 407 }; 408 409 #endif 410