1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Huawei HiNIC PCI Express Linux driver
4  * Copyright(c) 2017 Huawei Technologies Co., Ltd
5  */
6 
7 #ifndef HINIC_HW_QP_H
8 #define HINIC_HW_QP_H
9 
10 #include <linux/kernel.h>
11 #include <linux/types.h>
12 #include <linux/sizes.h>
13 #include <linux/pci.h>
14 #include <linux/skbuff.h>
15 
16 #include "hinic_common.h"
17 #include "hinic_hw_if.h"
18 #include "hinic_hw_wqe.h"
19 #include "hinic_hw_wq.h"
20 #include "hinic_hw_qp_ctxt.h"
21 
22 #define HINIC_SQ_DB_INFO_PI_HI_SHIFT            0
23 #define HINIC_SQ_DB_INFO_QID_SHIFT              8
24 #define HINIC_SQ_DB_INFO_PATH_SHIFT             23
25 #define HINIC_SQ_DB_INFO_COS_SHIFT              24
26 #define HINIC_SQ_DB_INFO_TYPE_SHIFT             27
27 
28 #define HINIC_SQ_DB_INFO_PI_HI_MASK             0xFF
29 #define HINIC_SQ_DB_INFO_QID_MASK               0x3FF
30 #define HINIC_SQ_DB_INFO_PATH_MASK              0x1
31 #define HINIC_SQ_DB_INFO_COS_MASK               0x7
32 #define HINIC_SQ_DB_INFO_TYPE_MASK              0x1F
33 
34 #define HINIC_SQ_DB_INFO_SET(val, member)       \
35 		(((u32)(val) & HINIC_SQ_DB_INFO_##member##_MASK) \
36 		 << HINIC_SQ_DB_INFO_##member##_SHIFT)
37 
38 #define HINIC_SQ_WQEBB_SIZE                     64
39 #define HINIC_RQ_WQEBB_SIZE                     32
40 
41 #define HINIC_SQ_PAGE_SIZE                      SZ_4K
42 #define HINIC_RQ_PAGE_SIZE                      SZ_4K
43 
44 #define HINIC_SQ_DEPTH                          SZ_4K
45 #define HINIC_RQ_DEPTH                          SZ_4K
46 
47 /* In any change to HINIC_RX_BUF_SZ, HINIC_RX_BUF_SZ_IDX must be changed */
48 #define HINIC_RX_BUF_SZ                         2048
49 #define HINIC_RX_BUF_SZ_IDX			HINIC_RX_BUF_SZ_2048_IDX
50 
51 #define HINIC_MIN_TX_WQE_SIZE(wq)               \
52 		ALIGN(HINIC_SQ_WQE_SIZE(1), (wq)->wqebb_size)
53 
54 #define HINIC_MIN_TX_NUM_WQEBBS(sq)             \
55 		(HINIC_MIN_TX_WQE_SIZE((sq)->wq) / (sq)->wq->wqebb_size)
56 
57 enum hinic_rx_buf_sz_idx {
58 	HINIC_RX_BUF_SZ_32_IDX,
59 	HINIC_RX_BUF_SZ_64_IDX,
60 	HINIC_RX_BUF_SZ_96_IDX,
61 	HINIC_RX_BUF_SZ_128_IDX,
62 	HINIC_RX_BUF_SZ_192_IDX,
63 	HINIC_RX_BUF_SZ_256_IDX,
64 	HINIC_RX_BUF_SZ_384_IDX,
65 	HINIC_RX_BUF_SZ_512_IDX,
66 	HINIC_RX_BUF_SZ_768_IDX,
67 	HINIC_RX_BUF_SZ_1024_IDX,
68 	HINIC_RX_BUF_SZ_1536_IDX,
69 	HINIC_RX_BUF_SZ_2048_IDX,
70 	HINIC_RX_BUF_SZ_3072_IDX,
71 	HINIC_RX_BUF_SZ_4096_IDX,
72 	HINIC_RX_BUF_SZ_8192_IDX,
73 	HINIC_RX_BUF_SZ_16384_IDX,
74 };
75 
76 struct hinic_sq {
77 	struct hinic_hwif       *hwif;
78 
79 	struct hinic_wq         *wq;
80 
81 	u32                     irq;
82 	u16                     msix_entry;
83 
84 	void                    *hw_ci_addr;
85 	dma_addr_t              hw_ci_dma_addr;
86 
87 	void __iomem            *db_base;
88 
89 	struct sk_buff          **saved_skb;
90 };
91 
92 struct hinic_rq {
93 	struct hinic_hwif       *hwif;
94 
95 	struct hinic_wq         *wq;
96 
97 	struct cpumask		affinity_mask;
98 	u32                     irq;
99 	u16                     msix_entry;
100 
101 	size_t                  buf_sz;
102 
103 	struct sk_buff          **saved_skb;
104 
105 	struct hinic_rq_cqe     **cqe;
106 	dma_addr_t              *cqe_dma;
107 
108 	u16                     *pi_virt_addr;
109 	dma_addr_t              pi_dma_addr;
110 };
111 
112 struct hinic_qp {
113 	struct hinic_sq         sq;
114 	struct hinic_rq         rq;
115 
116 	u16     q_id;
117 };
118 
119 void hinic_qp_prepare_header(struct hinic_qp_ctxt_header *qp_ctxt_hdr,
120 			     enum hinic_qp_ctxt_type ctxt_type,
121 			     u16 num_queues, u16 max_queues);
122 
123 void hinic_sq_prepare_ctxt(struct hinic_sq_ctxt *sq_ctxt,
124 			   struct hinic_sq *sq, u16 global_qid);
125 
126 void hinic_rq_prepare_ctxt(struct hinic_rq_ctxt *rq_ctxt,
127 			   struct hinic_rq *rq, u16 global_qid);
128 
129 int hinic_init_sq(struct hinic_sq *sq, struct hinic_hwif *hwif,
130 		  struct hinic_wq *wq, struct msix_entry *entry, void *ci_addr,
131 		  dma_addr_t ci_dma_addr, void __iomem *db_base);
132 
133 void hinic_clean_sq(struct hinic_sq *sq);
134 
135 int hinic_init_rq(struct hinic_rq *rq, struct hinic_hwif *hwif,
136 		  struct hinic_wq *wq, struct msix_entry *entry);
137 
138 void hinic_clean_rq(struct hinic_rq *rq);
139 
140 int hinic_get_sq_free_wqebbs(struct hinic_sq *sq);
141 
142 int hinic_get_rq_free_wqebbs(struct hinic_rq *rq);
143 
144 void hinic_task_set_l2hdr(struct hinic_sq_task *task, u32 len);
145 
146 void hinic_task_set_outter_l3(struct hinic_sq_task *task,
147 			      enum hinic_l3_offload_type l3_type,
148 			      u32 network_len);
149 
150 void hinic_task_set_inner_l3(struct hinic_sq_task *task,
151 			     enum hinic_l3_offload_type l3_type,
152 			     u32 network_len);
153 
154 void hinic_task_set_tunnel_l4(struct hinic_sq_task *task,
155 			      enum hinic_l4_tunnel_type l4_type,
156 			      u32 tunnel_len);
157 
158 void hinic_set_cs_inner_l4(struct hinic_sq_task *task,
159 			   u32 *queue_info,
160 			   enum hinic_l4_offload_type l4_offload,
161 			   u32 l4_len, u32 offset);
162 
163 void hinic_set_tso_inner_l4(struct hinic_sq_task *task,
164 			    u32 *queue_info,
165 			    enum hinic_l4_offload_type l4_offload,
166 			    u32 l4_len,
167 			    u32 offset, u32 ip_ident, u32 mss);
168 
169 void hinic_sq_prepare_wqe(struct hinic_sq *sq, u16 prod_idx,
170 			  struct hinic_sq_wqe *wqe, struct hinic_sge *sges,
171 			  int nr_sges);
172 
173 void hinic_sq_write_db(struct hinic_sq *sq, u16 prod_idx, unsigned int wqe_size,
174 		       unsigned int cos);
175 
176 struct hinic_sq_wqe *hinic_sq_get_wqe(struct hinic_sq *sq,
177 				      unsigned int wqe_size, u16 *prod_idx);
178 
179 void hinic_sq_return_wqe(struct hinic_sq *sq, unsigned int wqe_size);
180 
181 void hinic_sq_write_wqe(struct hinic_sq *sq, u16 prod_idx,
182 			struct hinic_sq_wqe *wqe, struct sk_buff *skb,
183 			unsigned int wqe_size);
184 
185 struct hinic_sq_wqe *hinic_sq_read_wqe(struct hinic_sq *sq,
186 				       struct sk_buff **skb,
187 				       unsigned int wqe_size, u16 *cons_idx);
188 
189 struct hinic_sq_wqe *hinic_sq_read_wqebb(struct hinic_sq *sq,
190 					 struct sk_buff **skb,
191 					 unsigned int *wqe_size, u16 *cons_idx);
192 
193 void hinic_sq_put_wqe(struct hinic_sq *sq, unsigned int wqe_size);
194 
195 void hinic_sq_get_sges(struct hinic_sq_wqe *wqe, struct hinic_sge *sges,
196 		       int nr_sges);
197 
198 struct hinic_rq_wqe *hinic_rq_get_wqe(struct hinic_rq *rq,
199 				      unsigned int wqe_size, u16 *prod_idx);
200 
201 void hinic_rq_write_wqe(struct hinic_rq *rq, u16 prod_idx,
202 			struct hinic_rq_wqe *wqe, struct sk_buff *skb);
203 
204 struct hinic_rq_wqe *hinic_rq_read_wqe(struct hinic_rq *rq,
205 				       unsigned int wqe_size,
206 				       struct sk_buff **skb, u16 *cons_idx);
207 
208 struct hinic_rq_wqe *hinic_rq_read_next_wqe(struct hinic_rq *rq,
209 					    unsigned int wqe_size,
210 					    struct sk_buff **skb,
211 					    u16 *cons_idx);
212 
213 void hinic_rq_put_wqe(struct hinic_rq *rq, u16 cons_idx,
214 		      unsigned int wqe_size);
215 
216 void hinic_rq_get_sge(struct hinic_rq *rq, struct hinic_rq_wqe *wqe,
217 		      u16 cons_idx, struct hinic_sge *sge);
218 
219 void hinic_rq_prepare_wqe(struct hinic_rq *rq, u16 prod_idx,
220 			  struct hinic_rq_wqe *wqe, struct hinic_sge *sge);
221 
222 void hinic_rq_update(struct hinic_rq *rq, u16 prod_idx);
223 
224 #endif
225