12025cf9eSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 251ba902aSAviad Krawczyk /* 351ba902aSAviad Krawczyk * Huawei HiNIC PCI Express Linux driver 451ba902aSAviad Krawczyk * Copyright(c) 2017 Huawei Technologies Co., Ltd 551ba902aSAviad Krawczyk */ 651ba902aSAviad Krawczyk 751ba902aSAviad Krawczyk #ifndef HINIC_HW_IF_H 851ba902aSAviad Krawczyk #define HINIC_HW_IF_H 951ba902aSAviad Krawczyk 1051ba902aSAviad Krawczyk #include <linux/pci.h> 1151ba902aSAviad Krawczyk #include <linux/io.h> 1251ba902aSAviad Krawczyk #include <linux/types.h> 1351ba902aSAviad Krawczyk #include <asm/byteorder.h> 1451ba902aSAviad Krawczyk 1551ba902aSAviad Krawczyk #define HINIC_DMA_ATTR_ST_SHIFT 0 1651ba902aSAviad Krawczyk #define HINIC_DMA_ATTR_AT_SHIFT 8 1751ba902aSAviad Krawczyk #define HINIC_DMA_ATTR_PH_SHIFT 10 1851ba902aSAviad Krawczyk #define HINIC_DMA_ATTR_NO_SNOOPING_SHIFT 12 1951ba902aSAviad Krawczyk #define HINIC_DMA_ATTR_TPH_EN_SHIFT 13 2051ba902aSAviad Krawczyk 2151ba902aSAviad Krawczyk #define HINIC_DMA_ATTR_ST_MASK 0xFF 2251ba902aSAviad Krawczyk #define HINIC_DMA_ATTR_AT_MASK 0x3 2351ba902aSAviad Krawczyk #define HINIC_DMA_ATTR_PH_MASK 0x3 2451ba902aSAviad Krawczyk #define HINIC_DMA_ATTR_NO_SNOOPING_MASK 0x1 2551ba902aSAviad Krawczyk #define HINIC_DMA_ATTR_TPH_EN_MASK 0x1 2651ba902aSAviad Krawczyk 2751ba902aSAviad Krawczyk #define HINIC_DMA_ATTR_SET(val, member) \ 2851ba902aSAviad Krawczyk (((u32)(val) & HINIC_DMA_ATTR_##member##_MASK) << \ 2951ba902aSAviad Krawczyk HINIC_DMA_ATTR_##member##_SHIFT) 3051ba902aSAviad Krawczyk 3151ba902aSAviad Krawczyk #define HINIC_DMA_ATTR_CLEAR(val, member) \ 3251ba902aSAviad Krawczyk ((val) & (~(HINIC_DMA_ATTR_##member##_MASK \ 3351ba902aSAviad Krawczyk << HINIC_DMA_ATTR_##member##_SHIFT))) 3451ba902aSAviad Krawczyk 3551ba902aSAviad Krawczyk #define HINIC_FA0_FUNC_IDX_SHIFT 0 3651ba902aSAviad Krawczyk #define HINIC_FA0_PF_IDX_SHIFT 10 3751ba902aSAviad Krawczyk #define HINIC_FA0_PCI_INTF_IDX_SHIFT 14 3851ba902aSAviad Krawczyk /* reserved members - off 16 */ 3951ba902aSAviad Krawczyk #define HINIC_FA0_FUNC_TYPE_SHIFT 24 4051ba902aSAviad Krawczyk 4151ba902aSAviad Krawczyk #define HINIC_FA0_FUNC_IDX_MASK 0x3FF 4251ba902aSAviad Krawczyk #define HINIC_FA0_PF_IDX_MASK 0xF 4351ba902aSAviad Krawczyk #define HINIC_FA0_PCI_INTF_IDX_MASK 0x3 4451ba902aSAviad Krawczyk #define HINIC_FA0_FUNC_TYPE_MASK 0x1 4551ba902aSAviad Krawczyk 4651ba902aSAviad Krawczyk #define HINIC_FA0_GET(val, member) \ 4751ba902aSAviad Krawczyk (((val) >> HINIC_FA0_##member##_SHIFT) & HINIC_FA0_##member##_MASK) 4851ba902aSAviad Krawczyk 4951ba902aSAviad Krawczyk #define HINIC_FA1_AEQS_PER_FUNC_SHIFT 8 5051ba902aSAviad Krawczyk /* reserved members - off 10 */ 5151ba902aSAviad Krawczyk #define HINIC_FA1_CEQS_PER_FUNC_SHIFT 12 5251ba902aSAviad Krawczyk /* reserved members - off 15 */ 5351ba902aSAviad Krawczyk #define HINIC_FA1_IRQS_PER_FUNC_SHIFT 20 5451ba902aSAviad Krawczyk #define HINIC_FA1_DMA_ATTR_PER_FUNC_SHIFT 24 5551ba902aSAviad Krawczyk /* reserved members - off 27 */ 5651ba902aSAviad Krawczyk #define HINIC_FA1_INIT_STATUS_SHIFT 30 5751ba902aSAviad Krawczyk 5851ba902aSAviad Krawczyk #define HINIC_FA1_AEQS_PER_FUNC_MASK 0x3 5951ba902aSAviad Krawczyk #define HINIC_FA1_CEQS_PER_FUNC_MASK 0x7 6051ba902aSAviad Krawczyk #define HINIC_FA1_IRQS_PER_FUNC_MASK 0xF 6151ba902aSAviad Krawczyk #define HINIC_FA1_DMA_ATTR_PER_FUNC_MASK 0x7 6251ba902aSAviad Krawczyk #define HINIC_FA1_INIT_STATUS_MASK 0x1 6351ba902aSAviad Krawczyk 6451ba902aSAviad Krawczyk #define HINIC_FA1_GET(val, member) \ 6551ba902aSAviad Krawczyk (((val) >> HINIC_FA1_##member##_SHIFT) & HINIC_FA1_##member##_MASK) 6651ba902aSAviad Krawczyk 67e2585ea7SAviad Krawczyk #define HINIC_FA4_OUTBOUND_STATE_SHIFT 0 68e2585ea7SAviad Krawczyk #define HINIC_FA4_DB_STATE_SHIFT 1 69e2585ea7SAviad Krawczyk 70e2585ea7SAviad Krawczyk #define HINIC_FA4_OUTBOUND_STATE_MASK 0x1 71e2585ea7SAviad Krawczyk #define HINIC_FA4_DB_STATE_MASK 0x1 72e2585ea7SAviad Krawczyk 73e2585ea7SAviad Krawczyk #define HINIC_FA4_GET(val, member) \ 74e2585ea7SAviad Krawczyk (((val) >> HINIC_FA4_##member##_SHIFT) & HINIC_FA4_##member##_MASK) 75e2585ea7SAviad Krawczyk 76e2585ea7SAviad Krawczyk #define HINIC_FA4_SET(val, member) \ 77e2585ea7SAviad Krawczyk ((((u32)val) & HINIC_FA4_##member##_MASK) << HINIC_FA4_##member##_SHIFT) 78e2585ea7SAviad Krawczyk 79e2585ea7SAviad Krawczyk #define HINIC_FA4_CLEAR(val, member) \ 80e2585ea7SAviad Krawczyk ((val) & (~(HINIC_FA4_##member##_MASK << HINIC_FA4_##member##_SHIFT))) 81e2585ea7SAviad Krawczyk 82c4d06d2dSAviad Krawczyk #define HINIC_FA5_PF_ACTION_SHIFT 0 83c4d06d2dSAviad Krawczyk #define HINIC_FA5_PF_ACTION_MASK 0xFFFF 84c4d06d2dSAviad Krawczyk 85c4d06d2dSAviad Krawczyk #define HINIC_FA5_SET(val, member) \ 86c4d06d2dSAviad Krawczyk (((u32)(val) & HINIC_FA5_##member##_MASK) << HINIC_FA5_##member##_SHIFT) 87c4d06d2dSAviad Krawczyk 88c4d06d2dSAviad Krawczyk #define HINIC_FA5_CLEAR(val, member) \ 89c4d06d2dSAviad Krawczyk ((val) & (~(HINIC_FA5_##member##_MASK << HINIC_FA5_##member##_SHIFT))) 90c4d06d2dSAviad Krawczyk 9151ba902aSAviad Krawczyk #define HINIC_PPF_ELECTION_IDX_SHIFT 0 9251ba902aSAviad Krawczyk #define HINIC_PPF_ELECTION_IDX_MASK 0x1F 9351ba902aSAviad Krawczyk 9451ba902aSAviad Krawczyk #define HINIC_PPF_ELECTION_SET(val, member) \ 9551ba902aSAviad Krawczyk (((u32)(val) & HINIC_PPF_ELECTION_##member##_MASK) << \ 9651ba902aSAviad Krawczyk HINIC_PPF_ELECTION_##member##_SHIFT) 9751ba902aSAviad Krawczyk 9851ba902aSAviad Krawczyk #define HINIC_PPF_ELECTION_GET(val, member) \ 9951ba902aSAviad Krawczyk (((val) >> HINIC_PPF_ELECTION_##member##_SHIFT) & \ 10051ba902aSAviad Krawczyk HINIC_PPF_ELECTION_##member##_MASK) 10151ba902aSAviad Krawczyk 10251ba902aSAviad Krawczyk #define HINIC_PPF_ELECTION_CLEAR(val, member) \ 10351ba902aSAviad Krawczyk ((val) & (~(HINIC_PPF_ELECTION_##member##_MASK \ 10451ba902aSAviad Krawczyk << HINIC_PPF_ELECTION_##member##_SHIFT))) 10551ba902aSAviad Krawczyk 106f00fe738SAviad Krawczyk #define HINIC_MSIX_PENDING_LIMIT_SHIFT 0 107f00fe738SAviad Krawczyk #define HINIC_MSIX_COALESC_TIMER_SHIFT 8 108f00fe738SAviad Krawczyk #define HINIC_MSIX_LLI_TIMER_SHIFT 16 109f00fe738SAviad Krawczyk #define HINIC_MSIX_LLI_CREDIT_SHIFT 24 110f00fe738SAviad Krawczyk #define HINIC_MSIX_RESEND_TIMER_SHIFT 29 111f00fe738SAviad Krawczyk 112f00fe738SAviad Krawczyk #define HINIC_MSIX_PENDING_LIMIT_MASK 0xFF 113f00fe738SAviad Krawczyk #define HINIC_MSIX_COALESC_TIMER_MASK 0xFF 114f00fe738SAviad Krawczyk #define HINIC_MSIX_LLI_TIMER_MASK 0xFF 115f00fe738SAviad Krawczyk #define HINIC_MSIX_LLI_CREDIT_MASK 0x1F 116f00fe738SAviad Krawczyk #define HINIC_MSIX_RESEND_TIMER_MASK 0x7 117f00fe738SAviad Krawczyk 118f00fe738SAviad Krawczyk #define HINIC_MSIX_ATTR_SET(val, member) \ 119f00fe738SAviad Krawczyk (((u32)(val) & HINIC_MSIX_##member##_MASK) << \ 120f00fe738SAviad Krawczyk HINIC_MSIX_##member##_SHIFT) 121f00fe738SAviad Krawczyk 122f00fe738SAviad Krawczyk #define HINIC_MSIX_ATTR_GET(val, member) \ 123f00fe738SAviad Krawczyk (((val) >> HINIC_MSIX_##member##_SHIFT) & \ 124f00fe738SAviad Krawczyk HINIC_MSIX_##member##_MASK) 125f00fe738SAviad Krawczyk 126f00fe738SAviad Krawczyk #define HINIC_MSIX_CNT_RESEND_TIMER_SHIFT 29 127f00fe738SAviad Krawczyk 128f00fe738SAviad Krawczyk #define HINIC_MSIX_CNT_RESEND_TIMER_MASK 0x1 129f00fe738SAviad Krawczyk 130f00fe738SAviad Krawczyk #define HINIC_MSIX_CNT_SET(val, member) \ 131f00fe738SAviad Krawczyk (((u32)(val) & HINIC_MSIX_CNT_##member##_MASK) << \ 132f00fe738SAviad Krawczyk HINIC_MSIX_CNT_##member##_SHIFT) 133f00fe738SAviad Krawczyk 13451ba902aSAviad Krawczyk #define HINIC_HWIF_NUM_AEQS(hwif) ((hwif)->attr.num_aeqs) 13551ba902aSAviad Krawczyk #define HINIC_HWIF_NUM_CEQS(hwif) ((hwif)->attr.num_ceqs) 13651ba902aSAviad Krawczyk #define HINIC_HWIF_NUM_IRQS(hwif) ((hwif)->attr.num_irqs) 13751ba902aSAviad Krawczyk #define HINIC_HWIF_FUNC_IDX(hwif) ((hwif)->attr.func_idx) 13851ba902aSAviad Krawczyk #define HINIC_HWIF_PCI_INTF(hwif) ((hwif)->attr.pci_intf_idx) 1396dd8b682SAviad Krawczyk #define HINIC_HWIF_PF_IDX(hwif) ((hwif)->attr.pf_idx) 14051ba902aSAviad Krawczyk 14151ba902aSAviad Krawczyk #define HINIC_FUNC_TYPE(hwif) ((hwif)->attr.func_type) 14251ba902aSAviad Krawczyk #define HINIC_IS_PF(hwif) (HINIC_FUNC_TYPE(hwif) == HINIC_PF) 14351ba902aSAviad Krawczyk #define HINIC_IS_PPF(hwif) (HINIC_FUNC_TYPE(hwif) == HINIC_PPF) 14451ba902aSAviad Krawczyk 14551ba902aSAviad Krawczyk #define HINIC_PCI_CFG_REGS_BAR 0 146905b464aSXue Chaojing #define HINIC_PCI_INTR_REGS_BAR 2 147f91090f7SAviad Krawczyk #define HINIC_PCI_DB_BAR 4 14851ba902aSAviad Krawczyk 14951ba902aSAviad Krawczyk #define HINIC_PCIE_ST_DISABLE 0 15051ba902aSAviad Krawczyk #define HINIC_PCIE_AT_DISABLE 0 15151ba902aSAviad Krawczyk #define HINIC_PCIE_PH_DISABLE 0 15251ba902aSAviad Krawczyk 153f00fe738SAviad Krawczyk #define HINIC_EQ_MSIX_PENDING_LIMIT_DEFAULT 0 /* Disabled */ 154f00fe738SAviad Krawczyk #define HINIC_EQ_MSIX_COALESC_TIMER_DEFAULT 0xFF /* max */ 155f00fe738SAviad Krawczyk #define HINIC_EQ_MSIX_LLI_TIMER_DEFAULT 0 /* Disabled */ 156f00fe738SAviad Krawczyk #define HINIC_EQ_MSIX_LLI_CREDIT_LIMIT_DEFAULT 0 /* Disabled */ 157f00fe738SAviad Krawczyk #define HINIC_EQ_MSIX_RESEND_TIMER_DEFAULT 7 /* max */ 158f00fe738SAviad Krawczyk 159905b464aSXue Chaojing #define HINIC_PCI_MSIX_ENTRY_SIZE 16 160905b464aSXue Chaojing #define HINIC_PCI_MSIX_ENTRY_VECTOR_CTRL 12 161905b464aSXue Chaojing #define HINIC_PCI_MSIX_ENTRY_CTRL_MASKBIT 1 162905b464aSXue Chaojing 16351ba902aSAviad Krawczyk enum hinic_pcie_nosnoop { 16451ba902aSAviad Krawczyk HINIC_PCIE_SNOOP = 0, 16551ba902aSAviad Krawczyk HINIC_PCIE_NO_SNOOP = 1, 16651ba902aSAviad Krawczyk }; 16751ba902aSAviad Krawczyk 16851ba902aSAviad Krawczyk enum hinic_pcie_tph { 16951ba902aSAviad Krawczyk HINIC_PCIE_TPH_DISABLE = 0, 17051ba902aSAviad Krawczyk HINIC_PCIE_TPH_ENABLE = 1, 17151ba902aSAviad Krawczyk }; 17251ba902aSAviad Krawczyk 17351ba902aSAviad Krawczyk enum hinic_func_type { 17451ba902aSAviad Krawczyk HINIC_PF = 0, 17551ba902aSAviad Krawczyk HINIC_PPF = 2, 17651ba902aSAviad Krawczyk }; 17751ba902aSAviad Krawczyk 178a5564e7eSAviad Krawczyk enum hinic_mod_type { 179a5564e7eSAviad Krawczyk HINIC_MOD_COMM = 0, /* HW communication module */ 180a5564e7eSAviad Krawczyk HINIC_MOD_L2NIC = 1, /* L2NIC module */ 181a5564e7eSAviad Krawczyk HINIC_MOD_CFGM = 7, /* Configuration module */ 182a5564e7eSAviad Krawczyk 183a5564e7eSAviad Krawczyk HINIC_MOD_MAX = 15 184a5564e7eSAviad Krawczyk }; 185a5564e7eSAviad Krawczyk 1866dd8b682SAviad Krawczyk enum hinic_node_id { 1876dd8b682SAviad Krawczyk HINIC_NODE_ID_MGMT = 21, 1886dd8b682SAviad Krawczyk }; 1896dd8b682SAviad Krawczyk 190c4d06d2dSAviad Krawczyk enum hinic_pf_action { 191c4d06d2dSAviad Krawczyk HINIC_PF_MGMT_INIT = 0x0, 192c4d06d2dSAviad Krawczyk 193c4d06d2dSAviad Krawczyk HINIC_PF_MGMT_ACTIVE = 0x11, 194c4d06d2dSAviad Krawczyk }; 195c4d06d2dSAviad Krawczyk 196e2585ea7SAviad Krawczyk enum hinic_outbound_state { 197e2585ea7SAviad Krawczyk HINIC_OUTBOUND_ENABLE = 0, 198e2585ea7SAviad Krawczyk HINIC_OUTBOUND_DISABLE = 1, 199e2585ea7SAviad Krawczyk }; 200e2585ea7SAviad Krawczyk 201e2585ea7SAviad Krawczyk enum hinic_db_state { 202e2585ea7SAviad Krawczyk HINIC_DB_ENABLE = 0, 203e2585ea7SAviad Krawczyk HINIC_DB_DISABLE = 1, 204e2585ea7SAviad Krawczyk }; 205e2585ea7SAviad Krawczyk 206905b464aSXue Chaojing enum hinic_msix_state { 207905b464aSXue Chaojing HINIC_MSIX_ENABLE, 208905b464aSXue Chaojing HINIC_MSIX_DISABLE, 209905b464aSXue Chaojing }; 210905b464aSXue Chaojing 21151ba902aSAviad Krawczyk struct hinic_func_attr { 21251ba902aSAviad Krawczyk u16 func_idx; 21351ba902aSAviad Krawczyk u8 pf_idx; 21451ba902aSAviad Krawczyk u8 pci_intf_idx; 21551ba902aSAviad Krawczyk 21651ba902aSAviad Krawczyk enum hinic_func_type func_type; 21751ba902aSAviad Krawczyk 21851ba902aSAviad Krawczyk u8 ppf_idx; 21951ba902aSAviad Krawczyk 22051ba902aSAviad Krawczyk u16 num_irqs; 22151ba902aSAviad Krawczyk u8 num_aeqs; 22251ba902aSAviad Krawczyk u8 num_ceqs; 22351ba902aSAviad Krawczyk 22451ba902aSAviad Krawczyk u8 num_dma_attr; 22551ba902aSAviad Krawczyk }; 22651ba902aSAviad Krawczyk 22751ba902aSAviad Krawczyk struct hinic_hwif { 22851ba902aSAviad Krawczyk struct pci_dev *pdev; 22951ba902aSAviad Krawczyk void __iomem *cfg_regs_bar; 230905b464aSXue Chaojing void __iomem *intr_regs_base; 23151ba902aSAviad Krawczyk 23251ba902aSAviad Krawczyk struct hinic_func_attr attr; 23351ba902aSAviad Krawczyk }; 23451ba902aSAviad Krawczyk 23551ba902aSAviad Krawczyk static inline u32 hinic_hwif_read_reg(struct hinic_hwif *hwif, u32 reg) 23651ba902aSAviad Krawczyk { 23751ba902aSAviad Krawczyk return be32_to_cpu(readl(hwif->cfg_regs_bar + reg)); 23851ba902aSAviad Krawczyk } 23951ba902aSAviad Krawczyk 24051ba902aSAviad Krawczyk static inline void hinic_hwif_write_reg(struct hinic_hwif *hwif, u32 reg, 24151ba902aSAviad Krawczyk u32 val) 24251ba902aSAviad Krawczyk { 24351ba902aSAviad Krawczyk writel(cpu_to_be32(val), hwif->cfg_regs_bar + reg); 24451ba902aSAviad Krawczyk } 24551ba902aSAviad Krawczyk 246f00fe738SAviad Krawczyk int hinic_msix_attr_set(struct hinic_hwif *hwif, u16 msix_index, 247f00fe738SAviad Krawczyk u8 pending_limit, u8 coalesc_timer, 248f00fe738SAviad Krawczyk u8 lli_timer_cfg, u8 lli_credit_limit, 249f00fe738SAviad Krawczyk u8 resend_timer); 250f00fe738SAviad Krawczyk 251f00fe738SAviad Krawczyk int hinic_msix_attr_get(struct hinic_hwif *hwif, u16 msix_index, 252f00fe738SAviad Krawczyk u8 *pending_limit, u8 *coalesc_timer_cfg, 253f00fe738SAviad Krawczyk u8 *lli_timer, u8 *lli_credit_limit, 254f00fe738SAviad Krawczyk u8 *resend_timer); 255f00fe738SAviad Krawczyk 256905b464aSXue Chaojing void hinic_set_msix_state(struct hinic_hwif *hwif, u16 msix_idx, 257905b464aSXue Chaojing enum hinic_msix_state flag); 258905b464aSXue Chaojing 259f00fe738SAviad Krawczyk int hinic_msix_attr_cnt_clear(struct hinic_hwif *hwif, u16 msix_index); 260f00fe738SAviad Krawczyk 261c4d06d2dSAviad Krawczyk void hinic_set_pf_action(struct hinic_hwif *hwif, enum hinic_pf_action action); 262c4d06d2dSAviad Krawczyk 263e2585ea7SAviad Krawczyk enum hinic_outbound_state hinic_outbound_state_get(struct hinic_hwif *hwif); 264e2585ea7SAviad Krawczyk 265e2585ea7SAviad Krawczyk void hinic_outbound_state_set(struct hinic_hwif *hwif, 266e2585ea7SAviad Krawczyk enum hinic_outbound_state outbound_state); 267e2585ea7SAviad Krawczyk 268e2585ea7SAviad Krawczyk enum hinic_db_state hinic_db_state_get(struct hinic_hwif *hwif); 269e2585ea7SAviad Krawczyk 270e2585ea7SAviad Krawczyk void hinic_db_state_set(struct hinic_hwif *hwif, 271e2585ea7SAviad Krawczyk enum hinic_db_state db_state); 272e2585ea7SAviad Krawczyk 27351ba902aSAviad Krawczyk int hinic_init_hwif(struct hinic_hwif *hwif, struct pci_dev *pdev); 27451ba902aSAviad Krawczyk 27551ba902aSAviad Krawczyk void hinic_free_hwif(struct hinic_hwif *hwif); 27651ba902aSAviad Krawczyk 27751ba902aSAviad Krawczyk #endif 278