12025cf9eSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */
251ba902aSAviad Krawczyk /*
351ba902aSAviad Krawczyk * Huawei HiNIC PCI Express Linux driver
451ba902aSAviad Krawczyk * Copyright(c) 2017 Huawei Technologies Co., Ltd
551ba902aSAviad Krawczyk */
651ba902aSAviad Krawczyk
751ba902aSAviad Krawczyk #ifndef HINIC_HW_IF_H
851ba902aSAviad Krawczyk #define HINIC_HW_IF_H
951ba902aSAviad Krawczyk
1051ba902aSAviad Krawczyk #include <linux/pci.h>
1151ba902aSAviad Krawczyk #include <linux/io.h>
1251ba902aSAviad Krawczyk #include <linux/types.h>
1351ba902aSAviad Krawczyk #include <asm/byteorder.h>
1451ba902aSAviad Krawczyk
15*90f86b8aSLuo bin #define HINIC_PCIE_LINK_DOWN 0xFFFFFFFF
16*90f86b8aSLuo bin
1751ba902aSAviad Krawczyk #define HINIC_DMA_ATTR_ST_SHIFT 0
1851ba902aSAviad Krawczyk #define HINIC_DMA_ATTR_AT_SHIFT 8
1951ba902aSAviad Krawczyk #define HINIC_DMA_ATTR_PH_SHIFT 10
2051ba902aSAviad Krawczyk #define HINIC_DMA_ATTR_NO_SNOOPING_SHIFT 12
2151ba902aSAviad Krawczyk #define HINIC_DMA_ATTR_TPH_EN_SHIFT 13
2251ba902aSAviad Krawczyk
2351ba902aSAviad Krawczyk #define HINIC_DMA_ATTR_ST_MASK 0xFF
2451ba902aSAviad Krawczyk #define HINIC_DMA_ATTR_AT_MASK 0x3
2551ba902aSAviad Krawczyk #define HINIC_DMA_ATTR_PH_MASK 0x3
2651ba902aSAviad Krawczyk #define HINIC_DMA_ATTR_NO_SNOOPING_MASK 0x1
2751ba902aSAviad Krawczyk #define HINIC_DMA_ATTR_TPH_EN_MASK 0x1
2851ba902aSAviad Krawczyk
2951ba902aSAviad Krawczyk #define HINIC_DMA_ATTR_SET(val, member) \
3051ba902aSAviad Krawczyk (((u32)(val) & HINIC_DMA_ATTR_##member##_MASK) << \
3151ba902aSAviad Krawczyk HINIC_DMA_ATTR_##member##_SHIFT)
3251ba902aSAviad Krawczyk
3351ba902aSAviad Krawczyk #define HINIC_DMA_ATTR_CLEAR(val, member) \
3451ba902aSAviad Krawczyk ((val) & (~(HINIC_DMA_ATTR_##member##_MASK \
3551ba902aSAviad Krawczyk << HINIC_DMA_ATTR_##member##_SHIFT)))
3651ba902aSAviad Krawczyk
3751ba902aSAviad Krawczyk #define HINIC_FA0_FUNC_IDX_SHIFT 0
3851ba902aSAviad Krawczyk #define HINIC_FA0_PF_IDX_SHIFT 10
3951ba902aSAviad Krawczyk #define HINIC_FA0_PCI_INTF_IDX_SHIFT 14
40a425b6e1SLuo bin #define HINIC_FA0_VF_IN_PF_SHIFT 16
4151ba902aSAviad Krawczyk /* reserved members - off 16 */
4251ba902aSAviad Krawczyk #define HINIC_FA0_FUNC_TYPE_SHIFT 24
4351ba902aSAviad Krawczyk
4451ba902aSAviad Krawczyk #define HINIC_FA0_FUNC_IDX_MASK 0x3FF
4551ba902aSAviad Krawczyk #define HINIC_FA0_PF_IDX_MASK 0xF
4651ba902aSAviad Krawczyk #define HINIC_FA0_PCI_INTF_IDX_MASK 0x3
4751ba902aSAviad Krawczyk #define HINIC_FA0_FUNC_TYPE_MASK 0x1
48a425b6e1SLuo bin #define HINIC_FA0_VF_IN_PF_MASK 0xFF
4951ba902aSAviad Krawczyk
5051ba902aSAviad Krawczyk #define HINIC_FA0_GET(val, member) \
5151ba902aSAviad Krawczyk (((val) >> HINIC_FA0_##member##_SHIFT) & HINIC_FA0_##member##_MASK)
5251ba902aSAviad Krawczyk
5351ba902aSAviad Krawczyk #define HINIC_FA1_AEQS_PER_FUNC_SHIFT 8
5451ba902aSAviad Krawczyk /* reserved members - off 10 */
5551ba902aSAviad Krawczyk #define HINIC_FA1_CEQS_PER_FUNC_SHIFT 12
5651ba902aSAviad Krawczyk /* reserved members - off 15 */
5751ba902aSAviad Krawczyk #define HINIC_FA1_IRQS_PER_FUNC_SHIFT 20
5851ba902aSAviad Krawczyk #define HINIC_FA1_DMA_ATTR_PER_FUNC_SHIFT 24
5951ba902aSAviad Krawczyk /* reserved members - off 27 */
6072ef908bSLuo bin #define HINIC_FA1_MGMT_INIT_STATUS_SHIFT 30
6172ef908bSLuo bin #define HINIC_FA1_PF_INIT_STATUS_SHIFT 31
6251ba902aSAviad Krawczyk
6351ba902aSAviad Krawczyk #define HINIC_FA1_AEQS_PER_FUNC_MASK 0x3
6451ba902aSAviad Krawczyk #define HINIC_FA1_CEQS_PER_FUNC_MASK 0x7
6551ba902aSAviad Krawczyk #define HINIC_FA1_IRQS_PER_FUNC_MASK 0xF
6651ba902aSAviad Krawczyk #define HINIC_FA1_DMA_ATTR_PER_FUNC_MASK 0x7
6772ef908bSLuo bin #define HINIC_FA1_MGMT_INIT_STATUS_MASK 0x1
6872ef908bSLuo bin #define HINIC_FA1_PF_INIT_STATUS_MASK 0x1
6951ba902aSAviad Krawczyk
7051ba902aSAviad Krawczyk #define HINIC_FA1_GET(val, member) \
7151ba902aSAviad Krawczyk (((val) >> HINIC_FA1_##member##_SHIFT) & HINIC_FA1_##member##_MASK)
7251ba902aSAviad Krawczyk
73a425b6e1SLuo bin #define HINIC_FA2_GLOBAL_VF_ID_OF_PF_SHIFT 16
74a425b6e1SLuo bin #define HINIC_FA2_GLOBAL_VF_ID_OF_PF_MASK 0x3FF
75a425b6e1SLuo bin
76a425b6e1SLuo bin #define HINIC_FA2_GET(val, member) \
77a425b6e1SLuo bin (((val) >> HINIC_FA2_##member##_SHIFT) & HINIC_FA2_##member##_MASK)
78a425b6e1SLuo bin
79e2585ea7SAviad Krawczyk #define HINIC_FA4_OUTBOUND_STATE_SHIFT 0
80e2585ea7SAviad Krawczyk #define HINIC_FA4_DB_STATE_SHIFT 1
81e2585ea7SAviad Krawczyk
82e2585ea7SAviad Krawczyk #define HINIC_FA4_OUTBOUND_STATE_MASK 0x1
83e2585ea7SAviad Krawczyk #define HINIC_FA4_DB_STATE_MASK 0x1
84e2585ea7SAviad Krawczyk
85e2585ea7SAviad Krawczyk #define HINIC_FA4_GET(val, member) \
86e2585ea7SAviad Krawczyk (((val) >> HINIC_FA4_##member##_SHIFT) & HINIC_FA4_##member##_MASK)
87e2585ea7SAviad Krawczyk
88e2585ea7SAviad Krawczyk #define HINIC_FA4_SET(val, member) \
89e2585ea7SAviad Krawczyk ((((u32)val) & HINIC_FA4_##member##_MASK) << HINIC_FA4_##member##_SHIFT)
90e2585ea7SAviad Krawczyk
91e2585ea7SAviad Krawczyk #define HINIC_FA4_CLEAR(val, member) \
92e2585ea7SAviad Krawczyk ((val) & (~(HINIC_FA4_##member##_MASK << HINIC_FA4_##member##_SHIFT)))
93e2585ea7SAviad Krawczyk
94c4d06d2dSAviad Krawczyk #define HINIC_FA5_PF_ACTION_SHIFT 0
95c4d06d2dSAviad Krawczyk #define HINIC_FA5_PF_ACTION_MASK 0xFFFF
96c4d06d2dSAviad Krawczyk
97c4d06d2dSAviad Krawczyk #define HINIC_FA5_SET(val, member) \
98c4d06d2dSAviad Krawczyk (((u32)(val) & HINIC_FA5_##member##_MASK) << HINIC_FA5_##member##_SHIFT)
99c4d06d2dSAviad Krawczyk
100c4d06d2dSAviad Krawczyk #define HINIC_FA5_CLEAR(val, member) \
101c4d06d2dSAviad Krawczyk ((val) & (~(HINIC_FA5_##member##_MASK << HINIC_FA5_##member##_SHIFT)))
102c4d06d2dSAviad Krawczyk
10351ba902aSAviad Krawczyk #define HINIC_PPF_ELECTION_IDX_SHIFT 0
10451ba902aSAviad Krawczyk #define HINIC_PPF_ELECTION_IDX_MASK 0x1F
10551ba902aSAviad Krawczyk
10651ba902aSAviad Krawczyk #define HINIC_PPF_ELECTION_SET(val, member) \
10751ba902aSAviad Krawczyk (((u32)(val) & HINIC_PPF_ELECTION_##member##_MASK) << \
10851ba902aSAviad Krawczyk HINIC_PPF_ELECTION_##member##_SHIFT)
10951ba902aSAviad Krawczyk
11051ba902aSAviad Krawczyk #define HINIC_PPF_ELECTION_GET(val, member) \
11151ba902aSAviad Krawczyk (((val) >> HINIC_PPF_ELECTION_##member##_SHIFT) & \
11251ba902aSAviad Krawczyk HINIC_PPF_ELECTION_##member##_MASK)
11351ba902aSAviad Krawczyk
11451ba902aSAviad Krawczyk #define HINIC_PPF_ELECTION_CLEAR(val, member) \
11551ba902aSAviad Krawczyk ((val) & (~(HINIC_PPF_ELECTION_##member##_MASK \
11651ba902aSAviad Krawczyk << HINIC_PPF_ELECTION_##member##_SHIFT)))
11751ba902aSAviad Krawczyk
118f00fe738SAviad Krawczyk #define HINIC_MSIX_PENDING_LIMIT_SHIFT 0
119f00fe738SAviad Krawczyk #define HINIC_MSIX_COALESC_TIMER_SHIFT 8
120f00fe738SAviad Krawczyk #define HINIC_MSIX_LLI_TIMER_SHIFT 16
121f00fe738SAviad Krawczyk #define HINIC_MSIX_LLI_CREDIT_SHIFT 24
122f00fe738SAviad Krawczyk #define HINIC_MSIX_RESEND_TIMER_SHIFT 29
123f00fe738SAviad Krawczyk
124f00fe738SAviad Krawczyk #define HINIC_MSIX_PENDING_LIMIT_MASK 0xFF
125f00fe738SAviad Krawczyk #define HINIC_MSIX_COALESC_TIMER_MASK 0xFF
126f00fe738SAviad Krawczyk #define HINIC_MSIX_LLI_TIMER_MASK 0xFF
127f00fe738SAviad Krawczyk #define HINIC_MSIX_LLI_CREDIT_MASK 0x1F
128f00fe738SAviad Krawczyk #define HINIC_MSIX_RESEND_TIMER_MASK 0x7
129f00fe738SAviad Krawczyk
130f00fe738SAviad Krawczyk #define HINIC_MSIX_ATTR_SET(val, member) \
131f00fe738SAviad Krawczyk (((u32)(val) & HINIC_MSIX_##member##_MASK) << \
132f00fe738SAviad Krawczyk HINIC_MSIX_##member##_SHIFT)
133f00fe738SAviad Krawczyk
134f00fe738SAviad Krawczyk #define HINIC_MSIX_CNT_RESEND_TIMER_SHIFT 29
135f00fe738SAviad Krawczyk
136f00fe738SAviad Krawczyk #define HINIC_MSIX_CNT_RESEND_TIMER_MASK 0x1
137f00fe738SAviad Krawczyk
138f00fe738SAviad Krawczyk #define HINIC_MSIX_CNT_SET(val, member) \
139f00fe738SAviad Krawczyk (((u32)(val) & HINIC_MSIX_CNT_##member##_MASK) << \
140f00fe738SAviad Krawczyk HINIC_MSIX_CNT_##member##_SHIFT)
141f00fe738SAviad Krawczyk
14251ba902aSAviad Krawczyk #define HINIC_HWIF_NUM_AEQS(hwif) ((hwif)->attr.num_aeqs)
14351ba902aSAviad Krawczyk #define HINIC_HWIF_NUM_CEQS(hwif) ((hwif)->attr.num_ceqs)
14451ba902aSAviad Krawczyk #define HINIC_HWIF_NUM_IRQS(hwif) ((hwif)->attr.num_irqs)
14551ba902aSAviad Krawczyk #define HINIC_HWIF_FUNC_IDX(hwif) ((hwif)->attr.func_idx)
14651ba902aSAviad Krawczyk #define HINIC_HWIF_PCI_INTF(hwif) ((hwif)->attr.pci_intf_idx)
1476dd8b682SAviad Krawczyk #define HINIC_HWIF_PF_IDX(hwif) ((hwif)->attr.pf_idx)
148d2ed69ceSLuo bin #define HINIC_HWIF_PPF_IDX(hwif) ((hwif)->attr.ppf_idx)
14951ba902aSAviad Krawczyk
15051ba902aSAviad Krawczyk #define HINIC_FUNC_TYPE(hwif) ((hwif)->attr.func_type)
151a425b6e1SLuo bin #define HINIC_IS_VF(hwif) (HINIC_FUNC_TYPE(hwif) == HINIC_VF)
15251ba902aSAviad Krawczyk #define HINIC_IS_PF(hwif) (HINIC_FUNC_TYPE(hwif) == HINIC_PF)
15351ba902aSAviad Krawczyk #define HINIC_IS_PPF(hwif) (HINIC_FUNC_TYPE(hwif) == HINIC_PPF)
15451ba902aSAviad Krawczyk
15551ba902aSAviad Krawczyk #define HINIC_PCI_CFG_REGS_BAR 0
156905b464aSXue Chaojing #define HINIC_PCI_INTR_REGS_BAR 2
157f91090f7SAviad Krawczyk #define HINIC_PCI_DB_BAR 4
15851ba902aSAviad Krawczyk
15951ba902aSAviad Krawczyk #define HINIC_PCIE_ST_DISABLE 0
16051ba902aSAviad Krawczyk #define HINIC_PCIE_AT_DISABLE 0
16151ba902aSAviad Krawczyk #define HINIC_PCIE_PH_DISABLE 0
16251ba902aSAviad Krawczyk
163f00fe738SAviad Krawczyk #define HINIC_EQ_MSIX_PENDING_LIMIT_DEFAULT 0 /* Disabled */
164f00fe738SAviad Krawczyk #define HINIC_EQ_MSIX_COALESC_TIMER_DEFAULT 0xFF /* max */
165f00fe738SAviad Krawczyk #define HINIC_EQ_MSIX_LLI_TIMER_DEFAULT 0 /* Disabled */
166f00fe738SAviad Krawczyk #define HINIC_EQ_MSIX_LLI_CREDIT_LIMIT_DEFAULT 0 /* Disabled */
167f00fe738SAviad Krawczyk #define HINIC_EQ_MSIX_RESEND_TIMER_DEFAULT 7 /* max */
168f00fe738SAviad Krawczyk
169905b464aSXue Chaojing #define HINIC_PCI_MSIX_ENTRY_SIZE 16
170905b464aSXue Chaojing #define HINIC_PCI_MSIX_ENTRY_VECTOR_CTRL 12
171905b464aSXue Chaojing #define HINIC_PCI_MSIX_ENTRY_CTRL_MASKBIT 1
172905b464aSXue Chaojing
17351ba902aSAviad Krawczyk enum hinic_pcie_nosnoop {
17451ba902aSAviad Krawczyk HINIC_PCIE_SNOOP = 0,
17551ba902aSAviad Krawczyk HINIC_PCIE_NO_SNOOP = 1,
17651ba902aSAviad Krawczyk };
17751ba902aSAviad Krawczyk
17851ba902aSAviad Krawczyk enum hinic_pcie_tph {
17951ba902aSAviad Krawczyk HINIC_PCIE_TPH_DISABLE = 0,
18051ba902aSAviad Krawczyk HINIC_PCIE_TPH_ENABLE = 1,
18151ba902aSAviad Krawczyk };
18251ba902aSAviad Krawczyk
18351ba902aSAviad Krawczyk enum hinic_func_type {
18451ba902aSAviad Krawczyk HINIC_PF = 0,
185a425b6e1SLuo bin HINIC_VF = 1,
18651ba902aSAviad Krawczyk HINIC_PPF = 2,
18751ba902aSAviad Krawczyk };
18851ba902aSAviad Krawczyk
189a5564e7eSAviad Krawczyk enum hinic_mod_type {
190a5564e7eSAviad Krawczyk HINIC_MOD_COMM = 0, /* HW communication module */
191a5564e7eSAviad Krawczyk HINIC_MOD_L2NIC = 1, /* L2NIC module */
192a5564e7eSAviad Krawczyk HINIC_MOD_CFGM = 7, /* Configuration module */
19301f2b3daSLuo bin HINIC_MOD_HILINK = 14, /* Hilink module */
194a5564e7eSAviad Krawczyk HINIC_MOD_MAX = 15
195a5564e7eSAviad Krawczyk };
196a5564e7eSAviad Krawczyk
1976dd8b682SAviad Krawczyk enum hinic_node_id {
1986dd8b682SAviad Krawczyk HINIC_NODE_ID_MGMT = 21,
1996dd8b682SAviad Krawczyk };
2006dd8b682SAviad Krawczyk
201c4d06d2dSAviad Krawczyk enum hinic_pf_action {
202c4d06d2dSAviad Krawczyk HINIC_PF_MGMT_INIT = 0x0,
203c4d06d2dSAviad Krawczyk
204c4d06d2dSAviad Krawczyk HINIC_PF_MGMT_ACTIVE = 0x11,
205c4d06d2dSAviad Krawczyk };
206c4d06d2dSAviad Krawczyk
207e2585ea7SAviad Krawczyk enum hinic_outbound_state {
208e2585ea7SAviad Krawczyk HINIC_OUTBOUND_ENABLE = 0,
209e2585ea7SAviad Krawczyk HINIC_OUTBOUND_DISABLE = 1,
210e2585ea7SAviad Krawczyk };
211e2585ea7SAviad Krawczyk
212e2585ea7SAviad Krawczyk enum hinic_db_state {
213e2585ea7SAviad Krawczyk HINIC_DB_ENABLE = 0,
214e2585ea7SAviad Krawczyk HINIC_DB_DISABLE = 1,
215e2585ea7SAviad Krawczyk };
216e2585ea7SAviad Krawczyk
217905b464aSXue Chaojing enum hinic_msix_state {
218905b464aSXue Chaojing HINIC_MSIX_ENABLE,
219905b464aSXue Chaojing HINIC_MSIX_DISABLE,
220905b464aSXue Chaojing };
221905b464aSXue Chaojing
22251ba902aSAviad Krawczyk struct hinic_func_attr {
22351ba902aSAviad Krawczyk u16 func_idx;
22451ba902aSAviad Krawczyk u8 pf_idx;
22551ba902aSAviad Krawczyk u8 pci_intf_idx;
22651ba902aSAviad Krawczyk
22751ba902aSAviad Krawczyk enum hinic_func_type func_type;
22851ba902aSAviad Krawczyk
22951ba902aSAviad Krawczyk u8 ppf_idx;
23051ba902aSAviad Krawczyk
23151ba902aSAviad Krawczyk u16 num_irqs;
23251ba902aSAviad Krawczyk u8 num_aeqs;
23351ba902aSAviad Krawczyk u8 num_ceqs;
23451ba902aSAviad Krawczyk
23551ba902aSAviad Krawczyk u8 num_dma_attr;
236a425b6e1SLuo bin
237a425b6e1SLuo bin u16 global_vf_id_of_pf;
23851ba902aSAviad Krawczyk };
23951ba902aSAviad Krawczyk
24051ba902aSAviad Krawczyk struct hinic_hwif {
24151ba902aSAviad Krawczyk struct pci_dev *pdev;
24251ba902aSAviad Krawczyk void __iomem *cfg_regs_bar;
243905b464aSXue Chaojing void __iomem *intr_regs_base;
24451ba902aSAviad Krawczyk
24551ba902aSAviad Krawczyk struct hinic_func_attr attr;
24651ba902aSAviad Krawczyk };
24751ba902aSAviad Krawczyk
hinic_hwif_read_reg(struct hinic_hwif * hwif,u32 reg)24851ba902aSAviad Krawczyk static inline u32 hinic_hwif_read_reg(struct hinic_hwif *hwif, u32 reg)
24951ba902aSAviad Krawczyk {
250*90f86b8aSLuo bin u32 out = readl(hwif->cfg_regs_bar + reg);
251*90f86b8aSLuo bin
252*90f86b8aSLuo bin return be32_to_cpu(*(__be32 *)&out);
25351ba902aSAviad Krawczyk }
25451ba902aSAviad Krawczyk
hinic_hwif_write_reg(struct hinic_hwif * hwif,u32 reg,u32 val)25551ba902aSAviad Krawczyk static inline void hinic_hwif_write_reg(struct hinic_hwif *hwif, u32 reg,
25651ba902aSAviad Krawczyk u32 val)
25751ba902aSAviad Krawczyk {
258*90f86b8aSLuo bin __be32 in = cpu_to_be32(val);
259*90f86b8aSLuo bin
260*90f86b8aSLuo bin writel(*(u32 *)&in, hwif->cfg_regs_bar + reg);
26151ba902aSAviad Krawczyk }
26251ba902aSAviad Krawczyk
263f00fe738SAviad Krawczyk int hinic_msix_attr_set(struct hinic_hwif *hwif, u16 msix_index,
264f00fe738SAviad Krawczyk u8 pending_limit, u8 coalesc_timer,
265f00fe738SAviad Krawczyk u8 lli_timer_cfg, u8 lli_credit_limit,
266f00fe738SAviad Krawczyk u8 resend_timer);
267f00fe738SAviad Krawczyk
268905b464aSXue Chaojing void hinic_set_msix_state(struct hinic_hwif *hwif, u16 msix_idx,
269905b464aSXue Chaojing enum hinic_msix_state flag);
270905b464aSXue Chaojing
271f00fe738SAviad Krawczyk int hinic_msix_attr_cnt_clear(struct hinic_hwif *hwif, u16 msix_index);
272f00fe738SAviad Krawczyk
273c4d06d2dSAviad Krawczyk void hinic_set_pf_action(struct hinic_hwif *hwif, enum hinic_pf_action action);
274c4d06d2dSAviad Krawczyk
275e2585ea7SAviad Krawczyk enum hinic_outbound_state hinic_outbound_state_get(struct hinic_hwif *hwif);
276e2585ea7SAviad Krawczyk
277e2585ea7SAviad Krawczyk void hinic_outbound_state_set(struct hinic_hwif *hwif,
278e2585ea7SAviad Krawczyk enum hinic_outbound_state outbound_state);
279e2585ea7SAviad Krawczyk
280e2585ea7SAviad Krawczyk enum hinic_db_state hinic_db_state_get(struct hinic_hwif *hwif);
281e2585ea7SAviad Krawczyk
282e2585ea7SAviad Krawczyk void hinic_db_state_set(struct hinic_hwif *hwif,
283e2585ea7SAviad Krawczyk enum hinic_db_state db_state);
284e2585ea7SAviad Krawczyk
285a425b6e1SLuo bin u16 hinic_glb_pf_vf_offset(struct hinic_hwif *hwif);
286a425b6e1SLuo bin
287a425b6e1SLuo bin u16 hinic_global_func_id_hw(struct hinic_hwif *hwif);
288a425b6e1SLuo bin
289a425b6e1SLuo bin u16 hinic_pf_id_of_vf_hw(struct hinic_hwif *hwif);
290a425b6e1SLuo bin
29151ba902aSAviad Krawczyk int hinic_init_hwif(struct hinic_hwif *hwif, struct pci_dev *pdev);
29251ba902aSAviad Krawczyk
29351ba902aSAviad Krawczyk void hinic_free_hwif(struct hinic_hwif *hwif);
29451ba902aSAviad Krawczyk
29551ba902aSAviad Krawczyk #endif
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