1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Huawei HiNIC PCI Express Linux driver 4 * Copyright(c) 2017 Huawei Technologies Co., Ltd 5 */ 6 7 #include <linux/pci.h> 8 #include <linux/device.h> 9 #include <linux/errno.h> 10 #include <linux/io.h> 11 #include <linux/types.h> 12 #include <linux/bitops.h> 13 14 #include "hinic_hw_csr.h" 15 #include "hinic_hw_if.h" 16 17 #define PCIE_ATTR_ENTRY 0 18 19 #define VALID_MSIX_IDX(attr, msix_index) ((msix_index) < (attr)->num_irqs) 20 21 /** 22 * hinic_msix_attr_set - set message attribute for msix entry 23 * @hwif: the HW interface of a pci function device 24 * @msix_index: msix_index 25 * @pending_limit: the maximum pending interrupt events (unit 8) 26 * @coalesc_timer: coalesc period for interrupt (unit 8 us) 27 * @lli_timer: replenishing period for low latency credit (unit 8 us) 28 * @lli_credit_limit: maximum credits for low latency msix messages (unit 8) 29 * @resend_timer: maximum wait for resending msix (unit coalesc period) 30 * 31 * Return 0 - Success, negative - Failure 32 **/ 33 int hinic_msix_attr_set(struct hinic_hwif *hwif, u16 msix_index, 34 u8 pending_limit, u8 coalesc_timer, 35 u8 lli_timer, u8 lli_credit_limit, 36 u8 resend_timer) 37 { 38 u32 msix_ctrl, addr; 39 40 if (!VALID_MSIX_IDX(&hwif->attr, msix_index)) 41 return -EINVAL; 42 43 msix_ctrl = HINIC_MSIX_ATTR_SET(pending_limit, PENDING_LIMIT) | 44 HINIC_MSIX_ATTR_SET(coalesc_timer, COALESC_TIMER) | 45 HINIC_MSIX_ATTR_SET(lli_timer, LLI_TIMER) | 46 HINIC_MSIX_ATTR_SET(lli_credit_limit, LLI_CREDIT) | 47 HINIC_MSIX_ATTR_SET(resend_timer, RESEND_TIMER); 48 49 addr = HINIC_CSR_MSIX_CTRL_ADDR(msix_index); 50 51 hinic_hwif_write_reg(hwif, addr, msix_ctrl); 52 return 0; 53 } 54 55 /** 56 * hinic_msix_attr_get - get message attribute of msix entry 57 * @hwif: the HW interface of a pci function device 58 * @msix_index: msix_index 59 * @pending_limit: the maximum pending interrupt events (unit 8) 60 * @coalesc_timer: coalesc period for interrupt (unit 8 us) 61 * @lli_timer: replenishing period for low latency credit (unit 8 us) 62 * @lli_credit_limit: maximum credits for low latency msix messages (unit 8) 63 * @resend_timer: maximum wait for resending msix (unit coalesc period) 64 * 65 * Return 0 - Success, negative - Failure 66 **/ 67 int hinic_msix_attr_get(struct hinic_hwif *hwif, u16 msix_index, 68 u8 *pending_limit, u8 *coalesc_timer, 69 u8 *lli_timer, u8 *lli_credit_limit, 70 u8 *resend_timer) 71 { 72 u32 addr, val; 73 74 if (!VALID_MSIX_IDX(&hwif->attr, msix_index)) 75 return -EINVAL; 76 77 addr = HINIC_CSR_MSIX_CTRL_ADDR(msix_index); 78 val = hinic_hwif_read_reg(hwif, addr); 79 80 *pending_limit = HINIC_MSIX_ATTR_GET(val, PENDING_LIMIT); 81 *coalesc_timer = HINIC_MSIX_ATTR_GET(val, COALESC_TIMER); 82 *lli_timer = HINIC_MSIX_ATTR_GET(val, LLI_TIMER); 83 *lli_credit_limit = HINIC_MSIX_ATTR_GET(val, LLI_CREDIT); 84 *resend_timer = HINIC_MSIX_ATTR_GET(val, RESEND_TIMER); 85 return 0; 86 } 87 88 /** 89 * hinic_msix_attr_cnt_clear - clear message attribute counters for msix entry 90 * @hwif: the HW interface of a pci function device 91 * @msix_index: msix_index 92 * 93 * Return 0 - Success, negative - Failure 94 **/ 95 int hinic_msix_attr_cnt_clear(struct hinic_hwif *hwif, u16 msix_index) 96 { 97 u32 msix_ctrl, addr; 98 99 if (!VALID_MSIX_IDX(&hwif->attr, msix_index)) 100 return -EINVAL; 101 102 msix_ctrl = HINIC_MSIX_CNT_SET(1, RESEND_TIMER); 103 addr = HINIC_CSR_MSIX_CNT_ADDR(msix_index); 104 105 hinic_hwif_write_reg(hwif, addr, msix_ctrl); 106 return 0; 107 } 108 109 /** 110 * hinic_set_pf_action - set action on pf channel 111 * @hwif: the HW interface of a pci function device 112 * @action: action on pf channel 113 * 114 * Return 0 - Success, negative - Failure 115 **/ 116 void hinic_set_pf_action(struct hinic_hwif *hwif, enum hinic_pf_action action) 117 { 118 u32 attr5 = hinic_hwif_read_reg(hwif, HINIC_CSR_FUNC_ATTR5_ADDR); 119 120 attr5 = HINIC_FA5_CLEAR(attr5, PF_ACTION); 121 attr5 |= HINIC_FA5_SET(action, PF_ACTION); 122 123 hinic_hwif_write_reg(hwif, HINIC_CSR_FUNC_ATTR5_ADDR, attr5); 124 } 125 126 enum hinic_outbound_state hinic_outbound_state_get(struct hinic_hwif *hwif) 127 { 128 u32 attr4 = hinic_hwif_read_reg(hwif, HINIC_CSR_FUNC_ATTR4_ADDR); 129 130 return HINIC_FA4_GET(attr4, OUTBOUND_STATE); 131 } 132 133 void hinic_outbound_state_set(struct hinic_hwif *hwif, 134 enum hinic_outbound_state outbound_state) 135 { 136 u32 attr4 = hinic_hwif_read_reg(hwif, HINIC_CSR_FUNC_ATTR4_ADDR); 137 138 attr4 = HINIC_FA4_CLEAR(attr4, OUTBOUND_STATE); 139 attr4 |= HINIC_FA4_SET(outbound_state, OUTBOUND_STATE); 140 141 hinic_hwif_write_reg(hwif, HINIC_CSR_FUNC_ATTR4_ADDR, attr4); 142 } 143 144 enum hinic_db_state hinic_db_state_get(struct hinic_hwif *hwif) 145 { 146 u32 attr4 = hinic_hwif_read_reg(hwif, HINIC_CSR_FUNC_ATTR4_ADDR); 147 148 return HINIC_FA4_GET(attr4, DB_STATE); 149 } 150 151 void hinic_db_state_set(struct hinic_hwif *hwif, 152 enum hinic_db_state db_state) 153 { 154 u32 attr4 = hinic_hwif_read_reg(hwif, HINIC_CSR_FUNC_ATTR4_ADDR); 155 156 attr4 = HINIC_FA4_CLEAR(attr4, DB_STATE); 157 attr4 |= HINIC_FA4_SET(db_state, DB_STATE); 158 159 hinic_hwif_write_reg(hwif, HINIC_CSR_FUNC_ATTR4_ADDR, attr4); 160 } 161 162 void hinic_set_msix_state(struct hinic_hwif *hwif, u16 msix_idx, 163 enum hinic_msix_state flag) 164 { 165 u32 offset = msix_idx * HINIC_PCI_MSIX_ENTRY_SIZE + 166 HINIC_PCI_MSIX_ENTRY_VECTOR_CTRL; 167 u32 mask_bits; 168 169 mask_bits = readl(hwif->intr_regs_base + offset); 170 mask_bits &= ~HINIC_PCI_MSIX_ENTRY_CTRL_MASKBIT; 171 172 if (flag) 173 mask_bits |= HINIC_PCI_MSIX_ENTRY_CTRL_MASKBIT; 174 175 writel(mask_bits, hwif->intr_regs_base + offset); 176 } 177 178 /** 179 * hwif_ready - test if the HW is ready for use 180 * @hwif: the HW interface of a pci function device 181 * 182 * Return 0 - Success, negative - Failure 183 **/ 184 static int hwif_ready(struct hinic_hwif *hwif) 185 { 186 struct pci_dev *pdev = hwif->pdev; 187 u32 addr, attr1; 188 189 addr = HINIC_CSR_FUNC_ATTR1_ADDR; 190 attr1 = hinic_hwif_read_reg(hwif, addr); 191 192 if (!HINIC_FA1_GET(attr1, INIT_STATUS)) { 193 dev_err(&pdev->dev, "hwif status is not ready\n"); 194 return -EFAULT; 195 } 196 197 return 0; 198 } 199 200 /** 201 * set_hwif_attr - set the attributes in the relevant members in hwif 202 * @hwif: the HW interface of a pci function device 203 * @attr0: the first attribute that was read from the hw 204 * @attr1: the second attribute that was read from the hw 205 **/ 206 static void set_hwif_attr(struct hinic_hwif *hwif, u32 attr0, u32 attr1) 207 { 208 hwif->attr.func_idx = HINIC_FA0_GET(attr0, FUNC_IDX); 209 hwif->attr.pf_idx = HINIC_FA0_GET(attr0, PF_IDX); 210 hwif->attr.pci_intf_idx = HINIC_FA0_GET(attr0, PCI_INTF_IDX); 211 hwif->attr.func_type = HINIC_FA0_GET(attr0, FUNC_TYPE); 212 213 hwif->attr.num_aeqs = BIT(HINIC_FA1_GET(attr1, AEQS_PER_FUNC)); 214 hwif->attr.num_ceqs = BIT(HINIC_FA1_GET(attr1, CEQS_PER_FUNC)); 215 hwif->attr.num_irqs = BIT(HINIC_FA1_GET(attr1, IRQS_PER_FUNC)); 216 hwif->attr.num_dma_attr = BIT(HINIC_FA1_GET(attr1, DMA_ATTR_PER_FUNC)); 217 } 218 219 /** 220 * read_hwif_attr - read the attributes and set members in hwif 221 * @hwif: the HW interface of a pci function device 222 **/ 223 static void read_hwif_attr(struct hinic_hwif *hwif) 224 { 225 u32 addr, attr0, attr1; 226 227 addr = HINIC_CSR_FUNC_ATTR0_ADDR; 228 attr0 = hinic_hwif_read_reg(hwif, addr); 229 230 addr = HINIC_CSR_FUNC_ATTR1_ADDR; 231 attr1 = hinic_hwif_read_reg(hwif, addr); 232 233 set_hwif_attr(hwif, attr0, attr1); 234 } 235 236 /** 237 * set_ppf - try to set hwif as ppf and set the type of hwif in this case 238 * @hwif: the HW interface of a pci function device 239 **/ 240 static void set_ppf(struct hinic_hwif *hwif) 241 { 242 struct hinic_func_attr *attr = &hwif->attr; 243 u32 addr, val, ppf_election; 244 245 /* Read Modify Write */ 246 addr = HINIC_CSR_PPF_ELECTION_ADDR(HINIC_HWIF_PCI_INTF(hwif)); 247 248 val = hinic_hwif_read_reg(hwif, addr); 249 val = HINIC_PPF_ELECTION_CLEAR(val, IDX); 250 251 ppf_election = HINIC_PPF_ELECTION_SET(HINIC_HWIF_FUNC_IDX(hwif), IDX); 252 253 val |= ppf_election; 254 hinic_hwif_write_reg(hwif, addr, val); 255 256 /* check PPF */ 257 val = hinic_hwif_read_reg(hwif, addr); 258 259 attr->ppf_idx = HINIC_PPF_ELECTION_GET(val, IDX); 260 if (attr->ppf_idx == HINIC_HWIF_FUNC_IDX(hwif)) 261 attr->func_type = HINIC_PPF; 262 } 263 264 /** 265 * set_dma_attr - set the dma attributes in the HW 266 * @hwif: the HW interface of a pci function device 267 * @entry_idx: the entry index in the dma table 268 * @st: PCIE TLP steering tag 269 * @at: PCIE TLP AT field 270 * @ph: PCIE TLP Processing Hint field 271 * @no_snooping: PCIE TLP No snooping 272 * @tph_en: PCIE TLP Processing Hint Enable 273 **/ 274 static void set_dma_attr(struct hinic_hwif *hwif, u32 entry_idx, 275 u8 st, u8 at, u8 ph, 276 enum hinic_pcie_nosnoop no_snooping, 277 enum hinic_pcie_tph tph_en) 278 { 279 u32 addr, val, dma_attr_entry; 280 281 /* Read Modify Write */ 282 addr = HINIC_CSR_DMA_ATTR_ADDR(entry_idx); 283 284 val = hinic_hwif_read_reg(hwif, addr); 285 val = HINIC_DMA_ATTR_CLEAR(val, ST) & 286 HINIC_DMA_ATTR_CLEAR(val, AT) & 287 HINIC_DMA_ATTR_CLEAR(val, PH) & 288 HINIC_DMA_ATTR_CLEAR(val, NO_SNOOPING) & 289 HINIC_DMA_ATTR_CLEAR(val, TPH_EN); 290 291 dma_attr_entry = HINIC_DMA_ATTR_SET(st, ST) | 292 HINIC_DMA_ATTR_SET(at, AT) | 293 HINIC_DMA_ATTR_SET(ph, PH) | 294 HINIC_DMA_ATTR_SET(no_snooping, NO_SNOOPING) | 295 HINIC_DMA_ATTR_SET(tph_en, TPH_EN); 296 297 val |= dma_attr_entry; 298 hinic_hwif_write_reg(hwif, addr, val); 299 } 300 301 /** 302 * dma_attr_table_init - initialize the the default dma attributes 303 * @hwif: the HW interface of a pci function device 304 **/ 305 static void dma_attr_init(struct hinic_hwif *hwif) 306 { 307 set_dma_attr(hwif, PCIE_ATTR_ENTRY, HINIC_PCIE_ST_DISABLE, 308 HINIC_PCIE_AT_DISABLE, HINIC_PCIE_PH_DISABLE, 309 HINIC_PCIE_SNOOP, HINIC_PCIE_TPH_DISABLE); 310 } 311 312 /** 313 * hinic_init_hwif - initialize the hw interface 314 * @hwif: the HW interface of a pci function device 315 * @pdev: the pci device for acessing PCI resources 316 * 317 * Return 0 - Success, negative - Failure 318 **/ 319 int hinic_init_hwif(struct hinic_hwif *hwif, struct pci_dev *pdev) 320 { 321 int err; 322 323 hwif->pdev = pdev; 324 325 hwif->cfg_regs_bar = pci_ioremap_bar(pdev, HINIC_PCI_CFG_REGS_BAR); 326 if (!hwif->cfg_regs_bar) { 327 dev_err(&pdev->dev, "Failed to map configuration regs\n"); 328 return -ENOMEM; 329 } 330 331 hwif->intr_regs_base = pci_ioremap_bar(pdev, HINIC_PCI_INTR_REGS_BAR); 332 if (!hwif->intr_regs_base) { 333 dev_err(&pdev->dev, "Failed to map configuration regs\n"); 334 err = -ENOMEM; 335 goto err_map_intr_bar; 336 } 337 338 err = hwif_ready(hwif); 339 if (err) { 340 dev_err(&pdev->dev, "HW interface is not ready\n"); 341 goto err_hwif_ready; 342 } 343 344 read_hwif_attr(hwif); 345 346 if (HINIC_IS_PF(hwif)) 347 set_ppf(hwif); 348 349 /* No transactionss before DMA is initialized */ 350 dma_attr_init(hwif); 351 return 0; 352 353 err_hwif_ready: 354 iounmap(hwif->intr_regs_base); 355 356 err_map_intr_bar: 357 iounmap(hwif->cfg_regs_bar); 358 359 return err; 360 } 361 362 /** 363 * hinic_free_hwif - free the HW interface 364 * @hwif: the HW interface of a pci function device 365 **/ 366 void hinic_free_hwif(struct hinic_hwif *hwif) 367 { 368 iounmap(hwif->intr_regs_base); 369 iounmap(hwif->cfg_regs_bar); 370 } 371