1 /* 2 * Huawei HiNIC PCI Express Linux driver 3 * Copyright(c) 2017 Huawei Technologies Co., Ltd 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * for more details. 13 * 14 */ 15 16 #ifndef HINIC_HW_DEV_H 17 #define HINIC_HW_DEV_H 18 19 #include <linux/pci.h> 20 #include <linux/types.h> 21 #include <linux/bitops.h> 22 23 #include "hinic_hw_if.h" 24 #include "hinic_hw_eqs.h" 25 #include "hinic_hw_mgmt.h" 26 #include "hinic_hw_qp.h" 27 #include "hinic_hw_io.h" 28 29 #define HINIC_MAX_QPS 32 30 31 #define HINIC_MGMT_NUM_MSG_CMD (HINIC_MGMT_MSG_CMD_MAX - \ 32 HINIC_MGMT_MSG_CMD_BASE) 33 34 struct hinic_cap { 35 u16 max_qps; 36 u16 num_qps; 37 }; 38 39 enum hinic_port_cmd { 40 HINIC_PORT_CMD_CHANGE_MTU = 2, 41 42 HINIC_PORT_CMD_ADD_VLAN = 3, 43 HINIC_PORT_CMD_DEL_VLAN = 4, 44 45 HINIC_PORT_CMD_SET_MAC = 9, 46 HINIC_PORT_CMD_GET_MAC = 10, 47 HINIC_PORT_CMD_DEL_MAC = 11, 48 49 HINIC_PORT_CMD_SET_RX_MODE = 12, 50 51 HINIC_PORT_CMD_GET_LINK_STATE = 24, 52 53 HINIC_PORT_CMD_SET_PORT_STATE = 41, 54 55 HINIC_PORT_CMD_FWCTXT_INIT = 69, 56 57 HINIC_PORT_CMD_SET_FUNC_STATE = 93, 58 59 HINIC_PORT_CMD_GET_GLOBAL_QPN = 102, 60 61 HINIC_PORT_CMD_SET_TSO = 112, 62 63 HINIC_PORT_CMD_GET_CAP = 170, 64 }; 65 66 enum hinic_mgmt_msg_cmd { 67 HINIC_MGMT_MSG_CMD_BASE = 160, 68 69 HINIC_MGMT_MSG_CMD_LINK_STATUS = 160, 70 71 HINIC_MGMT_MSG_CMD_MAX, 72 }; 73 74 enum hinic_cb_state { 75 HINIC_CB_ENABLED = BIT(0), 76 HINIC_CB_RUNNING = BIT(1), 77 }; 78 79 enum hinic_res_state { 80 HINIC_RES_CLEAN = 0, 81 HINIC_RES_ACTIVE = 1, 82 }; 83 84 struct hinic_cmd_fw_ctxt { 85 u8 status; 86 u8 version; 87 u8 rsvd0[6]; 88 89 u16 func_idx; 90 u16 rx_buf_sz; 91 92 u32 rsvd1; 93 }; 94 95 struct hinic_cmd_hw_ioctxt { 96 u8 status; 97 u8 version; 98 u8 rsvd0[6]; 99 100 u16 func_idx; 101 102 u16 rsvd1; 103 104 u8 set_cmdq_depth; 105 u8 cmdq_depth; 106 107 u8 rsvd2; 108 u8 rsvd3; 109 u8 rsvd4; 110 u8 rsvd5; 111 112 u16 rq_depth; 113 u16 rx_buf_sz_idx; 114 u16 sq_depth; 115 }; 116 117 struct hinic_cmd_io_status { 118 u8 status; 119 u8 version; 120 u8 rsvd0[6]; 121 122 u16 func_idx; 123 u8 rsvd1; 124 u8 rsvd2; 125 u32 io_status; 126 }; 127 128 struct hinic_cmd_clear_io_res { 129 u8 status; 130 u8 version; 131 u8 rsvd0[6]; 132 133 u16 func_idx; 134 u8 rsvd1; 135 u8 rsvd2; 136 }; 137 138 struct hinic_cmd_set_res_state { 139 u8 status; 140 u8 version; 141 u8 rsvd0[6]; 142 143 u16 func_idx; 144 u8 state; 145 u8 rsvd1; 146 u32 rsvd2; 147 }; 148 149 struct hinic_cmd_base_qpn { 150 u8 status; 151 u8 version; 152 u8 rsvd0[6]; 153 154 u16 func_idx; 155 u16 qpn; 156 }; 157 158 struct hinic_cmd_hw_ci { 159 u8 status; 160 u8 version; 161 u8 rsvd0[6]; 162 163 u16 func_idx; 164 165 u8 dma_attr_off; 166 u8 pending_limit; 167 u8 coalesc_timer; 168 169 u8 msix_en; 170 u16 msix_entry_idx; 171 172 u32 sq_id; 173 u32 rsvd1; 174 u64 ci_addr; 175 }; 176 177 struct hinic_hwdev { 178 struct hinic_hwif *hwif; 179 struct msix_entry *msix_entries; 180 181 struct hinic_aeqs aeqs; 182 struct hinic_func_to_io func_to_io; 183 184 struct hinic_cap nic_cap; 185 }; 186 187 struct hinic_nic_cb { 188 void (*handler)(void *handle, void *buf_in, 189 u16 in_size, void *buf_out, 190 u16 *out_size); 191 192 void *handle; 193 unsigned long cb_state; 194 }; 195 196 struct hinic_pfhwdev { 197 struct hinic_hwdev hwdev; 198 199 struct hinic_pf_to_mgmt pf_to_mgmt; 200 201 struct hinic_nic_cb nic_cb[HINIC_MGMT_NUM_MSG_CMD]; 202 }; 203 204 void hinic_hwdev_cb_register(struct hinic_hwdev *hwdev, 205 enum hinic_mgmt_msg_cmd cmd, void *handle, 206 void (*handler)(void *handle, void *buf_in, 207 u16 in_size, void *buf_out, 208 u16 *out_size)); 209 210 void hinic_hwdev_cb_unregister(struct hinic_hwdev *hwdev, 211 enum hinic_mgmt_msg_cmd cmd); 212 213 int hinic_port_msg_cmd(struct hinic_hwdev *hwdev, enum hinic_port_cmd cmd, 214 void *buf_in, u16 in_size, void *buf_out, 215 u16 *out_size); 216 217 int hinic_hwdev_ifup(struct hinic_hwdev *hwdev); 218 219 void hinic_hwdev_ifdown(struct hinic_hwdev *hwdev); 220 221 struct hinic_hwdev *hinic_init_hwdev(struct pci_dev *pdev); 222 223 void hinic_free_hwdev(struct hinic_hwdev *hwdev); 224 225 int hinic_hwdev_num_qps(struct hinic_hwdev *hwdev); 226 227 struct hinic_sq *hinic_hwdev_get_sq(struct hinic_hwdev *hwdev, int i); 228 229 struct hinic_rq *hinic_hwdev_get_rq(struct hinic_hwdev *hwdev, int i); 230 231 int hinic_hwdev_msix_cnt_set(struct hinic_hwdev *hwdev, u16 msix_index); 232 233 int hinic_hwdev_msix_set(struct hinic_hwdev *hwdev, u16 msix_index, 234 u8 pending_limit, u8 coalesc_timer, 235 u8 lli_timer_cfg, u8 lli_credit_limit, 236 u8 resend_timer); 237 238 int hinic_hwdev_hw_ci_addr_set(struct hinic_hwdev *hwdev, struct hinic_sq *sq, 239 u8 pending_limit, u8 coalesc_timer); 240 241 #endif 242