1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Huawei HiNIC PCI Express Linux driver 4 * Copyright(c) 2017 Huawei Technologies Co., Ltd 5 */ 6 7 #ifndef HINIC_HW_DEV_H 8 #define HINIC_HW_DEV_H 9 10 #include <linux/pci.h> 11 #include <linux/types.h> 12 #include <linux/bitops.h> 13 14 #include "hinic_hw_if.h" 15 #include "hinic_hw_eqs.h" 16 #include "hinic_hw_mgmt.h" 17 #include "hinic_hw_qp.h" 18 #include "hinic_hw_io.h" 19 #include "hinic_hw_mbox.h" 20 21 #define HINIC_MAX_QPS 32 22 23 #define HINIC_MGMT_NUM_MSG_CMD (HINIC_MGMT_MSG_CMD_MAX - \ 24 HINIC_MGMT_MSG_CMD_BASE) 25 26 #define HINIC_PF_SET_VF_ALREADY 0x4 27 #define HINIC_MGMT_STATUS_EXIST 0x6 28 #define HINIC_MGMT_CMD_UNSUPPORTED 0xFF 29 30 struct hinic_cap { 31 u16 max_qps; 32 u16 num_qps; 33 u8 max_vf; 34 u16 max_vf_qps; 35 }; 36 37 enum hw_ioctxt_set_cmdq_depth { 38 HW_IOCTXT_SET_CMDQ_DEPTH_DEFAULT, 39 HW_IOCTXT_SET_CMDQ_DEPTH_ENABLE, 40 }; 41 42 enum hinic_port_cmd { 43 HINIC_PORT_CMD_VF_REGISTER = 0x0, 44 HINIC_PORT_CMD_VF_UNREGISTER = 0x1, 45 46 HINIC_PORT_CMD_CHANGE_MTU = 2, 47 48 HINIC_PORT_CMD_ADD_VLAN = 3, 49 HINIC_PORT_CMD_DEL_VLAN = 4, 50 51 HINIC_PORT_CMD_SET_PFC = 5, 52 53 HINIC_PORT_CMD_SET_MAC = 9, 54 HINIC_PORT_CMD_GET_MAC = 10, 55 HINIC_PORT_CMD_DEL_MAC = 11, 56 57 HINIC_PORT_CMD_SET_RX_MODE = 12, 58 59 HINIC_PORT_CMD_GET_PAUSE_INFO = 20, 60 HINIC_PORT_CMD_SET_PAUSE_INFO = 21, 61 62 HINIC_PORT_CMD_GET_LINK_STATE = 24, 63 64 HINIC_PORT_CMD_SET_LRO = 25, 65 66 HINIC_PORT_CMD_SET_RX_CSUM = 26, 67 68 HINIC_PORT_CMD_SET_RX_VLAN_OFFLOAD = 27, 69 70 HINIC_PORT_CMD_GET_PORT_STATISTICS = 28, 71 72 HINIC_PORT_CMD_CLEAR_PORT_STATISTICS = 29, 73 74 HINIC_PORT_CMD_GET_VPORT_STAT = 30, 75 76 HINIC_PORT_CMD_CLEAN_VPORT_STAT = 31, 77 78 HINIC_PORT_CMD_GET_RSS_TEMPLATE_INDIR_TBL = 37, 79 80 HINIC_PORT_CMD_SET_PORT_STATE = 41, 81 82 HINIC_PORT_CMD_SET_RSS_TEMPLATE_TBL = 43, 83 84 HINIC_PORT_CMD_GET_RSS_TEMPLATE_TBL = 44, 85 86 HINIC_PORT_CMD_SET_RSS_HASH_ENGINE = 45, 87 88 HINIC_PORT_CMD_GET_RSS_HASH_ENGINE = 46, 89 90 HINIC_PORT_CMD_GET_RSS_CTX_TBL = 47, 91 92 HINIC_PORT_CMD_SET_RSS_CTX_TBL = 48, 93 94 HINIC_PORT_CMD_RSS_TEMP_MGR = 49, 95 96 HINIC_PORT_CMD_RSS_CFG = 66, 97 98 HINIC_PORT_CMD_FWCTXT_INIT = 69, 99 100 HINIC_PORT_CMD_GET_LOOPBACK_MODE = 72, 101 HINIC_PORT_CMD_SET_LOOPBACK_MODE, 102 103 HINIC_PORT_CMD_ENABLE_SPOOFCHK = 78, 104 105 HINIC_PORT_CMD_GET_MGMT_VERSION = 88, 106 107 HINIC_PORT_CMD_SET_FUNC_STATE = 93, 108 109 HINIC_PORT_CMD_GET_GLOBAL_QPN = 102, 110 111 HINIC_PORT_CMD_SET_VF_RATE = 105, 112 113 HINIC_PORT_CMD_SET_VF_VLAN = 106, 114 115 HINIC_PORT_CMD_CLR_VF_VLAN, 116 117 HINIC_PORT_CMD_SET_TSO = 112, 118 119 HINIC_PORT_CMD_UPDATE_FW = 114, 120 121 HINIC_PORT_CMD_SET_RQ_IQ_MAP = 115, 122 123 HINIC_PORT_CMD_LINK_STATUS_REPORT = 160, 124 125 HINIC_PORT_CMD_UPDATE_MAC = 164, 126 127 HINIC_PORT_CMD_GET_CAP = 170, 128 129 HINIC_PORT_CMD_GET_LINK_MODE = 217, 130 131 HINIC_PORT_CMD_SET_SPEED = 218, 132 133 HINIC_PORT_CMD_SET_AUTONEG = 219, 134 135 HINIC_PORT_CMD_GET_STD_SFP_INFO = 240, 136 137 HINIC_PORT_CMD_SET_LRO_TIMER = 244, 138 139 HINIC_PORT_CMD_SET_VF_MAX_MIN_RATE = 249, 140 141 HINIC_PORT_CMD_GET_SFP_ABS = 251, 142 }; 143 144 /* cmd of mgmt CPU message for HILINK module */ 145 enum hinic_hilink_cmd { 146 HINIC_HILINK_CMD_GET_LINK_INFO = 0x3, 147 HINIC_HILINK_CMD_SET_LINK_SETTINGS = 0x8, 148 }; 149 150 enum hinic_ucode_cmd { 151 HINIC_UCODE_CMD_MODIFY_QUEUE_CONTEXT = 0, 152 HINIC_UCODE_CMD_CLEAN_QUEUE_CONTEXT, 153 HINIC_UCODE_CMD_ARM_SQ, 154 HINIC_UCODE_CMD_ARM_RQ, 155 HINIC_UCODE_CMD_SET_RSS_INDIR_TABLE, 156 HINIC_UCODE_CMD_SET_RSS_CONTEXT_TABLE, 157 HINIC_UCODE_CMD_GET_RSS_INDIR_TABLE, 158 HINIC_UCODE_CMD_GET_RSS_CONTEXT_TABLE, 159 HINIC_UCODE_CMD_SET_IQ_ENABLE, 160 HINIC_UCODE_CMD_SET_RQ_FLUSH = 10 161 }; 162 163 #define NIC_RSS_CMD_TEMP_ALLOC 0x01 164 #define NIC_RSS_CMD_TEMP_FREE 0x02 165 166 enum hinic_mgmt_msg_cmd { 167 HINIC_MGMT_MSG_CMD_BASE = 160, 168 169 HINIC_MGMT_MSG_CMD_LINK_STATUS = 160, 170 171 HINIC_MGMT_MSG_CMD_MAX, 172 }; 173 174 enum hinic_cb_state { 175 HINIC_CB_ENABLED = BIT(0), 176 HINIC_CB_RUNNING = BIT(1), 177 }; 178 179 enum hinic_res_state { 180 HINIC_RES_CLEAN = 0, 181 HINIC_RES_ACTIVE = 1, 182 }; 183 184 struct hinic_cmd_fw_ctxt { 185 u8 status; 186 u8 version; 187 u8 rsvd0[6]; 188 189 u16 func_idx; 190 u16 rx_buf_sz; 191 192 u32 rsvd1; 193 }; 194 195 struct hinic_cmd_hw_ioctxt { 196 u8 status; 197 u8 version; 198 u8 rsvd0[6]; 199 200 u16 func_idx; 201 202 u16 rsvd1; 203 204 u8 set_cmdq_depth; 205 u8 cmdq_depth; 206 207 u8 lro_en; 208 u8 rsvd3; 209 u8 ppf_idx; 210 u8 rsvd4; 211 212 u16 rq_depth; 213 u16 rx_buf_sz_idx; 214 u16 sq_depth; 215 }; 216 217 struct hinic_cmd_io_status { 218 u8 status; 219 u8 version; 220 u8 rsvd0[6]; 221 222 u16 func_idx; 223 u8 rsvd1; 224 u8 rsvd2; 225 u32 io_status; 226 }; 227 228 struct hinic_cmd_clear_io_res { 229 u8 status; 230 u8 version; 231 u8 rsvd0[6]; 232 233 u16 func_idx; 234 u8 rsvd1; 235 u8 rsvd2; 236 }; 237 238 struct hinic_cmd_set_res_state { 239 u8 status; 240 u8 version; 241 u8 rsvd0[6]; 242 243 u16 func_idx; 244 u8 state; 245 u8 rsvd1; 246 u32 rsvd2; 247 }; 248 249 struct hinic_ceq_ctrl_reg { 250 u8 status; 251 u8 version; 252 u8 rsvd0[6]; 253 254 u16 func_id; 255 u16 q_id; 256 u32 ctrl0; 257 u32 ctrl1; 258 }; 259 260 struct hinic_cmd_base_qpn { 261 u8 status; 262 u8 version; 263 u8 rsvd0[6]; 264 265 u16 func_idx; 266 u16 qpn; 267 }; 268 269 struct hinic_cmd_hw_ci { 270 u8 status; 271 u8 version; 272 u8 rsvd0[6]; 273 274 u16 func_idx; 275 276 u8 dma_attr_off; 277 u8 pending_limit; 278 u8 coalesc_timer; 279 280 u8 msix_en; 281 u16 msix_entry_idx; 282 283 u32 sq_id; 284 u32 rsvd1; 285 u64 ci_addr; 286 }; 287 288 struct hinic_cmd_l2nic_reset { 289 u8 status; 290 u8 version; 291 u8 rsvd0[6]; 292 293 u16 func_id; 294 u16 reset_flag; 295 }; 296 297 struct hinic_msix_config { 298 u8 status; 299 u8 version; 300 u8 rsvd0[6]; 301 302 u16 func_id; 303 u16 msix_index; 304 u8 pending_cnt; 305 u8 coalesce_timer_cnt; 306 u8 lli_timer_cnt; 307 u8 lli_credit_cnt; 308 u8 resend_timer_cnt; 309 u8 rsvd1[3]; 310 }; 311 312 struct hinic_board_info { 313 u32 board_type; 314 u32 port_num; 315 u32 port_speed; 316 u32 pcie_width; 317 u32 host_num; 318 u32 pf_num; 319 u32 vf_total_num; 320 u32 tile_num; 321 u32 qcm_num; 322 u32 core_num; 323 u32 work_mode; 324 u32 service_mode; 325 u32 pcie_mode; 326 u32 cfg_addr; 327 u32 boot_sel; 328 u32 board_id; 329 }; 330 331 struct hinic_comm_board_info { 332 u8 status; 333 u8 version; 334 u8 rsvd0[6]; 335 336 struct hinic_board_info info; 337 338 u32 rsvd1[4]; 339 }; 340 341 struct hinic_hwdev { 342 struct hinic_hwif *hwif; 343 struct msix_entry *msix_entries; 344 345 struct hinic_aeqs aeqs; 346 struct hinic_func_to_io func_to_io; 347 struct hinic_mbox_func_to_func *func_to_func; 348 349 struct hinic_cap nic_cap; 350 u8 port_id; 351 }; 352 353 struct hinic_nic_cb { 354 void (*handler)(void *handle, void *buf_in, 355 u16 in_size, void *buf_out, 356 u16 *out_size); 357 358 void *handle; 359 unsigned long cb_state; 360 }; 361 362 struct hinic_pfhwdev { 363 struct hinic_hwdev hwdev; 364 365 struct hinic_pf_to_mgmt pf_to_mgmt; 366 367 struct hinic_nic_cb nic_cb[HINIC_MGMT_NUM_MSG_CMD]; 368 }; 369 370 struct hinic_dev_cap { 371 u8 status; 372 u8 version; 373 u8 rsvd0[6]; 374 375 u8 rsvd1[5]; 376 u8 intr_type; 377 u8 max_cos_id; 378 u8 er_id; 379 u8 port_id; 380 u8 max_vf; 381 u8 rsvd2[62]; 382 u16 max_sqs; 383 u16 max_rqs; 384 u16 max_vf_sqs; 385 u16 max_vf_rqs; 386 u8 rsvd3[204]; 387 }; 388 389 void hinic_hwdev_cb_register(struct hinic_hwdev *hwdev, 390 enum hinic_mgmt_msg_cmd cmd, void *handle, 391 void (*handler)(void *handle, void *buf_in, 392 u16 in_size, void *buf_out, 393 u16 *out_size)); 394 395 void hinic_hwdev_cb_unregister(struct hinic_hwdev *hwdev, 396 enum hinic_mgmt_msg_cmd cmd); 397 398 int hinic_port_msg_cmd(struct hinic_hwdev *hwdev, enum hinic_port_cmd cmd, 399 void *buf_in, u16 in_size, void *buf_out, 400 u16 *out_size); 401 402 int hinic_hilink_msg_cmd(struct hinic_hwdev *hwdev, enum hinic_hilink_cmd cmd, 403 void *buf_in, u16 in_size, void *buf_out, 404 u16 *out_size); 405 406 int hinic_hwdev_ifup(struct hinic_hwdev *hwdev, u16 sq_depth, u16 rq_depth); 407 408 void hinic_hwdev_ifdown(struct hinic_hwdev *hwdev); 409 410 struct hinic_hwdev *hinic_init_hwdev(struct pci_dev *pdev); 411 412 void hinic_free_hwdev(struct hinic_hwdev *hwdev); 413 414 int hinic_hwdev_max_num_qps(struct hinic_hwdev *hwdev); 415 416 int hinic_hwdev_num_qps(struct hinic_hwdev *hwdev); 417 418 struct hinic_sq *hinic_hwdev_get_sq(struct hinic_hwdev *hwdev, int i); 419 420 struct hinic_rq *hinic_hwdev_get_rq(struct hinic_hwdev *hwdev, int i); 421 422 int hinic_hwdev_msix_cnt_set(struct hinic_hwdev *hwdev, u16 msix_index); 423 424 int hinic_hwdev_msix_set(struct hinic_hwdev *hwdev, u16 msix_index, 425 u8 pending_limit, u8 coalesc_timer, 426 u8 lli_timer_cfg, u8 lli_credit_limit, 427 u8 resend_timer); 428 429 int hinic_hwdev_hw_ci_addr_set(struct hinic_hwdev *hwdev, struct hinic_sq *sq, 430 u8 pending_limit, u8 coalesc_timer); 431 432 void hinic_hwdev_set_msix_state(struct hinic_hwdev *hwdev, u16 msix_index, 433 enum hinic_msix_state flag); 434 435 int hinic_get_interrupt_cfg(struct hinic_hwdev *hwdev, 436 struct hinic_msix_config *interrupt_info); 437 438 int hinic_set_interrupt_cfg(struct hinic_hwdev *hwdev, 439 struct hinic_msix_config *interrupt_info); 440 441 int hinic_get_board_info(struct hinic_hwdev *hwdev, 442 struct hinic_comm_board_info *board_info); 443 444 #endif 445