1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Huawei HiNIC PCI Express Linux driver 4 * Copyright(c) 2017 Huawei Technologies Co., Ltd 5 */ 6 7 #include <linux/kernel.h> 8 #include <linux/types.h> 9 #include <linux/pci.h> 10 #include <linux/device.h> 11 #include <linux/errno.h> 12 #include <linux/slab.h> 13 #include <linux/bitops.h> 14 #include <linux/delay.h> 15 #include <linux/jiffies.h> 16 #include <linux/log2.h> 17 #include <linux/err.h> 18 19 #include "hinic_hw_if.h" 20 #include "hinic_hw_eqs.h" 21 #include "hinic_hw_mgmt.h" 22 #include "hinic_hw_qp_ctxt.h" 23 #include "hinic_hw_qp.h" 24 #include "hinic_hw_io.h" 25 #include "hinic_hw_dev.h" 26 27 #define IO_STATUS_TIMEOUT 100 28 #define OUTBOUND_STATE_TIMEOUT 100 29 #define DB_STATE_TIMEOUT 100 30 31 #define MAX_IRQS(max_qps, num_aeqs, num_ceqs) \ 32 (2 * (max_qps) + (num_aeqs) + (num_ceqs)) 33 34 #define ADDR_IN_4BYTES(addr) ((addr) >> 2) 35 36 enum intr_type { 37 INTR_MSIX_TYPE, 38 }; 39 40 enum io_status { 41 IO_STOPPED = 0, 42 IO_RUNNING = 1, 43 }; 44 45 enum hw_ioctxt_set_cmdq_depth { 46 HW_IOCTXT_SET_CMDQ_DEPTH_DEFAULT, 47 }; 48 49 /* HW struct */ 50 struct hinic_dev_cap { 51 u8 status; 52 u8 version; 53 u8 rsvd0[6]; 54 55 u8 rsvd1[5]; 56 u8 intr_type; 57 u8 rsvd2[66]; 58 u16 max_sqs; 59 u16 max_rqs; 60 u8 rsvd3[208]; 61 }; 62 63 /** 64 * get_capability - convert device capabilities to NIC capabilities 65 * @hwdev: the HW device to set and convert device capabilities for 66 * @dev_cap: device capabilities from FW 67 * 68 * Return 0 - Success, negative - Failure 69 **/ 70 static int get_capability(struct hinic_hwdev *hwdev, 71 struct hinic_dev_cap *dev_cap) 72 { 73 struct hinic_cap *nic_cap = &hwdev->nic_cap; 74 int num_aeqs, num_ceqs, num_irqs; 75 76 if (!HINIC_IS_PF(hwdev->hwif) && !HINIC_IS_PPF(hwdev->hwif)) 77 return -EINVAL; 78 79 if (dev_cap->intr_type != INTR_MSIX_TYPE) 80 return -EFAULT; 81 82 num_aeqs = HINIC_HWIF_NUM_AEQS(hwdev->hwif); 83 num_ceqs = HINIC_HWIF_NUM_CEQS(hwdev->hwif); 84 num_irqs = HINIC_HWIF_NUM_IRQS(hwdev->hwif); 85 86 /* Each QP has its own (SQ + RQ) interrupts */ 87 nic_cap->num_qps = (num_irqs - (num_aeqs + num_ceqs)) / 2; 88 89 if (nic_cap->num_qps > HINIC_Q_CTXT_MAX) 90 nic_cap->num_qps = HINIC_Q_CTXT_MAX; 91 92 /* num_qps must be power of 2 */ 93 nic_cap->num_qps = BIT(fls(nic_cap->num_qps) - 1); 94 95 nic_cap->max_qps = dev_cap->max_sqs + 1; 96 if (nic_cap->max_qps != (dev_cap->max_rqs + 1)) 97 return -EFAULT; 98 99 if (nic_cap->num_qps > nic_cap->max_qps) 100 nic_cap->num_qps = nic_cap->max_qps; 101 102 return 0; 103 } 104 105 /** 106 * get_cap_from_fw - get device capabilities from FW 107 * @pfhwdev: the PF HW device to get capabilities for 108 * 109 * Return 0 - Success, negative - Failure 110 **/ 111 static int get_cap_from_fw(struct hinic_pfhwdev *pfhwdev) 112 { 113 struct hinic_hwdev *hwdev = &pfhwdev->hwdev; 114 struct hinic_hwif *hwif = hwdev->hwif; 115 struct pci_dev *pdev = hwif->pdev; 116 struct hinic_dev_cap dev_cap; 117 u16 in_len, out_len; 118 int err; 119 120 in_len = 0; 121 out_len = sizeof(dev_cap); 122 123 err = hinic_msg_to_mgmt(&pfhwdev->pf_to_mgmt, HINIC_MOD_CFGM, 124 HINIC_CFG_NIC_CAP, &dev_cap, in_len, &dev_cap, 125 &out_len, HINIC_MGMT_MSG_SYNC); 126 if (err) { 127 dev_err(&pdev->dev, "Failed to get capability from FW\n"); 128 return err; 129 } 130 131 return get_capability(hwdev, &dev_cap); 132 } 133 134 /** 135 * get_dev_cap - get device capabilities 136 * @hwdev: the NIC HW device to get capabilities for 137 * 138 * Return 0 - Success, negative - Failure 139 **/ 140 static int get_dev_cap(struct hinic_hwdev *hwdev) 141 { 142 struct hinic_hwif *hwif = hwdev->hwif; 143 struct pci_dev *pdev = hwif->pdev; 144 struct hinic_pfhwdev *pfhwdev; 145 int err; 146 147 switch (HINIC_FUNC_TYPE(hwif)) { 148 case HINIC_PPF: 149 case HINIC_PF: 150 pfhwdev = container_of(hwdev, struct hinic_pfhwdev, hwdev); 151 152 err = get_cap_from_fw(pfhwdev); 153 if (err) { 154 dev_err(&pdev->dev, "Failed to get capability from FW\n"); 155 return err; 156 } 157 break; 158 159 default: 160 dev_err(&pdev->dev, "Unsupported PCI Function type\n"); 161 return -EINVAL; 162 } 163 164 return 0; 165 } 166 167 /** 168 * init_msix - enable the msix and save the entries 169 * @hwdev: the NIC HW device 170 * 171 * Return 0 - Success, negative - Failure 172 **/ 173 static int init_msix(struct hinic_hwdev *hwdev) 174 { 175 struct hinic_hwif *hwif = hwdev->hwif; 176 struct pci_dev *pdev = hwif->pdev; 177 int nr_irqs, num_aeqs, num_ceqs; 178 size_t msix_entries_size; 179 int i, err; 180 181 num_aeqs = HINIC_HWIF_NUM_AEQS(hwif); 182 num_ceqs = HINIC_HWIF_NUM_CEQS(hwif); 183 nr_irqs = MAX_IRQS(HINIC_MAX_QPS, num_aeqs, num_ceqs); 184 if (nr_irqs > HINIC_HWIF_NUM_IRQS(hwif)) 185 nr_irqs = HINIC_HWIF_NUM_IRQS(hwif); 186 187 msix_entries_size = nr_irqs * sizeof(*hwdev->msix_entries); 188 hwdev->msix_entries = devm_kzalloc(&pdev->dev, msix_entries_size, 189 GFP_KERNEL); 190 if (!hwdev->msix_entries) 191 return -ENOMEM; 192 193 for (i = 0; i < nr_irqs; i++) 194 hwdev->msix_entries[i].entry = i; 195 196 err = pci_enable_msix_exact(pdev, hwdev->msix_entries, nr_irqs); 197 if (err) { 198 dev_err(&pdev->dev, "Failed to enable pci msix\n"); 199 return err; 200 } 201 202 return 0; 203 } 204 205 /** 206 * disable_msix - disable the msix 207 * @hwdev: the NIC HW device 208 **/ 209 static void disable_msix(struct hinic_hwdev *hwdev) 210 { 211 struct hinic_hwif *hwif = hwdev->hwif; 212 struct pci_dev *pdev = hwif->pdev; 213 214 pci_disable_msix(pdev); 215 } 216 217 /** 218 * hinic_port_msg_cmd - send port msg to mgmt 219 * @hwdev: the NIC HW device 220 * @cmd: the port command 221 * @buf_in: input buffer 222 * @in_size: input size 223 * @buf_out: output buffer 224 * @out_size: returned output size 225 * 226 * Return 0 - Success, negative - Failure 227 **/ 228 int hinic_port_msg_cmd(struct hinic_hwdev *hwdev, enum hinic_port_cmd cmd, 229 void *buf_in, u16 in_size, void *buf_out, u16 *out_size) 230 { 231 struct hinic_hwif *hwif = hwdev->hwif; 232 struct pci_dev *pdev = hwif->pdev; 233 struct hinic_pfhwdev *pfhwdev; 234 235 if (!HINIC_IS_PF(hwif) && !HINIC_IS_PPF(hwif)) { 236 dev_err(&pdev->dev, "unsupported PCI Function type\n"); 237 return -EINVAL; 238 } 239 240 pfhwdev = container_of(hwdev, struct hinic_pfhwdev, hwdev); 241 242 return hinic_msg_to_mgmt(&pfhwdev->pf_to_mgmt, HINIC_MOD_L2NIC, cmd, 243 buf_in, in_size, buf_out, out_size, 244 HINIC_MGMT_MSG_SYNC); 245 } 246 247 /** 248 * init_fw_ctxt- Init Firmware tables before network mgmt and io operations 249 * @hwdev: the NIC HW device 250 * 251 * Return 0 - Success, negative - Failure 252 **/ 253 static int init_fw_ctxt(struct hinic_hwdev *hwdev) 254 { 255 struct hinic_hwif *hwif = hwdev->hwif; 256 struct pci_dev *pdev = hwif->pdev; 257 struct hinic_cmd_fw_ctxt fw_ctxt; 258 u16 out_size; 259 int err; 260 261 if (!HINIC_IS_PF(hwif) && !HINIC_IS_PPF(hwif)) { 262 dev_err(&pdev->dev, "Unsupported PCI Function type\n"); 263 return -EINVAL; 264 } 265 266 fw_ctxt.func_idx = HINIC_HWIF_FUNC_IDX(hwif); 267 fw_ctxt.rx_buf_sz = HINIC_RX_BUF_SZ; 268 269 err = hinic_port_msg_cmd(hwdev, HINIC_PORT_CMD_FWCTXT_INIT, 270 &fw_ctxt, sizeof(fw_ctxt), 271 &fw_ctxt, &out_size); 272 if (err || (out_size != sizeof(fw_ctxt)) || fw_ctxt.status) { 273 dev_err(&pdev->dev, "Failed to init FW ctxt, ret = %d\n", 274 fw_ctxt.status); 275 return -EFAULT; 276 } 277 278 return 0; 279 } 280 281 /** 282 * set_hw_ioctxt - set the shape of the IO queues in FW 283 * @hwdev: the NIC HW device 284 * @rq_depth: rq depth 285 * @sq_depth: sq depth 286 * 287 * Return 0 - Success, negative - Failure 288 **/ 289 static int set_hw_ioctxt(struct hinic_hwdev *hwdev, unsigned int rq_depth, 290 unsigned int sq_depth) 291 { 292 struct hinic_hwif *hwif = hwdev->hwif; 293 struct hinic_cmd_hw_ioctxt hw_ioctxt; 294 struct pci_dev *pdev = hwif->pdev; 295 struct hinic_pfhwdev *pfhwdev; 296 297 if (!HINIC_IS_PF(hwif) && !HINIC_IS_PPF(hwif)) { 298 dev_err(&pdev->dev, "Unsupported PCI Function type\n"); 299 return -EINVAL; 300 } 301 302 hw_ioctxt.func_idx = HINIC_HWIF_FUNC_IDX(hwif); 303 304 hw_ioctxt.set_cmdq_depth = HW_IOCTXT_SET_CMDQ_DEPTH_DEFAULT; 305 hw_ioctxt.cmdq_depth = 0; 306 307 hw_ioctxt.rq_depth = ilog2(rq_depth); 308 309 hw_ioctxt.rx_buf_sz_idx = HINIC_RX_BUF_SZ_IDX; 310 311 hw_ioctxt.sq_depth = ilog2(sq_depth); 312 313 pfhwdev = container_of(hwdev, struct hinic_pfhwdev, hwdev); 314 315 return hinic_msg_to_mgmt(&pfhwdev->pf_to_mgmt, HINIC_MOD_COMM, 316 HINIC_COMM_CMD_HWCTXT_SET, 317 &hw_ioctxt, sizeof(hw_ioctxt), NULL, 318 NULL, HINIC_MGMT_MSG_SYNC); 319 } 320 321 static int wait_for_outbound_state(struct hinic_hwdev *hwdev) 322 { 323 enum hinic_outbound_state outbound_state; 324 struct hinic_hwif *hwif = hwdev->hwif; 325 struct pci_dev *pdev = hwif->pdev; 326 unsigned long end; 327 328 end = jiffies + msecs_to_jiffies(OUTBOUND_STATE_TIMEOUT); 329 do { 330 outbound_state = hinic_outbound_state_get(hwif); 331 332 if (outbound_state == HINIC_OUTBOUND_ENABLE) 333 return 0; 334 335 msleep(20); 336 } while (time_before(jiffies, end)); 337 338 dev_err(&pdev->dev, "Wait for OUTBOUND - Timeout\n"); 339 return -EFAULT; 340 } 341 342 static int wait_for_db_state(struct hinic_hwdev *hwdev) 343 { 344 struct hinic_hwif *hwif = hwdev->hwif; 345 struct pci_dev *pdev = hwif->pdev; 346 enum hinic_db_state db_state; 347 unsigned long end; 348 349 end = jiffies + msecs_to_jiffies(DB_STATE_TIMEOUT); 350 do { 351 db_state = hinic_db_state_get(hwif); 352 353 if (db_state == HINIC_DB_ENABLE) 354 return 0; 355 356 msleep(20); 357 } while (time_before(jiffies, end)); 358 359 dev_err(&pdev->dev, "Wait for DB - Timeout\n"); 360 return -EFAULT; 361 } 362 363 static int wait_for_io_stopped(struct hinic_hwdev *hwdev) 364 { 365 struct hinic_cmd_io_status cmd_io_status; 366 struct hinic_hwif *hwif = hwdev->hwif; 367 struct pci_dev *pdev = hwif->pdev; 368 struct hinic_pfhwdev *pfhwdev; 369 unsigned long end; 370 u16 out_size; 371 int err; 372 373 if (!HINIC_IS_PF(hwif) && !HINIC_IS_PPF(hwif)) { 374 dev_err(&pdev->dev, "Unsupported PCI Function type\n"); 375 return -EINVAL; 376 } 377 378 pfhwdev = container_of(hwdev, struct hinic_pfhwdev, hwdev); 379 380 cmd_io_status.func_idx = HINIC_HWIF_FUNC_IDX(hwif); 381 382 end = jiffies + msecs_to_jiffies(IO_STATUS_TIMEOUT); 383 do { 384 err = hinic_msg_to_mgmt(&pfhwdev->pf_to_mgmt, HINIC_MOD_COMM, 385 HINIC_COMM_CMD_IO_STATUS_GET, 386 &cmd_io_status, sizeof(cmd_io_status), 387 &cmd_io_status, &out_size, 388 HINIC_MGMT_MSG_SYNC); 389 if ((err) || (out_size != sizeof(cmd_io_status))) { 390 dev_err(&pdev->dev, "Failed to get IO status, ret = %d\n", 391 err); 392 return err; 393 } 394 395 if (cmd_io_status.status == IO_STOPPED) { 396 dev_info(&pdev->dev, "IO stopped\n"); 397 return 0; 398 } 399 400 msleep(20); 401 } while (time_before(jiffies, end)); 402 403 dev_err(&pdev->dev, "Wait for IO stopped - Timeout\n"); 404 return -ETIMEDOUT; 405 } 406 407 /** 408 * clear_io_resource - set the IO resources as not active in the NIC 409 * @hwdev: the NIC HW device 410 * 411 * Return 0 - Success, negative - Failure 412 **/ 413 static int clear_io_resources(struct hinic_hwdev *hwdev) 414 { 415 struct hinic_cmd_clear_io_res cmd_clear_io_res; 416 struct hinic_hwif *hwif = hwdev->hwif; 417 struct pci_dev *pdev = hwif->pdev; 418 struct hinic_pfhwdev *pfhwdev; 419 int err; 420 421 if (!HINIC_IS_PF(hwif) && !HINIC_IS_PPF(hwif)) { 422 dev_err(&pdev->dev, "Unsupported PCI Function type\n"); 423 return -EINVAL; 424 } 425 426 err = wait_for_io_stopped(hwdev); 427 if (err) { 428 dev_err(&pdev->dev, "IO has not stopped yet\n"); 429 return err; 430 } 431 432 cmd_clear_io_res.func_idx = HINIC_HWIF_FUNC_IDX(hwif); 433 434 pfhwdev = container_of(hwdev, struct hinic_pfhwdev, hwdev); 435 436 err = hinic_msg_to_mgmt(&pfhwdev->pf_to_mgmt, HINIC_MOD_COMM, 437 HINIC_COMM_CMD_IO_RES_CLEAR, &cmd_clear_io_res, 438 sizeof(cmd_clear_io_res), NULL, NULL, 439 HINIC_MGMT_MSG_SYNC); 440 if (err) { 441 dev_err(&pdev->dev, "Failed to clear IO resources\n"); 442 return err; 443 } 444 445 return 0; 446 } 447 448 /** 449 * set_resources_state - set the state of the resources in the NIC 450 * @hwdev: the NIC HW device 451 * @state: the state to set 452 * 453 * Return 0 - Success, negative - Failure 454 **/ 455 static int set_resources_state(struct hinic_hwdev *hwdev, 456 enum hinic_res_state state) 457 { 458 struct hinic_cmd_set_res_state res_state; 459 struct hinic_hwif *hwif = hwdev->hwif; 460 struct pci_dev *pdev = hwif->pdev; 461 struct hinic_pfhwdev *pfhwdev; 462 463 if (!HINIC_IS_PF(hwif) && !HINIC_IS_PPF(hwif)) { 464 dev_err(&pdev->dev, "Unsupported PCI Function type\n"); 465 return -EINVAL; 466 } 467 468 res_state.func_idx = HINIC_HWIF_FUNC_IDX(hwif); 469 res_state.state = state; 470 471 pfhwdev = container_of(hwdev, struct hinic_pfhwdev, hwdev); 472 473 return hinic_msg_to_mgmt(&pfhwdev->pf_to_mgmt, 474 HINIC_MOD_COMM, 475 HINIC_COMM_CMD_RES_STATE_SET, 476 &res_state, sizeof(res_state), NULL, 477 NULL, HINIC_MGMT_MSG_SYNC); 478 } 479 480 /** 481 * get_base_qpn - get the first qp number 482 * @hwdev: the NIC HW device 483 * @base_qpn: returned qp number 484 * 485 * Return 0 - Success, negative - Failure 486 **/ 487 static int get_base_qpn(struct hinic_hwdev *hwdev, u16 *base_qpn) 488 { 489 struct hinic_cmd_base_qpn cmd_base_qpn; 490 struct hinic_hwif *hwif = hwdev->hwif; 491 struct pci_dev *pdev = hwif->pdev; 492 u16 out_size; 493 int err; 494 495 cmd_base_qpn.func_idx = HINIC_HWIF_FUNC_IDX(hwif); 496 497 err = hinic_port_msg_cmd(hwdev, HINIC_PORT_CMD_GET_GLOBAL_QPN, 498 &cmd_base_qpn, sizeof(cmd_base_qpn), 499 &cmd_base_qpn, &out_size); 500 if (err || (out_size != sizeof(cmd_base_qpn)) || cmd_base_qpn.status) { 501 dev_err(&pdev->dev, "Failed to get base qpn, status = %d\n", 502 cmd_base_qpn.status); 503 return -EFAULT; 504 } 505 506 *base_qpn = cmd_base_qpn.qpn; 507 return 0; 508 } 509 510 /** 511 * hinic_hwdev_ifup - Preparing the HW for passing IO 512 * @hwdev: the NIC HW device 513 * 514 * Return 0 - Success, negative - Failure 515 **/ 516 int hinic_hwdev_ifup(struct hinic_hwdev *hwdev) 517 { 518 struct hinic_func_to_io *func_to_io = &hwdev->func_to_io; 519 struct hinic_cap *nic_cap = &hwdev->nic_cap; 520 struct hinic_hwif *hwif = hwdev->hwif; 521 int err, num_aeqs, num_ceqs, num_qps; 522 struct msix_entry *ceq_msix_entries; 523 struct msix_entry *sq_msix_entries; 524 struct msix_entry *rq_msix_entries; 525 struct pci_dev *pdev = hwif->pdev; 526 u16 base_qpn; 527 528 err = get_base_qpn(hwdev, &base_qpn); 529 if (err) { 530 dev_err(&pdev->dev, "Failed to get global base qp number\n"); 531 return err; 532 } 533 534 num_aeqs = HINIC_HWIF_NUM_AEQS(hwif); 535 num_ceqs = HINIC_HWIF_NUM_CEQS(hwif); 536 537 ceq_msix_entries = &hwdev->msix_entries[num_aeqs]; 538 539 err = hinic_io_init(func_to_io, hwif, nic_cap->max_qps, num_ceqs, 540 ceq_msix_entries); 541 if (err) { 542 dev_err(&pdev->dev, "Failed to init IO channel\n"); 543 return err; 544 } 545 546 num_qps = nic_cap->num_qps; 547 sq_msix_entries = &hwdev->msix_entries[num_aeqs + num_ceqs]; 548 rq_msix_entries = &hwdev->msix_entries[num_aeqs + num_ceqs + num_qps]; 549 550 err = hinic_io_create_qps(func_to_io, base_qpn, num_qps, 551 sq_msix_entries, rq_msix_entries); 552 if (err) { 553 dev_err(&pdev->dev, "Failed to create QPs\n"); 554 goto err_create_qps; 555 } 556 557 err = wait_for_db_state(hwdev); 558 if (err) { 559 dev_warn(&pdev->dev, "db - disabled, try again\n"); 560 hinic_db_state_set(hwif, HINIC_DB_ENABLE); 561 } 562 563 err = set_hw_ioctxt(hwdev, HINIC_SQ_DEPTH, HINIC_RQ_DEPTH); 564 if (err) { 565 dev_err(&pdev->dev, "Failed to set HW IO ctxt\n"); 566 goto err_hw_ioctxt; 567 } 568 569 return 0; 570 571 err_hw_ioctxt: 572 hinic_io_destroy_qps(func_to_io, num_qps); 573 574 err_create_qps: 575 hinic_io_free(func_to_io); 576 return err; 577 } 578 579 /** 580 * hinic_hwdev_ifdown - Closing the HW for passing IO 581 * @hwdev: the NIC HW device 582 * 583 **/ 584 void hinic_hwdev_ifdown(struct hinic_hwdev *hwdev) 585 { 586 struct hinic_func_to_io *func_to_io = &hwdev->func_to_io; 587 struct hinic_cap *nic_cap = &hwdev->nic_cap; 588 589 clear_io_resources(hwdev); 590 591 hinic_io_destroy_qps(func_to_io, nic_cap->num_qps); 592 hinic_io_free(func_to_io); 593 } 594 595 /** 596 * hinic_hwdev_cb_register - register callback handler for MGMT events 597 * @hwdev: the NIC HW device 598 * @cmd: the mgmt event 599 * @handle: private data for the handler 600 * @handler: event handler 601 **/ 602 void hinic_hwdev_cb_register(struct hinic_hwdev *hwdev, 603 enum hinic_mgmt_msg_cmd cmd, void *handle, 604 void (*handler)(void *handle, void *buf_in, 605 u16 in_size, void *buf_out, 606 u16 *out_size)) 607 { 608 struct hinic_hwif *hwif = hwdev->hwif; 609 struct pci_dev *pdev = hwif->pdev; 610 struct hinic_pfhwdev *pfhwdev; 611 struct hinic_nic_cb *nic_cb; 612 u8 cmd_cb; 613 614 if (!HINIC_IS_PF(hwif) && !HINIC_IS_PPF(hwif)) { 615 dev_err(&pdev->dev, "unsupported PCI Function type\n"); 616 return; 617 } 618 619 pfhwdev = container_of(hwdev, struct hinic_pfhwdev, hwdev); 620 621 cmd_cb = cmd - HINIC_MGMT_MSG_CMD_BASE; 622 nic_cb = &pfhwdev->nic_cb[cmd_cb]; 623 624 nic_cb->handler = handler; 625 nic_cb->handle = handle; 626 nic_cb->cb_state = HINIC_CB_ENABLED; 627 } 628 629 /** 630 * hinic_hwdev_cb_unregister - unregister callback handler for MGMT events 631 * @hwdev: the NIC HW device 632 * @cmd: the mgmt event 633 **/ 634 void hinic_hwdev_cb_unregister(struct hinic_hwdev *hwdev, 635 enum hinic_mgmt_msg_cmd cmd) 636 { 637 struct hinic_hwif *hwif = hwdev->hwif; 638 struct pci_dev *pdev = hwif->pdev; 639 struct hinic_pfhwdev *pfhwdev; 640 struct hinic_nic_cb *nic_cb; 641 u8 cmd_cb; 642 643 if (!HINIC_IS_PF(hwif) && !HINIC_IS_PPF(hwif)) { 644 dev_err(&pdev->dev, "unsupported PCI Function type\n"); 645 return; 646 } 647 648 pfhwdev = container_of(hwdev, struct hinic_pfhwdev, hwdev); 649 650 cmd_cb = cmd - HINIC_MGMT_MSG_CMD_BASE; 651 nic_cb = &pfhwdev->nic_cb[cmd_cb]; 652 653 nic_cb->cb_state &= ~HINIC_CB_ENABLED; 654 655 while (nic_cb->cb_state & HINIC_CB_RUNNING) 656 schedule(); 657 658 nic_cb->handler = NULL; 659 } 660 661 /** 662 * nic_mgmt_msg_handler - nic mgmt event handler 663 * @handle: private data for the handler 664 * @buf_in: input buffer 665 * @in_size: input size 666 * @buf_out: output buffer 667 * @out_size: returned output size 668 **/ 669 static void nic_mgmt_msg_handler(void *handle, u8 cmd, void *buf_in, 670 u16 in_size, void *buf_out, u16 *out_size) 671 { 672 struct hinic_pfhwdev *pfhwdev = handle; 673 enum hinic_cb_state cb_state; 674 struct hinic_nic_cb *nic_cb; 675 struct hinic_hwdev *hwdev; 676 struct hinic_hwif *hwif; 677 struct pci_dev *pdev; 678 u8 cmd_cb; 679 680 hwdev = &pfhwdev->hwdev; 681 hwif = hwdev->hwif; 682 pdev = hwif->pdev; 683 684 if ((cmd < HINIC_MGMT_MSG_CMD_BASE) || 685 (cmd >= HINIC_MGMT_MSG_CMD_MAX)) { 686 dev_err(&pdev->dev, "unknown L2NIC event, cmd = %d\n", cmd); 687 return; 688 } 689 690 cmd_cb = cmd - HINIC_MGMT_MSG_CMD_BASE; 691 692 nic_cb = &pfhwdev->nic_cb[cmd_cb]; 693 694 cb_state = cmpxchg(&nic_cb->cb_state, 695 HINIC_CB_ENABLED, 696 HINIC_CB_ENABLED | HINIC_CB_RUNNING); 697 698 if ((cb_state == HINIC_CB_ENABLED) && (nic_cb->handler)) 699 nic_cb->handler(nic_cb->handle, buf_in, 700 in_size, buf_out, out_size); 701 else 702 dev_err(&pdev->dev, "Unhandled NIC Event %d\n", cmd); 703 704 nic_cb->cb_state &= ~HINIC_CB_RUNNING; 705 } 706 707 /** 708 * init_pfhwdev - Initialize the extended components of PF 709 * @pfhwdev: the HW device for PF 710 * 711 * Return 0 - success, negative - failure 712 **/ 713 static int init_pfhwdev(struct hinic_pfhwdev *pfhwdev) 714 { 715 struct hinic_hwdev *hwdev = &pfhwdev->hwdev; 716 struct hinic_hwif *hwif = hwdev->hwif; 717 struct pci_dev *pdev = hwif->pdev; 718 int err; 719 720 err = hinic_pf_to_mgmt_init(&pfhwdev->pf_to_mgmt, hwif); 721 if (err) { 722 dev_err(&pdev->dev, "Failed to initialize PF to MGMT channel\n"); 723 return err; 724 } 725 726 hinic_register_mgmt_msg_cb(&pfhwdev->pf_to_mgmt, HINIC_MOD_L2NIC, 727 pfhwdev, nic_mgmt_msg_handler); 728 729 hinic_set_pf_action(hwif, HINIC_PF_MGMT_ACTIVE); 730 return 0; 731 } 732 733 /** 734 * free_pfhwdev - Free the extended components of PF 735 * @pfhwdev: the HW device for PF 736 **/ 737 static void free_pfhwdev(struct hinic_pfhwdev *pfhwdev) 738 { 739 struct hinic_hwdev *hwdev = &pfhwdev->hwdev; 740 741 hinic_set_pf_action(hwdev->hwif, HINIC_PF_MGMT_INIT); 742 743 hinic_unregister_mgmt_msg_cb(&pfhwdev->pf_to_mgmt, HINIC_MOD_L2NIC); 744 745 hinic_pf_to_mgmt_free(&pfhwdev->pf_to_mgmt); 746 } 747 748 /** 749 * hinic_init_hwdev - Initialize the NIC HW 750 * @pdev: the NIC pci device 751 * 752 * Return initialized NIC HW device 753 * 754 * Initialize the NIC HW device and return a pointer to it 755 **/ 756 struct hinic_hwdev *hinic_init_hwdev(struct pci_dev *pdev) 757 { 758 struct hinic_pfhwdev *pfhwdev; 759 struct hinic_hwdev *hwdev; 760 struct hinic_hwif *hwif; 761 int err, num_aeqs; 762 763 hwif = devm_kzalloc(&pdev->dev, sizeof(*hwif), GFP_KERNEL); 764 if (!hwif) 765 return ERR_PTR(-ENOMEM); 766 767 err = hinic_init_hwif(hwif, pdev); 768 if (err) { 769 dev_err(&pdev->dev, "Failed to init HW interface\n"); 770 return ERR_PTR(err); 771 } 772 773 if (!HINIC_IS_PF(hwif) && !HINIC_IS_PPF(hwif)) { 774 dev_err(&pdev->dev, "Unsupported PCI Function type\n"); 775 err = -EFAULT; 776 goto err_func_type; 777 } 778 779 pfhwdev = devm_kzalloc(&pdev->dev, sizeof(*pfhwdev), GFP_KERNEL); 780 if (!pfhwdev) { 781 err = -ENOMEM; 782 goto err_pfhwdev_alloc; 783 } 784 785 hwdev = &pfhwdev->hwdev; 786 hwdev->hwif = hwif; 787 788 err = init_msix(hwdev); 789 if (err) { 790 dev_err(&pdev->dev, "Failed to init msix\n"); 791 goto err_init_msix; 792 } 793 794 err = wait_for_outbound_state(hwdev); 795 if (err) { 796 dev_warn(&pdev->dev, "outbound - disabled, try again\n"); 797 hinic_outbound_state_set(hwif, HINIC_OUTBOUND_ENABLE); 798 } 799 800 num_aeqs = HINIC_HWIF_NUM_AEQS(hwif); 801 802 err = hinic_aeqs_init(&hwdev->aeqs, hwif, num_aeqs, 803 HINIC_DEFAULT_AEQ_LEN, HINIC_EQ_PAGE_SIZE, 804 hwdev->msix_entries); 805 if (err) { 806 dev_err(&pdev->dev, "Failed to init async event queues\n"); 807 goto err_aeqs_init; 808 } 809 810 err = init_pfhwdev(pfhwdev); 811 if (err) { 812 dev_err(&pdev->dev, "Failed to init PF HW device\n"); 813 goto err_init_pfhwdev; 814 } 815 816 err = get_dev_cap(hwdev); 817 if (err) { 818 dev_err(&pdev->dev, "Failed to get device capabilities\n"); 819 goto err_dev_cap; 820 } 821 822 err = init_fw_ctxt(hwdev); 823 if (err) { 824 dev_err(&pdev->dev, "Failed to init function table\n"); 825 goto err_init_fw_ctxt; 826 } 827 828 err = set_resources_state(hwdev, HINIC_RES_ACTIVE); 829 if (err) { 830 dev_err(&pdev->dev, "Failed to set resources state\n"); 831 goto err_resources_state; 832 } 833 834 return hwdev; 835 836 err_resources_state: 837 err_init_fw_ctxt: 838 err_dev_cap: 839 free_pfhwdev(pfhwdev); 840 841 err_init_pfhwdev: 842 hinic_aeqs_free(&hwdev->aeqs); 843 844 err_aeqs_init: 845 disable_msix(hwdev); 846 847 err_init_msix: 848 err_pfhwdev_alloc: 849 err_func_type: 850 hinic_free_hwif(hwif); 851 return ERR_PTR(err); 852 } 853 854 /** 855 * hinic_free_hwdev - Free the NIC HW device 856 * @hwdev: the NIC HW device 857 **/ 858 void hinic_free_hwdev(struct hinic_hwdev *hwdev) 859 { 860 struct hinic_pfhwdev *pfhwdev = container_of(hwdev, 861 struct hinic_pfhwdev, 862 hwdev); 863 864 set_resources_state(hwdev, HINIC_RES_CLEAN); 865 866 free_pfhwdev(pfhwdev); 867 868 hinic_aeqs_free(&hwdev->aeqs); 869 870 disable_msix(hwdev); 871 872 hinic_free_hwif(hwdev->hwif); 873 } 874 875 /** 876 * hinic_hwdev_num_qps - return the number QPs available for use 877 * @hwdev: the NIC HW device 878 * 879 * Return number QPs available for use 880 **/ 881 int hinic_hwdev_num_qps(struct hinic_hwdev *hwdev) 882 { 883 struct hinic_cap *nic_cap = &hwdev->nic_cap; 884 885 return nic_cap->num_qps; 886 } 887 888 /** 889 * hinic_hwdev_get_sq - get SQ 890 * @hwdev: the NIC HW device 891 * @i: the position of the SQ 892 * 893 * Return: the SQ in the i position 894 **/ 895 struct hinic_sq *hinic_hwdev_get_sq(struct hinic_hwdev *hwdev, int i) 896 { 897 struct hinic_func_to_io *func_to_io = &hwdev->func_to_io; 898 struct hinic_qp *qp = &func_to_io->qps[i]; 899 900 if (i >= hinic_hwdev_num_qps(hwdev)) 901 return NULL; 902 903 return &qp->sq; 904 } 905 906 /** 907 * hinic_hwdev_get_sq - get RQ 908 * @hwdev: the NIC HW device 909 * @i: the position of the RQ 910 * 911 * Return: the RQ in the i position 912 **/ 913 struct hinic_rq *hinic_hwdev_get_rq(struct hinic_hwdev *hwdev, int i) 914 { 915 struct hinic_func_to_io *func_to_io = &hwdev->func_to_io; 916 struct hinic_qp *qp = &func_to_io->qps[i]; 917 918 if (i >= hinic_hwdev_num_qps(hwdev)) 919 return NULL; 920 921 return &qp->rq; 922 } 923 924 /** 925 * hinic_hwdev_msix_cnt_set - clear message attribute counters for msix entry 926 * @hwdev: the NIC HW device 927 * @msix_index: msix_index 928 * 929 * Return 0 - Success, negative - Failure 930 **/ 931 int hinic_hwdev_msix_cnt_set(struct hinic_hwdev *hwdev, u16 msix_index) 932 { 933 return hinic_msix_attr_cnt_clear(hwdev->hwif, msix_index); 934 } 935 936 /** 937 * hinic_hwdev_msix_set - set message attribute for msix entry 938 * @hwdev: the NIC HW device 939 * @msix_index: msix_index 940 * @pending_limit: the maximum pending interrupt events (unit 8) 941 * @coalesc_timer: coalesc period for interrupt (unit 8 us) 942 * @lli_timer: replenishing period for low latency credit (unit 8 us) 943 * @lli_credit_limit: maximum credits for low latency msix messages (unit 8) 944 * @resend_timer: maximum wait for resending msix (unit coalesc period) 945 * 946 * Return 0 - Success, negative - Failure 947 **/ 948 int hinic_hwdev_msix_set(struct hinic_hwdev *hwdev, u16 msix_index, 949 u8 pending_limit, u8 coalesc_timer, 950 u8 lli_timer_cfg, u8 lli_credit_limit, 951 u8 resend_timer) 952 { 953 return hinic_msix_attr_set(hwdev->hwif, msix_index, 954 pending_limit, coalesc_timer, 955 lli_timer_cfg, lli_credit_limit, 956 resend_timer); 957 } 958 959 /** 960 * hinic_hwdev_hw_ci_addr_set - set cons idx addr and attributes in HW for sq 961 * @hwdev: the NIC HW device 962 * @sq: send queue 963 * @pending_limit: the maximum pending update ci events (unit 8) 964 * @coalesc_timer: coalesc period for update ci (unit 8 us) 965 * 966 * Return 0 - Success, negative - Failure 967 **/ 968 int hinic_hwdev_hw_ci_addr_set(struct hinic_hwdev *hwdev, struct hinic_sq *sq, 969 u8 pending_limit, u8 coalesc_timer) 970 { 971 struct hinic_qp *qp = container_of(sq, struct hinic_qp, sq); 972 struct hinic_hwif *hwif = hwdev->hwif; 973 struct pci_dev *pdev = hwif->pdev; 974 struct hinic_pfhwdev *pfhwdev; 975 struct hinic_cmd_hw_ci hw_ci; 976 977 if (!HINIC_IS_PF(hwif) && !HINIC_IS_PPF(hwif)) { 978 dev_err(&pdev->dev, "Unsupported PCI Function type\n"); 979 return -EINVAL; 980 } 981 982 hw_ci.dma_attr_off = 0; 983 hw_ci.pending_limit = pending_limit; 984 hw_ci.coalesc_timer = coalesc_timer; 985 986 hw_ci.msix_en = 1; 987 hw_ci.msix_entry_idx = sq->msix_entry; 988 989 hw_ci.func_idx = HINIC_HWIF_FUNC_IDX(hwif); 990 991 hw_ci.sq_id = qp->q_id; 992 993 hw_ci.ci_addr = ADDR_IN_4BYTES(sq->hw_ci_dma_addr); 994 995 pfhwdev = container_of(hwdev, struct hinic_pfhwdev, hwdev); 996 return hinic_msg_to_mgmt(&pfhwdev->pf_to_mgmt, 997 HINIC_MOD_COMM, 998 HINIC_COMM_CMD_SQ_HI_CI_SET, 999 &hw_ci, sizeof(hw_ci), NULL, 1000 NULL, HINIC_MGMT_MSG_SYNC); 1001 } 1002 1003 /** 1004 * hinic_hwdev_set_msix_state- set msix state 1005 * @hwdev: the NIC HW device 1006 * @msix_index: IRQ corresponding index number 1007 * @flag: msix state 1008 * 1009 **/ 1010 void hinic_hwdev_set_msix_state(struct hinic_hwdev *hwdev, u16 msix_index, 1011 enum hinic_msix_state flag) 1012 { 1013 hinic_set_msix_state(hwdev->hwif, msix_index, flag); 1014 } 1015