1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Huawei HiNIC PCI Express Linux driver 4 * Copyright(c) 2017 Huawei Technologies Co., Ltd 5 */ 6 7 #include <linux/kernel.h> 8 #include <linux/types.h> 9 #include <linux/pci.h> 10 #include <linux/device.h> 11 #include <linux/errno.h> 12 #include <linux/slab.h> 13 #include <linux/bitops.h> 14 #include <linux/delay.h> 15 #include <linux/jiffies.h> 16 #include <linux/log2.h> 17 #include <linux/err.h> 18 19 #include "hinic_hw_if.h" 20 #include "hinic_hw_eqs.h" 21 #include "hinic_hw_mgmt.h" 22 #include "hinic_hw_qp_ctxt.h" 23 #include "hinic_hw_qp.h" 24 #include "hinic_hw_io.h" 25 #include "hinic_hw_dev.h" 26 27 #define IO_STATUS_TIMEOUT 100 28 #define OUTBOUND_STATE_TIMEOUT 100 29 #define DB_STATE_TIMEOUT 100 30 31 #define MAX_IRQS(max_qps, num_aeqs, num_ceqs) \ 32 (2 * (max_qps) + (num_aeqs) + (num_ceqs)) 33 34 #define ADDR_IN_4BYTES(addr) ((addr) >> 2) 35 36 enum intr_type { 37 INTR_MSIX_TYPE, 38 }; 39 40 enum io_status { 41 IO_STOPPED = 0, 42 IO_RUNNING = 1, 43 }; 44 45 enum hw_ioctxt_set_cmdq_depth { 46 HW_IOCTXT_SET_CMDQ_DEPTH_DEFAULT, 47 }; 48 49 /* HW struct */ 50 struct hinic_dev_cap { 51 u8 status; 52 u8 version; 53 u8 rsvd0[6]; 54 55 u8 rsvd1[5]; 56 u8 intr_type; 57 u8 rsvd2[66]; 58 u16 max_sqs; 59 u16 max_rqs; 60 u8 rsvd3[208]; 61 }; 62 63 /** 64 * get_capability - convert device capabilities to NIC capabilities 65 * @hwdev: the HW device to set and convert device capabilities for 66 * @dev_cap: device capabilities from FW 67 * 68 * Return 0 - Success, negative - Failure 69 **/ 70 static int get_capability(struct hinic_hwdev *hwdev, 71 struct hinic_dev_cap *dev_cap) 72 { 73 struct hinic_cap *nic_cap = &hwdev->nic_cap; 74 int num_aeqs, num_ceqs, num_irqs; 75 76 if (!HINIC_IS_PF(hwdev->hwif) && !HINIC_IS_PPF(hwdev->hwif)) 77 return -EINVAL; 78 79 if (dev_cap->intr_type != INTR_MSIX_TYPE) 80 return -EFAULT; 81 82 num_aeqs = HINIC_HWIF_NUM_AEQS(hwdev->hwif); 83 num_ceqs = HINIC_HWIF_NUM_CEQS(hwdev->hwif); 84 num_irqs = HINIC_HWIF_NUM_IRQS(hwdev->hwif); 85 86 /* Each QP has its own (SQ + RQ) interrupts */ 87 nic_cap->num_qps = (num_irqs - (num_aeqs + num_ceqs)) / 2; 88 89 if (nic_cap->num_qps > HINIC_Q_CTXT_MAX) 90 nic_cap->num_qps = HINIC_Q_CTXT_MAX; 91 92 nic_cap->max_qps = dev_cap->max_sqs + 1; 93 if (nic_cap->max_qps != (dev_cap->max_rqs + 1)) 94 return -EFAULT; 95 96 if (nic_cap->num_qps > nic_cap->max_qps) 97 nic_cap->num_qps = nic_cap->max_qps; 98 99 return 0; 100 } 101 102 /** 103 * get_cap_from_fw - get device capabilities from FW 104 * @pfhwdev: the PF HW device to get capabilities for 105 * 106 * Return 0 - Success, negative - Failure 107 **/ 108 static int get_cap_from_fw(struct hinic_pfhwdev *pfhwdev) 109 { 110 struct hinic_hwdev *hwdev = &pfhwdev->hwdev; 111 struct hinic_hwif *hwif = hwdev->hwif; 112 struct pci_dev *pdev = hwif->pdev; 113 struct hinic_dev_cap dev_cap; 114 u16 in_len, out_len; 115 int err; 116 117 in_len = 0; 118 out_len = sizeof(dev_cap); 119 120 err = hinic_msg_to_mgmt(&pfhwdev->pf_to_mgmt, HINIC_MOD_CFGM, 121 HINIC_CFG_NIC_CAP, &dev_cap, in_len, &dev_cap, 122 &out_len, HINIC_MGMT_MSG_SYNC); 123 if (err) { 124 dev_err(&pdev->dev, "Failed to get capability from FW\n"); 125 return err; 126 } 127 128 return get_capability(hwdev, &dev_cap); 129 } 130 131 /** 132 * get_dev_cap - get device capabilities 133 * @hwdev: the NIC HW device to get capabilities for 134 * 135 * Return 0 - Success, negative - Failure 136 **/ 137 static int get_dev_cap(struct hinic_hwdev *hwdev) 138 { 139 struct hinic_hwif *hwif = hwdev->hwif; 140 struct pci_dev *pdev = hwif->pdev; 141 struct hinic_pfhwdev *pfhwdev; 142 int err; 143 144 switch (HINIC_FUNC_TYPE(hwif)) { 145 case HINIC_PPF: 146 case HINIC_PF: 147 pfhwdev = container_of(hwdev, struct hinic_pfhwdev, hwdev); 148 149 err = get_cap_from_fw(pfhwdev); 150 if (err) { 151 dev_err(&pdev->dev, "Failed to get capability from FW\n"); 152 return err; 153 } 154 break; 155 156 default: 157 dev_err(&pdev->dev, "Unsupported PCI Function type\n"); 158 return -EINVAL; 159 } 160 161 return 0; 162 } 163 164 /** 165 * init_msix - enable the msix and save the entries 166 * @hwdev: the NIC HW device 167 * 168 * Return 0 - Success, negative - Failure 169 **/ 170 static int init_msix(struct hinic_hwdev *hwdev) 171 { 172 struct hinic_hwif *hwif = hwdev->hwif; 173 struct pci_dev *pdev = hwif->pdev; 174 int nr_irqs, num_aeqs, num_ceqs; 175 size_t msix_entries_size; 176 int i, err; 177 178 num_aeqs = HINIC_HWIF_NUM_AEQS(hwif); 179 num_ceqs = HINIC_HWIF_NUM_CEQS(hwif); 180 nr_irqs = MAX_IRQS(HINIC_MAX_QPS, num_aeqs, num_ceqs); 181 if (nr_irqs > HINIC_HWIF_NUM_IRQS(hwif)) 182 nr_irqs = HINIC_HWIF_NUM_IRQS(hwif); 183 184 msix_entries_size = nr_irqs * sizeof(*hwdev->msix_entries); 185 hwdev->msix_entries = devm_kzalloc(&pdev->dev, msix_entries_size, 186 GFP_KERNEL); 187 if (!hwdev->msix_entries) 188 return -ENOMEM; 189 190 for (i = 0; i < nr_irqs; i++) 191 hwdev->msix_entries[i].entry = i; 192 193 err = pci_enable_msix_exact(pdev, hwdev->msix_entries, nr_irqs); 194 if (err) { 195 dev_err(&pdev->dev, "Failed to enable pci msix\n"); 196 return err; 197 } 198 199 return 0; 200 } 201 202 /** 203 * disable_msix - disable the msix 204 * @hwdev: the NIC HW device 205 **/ 206 static void disable_msix(struct hinic_hwdev *hwdev) 207 { 208 struct hinic_hwif *hwif = hwdev->hwif; 209 struct pci_dev *pdev = hwif->pdev; 210 211 pci_disable_msix(pdev); 212 } 213 214 /** 215 * hinic_port_msg_cmd - send port msg to mgmt 216 * @hwdev: the NIC HW device 217 * @cmd: the port command 218 * @buf_in: input buffer 219 * @in_size: input size 220 * @buf_out: output buffer 221 * @out_size: returned output size 222 * 223 * Return 0 - Success, negative - Failure 224 **/ 225 int hinic_port_msg_cmd(struct hinic_hwdev *hwdev, enum hinic_port_cmd cmd, 226 void *buf_in, u16 in_size, void *buf_out, u16 *out_size) 227 { 228 struct hinic_hwif *hwif = hwdev->hwif; 229 struct pci_dev *pdev = hwif->pdev; 230 struct hinic_pfhwdev *pfhwdev; 231 232 if (!HINIC_IS_PF(hwif) && !HINIC_IS_PPF(hwif)) { 233 dev_err(&pdev->dev, "unsupported PCI Function type\n"); 234 return -EINVAL; 235 } 236 237 pfhwdev = container_of(hwdev, struct hinic_pfhwdev, hwdev); 238 239 return hinic_msg_to_mgmt(&pfhwdev->pf_to_mgmt, HINIC_MOD_L2NIC, cmd, 240 buf_in, in_size, buf_out, out_size, 241 HINIC_MGMT_MSG_SYNC); 242 } 243 244 /** 245 * init_fw_ctxt- Init Firmware tables before network mgmt and io operations 246 * @hwdev: the NIC HW device 247 * 248 * Return 0 - Success, negative - Failure 249 **/ 250 static int init_fw_ctxt(struct hinic_hwdev *hwdev) 251 { 252 struct hinic_hwif *hwif = hwdev->hwif; 253 struct pci_dev *pdev = hwif->pdev; 254 struct hinic_cmd_fw_ctxt fw_ctxt; 255 u16 out_size; 256 int err; 257 258 if (!HINIC_IS_PF(hwif) && !HINIC_IS_PPF(hwif)) { 259 dev_err(&pdev->dev, "Unsupported PCI Function type\n"); 260 return -EINVAL; 261 } 262 263 fw_ctxt.func_idx = HINIC_HWIF_FUNC_IDX(hwif); 264 fw_ctxt.rx_buf_sz = HINIC_RX_BUF_SZ; 265 266 err = hinic_port_msg_cmd(hwdev, HINIC_PORT_CMD_FWCTXT_INIT, 267 &fw_ctxt, sizeof(fw_ctxt), 268 &fw_ctxt, &out_size); 269 if (err || (out_size != sizeof(fw_ctxt)) || fw_ctxt.status) { 270 dev_err(&pdev->dev, "Failed to init FW ctxt, ret = %d\n", 271 fw_ctxt.status); 272 return -EFAULT; 273 } 274 275 return 0; 276 } 277 278 /** 279 * set_hw_ioctxt - set the shape of the IO queues in FW 280 * @hwdev: the NIC HW device 281 * @rq_depth: rq depth 282 * @sq_depth: sq depth 283 * 284 * Return 0 - Success, negative - Failure 285 **/ 286 static int set_hw_ioctxt(struct hinic_hwdev *hwdev, unsigned int rq_depth, 287 unsigned int sq_depth) 288 { 289 struct hinic_hwif *hwif = hwdev->hwif; 290 struct hinic_cmd_hw_ioctxt hw_ioctxt; 291 struct pci_dev *pdev = hwif->pdev; 292 struct hinic_pfhwdev *pfhwdev; 293 294 if (!HINIC_IS_PF(hwif) && !HINIC_IS_PPF(hwif)) { 295 dev_err(&pdev->dev, "Unsupported PCI Function type\n"); 296 return -EINVAL; 297 } 298 299 hw_ioctxt.func_idx = HINIC_HWIF_FUNC_IDX(hwif); 300 301 hw_ioctxt.set_cmdq_depth = HW_IOCTXT_SET_CMDQ_DEPTH_DEFAULT; 302 hw_ioctxt.cmdq_depth = 0; 303 304 hw_ioctxt.lro_en = 1; 305 306 hw_ioctxt.rq_depth = ilog2(rq_depth); 307 308 hw_ioctxt.rx_buf_sz_idx = HINIC_RX_BUF_SZ_IDX; 309 310 hw_ioctxt.sq_depth = ilog2(sq_depth); 311 312 pfhwdev = container_of(hwdev, struct hinic_pfhwdev, hwdev); 313 314 return hinic_msg_to_mgmt(&pfhwdev->pf_to_mgmt, HINIC_MOD_COMM, 315 HINIC_COMM_CMD_HWCTXT_SET, 316 &hw_ioctxt, sizeof(hw_ioctxt), NULL, 317 NULL, HINIC_MGMT_MSG_SYNC); 318 } 319 320 static int wait_for_outbound_state(struct hinic_hwdev *hwdev) 321 { 322 enum hinic_outbound_state outbound_state; 323 struct hinic_hwif *hwif = hwdev->hwif; 324 struct pci_dev *pdev = hwif->pdev; 325 unsigned long end; 326 327 end = jiffies + msecs_to_jiffies(OUTBOUND_STATE_TIMEOUT); 328 do { 329 outbound_state = hinic_outbound_state_get(hwif); 330 331 if (outbound_state == HINIC_OUTBOUND_ENABLE) 332 return 0; 333 334 msleep(20); 335 } while (time_before(jiffies, end)); 336 337 dev_err(&pdev->dev, "Wait for OUTBOUND - Timeout\n"); 338 return -EFAULT; 339 } 340 341 static int wait_for_db_state(struct hinic_hwdev *hwdev) 342 { 343 struct hinic_hwif *hwif = hwdev->hwif; 344 struct pci_dev *pdev = hwif->pdev; 345 enum hinic_db_state db_state; 346 unsigned long end; 347 348 end = jiffies + msecs_to_jiffies(DB_STATE_TIMEOUT); 349 do { 350 db_state = hinic_db_state_get(hwif); 351 352 if (db_state == HINIC_DB_ENABLE) 353 return 0; 354 355 msleep(20); 356 } while (time_before(jiffies, end)); 357 358 dev_err(&pdev->dev, "Wait for DB - Timeout\n"); 359 return -EFAULT; 360 } 361 362 static int wait_for_io_stopped(struct hinic_hwdev *hwdev) 363 { 364 struct hinic_cmd_io_status cmd_io_status; 365 struct hinic_hwif *hwif = hwdev->hwif; 366 struct pci_dev *pdev = hwif->pdev; 367 struct hinic_pfhwdev *pfhwdev; 368 unsigned long end; 369 u16 out_size; 370 int err; 371 372 if (!HINIC_IS_PF(hwif) && !HINIC_IS_PPF(hwif)) { 373 dev_err(&pdev->dev, "Unsupported PCI Function type\n"); 374 return -EINVAL; 375 } 376 377 pfhwdev = container_of(hwdev, struct hinic_pfhwdev, hwdev); 378 379 cmd_io_status.func_idx = HINIC_HWIF_FUNC_IDX(hwif); 380 381 end = jiffies + msecs_to_jiffies(IO_STATUS_TIMEOUT); 382 do { 383 err = hinic_msg_to_mgmt(&pfhwdev->pf_to_mgmt, HINIC_MOD_COMM, 384 HINIC_COMM_CMD_IO_STATUS_GET, 385 &cmd_io_status, sizeof(cmd_io_status), 386 &cmd_io_status, &out_size, 387 HINIC_MGMT_MSG_SYNC); 388 if ((err) || (out_size != sizeof(cmd_io_status))) { 389 dev_err(&pdev->dev, "Failed to get IO status, ret = %d\n", 390 err); 391 return err; 392 } 393 394 if (cmd_io_status.status == IO_STOPPED) { 395 dev_info(&pdev->dev, "IO stopped\n"); 396 return 0; 397 } 398 399 msleep(20); 400 } while (time_before(jiffies, end)); 401 402 dev_err(&pdev->dev, "Wait for IO stopped - Timeout\n"); 403 return -ETIMEDOUT; 404 } 405 406 /** 407 * clear_io_resource - set the IO resources as not active in the NIC 408 * @hwdev: the NIC HW device 409 * 410 * Return 0 - Success, negative - Failure 411 **/ 412 static int clear_io_resources(struct hinic_hwdev *hwdev) 413 { 414 struct hinic_cmd_clear_io_res cmd_clear_io_res; 415 struct hinic_hwif *hwif = hwdev->hwif; 416 struct pci_dev *pdev = hwif->pdev; 417 struct hinic_pfhwdev *pfhwdev; 418 int err; 419 420 if (!HINIC_IS_PF(hwif) && !HINIC_IS_PPF(hwif)) { 421 dev_err(&pdev->dev, "Unsupported PCI Function type\n"); 422 return -EINVAL; 423 } 424 425 err = wait_for_io_stopped(hwdev); 426 if (err) { 427 dev_err(&pdev->dev, "IO has not stopped yet\n"); 428 return err; 429 } 430 431 cmd_clear_io_res.func_idx = HINIC_HWIF_FUNC_IDX(hwif); 432 433 pfhwdev = container_of(hwdev, struct hinic_pfhwdev, hwdev); 434 435 err = hinic_msg_to_mgmt(&pfhwdev->pf_to_mgmt, HINIC_MOD_COMM, 436 HINIC_COMM_CMD_IO_RES_CLEAR, &cmd_clear_io_res, 437 sizeof(cmd_clear_io_res), NULL, NULL, 438 HINIC_MGMT_MSG_SYNC); 439 if (err) { 440 dev_err(&pdev->dev, "Failed to clear IO resources\n"); 441 return err; 442 } 443 444 return 0; 445 } 446 447 /** 448 * set_resources_state - set the state of the resources in the NIC 449 * @hwdev: the NIC HW device 450 * @state: the state to set 451 * 452 * Return 0 - Success, negative - Failure 453 **/ 454 static int set_resources_state(struct hinic_hwdev *hwdev, 455 enum hinic_res_state state) 456 { 457 struct hinic_cmd_set_res_state res_state; 458 struct hinic_hwif *hwif = hwdev->hwif; 459 struct pci_dev *pdev = hwif->pdev; 460 struct hinic_pfhwdev *pfhwdev; 461 462 if (!HINIC_IS_PF(hwif) && !HINIC_IS_PPF(hwif)) { 463 dev_err(&pdev->dev, "Unsupported PCI Function type\n"); 464 return -EINVAL; 465 } 466 467 res_state.func_idx = HINIC_HWIF_FUNC_IDX(hwif); 468 res_state.state = state; 469 470 pfhwdev = container_of(hwdev, struct hinic_pfhwdev, hwdev); 471 472 return hinic_msg_to_mgmt(&pfhwdev->pf_to_mgmt, 473 HINIC_MOD_COMM, 474 HINIC_COMM_CMD_RES_STATE_SET, 475 &res_state, sizeof(res_state), NULL, 476 NULL, HINIC_MGMT_MSG_SYNC); 477 } 478 479 /** 480 * get_base_qpn - get the first qp number 481 * @hwdev: the NIC HW device 482 * @base_qpn: returned qp number 483 * 484 * Return 0 - Success, negative - Failure 485 **/ 486 static int get_base_qpn(struct hinic_hwdev *hwdev, u16 *base_qpn) 487 { 488 struct hinic_cmd_base_qpn cmd_base_qpn; 489 struct hinic_hwif *hwif = hwdev->hwif; 490 struct pci_dev *pdev = hwif->pdev; 491 u16 out_size; 492 int err; 493 494 cmd_base_qpn.func_idx = HINIC_HWIF_FUNC_IDX(hwif); 495 496 err = hinic_port_msg_cmd(hwdev, HINIC_PORT_CMD_GET_GLOBAL_QPN, 497 &cmd_base_qpn, sizeof(cmd_base_qpn), 498 &cmd_base_qpn, &out_size); 499 if (err || (out_size != sizeof(cmd_base_qpn)) || cmd_base_qpn.status) { 500 dev_err(&pdev->dev, "Failed to get base qpn, status = %d\n", 501 cmd_base_qpn.status); 502 return -EFAULT; 503 } 504 505 *base_qpn = cmd_base_qpn.qpn; 506 return 0; 507 } 508 509 /** 510 * hinic_hwdev_ifup - Preparing the HW for passing IO 511 * @hwdev: the NIC HW device 512 * 513 * Return 0 - Success, negative - Failure 514 **/ 515 int hinic_hwdev_ifup(struct hinic_hwdev *hwdev) 516 { 517 struct hinic_func_to_io *func_to_io = &hwdev->func_to_io; 518 struct hinic_cap *nic_cap = &hwdev->nic_cap; 519 struct hinic_hwif *hwif = hwdev->hwif; 520 int err, num_aeqs, num_ceqs, num_qps; 521 struct msix_entry *ceq_msix_entries; 522 struct msix_entry *sq_msix_entries; 523 struct msix_entry *rq_msix_entries; 524 struct pci_dev *pdev = hwif->pdev; 525 u16 base_qpn; 526 527 err = get_base_qpn(hwdev, &base_qpn); 528 if (err) { 529 dev_err(&pdev->dev, "Failed to get global base qp number\n"); 530 return err; 531 } 532 533 num_aeqs = HINIC_HWIF_NUM_AEQS(hwif); 534 num_ceqs = HINIC_HWIF_NUM_CEQS(hwif); 535 536 ceq_msix_entries = &hwdev->msix_entries[num_aeqs]; 537 538 err = hinic_io_init(func_to_io, hwif, nic_cap->max_qps, num_ceqs, 539 ceq_msix_entries); 540 if (err) { 541 dev_err(&pdev->dev, "Failed to init IO channel\n"); 542 return err; 543 } 544 545 num_qps = nic_cap->num_qps; 546 sq_msix_entries = &hwdev->msix_entries[num_aeqs + num_ceqs]; 547 rq_msix_entries = &hwdev->msix_entries[num_aeqs + num_ceqs + num_qps]; 548 549 err = hinic_io_create_qps(func_to_io, base_qpn, num_qps, 550 sq_msix_entries, rq_msix_entries); 551 if (err) { 552 dev_err(&pdev->dev, "Failed to create QPs\n"); 553 goto err_create_qps; 554 } 555 556 err = wait_for_db_state(hwdev); 557 if (err) { 558 dev_warn(&pdev->dev, "db - disabled, try again\n"); 559 hinic_db_state_set(hwif, HINIC_DB_ENABLE); 560 } 561 562 err = set_hw_ioctxt(hwdev, HINIC_SQ_DEPTH, HINIC_RQ_DEPTH); 563 if (err) { 564 dev_err(&pdev->dev, "Failed to set HW IO ctxt\n"); 565 goto err_hw_ioctxt; 566 } 567 568 return 0; 569 570 err_hw_ioctxt: 571 hinic_io_destroy_qps(func_to_io, num_qps); 572 573 err_create_qps: 574 hinic_io_free(func_to_io); 575 return err; 576 } 577 578 /** 579 * hinic_hwdev_ifdown - Closing the HW for passing IO 580 * @hwdev: the NIC HW device 581 * 582 **/ 583 void hinic_hwdev_ifdown(struct hinic_hwdev *hwdev) 584 { 585 struct hinic_func_to_io *func_to_io = &hwdev->func_to_io; 586 struct hinic_cap *nic_cap = &hwdev->nic_cap; 587 588 clear_io_resources(hwdev); 589 590 hinic_io_destroy_qps(func_to_io, nic_cap->num_qps); 591 hinic_io_free(func_to_io); 592 } 593 594 /** 595 * hinic_hwdev_cb_register - register callback handler for MGMT events 596 * @hwdev: the NIC HW device 597 * @cmd: the mgmt event 598 * @handle: private data for the handler 599 * @handler: event handler 600 **/ 601 void hinic_hwdev_cb_register(struct hinic_hwdev *hwdev, 602 enum hinic_mgmt_msg_cmd cmd, void *handle, 603 void (*handler)(void *handle, void *buf_in, 604 u16 in_size, void *buf_out, 605 u16 *out_size)) 606 { 607 struct hinic_hwif *hwif = hwdev->hwif; 608 struct pci_dev *pdev = hwif->pdev; 609 struct hinic_pfhwdev *pfhwdev; 610 struct hinic_nic_cb *nic_cb; 611 u8 cmd_cb; 612 613 if (!HINIC_IS_PF(hwif) && !HINIC_IS_PPF(hwif)) { 614 dev_err(&pdev->dev, "unsupported PCI Function type\n"); 615 return; 616 } 617 618 pfhwdev = container_of(hwdev, struct hinic_pfhwdev, hwdev); 619 620 cmd_cb = cmd - HINIC_MGMT_MSG_CMD_BASE; 621 nic_cb = &pfhwdev->nic_cb[cmd_cb]; 622 623 nic_cb->handler = handler; 624 nic_cb->handle = handle; 625 nic_cb->cb_state = HINIC_CB_ENABLED; 626 } 627 628 /** 629 * hinic_hwdev_cb_unregister - unregister callback handler for MGMT events 630 * @hwdev: the NIC HW device 631 * @cmd: the mgmt event 632 **/ 633 void hinic_hwdev_cb_unregister(struct hinic_hwdev *hwdev, 634 enum hinic_mgmt_msg_cmd cmd) 635 { 636 struct hinic_hwif *hwif = hwdev->hwif; 637 struct pci_dev *pdev = hwif->pdev; 638 struct hinic_pfhwdev *pfhwdev; 639 struct hinic_nic_cb *nic_cb; 640 u8 cmd_cb; 641 642 if (!HINIC_IS_PF(hwif) && !HINIC_IS_PPF(hwif)) { 643 dev_err(&pdev->dev, "unsupported PCI Function type\n"); 644 return; 645 } 646 647 pfhwdev = container_of(hwdev, struct hinic_pfhwdev, hwdev); 648 649 cmd_cb = cmd - HINIC_MGMT_MSG_CMD_BASE; 650 nic_cb = &pfhwdev->nic_cb[cmd_cb]; 651 652 nic_cb->cb_state &= ~HINIC_CB_ENABLED; 653 654 while (nic_cb->cb_state & HINIC_CB_RUNNING) 655 schedule(); 656 657 nic_cb->handler = NULL; 658 } 659 660 /** 661 * nic_mgmt_msg_handler - nic mgmt event handler 662 * @handle: private data for the handler 663 * @buf_in: input buffer 664 * @in_size: input size 665 * @buf_out: output buffer 666 * @out_size: returned output size 667 **/ 668 static void nic_mgmt_msg_handler(void *handle, u8 cmd, void *buf_in, 669 u16 in_size, void *buf_out, u16 *out_size) 670 { 671 struct hinic_pfhwdev *pfhwdev = handle; 672 enum hinic_cb_state cb_state; 673 struct hinic_nic_cb *nic_cb; 674 struct hinic_hwdev *hwdev; 675 struct hinic_hwif *hwif; 676 struct pci_dev *pdev; 677 u8 cmd_cb; 678 679 hwdev = &pfhwdev->hwdev; 680 hwif = hwdev->hwif; 681 pdev = hwif->pdev; 682 683 if ((cmd < HINIC_MGMT_MSG_CMD_BASE) || 684 (cmd >= HINIC_MGMT_MSG_CMD_MAX)) { 685 dev_err(&pdev->dev, "unknown L2NIC event, cmd = %d\n", cmd); 686 return; 687 } 688 689 cmd_cb = cmd - HINIC_MGMT_MSG_CMD_BASE; 690 691 nic_cb = &pfhwdev->nic_cb[cmd_cb]; 692 693 cb_state = cmpxchg(&nic_cb->cb_state, 694 HINIC_CB_ENABLED, 695 HINIC_CB_ENABLED | HINIC_CB_RUNNING); 696 697 if ((cb_state == HINIC_CB_ENABLED) && (nic_cb->handler)) 698 nic_cb->handler(nic_cb->handle, buf_in, 699 in_size, buf_out, out_size); 700 else 701 dev_err(&pdev->dev, "Unhandled NIC Event %d\n", cmd); 702 703 nic_cb->cb_state &= ~HINIC_CB_RUNNING; 704 } 705 706 /** 707 * init_pfhwdev - Initialize the extended components of PF 708 * @pfhwdev: the HW device for PF 709 * 710 * Return 0 - success, negative - failure 711 **/ 712 static int init_pfhwdev(struct hinic_pfhwdev *pfhwdev) 713 { 714 struct hinic_hwdev *hwdev = &pfhwdev->hwdev; 715 struct hinic_hwif *hwif = hwdev->hwif; 716 struct pci_dev *pdev = hwif->pdev; 717 int err; 718 719 err = hinic_pf_to_mgmt_init(&pfhwdev->pf_to_mgmt, hwif); 720 if (err) { 721 dev_err(&pdev->dev, "Failed to initialize PF to MGMT channel\n"); 722 return err; 723 } 724 725 hinic_register_mgmt_msg_cb(&pfhwdev->pf_to_mgmt, HINIC_MOD_L2NIC, 726 pfhwdev, nic_mgmt_msg_handler); 727 728 hinic_set_pf_action(hwif, HINIC_PF_MGMT_ACTIVE); 729 return 0; 730 } 731 732 /** 733 * free_pfhwdev - Free the extended components of PF 734 * @pfhwdev: the HW device for PF 735 **/ 736 static void free_pfhwdev(struct hinic_pfhwdev *pfhwdev) 737 { 738 struct hinic_hwdev *hwdev = &pfhwdev->hwdev; 739 740 hinic_set_pf_action(hwdev->hwif, HINIC_PF_MGMT_INIT); 741 742 hinic_unregister_mgmt_msg_cb(&pfhwdev->pf_to_mgmt, HINIC_MOD_L2NIC); 743 744 hinic_pf_to_mgmt_free(&pfhwdev->pf_to_mgmt); 745 } 746 747 /** 748 * hinic_init_hwdev - Initialize the NIC HW 749 * @pdev: the NIC pci device 750 * 751 * Return initialized NIC HW device 752 * 753 * Initialize the NIC HW device and return a pointer to it 754 **/ 755 struct hinic_hwdev *hinic_init_hwdev(struct pci_dev *pdev) 756 { 757 struct hinic_pfhwdev *pfhwdev; 758 struct hinic_hwdev *hwdev; 759 struct hinic_hwif *hwif; 760 int err, num_aeqs; 761 762 hwif = devm_kzalloc(&pdev->dev, sizeof(*hwif), GFP_KERNEL); 763 if (!hwif) 764 return ERR_PTR(-ENOMEM); 765 766 err = hinic_init_hwif(hwif, pdev); 767 if (err) { 768 dev_err(&pdev->dev, "Failed to init HW interface\n"); 769 return ERR_PTR(err); 770 } 771 772 if (!HINIC_IS_PF(hwif) && !HINIC_IS_PPF(hwif)) { 773 dev_err(&pdev->dev, "Unsupported PCI Function type\n"); 774 err = -EFAULT; 775 goto err_func_type; 776 } 777 778 pfhwdev = devm_kzalloc(&pdev->dev, sizeof(*pfhwdev), GFP_KERNEL); 779 if (!pfhwdev) { 780 err = -ENOMEM; 781 goto err_pfhwdev_alloc; 782 } 783 784 hwdev = &pfhwdev->hwdev; 785 hwdev->hwif = hwif; 786 787 err = init_msix(hwdev); 788 if (err) { 789 dev_err(&pdev->dev, "Failed to init msix\n"); 790 goto err_init_msix; 791 } 792 793 err = wait_for_outbound_state(hwdev); 794 if (err) { 795 dev_warn(&pdev->dev, "outbound - disabled, try again\n"); 796 hinic_outbound_state_set(hwif, HINIC_OUTBOUND_ENABLE); 797 } 798 799 num_aeqs = HINIC_HWIF_NUM_AEQS(hwif); 800 801 err = hinic_aeqs_init(&hwdev->aeqs, hwif, num_aeqs, 802 HINIC_DEFAULT_AEQ_LEN, HINIC_EQ_PAGE_SIZE, 803 hwdev->msix_entries); 804 if (err) { 805 dev_err(&pdev->dev, "Failed to init async event queues\n"); 806 goto err_aeqs_init; 807 } 808 809 err = init_pfhwdev(pfhwdev); 810 if (err) { 811 dev_err(&pdev->dev, "Failed to init PF HW device\n"); 812 goto err_init_pfhwdev; 813 } 814 815 err = get_dev_cap(hwdev); 816 if (err) { 817 dev_err(&pdev->dev, "Failed to get device capabilities\n"); 818 goto err_dev_cap; 819 } 820 821 err = init_fw_ctxt(hwdev); 822 if (err) { 823 dev_err(&pdev->dev, "Failed to init function table\n"); 824 goto err_init_fw_ctxt; 825 } 826 827 err = set_resources_state(hwdev, HINIC_RES_ACTIVE); 828 if (err) { 829 dev_err(&pdev->dev, "Failed to set resources state\n"); 830 goto err_resources_state; 831 } 832 833 return hwdev; 834 835 err_resources_state: 836 err_init_fw_ctxt: 837 err_dev_cap: 838 free_pfhwdev(pfhwdev); 839 840 err_init_pfhwdev: 841 hinic_aeqs_free(&hwdev->aeqs); 842 843 err_aeqs_init: 844 disable_msix(hwdev); 845 846 err_init_msix: 847 err_pfhwdev_alloc: 848 err_func_type: 849 hinic_free_hwif(hwif); 850 return ERR_PTR(err); 851 } 852 853 /** 854 * hinic_free_hwdev - Free the NIC HW device 855 * @hwdev: the NIC HW device 856 **/ 857 void hinic_free_hwdev(struct hinic_hwdev *hwdev) 858 { 859 struct hinic_pfhwdev *pfhwdev = container_of(hwdev, 860 struct hinic_pfhwdev, 861 hwdev); 862 863 set_resources_state(hwdev, HINIC_RES_CLEAN); 864 865 free_pfhwdev(pfhwdev); 866 867 hinic_aeqs_free(&hwdev->aeqs); 868 869 disable_msix(hwdev); 870 871 hinic_free_hwif(hwdev->hwif); 872 } 873 874 int hinic_hwdev_max_num_qps(struct hinic_hwdev *hwdev) 875 { 876 struct hinic_cap *nic_cap = &hwdev->nic_cap; 877 878 return nic_cap->max_qps; 879 } 880 881 /** 882 * hinic_hwdev_num_qps - return the number QPs available for use 883 * @hwdev: the NIC HW device 884 * 885 * Return number QPs available for use 886 **/ 887 int hinic_hwdev_num_qps(struct hinic_hwdev *hwdev) 888 { 889 struct hinic_cap *nic_cap = &hwdev->nic_cap; 890 891 return nic_cap->num_qps; 892 } 893 894 /** 895 * hinic_hwdev_get_sq - get SQ 896 * @hwdev: the NIC HW device 897 * @i: the position of the SQ 898 * 899 * Return: the SQ in the i position 900 **/ 901 struct hinic_sq *hinic_hwdev_get_sq(struct hinic_hwdev *hwdev, int i) 902 { 903 struct hinic_func_to_io *func_to_io = &hwdev->func_to_io; 904 struct hinic_qp *qp = &func_to_io->qps[i]; 905 906 if (i >= hinic_hwdev_num_qps(hwdev)) 907 return NULL; 908 909 return &qp->sq; 910 } 911 912 /** 913 * hinic_hwdev_get_sq - get RQ 914 * @hwdev: the NIC HW device 915 * @i: the position of the RQ 916 * 917 * Return: the RQ in the i position 918 **/ 919 struct hinic_rq *hinic_hwdev_get_rq(struct hinic_hwdev *hwdev, int i) 920 { 921 struct hinic_func_to_io *func_to_io = &hwdev->func_to_io; 922 struct hinic_qp *qp = &func_to_io->qps[i]; 923 924 if (i >= hinic_hwdev_num_qps(hwdev)) 925 return NULL; 926 927 return &qp->rq; 928 } 929 930 /** 931 * hinic_hwdev_msix_cnt_set - clear message attribute counters for msix entry 932 * @hwdev: the NIC HW device 933 * @msix_index: msix_index 934 * 935 * Return 0 - Success, negative - Failure 936 **/ 937 int hinic_hwdev_msix_cnt_set(struct hinic_hwdev *hwdev, u16 msix_index) 938 { 939 return hinic_msix_attr_cnt_clear(hwdev->hwif, msix_index); 940 } 941 942 /** 943 * hinic_hwdev_msix_set - set message attribute for msix entry 944 * @hwdev: the NIC HW device 945 * @msix_index: msix_index 946 * @pending_limit: the maximum pending interrupt events (unit 8) 947 * @coalesc_timer: coalesc period for interrupt (unit 8 us) 948 * @lli_timer: replenishing period for low latency credit (unit 8 us) 949 * @lli_credit_limit: maximum credits for low latency msix messages (unit 8) 950 * @resend_timer: maximum wait for resending msix (unit coalesc period) 951 * 952 * Return 0 - Success, negative - Failure 953 **/ 954 int hinic_hwdev_msix_set(struct hinic_hwdev *hwdev, u16 msix_index, 955 u8 pending_limit, u8 coalesc_timer, 956 u8 lli_timer_cfg, u8 lli_credit_limit, 957 u8 resend_timer) 958 { 959 return hinic_msix_attr_set(hwdev->hwif, msix_index, 960 pending_limit, coalesc_timer, 961 lli_timer_cfg, lli_credit_limit, 962 resend_timer); 963 } 964 965 /** 966 * hinic_hwdev_hw_ci_addr_set - set cons idx addr and attributes in HW for sq 967 * @hwdev: the NIC HW device 968 * @sq: send queue 969 * @pending_limit: the maximum pending update ci events (unit 8) 970 * @coalesc_timer: coalesc period for update ci (unit 8 us) 971 * 972 * Return 0 - Success, negative - Failure 973 **/ 974 int hinic_hwdev_hw_ci_addr_set(struct hinic_hwdev *hwdev, struct hinic_sq *sq, 975 u8 pending_limit, u8 coalesc_timer) 976 { 977 struct hinic_qp *qp = container_of(sq, struct hinic_qp, sq); 978 struct hinic_hwif *hwif = hwdev->hwif; 979 struct pci_dev *pdev = hwif->pdev; 980 struct hinic_pfhwdev *pfhwdev; 981 struct hinic_cmd_hw_ci hw_ci; 982 983 if (!HINIC_IS_PF(hwif) && !HINIC_IS_PPF(hwif)) { 984 dev_err(&pdev->dev, "Unsupported PCI Function type\n"); 985 return -EINVAL; 986 } 987 988 hw_ci.dma_attr_off = 0; 989 hw_ci.pending_limit = pending_limit; 990 hw_ci.coalesc_timer = coalesc_timer; 991 992 hw_ci.msix_en = 1; 993 hw_ci.msix_entry_idx = sq->msix_entry; 994 995 hw_ci.func_idx = HINIC_HWIF_FUNC_IDX(hwif); 996 997 hw_ci.sq_id = qp->q_id; 998 999 hw_ci.ci_addr = ADDR_IN_4BYTES(sq->hw_ci_dma_addr); 1000 1001 pfhwdev = container_of(hwdev, struct hinic_pfhwdev, hwdev); 1002 return hinic_msg_to_mgmt(&pfhwdev->pf_to_mgmt, 1003 HINIC_MOD_COMM, 1004 HINIC_COMM_CMD_SQ_HI_CI_SET, 1005 &hw_ci, sizeof(hw_ci), NULL, 1006 NULL, HINIC_MGMT_MSG_SYNC); 1007 } 1008 1009 /** 1010 * hinic_hwdev_set_msix_state- set msix state 1011 * @hwdev: the NIC HW device 1012 * @msix_index: IRQ corresponding index number 1013 * @flag: msix state 1014 * 1015 **/ 1016 void hinic_hwdev_set_msix_state(struct hinic_hwdev *hwdev, u16 msix_index, 1017 enum hinic_msix_state flag) 1018 { 1019 hinic_set_msix_state(hwdev->hwif, msix_index, flag); 1020 } 1021