1 /*
2  * Huawei HiNIC PCI Express Linux driver
3  * Copyright(c) 2017 Huawei Technologies Co., Ltd
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms and conditions of the GNU General Public License,
7  * version 2, as published by the Free Software Foundation.
8  *
9  * This program is distributed in the hope it will be useful, but WITHOUT
10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
12  * for more details.
13  *
14  */
15 
16 #ifndef HINIC_HW_CSR_H
17 #define HINIC_HW_CSR_H
18 
19 /* HW interface registers */
20 #define HINIC_CSR_FUNC_ATTR0_ADDR                       0x0
21 #define HINIC_CSR_FUNC_ATTR1_ADDR                       0x4
22 
23 #define HINIC_CSR_FUNC_ATTR4_ADDR                       0x10
24 #define HINIC_CSR_FUNC_ATTR5_ADDR                       0x14
25 
26 #define HINIC_DMA_ATTR_BASE                             0xC80
27 #define HINIC_ELECTION_BASE                             0x4200
28 
29 #define HINIC_DMA_ATTR_STRIDE                           0x4
30 #define HINIC_CSR_DMA_ATTR_ADDR(idx)                    \
31 	(HINIC_DMA_ATTR_BASE + (idx) * HINIC_DMA_ATTR_STRIDE)
32 
33 #define HINIC_PPF_ELECTION_STRIDE                       0x4
34 #define HINIC_CSR_MAX_PORTS                             4
35 
36 #define HINIC_CSR_PPF_ELECTION_ADDR(idx)                \
37 	(HINIC_ELECTION_BASE +  (idx) * HINIC_PPF_ELECTION_STRIDE)
38 
39 /* API CMD registers */
40 #define HINIC_CSR_API_CMD_BASE                          0xF000
41 
42 #define HINIC_CSR_API_CMD_STRIDE                        0x100
43 
44 #define HINIC_CSR_API_CMD_CHAIN_HEAD_HI_ADDR(idx)       \
45 	(HINIC_CSR_API_CMD_BASE + 0x0 + (idx) * HINIC_CSR_API_CMD_STRIDE)
46 
47 #define HINIC_CSR_API_CMD_CHAIN_HEAD_LO_ADDR(idx)       \
48 	(HINIC_CSR_API_CMD_BASE + 0x4 + (idx) * HINIC_CSR_API_CMD_STRIDE)
49 
50 #define HINIC_CSR_API_CMD_STATUS_HI_ADDR(idx)           \
51 	(HINIC_CSR_API_CMD_BASE + 0x8 + (idx) * HINIC_CSR_API_CMD_STRIDE)
52 
53 #define HINIC_CSR_API_CMD_STATUS_LO_ADDR(idx)           \
54 	(HINIC_CSR_API_CMD_BASE + 0xC + (idx) * HINIC_CSR_API_CMD_STRIDE)
55 
56 #define HINIC_CSR_API_CMD_CHAIN_NUM_CELLS_ADDR(idx)     \
57 	(HINIC_CSR_API_CMD_BASE + 0x10 + (idx) * HINIC_CSR_API_CMD_STRIDE)
58 
59 #define HINIC_CSR_API_CMD_CHAIN_CTRL_ADDR(idx)          \
60 	(HINIC_CSR_API_CMD_BASE + 0x14 + (idx) * HINIC_CSR_API_CMD_STRIDE)
61 
62 #define HINIC_CSR_API_CMD_CHAIN_PI_ADDR(idx)            \
63 	(HINIC_CSR_API_CMD_BASE + 0x1C + (idx) * HINIC_CSR_API_CMD_STRIDE)
64 
65 #define HINIC_CSR_API_CMD_CHAIN_REQ_ADDR(idx)           \
66 	(HINIC_CSR_API_CMD_BASE + 0x20 + (idx) * HINIC_CSR_API_CMD_STRIDE)
67 
68 #define HINIC_CSR_API_CMD_STATUS_ADDR(idx)              \
69 	(HINIC_CSR_API_CMD_BASE + 0x30 + (idx) * HINIC_CSR_API_CMD_STRIDE)
70 
71 /* MSI-X registers */
72 #define HINIC_CSR_MSIX_CTRL_BASE                        0x2000
73 #define HINIC_CSR_MSIX_CNT_BASE                         0x2004
74 
75 #define HINIC_CSR_MSIX_STRIDE                           0x8
76 
77 #define HINIC_CSR_MSIX_CTRL_ADDR(idx)                   \
78 	(HINIC_CSR_MSIX_CTRL_BASE + (idx) * HINIC_CSR_MSIX_STRIDE)
79 
80 #define HINIC_CSR_MSIX_CNT_ADDR(idx)                    \
81 	(HINIC_CSR_MSIX_CNT_BASE + (idx) * HINIC_CSR_MSIX_STRIDE)
82 
83 /* EQ registers */
84 #define HINIC_AEQ_MTT_OFF_BASE_ADDR                     0x200
85 #define HINIC_CEQ_MTT_OFF_BASE_ADDR                     0x400
86 
87 #define HINIC_EQ_MTT_OFF_STRIDE                         0x40
88 
89 #define HINIC_CSR_AEQ_MTT_OFF(id)                       \
90 	(HINIC_AEQ_MTT_OFF_BASE_ADDR + (id) * HINIC_EQ_MTT_OFF_STRIDE)
91 
92 #define HINIC_CSR_CEQ_MTT_OFF(id)                       \
93 	(HINIC_CEQ_MTT_OFF_BASE_ADDR + (id) * HINIC_EQ_MTT_OFF_STRIDE)
94 
95 #define HINIC_CSR_EQ_PAGE_OFF_STRIDE                    8
96 
97 #define HINIC_CSR_AEQ_HI_PHYS_ADDR_REG(q_id, pg_num)    \
98 	(HINIC_CSR_AEQ_MTT_OFF(q_id) + \
99 	 (pg_num) * HINIC_CSR_EQ_PAGE_OFF_STRIDE)
100 
101 #define HINIC_CSR_CEQ_HI_PHYS_ADDR_REG(q_id, pg_num)    \
102 	(HINIC_CSR_CEQ_MTT_OFF(q_id) +          \
103 	 (pg_num) * HINIC_CSR_EQ_PAGE_OFF_STRIDE)
104 
105 #define HINIC_CSR_AEQ_LO_PHYS_ADDR_REG(q_id, pg_num)    \
106 	(HINIC_CSR_AEQ_MTT_OFF(q_id) + \
107 	 (pg_num) * HINIC_CSR_EQ_PAGE_OFF_STRIDE + 4)
108 
109 #define HINIC_CSR_CEQ_LO_PHYS_ADDR_REG(q_id, pg_num)    \
110 	(HINIC_CSR_CEQ_MTT_OFF(q_id) +  \
111 	 (pg_num) * HINIC_CSR_EQ_PAGE_OFF_STRIDE + 4)
112 
113 #define HINIC_AEQ_CTRL_0_ADDR_BASE                      0xE00
114 #define HINIC_AEQ_CTRL_1_ADDR_BASE                      0xE04
115 #define HINIC_AEQ_CONS_IDX_ADDR_BASE                    0xE08
116 #define HINIC_AEQ_PROD_IDX_ADDR_BASE                    0xE0C
117 
118 #define HINIC_CEQ_CTRL_0_ADDR_BASE                      0x1000
119 #define HINIC_CEQ_CTRL_1_ADDR_BASE                      0x1004
120 #define HINIC_CEQ_CONS_IDX_ADDR_BASE                    0x1008
121 #define HINIC_CEQ_PROD_IDX_ADDR_BASE                    0x100C
122 
123 #define HINIC_EQ_OFF_STRIDE                             0x80
124 
125 #define HINIC_CSR_AEQ_CTRL_0_ADDR(idx)                  \
126 	(HINIC_AEQ_CTRL_0_ADDR_BASE + (idx) * HINIC_EQ_OFF_STRIDE)
127 
128 #define HINIC_CSR_AEQ_CTRL_1_ADDR(idx)                  \
129 	(HINIC_AEQ_CTRL_1_ADDR_BASE + (idx) * HINIC_EQ_OFF_STRIDE)
130 
131 #define HINIC_CSR_AEQ_CONS_IDX_ADDR(idx)                \
132 	(HINIC_AEQ_CONS_IDX_ADDR_BASE + (idx) * HINIC_EQ_OFF_STRIDE)
133 
134 #define HINIC_CSR_AEQ_PROD_IDX_ADDR(idx)                \
135 	(HINIC_AEQ_PROD_IDX_ADDR_BASE + (idx) * HINIC_EQ_OFF_STRIDE)
136 
137 #define HINIC_CSR_CEQ_CTRL_0_ADDR(idx)                  \
138 	(HINIC_CEQ_CTRL_0_ADDR_BASE + (idx) * HINIC_EQ_OFF_STRIDE)
139 
140 #define HINIC_CSR_CEQ_CTRL_1_ADDR(idx)                  \
141 	(HINIC_CEQ_CTRL_1_ADDR_BASE + (idx) * HINIC_EQ_OFF_STRIDE)
142 
143 #define HINIC_CSR_CEQ_CONS_IDX_ADDR(idx)                \
144 	(HINIC_CEQ_CONS_IDX_ADDR_BASE + (idx) * HINIC_EQ_OFF_STRIDE)
145 
146 #define HINIC_CSR_CEQ_PROD_IDX_ADDR(idx)                \
147 	(HINIC_CEQ_PROD_IDX_ADDR_BASE + (idx) * HINIC_EQ_OFF_STRIDE)
148 
149 #endif
150