1253ac3a9SLuo bin /* SPDX-License-Identifier: GPL-2.0-only */ 2253ac3a9SLuo bin /* Huawei HiNIC PCI Express Linux driver 3253ac3a9SLuo bin * Copyright(c) 2017 Huawei Technologies Co., Ltd 4253ac3a9SLuo bin */ 5253ac3a9SLuo bin 6253ac3a9SLuo bin #ifndef HINIC_DEBUGFS_H 7253ac3a9SLuo bin #define HINIC_DEBUGFS_H 8253ac3a9SLuo bin 9253ac3a9SLuo bin #include "hinic_dev.h" 10253ac3a9SLuo bin 115215e162SLuo bin #define TBL_ID_FUNC_CFG_SM_NODE 11 125215e162SLuo bin #define TBL_ID_FUNC_CFG_SM_INST 1 135215e162SLuo bin 145215e162SLuo bin #define HINIC_FUNCTION_CONFIGURE_TABLE_SIZE 64 155215e162SLuo bin 165215e162SLuo bin struct hinic_cmd_lt_rd { 175215e162SLuo bin u8 status; 185215e162SLuo bin u8 version; 195215e162SLuo bin u8 rsvd0[6]; 205215e162SLuo bin 215215e162SLuo bin unsigned char node; 225215e162SLuo bin unsigned char inst; 235215e162SLuo bin unsigned char entry_size; 245215e162SLuo bin unsigned char rsvd; 255215e162SLuo bin unsigned int lt_index; 265215e162SLuo bin unsigned int offset; 275215e162SLuo bin unsigned int len; 285215e162SLuo bin unsigned char data[100]; 295215e162SLuo bin }; 305215e162SLuo bin 315215e162SLuo bin struct tag_sml_funcfg_tbl { 325215e162SLuo bin union { 335215e162SLuo bin struct { 345215e162SLuo bin u32 rsvd0 :8; 355215e162SLuo bin u32 nic_rx_mode :5; 365215e162SLuo bin u32 rsvd1 :18; 375215e162SLuo bin u32 valid :1; 385215e162SLuo bin } bs; 395215e162SLuo bin 405215e162SLuo bin u32 value; 415215e162SLuo bin } dw0; 425215e162SLuo bin 435215e162SLuo bin union { 445215e162SLuo bin struct { 455215e162SLuo bin u32 vlan_id :12; 465215e162SLuo bin u32 vlan_mode :3; 475215e162SLuo bin u32 fast_recycled_mode :1; 485215e162SLuo bin u32 mtu :16; 495215e162SLuo bin } bs; 505215e162SLuo bin 515215e162SLuo bin u32 value; 525215e162SLuo bin } dw1; 535215e162SLuo bin 545215e162SLuo bin u32 dw2; 555215e162SLuo bin u32 dw3; 565215e162SLuo bin u32 dw4; 575215e162SLuo bin u32 dw5; 585215e162SLuo bin u32 dw6; 595215e162SLuo bin u32 dw7; 605215e162SLuo bin u32 dw8; 615215e162SLuo bin u32 dw9; 625215e162SLuo bin u32 dw10; 635215e162SLuo bin u32 dw11; 645215e162SLuo bin u32 dw12; 655215e162SLuo bin 665215e162SLuo bin union { 675215e162SLuo bin struct { 685215e162SLuo bin u32 rsvd2 :15; 695215e162SLuo bin u32 cfg_q_num :9; 705215e162SLuo bin u32 cfg_rq_depth :6; 715215e162SLuo bin u32 vhd_type :2; 725215e162SLuo bin } bs; 735215e162SLuo bin 745215e162SLuo bin u32 value; 755215e162SLuo bin } dw13; 765215e162SLuo bin 775215e162SLuo bin u32 dw14; 785215e162SLuo bin u32 dw15; 795215e162SLuo bin }; 805215e162SLuo bin 81253ac3a9SLuo bin int hinic_sq_debug_add(struct hinic_dev *dev, u16 sq_id); 82253ac3a9SLuo bin 83253ac3a9SLuo bin void hinic_sq_debug_rem(struct hinic_sq *sq); 84253ac3a9SLuo bin 85626f0603SLuo bin int hinic_rq_debug_add(struct hinic_dev *dev, u16 rq_id); 86626f0603SLuo bin 87626f0603SLuo bin void hinic_rq_debug_rem(struct hinic_rq *rq); 88626f0603SLuo bin 895215e162SLuo bin int hinic_func_table_debug_add(struct hinic_dev *dev); 905215e162SLuo bin 915215e162SLuo bin void hinic_func_table_debug_rem(struct hinic_dev *dev); 925215e162SLuo bin 93253ac3a9SLuo bin void hinic_sq_dbgfs_init(struct hinic_dev *nic_dev); 94253ac3a9SLuo bin 95253ac3a9SLuo bin void hinic_sq_dbgfs_uninit(struct hinic_dev *nic_dev); 96253ac3a9SLuo bin 97626f0603SLuo bin void hinic_rq_dbgfs_init(struct hinic_dev *nic_dev); 98626f0603SLuo bin 99626f0603SLuo bin void hinic_rq_dbgfs_uninit(struct hinic_dev *nic_dev); 100626f0603SLuo bin 1015215e162SLuo bin void hinic_func_tbl_dbgfs_init(struct hinic_dev *nic_dev); 1025215e162SLuo bin 1035215e162SLuo bin void hinic_func_tbl_dbgfs_uninit(struct hinic_dev *nic_dev); 1045215e162SLuo bin 105253ac3a9SLuo bin void hinic_dbg_init(struct hinic_dev *nic_dev); 106253ac3a9SLuo bin 107253ac3a9SLuo bin void hinic_dbg_uninit(struct hinic_dev *nic_dev); 108253ac3a9SLuo bin 109253ac3a9SLuo bin void hinic_dbg_register_debugfs(const char *debugfs_dir_name); 110253ac3a9SLuo bin 111253ac3a9SLuo bin void hinic_dbg_unregister_debugfs(void); 112253ac3a9SLuo bin 113253ac3a9SLuo bin #endif 114