1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Copyright (c) 2014-2015 Hisilicon Limited.
4  */
5 
6 #include <linux/acpi.h>
7 #include <linux/errno.h>
8 #include <linux/etherdevice.h>
9 #include <linux/init.h>
10 #include <linux/kernel.h>
11 #include <linux/mfd/syscon.h>
12 #include <linux/module.h>
13 #include <linux/mutex.h>
14 #include <linux/netdevice.h>
15 #include <linux/of_address.h>
16 #include <linux/of.h>
17 #include <linux/of_mdio.h>
18 #include <linux/of_platform.h>
19 #include <linux/phy.h>
20 #include <linux/platform_device.h>
21 #include <linux/regmap.h>
22 
23 #define MDIO_DRV_NAME "Hi-HNS_MDIO"
24 #define MDIO_BUS_NAME "Hisilicon MII Bus"
25 
26 #define MDIO_TIMEOUT			1000000
27 
28 struct hns_mdio_sc_reg {
29 	u16 mdio_clk_en;
30 	u16 mdio_clk_dis;
31 	u16 mdio_reset_req;
32 	u16 mdio_reset_dreq;
33 	u16 mdio_clk_st;
34 	u16 mdio_reset_st;
35 };
36 
37 struct hns_mdio_device {
38 	u8 __iomem *vbase;		/* mdio reg base address */
39 	struct regmap *subctrl_vbase;
40 	struct hns_mdio_sc_reg sc_reg;
41 };
42 
43 /* mdio reg */
44 #define MDIO_COMMAND_REG		0x0
45 #define MDIO_ADDR_REG			0x4
46 #define MDIO_WDATA_REG			0x8
47 #define MDIO_RDATA_REG			0xc
48 #define MDIO_STA_REG			0x10
49 
50 /* cfg phy bit map */
51 #define MDIO_CMD_DEVAD_M	0x1f
52 #define MDIO_CMD_DEVAD_S	0
53 #define MDIO_CMD_PRTAD_M	0x1f
54 #define MDIO_CMD_PRTAD_S	5
55 #define MDIO_CMD_OP_S		10
56 #define MDIO_CMD_ST_S		12
57 #define MDIO_CMD_START_B	14
58 
59 #define MDIO_ADDR_DATA_M	0xffff
60 #define MDIO_ADDR_DATA_S	0
61 
62 #define MDIO_WDATA_DATA_M	0xffff
63 #define MDIO_WDATA_DATA_S	0
64 
65 #define MDIO_RDATA_DATA_M	0xffff
66 #define MDIO_RDATA_DATA_S	0
67 
68 #define MDIO_STATE_STA_B	0
69 
70 enum mdio_st_clause {
71 	MDIO_ST_CLAUSE_45 = 0,
72 	MDIO_ST_CLAUSE_22
73 };
74 
75 enum mdio_c22_op_seq {
76 	MDIO_C22_WRITE = 1,
77 	MDIO_C22_READ = 2
78 };
79 
80 enum mdio_c45_op_seq {
81 	MDIO_C45_WRITE_ADDR = 0,
82 	MDIO_C45_WRITE_DATA,
83 	MDIO_C45_READ_INCREMENT,
84 	MDIO_C45_READ
85 };
86 
87 /* peri subctrl reg */
88 #define MDIO_SC_CLK_EN		0x338
89 #define MDIO_SC_CLK_DIS		0x33C
90 #define MDIO_SC_RESET_REQ	0xA38
91 #define MDIO_SC_RESET_DREQ	0xA3C
92 #define MDIO_SC_CLK_ST		0x531C
93 #define MDIO_SC_RESET_ST	0x5A1C
94 
95 static void mdio_write_reg(u8 __iomem *base, u32 reg, u32 value)
96 {
97 	writel_relaxed(value, base + reg);
98 }
99 
100 #define MDIO_WRITE_REG(a, reg, value) \
101 	mdio_write_reg((a)->vbase, (reg), (value))
102 
103 static u32 mdio_read_reg(u8 __iomem *base, u32 reg)
104 {
105 	return readl_relaxed(base + reg);
106 }
107 
108 #define mdio_set_field(origin, mask, shift, val) \
109 	do { \
110 		(origin) &= (~((mask) << (shift))); \
111 		(origin) |= (((val) & (mask)) << (shift)); \
112 	} while (0)
113 
114 #define mdio_get_field(origin, mask, shift) (((origin) >> (shift)) & (mask))
115 
116 static void mdio_set_reg_field(u8 __iomem *base, u32 reg, u32 mask, u32 shift,
117 			       u32 val)
118 {
119 	u32 origin = mdio_read_reg(base, reg);
120 
121 	mdio_set_field(origin, mask, shift, val);
122 	mdio_write_reg(base, reg, origin);
123 }
124 
125 #define MDIO_SET_REG_FIELD(dev, reg, mask, shift, val) \
126 	mdio_set_reg_field((dev)->vbase, (reg), (mask), (shift), (val))
127 
128 static u32 mdio_get_reg_field(u8 __iomem *base, u32 reg, u32 mask, u32 shift)
129 {
130 	u32 origin;
131 
132 	origin = mdio_read_reg(base, reg);
133 	return mdio_get_field(origin, mask, shift);
134 }
135 
136 #define MDIO_GET_REG_FIELD(dev, reg, mask, shift) \
137 		mdio_get_reg_field((dev)->vbase, (reg), (mask), (shift))
138 
139 #define MDIO_GET_REG_BIT(dev, reg, bit) \
140 		mdio_get_reg_field((dev)->vbase, (reg), 0x1ull, (bit))
141 
142 #define MDIO_CHECK_SET_ST	1
143 #define MDIO_CHECK_CLR_ST	0
144 
145 static int mdio_sc_cfg_reg_write(struct hns_mdio_device *mdio_dev,
146 				 u32 cfg_reg, u32 set_val,
147 				 u32 st_reg, u32 st_msk, u8 check_st)
148 {
149 	u32 time_cnt;
150 	u32 reg_value;
151 
152 	regmap_write(mdio_dev->subctrl_vbase, cfg_reg, set_val);
153 
154 	for (time_cnt = MDIO_TIMEOUT; time_cnt; time_cnt--) {
155 		regmap_read(mdio_dev->subctrl_vbase, st_reg, &reg_value);
156 		reg_value &= st_msk;
157 		if ((!!check_st) == (!!reg_value))
158 			break;
159 	}
160 
161 	if ((!!check_st) != (!!reg_value))
162 		return -EBUSY;
163 
164 	return 0;
165 }
166 
167 static int hns_mdio_wait_ready(struct mii_bus *bus)
168 {
169 	struct hns_mdio_device *mdio_dev = bus->priv;
170 	u32 cmd_reg_value;
171 	int i;
172 
173 	/* waitting for MDIO_COMMAND_REG 's mdio_start==0 */
174 	/* after that can do read or write*/
175 	for (i = 0; i < MDIO_TIMEOUT; i++) {
176 		cmd_reg_value = MDIO_GET_REG_BIT(mdio_dev,
177 						 MDIO_COMMAND_REG,
178 						 MDIO_CMD_START_B);
179 		if (!cmd_reg_value)
180 			break;
181 	}
182 	if ((i == MDIO_TIMEOUT) && cmd_reg_value)
183 		return -ETIMEDOUT;
184 
185 	return 0;
186 }
187 
188 static void hns_mdio_cmd_write(struct hns_mdio_device *mdio_dev,
189 			       u8 is_c45, u8 op, u8 phy_id, u16 cmd)
190 {
191 	u32 cmd_reg_value;
192 	u8 st = is_c45 ? MDIO_ST_CLAUSE_45 : MDIO_ST_CLAUSE_22;
193 
194 	cmd_reg_value = st << MDIO_CMD_ST_S;
195 	cmd_reg_value |= op << MDIO_CMD_OP_S;
196 	cmd_reg_value |=
197 		(phy_id & MDIO_CMD_PRTAD_M) << MDIO_CMD_PRTAD_S;
198 	cmd_reg_value |= (cmd & MDIO_CMD_DEVAD_M) << MDIO_CMD_DEVAD_S;
199 	cmd_reg_value |= 1 << MDIO_CMD_START_B;
200 
201 	MDIO_WRITE_REG(mdio_dev, MDIO_COMMAND_REG, cmd_reg_value);
202 }
203 
204 /**
205  * hns_mdio_write - access phy register
206  * @bus: mdio bus
207  * @phy_id: phy id
208  * @regnum: register num
209  * @value: register value
210  *
211  * Return 0 on success, negative on failure
212  */
213 static int hns_mdio_write(struct mii_bus *bus,
214 			  int phy_id, int regnum, u16 data)
215 {
216 	int ret;
217 	struct hns_mdio_device *mdio_dev = (struct hns_mdio_device *)bus->priv;
218 	u8 devad = ((regnum >> 16) & 0x1f);
219 	u8 is_c45 = !!(regnum & MII_ADDR_C45);
220 	u16 reg = (u16)(regnum & 0xffff);
221 	u8 op;
222 	u16 cmd_reg_cfg;
223 
224 	dev_dbg(&bus->dev, "mdio write %s,base is %p\n",
225 		bus->id, mdio_dev->vbase);
226 	dev_dbg(&bus->dev, "phy id=%d, is_c45=%d, devad=%d, reg=%#x, write data=%d\n",
227 		phy_id, is_c45, devad, reg, data);
228 
229 	/* wait for ready */
230 	ret = hns_mdio_wait_ready(bus);
231 	if (ret) {
232 		dev_err(&bus->dev, "MDIO bus is busy\n");
233 		return ret;
234 	}
235 
236 	if (!is_c45) {
237 		cmd_reg_cfg = reg;
238 		op = MDIO_C22_WRITE;
239 	} else {
240 		/* config the cmd-reg to write addr*/
241 		MDIO_SET_REG_FIELD(mdio_dev, MDIO_ADDR_REG, MDIO_ADDR_DATA_M,
242 				   MDIO_ADDR_DATA_S, reg);
243 
244 		hns_mdio_cmd_write(mdio_dev, is_c45,
245 				   MDIO_C45_WRITE_ADDR, phy_id, devad);
246 
247 		/* check for read or write opt is finished */
248 		ret = hns_mdio_wait_ready(bus);
249 		if (ret) {
250 			dev_err(&bus->dev, "MDIO bus is busy\n");
251 			return ret;
252 		}
253 
254 		/* config the data needed writing */
255 		cmd_reg_cfg = devad;
256 		op = MDIO_C45_WRITE_DATA;
257 	}
258 
259 	MDIO_SET_REG_FIELD(mdio_dev, MDIO_WDATA_REG, MDIO_WDATA_DATA_M,
260 			   MDIO_WDATA_DATA_S, data);
261 
262 	hns_mdio_cmd_write(mdio_dev, is_c45, op, phy_id, cmd_reg_cfg);
263 
264 	return 0;
265 }
266 
267 /**
268  * hns_mdio_read - access phy register
269  * @bus: mdio bus
270  * @phy_id: phy id
271  * @regnum: register num
272  * @value: register value
273  *
274  * Return phy register value
275  */
276 static int hns_mdio_read(struct mii_bus *bus, int phy_id, int regnum)
277 {
278 	int ret;
279 	u16 reg_val = 0;
280 	u8 devad = ((regnum >> 16) & 0x1f);
281 	u8 is_c45 = !!(regnum & MII_ADDR_C45);
282 	u16 reg = (u16)(regnum & 0xffff);
283 	struct hns_mdio_device *mdio_dev = (struct hns_mdio_device *)bus->priv;
284 
285 	dev_dbg(&bus->dev, "mdio read %s,base is %p\n",
286 		bus->id, mdio_dev->vbase);
287 	dev_dbg(&bus->dev, "phy id=%d, is_c45=%d, devad=%d, reg=%#x!\n",
288 		phy_id, is_c45, devad, reg);
289 
290 	/* Step 1: wait for ready */
291 	ret = hns_mdio_wait_ready(bus);
292 	if (ret) {
293 		dev_err(&bus->dev, "MDIO bus is busy\n");
294 		return ret;
295 	}
296 
297 	if (!is_c45) {
298 		hns_mdio_cmd_write(mdio_dev, is_c45,
299 				   MDIO_C22_READ, phy_id, reg);
300 	} else {
301 		MDIO_SET_REG_FIELD(mdio_dev, MDIO_ADDR_REG, MDIO_ADDR_DATA_M,
302 				   MDIO_ADDR_DATA_S, reg);
303 
304 		/* Step 2; config the cmd-reg to write addr*/
305 		hns_mdio_cmd_write(mdio_dev, is_c45,
306 				   MDIO_C45_WRITE_ADDR, phy_id, devad);
307 
308 		/* Step 3: check for read or write opt is finished */
309 		ret = hns_mdio_wait_ready(bus);
310 		if (ret) {
311 			dev_err(&bus->dev, "MDIO bus is busy\n");
312 			return ret;
313 		}
314 
315 		hns_mdio_cmd_write(mdio_dev, is_c45,
316 				   MDIO_C45_READ, phy_id, devad);
317 	}
318 
319 	/* Step 5: waitting for MDIO_COMMAND_REG 's mdio_start==0,*/
320 	/* check for read or write opt is finished */
321 	ret = hns_mdio_wait_ready(bus);
322 	if (ret) {
323 		dev_err(&bus->dev, "MDIO bus is busy\n");
324 		return ret;
325 	}
326 
327 	reg_val = MDIO_GET_REG_BIT(mdio_dev, MDIO_STA_REG, MDIO_STATE_STA_B);
328 	if (reg_val) {
329 		dev_err(&bus->dev, " ERROR! MDIO Read failed!\n");
330 		return -EBUSY;
331 	}
332 
333 	/* Step 6; get out data*/
334 	reg_val = (u16)MDIO_GET_REG_FIELD(mdio_dev, MDIO_RDATA_REG,
335 					  MDIO_RDATA_DATA_M, MDIO_RDATA_DATA_S);
336 
337 	return reg_val;
338 }
339 
340 /**
341  * hns_mdio_reset - reset mdio bus
342  * @bus: mdio bus
343  *
344  * Return 0 on success, negative on failure
345  */
346 static int hns_mdio_reset(struct mii_bus *bus)
347 {
348 	struct hns_mdio_device *mdio_dev = (struct hns_mdio_device *)bus->priv;
349 	const struct hns_mdio_sc_reg *sc_reg;
350 	int ret;
351 
352 	if (dev_of_node(bus->parent)) {
353 		if (!mdio_dev->subctrl_vbase) {
354 			dev_err(&bus->dev, "mdio sys ctl reg has not maped\n");
355 			return -ENODEV;
356 		}
357 
358 		sc_reg = &mdio_dev->sc_reg;
359 		/* 1. reset req, and read reset st check */
360 		ret = mdio_sc_cfg_reg_write(mdio_dev, sc_reg->mdio_reset_req,
361 					    0x1, sc_reg->mdio_reset_st, 0x1,
362 					    MDIO_CHECK_SET_ST);
363 		if (ret) {
364 			dev_err(&bus->dev, "MDIO reset fail\n");
365 			return ret;
366 		}
367 
368 		/* 2. dis clk, and read clk st check */
369 		ret = mdio_sc_cfg_reg_write(mdio_dev, sc_reg->mdio_clk_dis,
370 					    0x1, sc_reg->mdio_clk_st, 0x1,
371 					    MDIO_CHECK_CLR_ST);
372 		if (ret) {
373 			dev_err(&bus->dev, "MDIO dis clk fail\n");
374 			return ret;
375 		}
376 
377 		/* 3. reset dreq, and read reset st check */
378 		ret = mdio_sc_cfg_reg_write(mdio_dev, sc_reg->mdio_reset_dreq,
379 					    0x1, sc_reg->mdio_reset_st, 0x1,
380 					    MDIO_CHECK_CLR_ST);
381 		if (ret) {
382 			dev_err(&bus->dev, "MDIO dis clk fail\n");
383 			return ret;
384 		}
385 
386 		/* 4. en clk, and read clk st check */
387 		ret = mdio_sc_cfg_reg_write(mdio_dev, sc_reg->mdio_clk_en,
388 					    0x1, sc_reg->mdio_clk_st, 0x1,
389 					    MDIO_CHECK_SET_ST);
390 		if (ret)
391 			dev_err(&bus->dev, "MDIO en clk fail\n");
392 	} else if (is_acpi_node(bus->parent->fwnode)) {
393 		acpi_status s;
394 
395 		s = acpi_evaluate_object(ACPI_HANDLE(bus->parent),
396 					 "_RST", NULL, NULL);
397 		if (ACPI_FAILURE(s)) {
398 			dev_err(&bus->dev, "Reset failed, return:%#x\n", s);
399 			ret = -EBUSY;
400 		} else {
401 			ret = 0;
402 		}
403 	} else {
404 		dev_err(&bus->dev, "Can not get cfg data from DT or ACPI\n");
405 		ret = -ENXIO;
406 	}
407 	return ret;
408 }
409 
410 /**
411  * hns_mdio_probe - probe mdio device
412  * @pdev: mdio platform device
413  *
414  * Return 0 on success, negative on failure
415  */
416 static int hns_mdio_probe(struct platform_device *pdev)
417 {
418 	struct hns_mdio_device *mdio_dev;
419 	struct mii_bus *new_bus;
420 	int ret = -ENODEV;
421 
422 	if (!pdev) {
423 		dev_err(NULL, "pdev is NULL!\r\n");
424 		return -ENODEV;
425 	}
426 
427 	mdio_dev = devm_kzalloc(&pdev->dev, sizeof(*mdio_dev), GFP_KERNEL);
428 	if (!mdio_dev)
429 		return -ENOMEM;
430 
431 	new_bus = devm_mdiobus_alloc(&pdev->dev);
432 	if (!new_bus) {
433 		dev_err(&pdev->dev, "mdiobus_alloc fail!\n");
434 		return -ENOMEM;
435 	}
436 
437 	new_bus->name = MDIO_BUS_NAME;
438 	new_bus->read = hns_mdio_read;
439 	new_bus->write = hns_mdio_write;
440 	new_bus->reset = hns_mdio_reset;
441 	new_bus->priv = mdio_dev;
442 	new_bus->parent = &pdev->dev;
443 
444 	mdio_dev->vbase = devm_platform_ioremap_resource(pdev, 0);
445 	if (IS_ERR(mdio_dev->vbase)) {
446 		ret = PTR_ERR(mdio_dev->vbase);
447 		return ret;
448 	}
449 
450 	platform_set_drvdata(pdev, new_bus);
451 	snprintf(new_bus->id, MII_BUS_ID_SIZE, "%s-%s", "Mii",
452 		 dev_name(&pdev->dev));
453 	if (dev_of_node(&pdev->dev)) {
454 		struct of_phandle_args reg_args;
455 
456 		ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
457 						       "subctrl-vbase",
458 						       4,
459 						       0,
460 						       &reg_args);
461 		if (!ret) {
462 			mdio_dev->subctrl_vbase =
463 				syscon_node_to_regmap(reg_args.np);
464 			if (IS_ERR(mdio_dev->subctrl_vbase)) {
465 				dev_warn(&pdev->dev, "syscon_node_to_regmap error\n");
466 				mdio_dev->subctrl_vbase = NULL;
467 			} else {
468 				if (reg_args.args_count == 4) {
469 					mdio_dev->sc_reg.mdio_clk_en =
470 						(u16)reg_args.args[0];
471 					mdio_dev->sc_reg.mdio_clk_dis =
472 						(u16)reg_args.args[0] + 4;
473 					mdio_dev->sc_reg.mdio_reset_req =
474 						(u16)reg_args.args[1];
475 					mdio_dev->sc_reg.mdio_reset_dreq =
476 						(u16)reg_args.args[1] + 4;
477 					mdio_dev->sc_reg.mdio_clk_st =
478 						(u16)reg_args.args[2];
479 					mdio_dev->sc_reg.mdio_reset_st =
480 						(u16)reg_args.args[3];
481 				} else {
482 					/* for compatible */
483 					mdio_dev->sc_reg.mdio_clk_en =
484 						MDIO_SC_CLK_EN;
485 					mdio_dev->sc_reg.mdio_clk_dis =
486 						MDIO_SC_CLK_DIS;
487 					mdio_dev->sc_reg.mdio_reset_req =
488 						MDIO_SC_RESET_REQ;
489 					mdio_dev->sc_reg.mdio_reset_dreq =
490 						MDIO_SC_RESET_DREQ;
491 					mdio_dev->sc_reg.mdio_clk_st =
492 						MDIO_SC_CLK_ST;
493 					mdio_dev->sc_reg.mdio_reset_st =
494 						MDIO_SC_RESET_ST;
495 				}
496 			}
497 		} else {
498 			dev_warn(&pdev->dev, "find syscon ret = %#x\n", ret);
499 			mdio_dev->subctrl_vbase = NULL;
500 		}
501 
502 		ret = of_mdiobus_register(new_bus, pdev->dev.of_node);
503 	} else if (is_acpi_node(pdev->dev.fwnode)) {
504 		/* Clear all the IRQ properties */
505 		memset(new_bus->irq, PHY_POLL, 4 * PHY_MAX_ADDR);
506 
507 		/* Mask out all PHYs from auto probing. */
508 		new_bus->phy_mask = ~0;
509 
510 		/* Register the MDIO bus */
511 		ret = mdiobus_register(new_bus);
512 	} else {
513 		dev_err(&pdev->dev, "Can not get cfg data from DT or ACPI\n");
514 		ret = -ENXIO;
515 	}
516 
517 	if (ret) {
518 		dev_err(&pdev->dev, "Cannot register as MDIO bus!\n");
519 		platform_set_drvdata(pdev, NULL);
520 		return ret;
521 	}
522 
523 	return 0;
524 }
525 
526 /**
527  * hns_mdio_remove - remove mdio device
528  * @pdev: mdio platform device
529  *
530  * Return 0 on success, negative on failure
531  */
532 static int hns_mdio_remove(struct platform_device *pdev)
533 {
534 	struct mii_bus *bus;
535 
536 	bus = platform_get_drvdata(pdev);
537 
538 	mdiobus_unregister(bus);
539 	platform_set_drvdata(pdev, NULL);
540 	return 0;
541 }
542 
543 static const struct of_device_id hns_mdio_match[] = {
544 	{.compatible = "hisilicon,mdio"},
545 	{.compatible = "hisilicon,hns-mdio"},
546 	{}
547 };
548 MODULE_DEVICE_TABLE(of, hns_mdio_match);
549 
550 static const struct acpi_device_id hns_mdio_acpi_match[] = {
551 	{ "HISI0141", 0 },
552 	{ },
553 };
554 MODULE_DEVICE_TABLE(acpi, hns_mdio_acpi_match);
555 
556 static struct platform_driver hns_mdio_driver = {
557 	.probe = hns_mdio_probe,
558 	.remove = hns_mdio_remove,
559 	.driver = {
560 		   .name = MDIO_DRV_NAME,
561 		   .of_match_table = hns_mdio_match,
562 		   .acpi_match_table = ACPI_PTR(hns_mdio_acpi_match),
563 		   },
564 };
565 
566 module_platform_driver(hns_mdio_driver);
567 
568 MODULE_LICENSE("GPL");
569 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
570 MODULE_DESCRIPTION("Hisilicon HNS MDIO driver");
571 MODULE_ALIAS("platform:" MDIO_DRV_NAME);
572