1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* Copyright (c) 2016-2017 Hisilicon Limited. */ 3 4 #ifndef __HCLGEVF_MAIN_H 5 #define __HCLGEVF_MAIN_H 6 #include <linux/fs.h> 7 #include <linux/if_vlan.h> 8 #include <linux/types.h> 9 #include <net/devlink.h> 10 #include "hclge_mbx.h" 11 #include "hclgevf_cmd.h" 12 #include "hnae3.h" 13 14 #define HCLGEVF_MOD_VERSION "1.0" 15 #define HCLGEVF_DRIVER_NAME "hclgevf" 16 17 #define HCLGEVF_MAX_VLAN_ID 4095 18 #define HCLGEVF_MISC_VECTOR_NUM 0 19 20 #define HCLGEVF_INVALID_VPORT 0xffff 21 #define HCLGEVF_GENERAL_TASK_INTERVAL 5 22 #define HCLGEVF_KEEP_ALIVE_TASK_INTERVAL 2 23 24 /* This number in actual depends upon the total number of VFs 25 * created by physical function. But the maximum number of 26 * possible vector-per-VF is {VFn(1-32), VECTn(32 + 1)}. 27 */ 28 #define HCLGEVF_MAX_VF_VECTOR_NUM (32 + 1) 29 30 #define HCLGEVF_VECTOR_REG_BASE 0x20000 31 #define HCLGEVF_MISC_VECTOR_REG_BASE 0x20400 32 #define HCLGEVF_VECTOR_REG_OFFSET 0x4 33 #define HCLGEVF_VECTOR_VF_OFFSET 0x100000 34 35 /* bar registers for cmdq */ 36 #define HCLGEVF_NIC_CSQ_BASEADDR_L_REG 0x27000 37 #define HCLGEVF_NIC_CSQ_BASEADDR_H_REG 0x27004 38 #define HCLGEVF_NIC_CSQ_DEPTH_REG 0x27008 39 #define HCLGEVF_NIC_CSQ_TAIL_REG 0x27010 40 #define HCLGEVF_NIC_CSQ_HEAD_REG 0x27014 41 #define HCLGEVF_NIC_CRQ_BASEADDR_L_REG 0x27018 42 #define HCLGEVF_NIC_CRQ_BASEADDR_H_REG 0x2701C 43 #define HCLGEVF_NIC_CRQ_DEPTH_REG 0x27020 44 #define HCLGEVF_NIC_CRQ_TAIL_REG 0x27024 45 #define HCLGEVF_NIC_CRQ_HEAD_REG 0x27028 46 47 #define HCLGEVF_CMDQ_INTR_EN_REG 0x27108 48 #define HCLGEVF_CMDQ_INTR_GEN_REG 0x2710C 49 50 /* bar registers for common func */ 51 #define HCLGEVF_GRO_EN_REG 0x28000 52 #define HCLGEVF_RXD_ADV_LAYOUT_EN_REG 0x28008 53 54 /* bar registers for rcb */ 55 #define HCLGEVF_RING_RX_ADDR_L_REG 0x80000 56 #define HCLGEVF_RING_RX_ADDR_H_REG 0x80004 57 #define HCLGEVF_RING_RX_BD_NUM_REG 0x80008 58 #define HCLGEVF_RING_RX_BD_LENGTH_REG 0x8000C 59 #define HCLGEVF_RING_RX_MERGE_EN_REG 0x80014 60 #define HCLGEVF_RING_RX_TAIL_REG 0x80018 61 #define HCLGEVF_RING_RX_HEAD_REG 0x8001C 62 #define HCLGEVF_RING_RX_FBD_NUM_REG 0x80020 63 #define HCLGEVF_RING_RX_OFFSET_REG 0x80024 64 #define HCLGEVF_RING_RX_FBD_OFFSET_REG 0x80028 65 #define HCLGEVF_RING_RX_STASH_REG 0x80030 66 #define HCLGEVF_RING_RX_BD_ERR_REG 0x80034 67 #define HCLGEVF_RING_TX_ADDR_L_REG 0x80040 68 #define HCLGEVF_RING_TX_ADDR_H_REG 0x80044 69 #define HCLGEVF_RING_TX_BD_NUM_REG 0x80048 70 #define HCLGEVF_RING_TX_PRIORITY_REG 0x8004C 71 #define HCLGEVF_RING_TX_TC_REG 0x80050 72 #define HCLGEVF_RING_TX_MERGE_EN_REG 0x80054 73 #define HCLGEVF_RING_TX_TAIL_REG 0x80058 74 #define HCLGEVF_RING_TX_HEAD_REG 0x8005C 75 #define HCLGEVF_RING_TX_FBD_NUM_REG 0x80060 76 #define HCLGEVF_RING_TX_OFFSET_REG 0x80064 77 #define HCLGEVF_RING_TX_EBD_NUM_REG 0x80068 78 #define HCLGEVF_RING_TX_EBD_OFFSET_REG 0x80070 79 #define HCLGEVF_RING_TX_BD_ERR_REG 0x80074 80 #define HCLGEVF_RING_EN_REG 0x80090 81 82 /* bar registers for tqp interrupt */ 83 #define HCLGEVF_TQP_INTR_CTRL_REG 0x20000 84 #define HCLGEVF_TQP_INTR_GL0_REG 0x20100 85 #define HCLGEVF_TQP_INTR_GL1_REG 0x20200 86 #define HCLGEVF_TQP_INTR_GL2_REG 0x20300 87 #define HCLGEVF_TQP_INTR_RL_REG 0x20900 88 89 /* Vector0 interrupt CMDQ event source register(RW) */ 90 #define HCLGEVF_VECTOR0_CMDQ_SRC_REG 0x27100 91 /* Vector0 interrupt CMDQ event status register(RO) */ 92 #define HCLGEVF_VECTOR0_CMDQ_STATE_REG 0x27104 93 /* CMDQ register bits for RX event(=MBX event) */ 94 #define HCLGEVF_VECTOR0_RX_CMDQ_INT_B 1 95 /* RST register bits for RESET event */ 96 #define HCLGEVF_VECTOR0_RST_INT_B 2 97 98 #define HCLGEVF_TQP_RESET_TRY_TIMES 10 99 /* Reset related Registers */ 100 #define HCLGEVF_RST_ING 0x20C00 101 #define HCLGEVF_FUN_RST_ING_BIT BIT(0) 102 #define HCLGEVF_GLOBAL_RST_ING_BIT BIT(5) 103 #define HCLGEVF_CORE_RST_ING_BIT BIT(6) 104 #define HCLGEVF_IMP_RST_ING_BIT BIT(7) 105 #define HCLGEVF_RST_ING_BITS \ 106 (HCLGEVF_FUN_RST_ING_BIT | HCLGEVF_GLOBAL_RST_ING_BIT | \ 107 HCLGEVF_CORE_RST_ING_BIT | HCLGEVF_IMP_RST_ING_BIT) 108 109 #define HCLGEVF_VF_RST_ING 0x07008 110 #define HCLGEVF_VF_RST_ING_BIT BIT(16) 111 112 #define HCLGEVF_RSS_IND_TBL_SIZE 512 113 #define HCLGEVF_RSS_SET_BITMAP_MSK 0xffff 114 #define HCLGEVF_RSS_KEY_SIZE 40 115 #define HCLGEVF_RSS_HASH_ALGO_TOEPLITZ 0 116 #define HCLGEVF_RSS_HASH_ALGO_SIMPLE 1 117 #define HCLGEVF_RSS_HASH_ALGO_SYMMETRIC 2 118 #define HCLGEVF_RSS_HASH_ALGO_MASK 0xf 119 120 #define HCLGEVF_RSS_INPUT_TUPLE_OTHER GENMASK(3, 0) 121 #define HCLGEVF_RSS_INPUT_TUPLE_SCTP GENMASK(4, 0) 122 #define HCLGEVF_D_PORT_BIT BIT(0) 123 #define HCLGEVF_S_PORT_BIT BIT(1) 124 #define HCLGEVF_D_IP_BIT BIT(2) 125 #define HCLGEVF_S_IP_BIT BIT(3) 126 #define HCLGEVF_V_TAG_BIT BIT(4) 127 #define HCLGEVF_RSS_INPUT_TUPLE_SCTP_NO_PORT \ 128 (HCLGEVF_D_IP_BIT | HCLGEVF_S_IP_BIT | HCLGEVF_V_TAG_BIT) 129 130 #define HCLGEVF_MAC_MAX_FRAME 9728 131 132 #define HCLGEVF_STATS_TIMER_INTERVAL 36U 133 134 enum hclgevf_evt_cause { 135 HCLGEVF_VECTOR0_EVENT_RST, 136 HCLGEVF_VECTOR0_EVENT_MBX, 137 HCLGEVF_VECTOR0_EVENT_OTHER, 138 }; 139 140 /* states of hclgevf device & tasks */ 141 enum hclgevf_states { 142 /* device states */ 143 HCLGEVF_STATE_DOWN, 144 HCLGEVF_STATE_DISABLED, 145 HCLGEVF_STATE_IRQ_INITED, 146 HCLGEVF_STATE_REMOVING, 147 HCLGEVF_STATE_NIC_REGISTERED, 148 HCLGEVF_STATE_ROCE_REGISTERED, 149 /* task states */ 150 HCLGEVF_STATE_RST_SERVICE_SCHED, 151 HCLGEVF_STATE_RST_HANDLING, 152 HCLGEVF_STATE_MBX_SERVICE_SCHED, 153 HCLGEVF_STATE_MBX_HANDLING, 154 HCLGEVF_STATE_CMD_DISABLE, 155 HCLGEVF_STATE_LINK_UPDATING, 156 HCLGEVF_STATE_PROMISC_CHANGED, 157 HCLGEVF_STATE_RST_FAIL, 158 HCLGEVF_STATE_PF_PUSH_LINK_STATUS, 159 }; 160 161 struct hclgevf_mac { 162 u8 media_type; 163 u8 module_type; 164 u8 mac_addr[ETH_ALEN]; 165 int link; 166 u8 duplex; 167 u32 speed; 168 u64 supported; 169 u64 advertising; 170 }; 171 172 struct hclgevf_hw { 173 void __iomem *io_base; 174 void __iomem *mem_base; 175 int num_vec; 176 struct hclgevf_cmq cmq; 177 struct hclgevf_mac mac; 178 void *hdev; /* hchgevf device it is part of */ 179 }; 180 181 /* TQP stats */ 182 struct hlcgevf_tqp_stats { 183 /* query_tqp_tx_queue_statistics, opcode id: 0x0B03 */ 184 u64 rcb_tx_ring_pktnum_rcd; /* 32bit */ 185 /* query_tqp_rx_queue_statistics, opcode id: 0x0B13 */ 186 u64 rcb_rx_ring_pktnum_rcd; /* 32bit */ 187 }; 188 189 struct hclgevf_tqp { 190 struct device *dev; /* device for DMA mapping */ 191 struct hnae3_queue q; 192 struct hlcgevf_tqp_stats tqp_stats; 193 u16 index; /* global index in a NIC controller */ 194 195 bool alloced; 196 }; 197 198 struct hclgevf_cfg { 199 u8 tc_num; 200 u16 tqp_desc_num; 201 u16 rx_buf_len; 202 u8 phy_addr; 203 u8 media_type; 204 u8 mac_addr[ETH_ALEN]; 205 u32 numa_node_map; 206 }; 207 208 struct hclgevf_rss_tuple_cfg { 209 u8 ipv4_tcp_en; 210 u8 ipv4_udp_en; 211 u8 ipv4_sctp_en; 212 u8 ipv4_fragment_en; 213 u8 ipv6_tcp_en; 214 u8 ipv6_udp_en; 215 u8 ipv6_sctp_en; 216 u8 ipv6_fragment_en; 217 }; 218 219 struct hclgevf_rss_cfg { 220 u8 rss_hash_key[HCLGEVF_RSS_KEY_SIZE]; /* user configured hash keys */ 221 u32 hash_algo; 222 u32 rss_size; 223 u8 hw_tc_map; 224 /* shadow table */ 225 u8 *rss_indirection_tbl; 226 struct hclgevf_rss_tuple_cfg rss_tuple_sets; 227 }; 228 229 struct hclgevf_misc_vector { 230 u8 __iomem *addr; 231 int vector_irq; 232 char name[HNAE3_INT_NAME_LEN]; 233 }; 234 235 struct hclgevf_rst_stats { 236 u32 rst_cnt; /* the number of reset */ 237 u32 vf_func_rst_cnt; /* the number of VF function reset */ 238 u32 flr_rst_cnt; /* the number of FLR */ 239 u32 vf_rst_cnt; /* the number of VF reset */ 240 u32 rst_done_cnt; /* the number of reset completed */ 241 u32 hw_rst_done_cnt; /* the number of HW reset completed */ 242 u32 rst_fail_cnt; /* the number of VF reset fail */ 243 }; 244 245 enum HCLGEVF_MAC_ADDR_TYPE { 246 HCLGEVF_MAC_ADDR_UC, 247 HCLGEVF_MAC_ADDR_MC 248 }; 249 250 enum HCLGEVF_MAC_NODE_STATE { 251 HCLGEVF_MAC_TO_ADD, 252 HCLGEVF_MAC_TO_DEL, 253 HCLGEVF_MAC_ACTIVE 254 }; 255 256 struct hclgevf_mac_addr_node { 257 struct list_head node; 258 enum HCLGEVF_MAC_NODE_STATE state; 259 u8 mac_addr[ETH_ALEN]; 260 }; 261 262 struct hclgevf_mac_table_cfg { 263 spinlock_t mac_list_lock; /* protect mac address need to add/detele */ 264 struct list_head uc_mac_list; 265 struct list_head mc_mac_list; 266 }; 267 268 struct hclgevf_dev { 269 struct pci_dev *pdev; 270 struct hnae3_ae_dev *ae_dev; 271 struct hclgevf_hw hw; 272 struct hclgevf_misc_vector misc_vector; 273 struct hclgevf_rss_cfg rss_cfg; 274 unsigned long state; 275 unsigned long flr_state; 276 unsigned long default_reset_request; 277 unsigned long last_reset_time; 278 enum hnae3_reset_type reset_level; 279 unsigned long reset_pending; 280 enum hnae3_reset_type reset_type; 281 282 #define HCLGEVF_RESET_REQUESTED 0 283 #define HCLGEVF_RESET_PENDING 1 284 unsigned long reset_state; /* requested, pending */ 285 struct hclgevf_rst_stats rst_stats; 286 u32 reset_attempts; 287 struct semaphore reset_sem; /* protect reset process */ 288 289 u32 fw_version; 290 u16 mbx_api_version; 291 u16 num_tqps; /* num task queue pairs of this VF */ 292 293 u16 alloc_rss_size; /* allocated RSS task queue */ 294 u16 rss_size_max; /* HW defined max RSS task queue */ 295 296 u16 num_alloc_vport; /* num vports this driver supports */ 297 u32 numa_node_mask; 298 u16 rx_buf_len; 299 u16 num_tx_desc; /* desc num of per tx queue */ 300 u16 num_rx_desc; /* desc num of per rx queue */ 301 u8 hw_tc_map; 302 u8 has_pf_mac; 303 304 u16 num_msi; 305 u16 num_msi_left; 306 u16 num_msi_used; 307 u16 num_nic_msix; /* Num of nic vectors for this VF */ 308 u16 num_roce_msix; /* Num of roce vectors for this VF */ 309 u16 roce_base_msix_offset; 310 int roce_base_vector; 311 u32 base_msi_vector; 312 u16 *vector_status; 313 int *vector_irq; 314 315 bool gro_en; 316 317 unsigned long vlan_del_fail_bmap[BITS_TO_LONGS(VLAN_N_VID)]; 318 319 struct hclgevf_mac_table_cfg mac_table; 320 321 struct hclgevf_mbx_resp_status mbx_resp; /* mailbox response */ 322 struct hclgevf_mbx_arq_ring arq; /* mailbox async rx queue */ 323 324 struct delayed_work service_task; 325 326 struct hclgevf_tqp *htqp; 327 328 struct hnae3_handle nic; 329 struct hnae3_handle roce; 330 331 struct hnae3_client *nic_client; 332 struct hnae3_client *roce_client; 333 u32 flag; 334 unsigned long serv_processed_cnt; 335 unsigned long last_serv_processed; 336 337 struct devlink *devlink; 338 }; 339 340 static inline bool hclgevf_is_reset_pending(struct hclgevf_dev *hdev) 341 { 342 return !!hdev->reset_pending; 343 } 344 345 int hclgevf_send_mbx_msg(struct hclgevf_dev *hdev, 346 struct hclge_vf_to_pf_msg *send_msg, bool need_resp, 347 u8 *resp_data, u16 resp_len); 348 void hclgevf_mbx_handler(struct hclgevf_dev *hdev); 349 void hclgevf_mbx_async_handler(struct hclgevf_dev *hdev); 350 351 void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state); 352 void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed, 353 u8 duplex); 354 void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev); 355 void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev); 356 void hclgevf_update_port_base_vlan_info(struct hclgevf_dev *hdev, u16 state, 357 u8 *port_base_vlan_info, u8 data_size); 358 #endif 359