1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* Copyright (c) 2016-2017 Hisilicon Limited. */ 3 4 #ifndef __HCLGEVF_MAIN_H 5 #define __HCLGEVF_MAIN_H 6 #include <linux/fs.h> 7 #include <linux/if_vlan.h> 8 #include <linux/types.h> 9 #include "hclge_mbx.h" 10 #include "hclgevf_cmd.h" 11 #include "hnae3.h" 12 13 #define HCLGEVF_MOD_VERSION "1.0" 14 #define HCLGEVF_DRIVER_NAME "hclgevf" 15 16 #define HCLGEVF_MAX_VLAN_ID 4095 17 #define HCLGEVF_MISC_VECTOR_NUM 0 18 19 #define HCLGEVF_INVALID_VPORT 0xffff 20 #define HCLGEVF_GENERAL_TASK_INTERVAL 5 21 #define HCLGEVF_KEEP_ALIVE_TASK_INTERVAL 2 22 23 /* This number in actual depends upon the total number of VFs 24 * created by physical function. But the maximum number of 25 * possible vector-per-VF is {VFn(1-32), VECTn(32 + 1)}. 26 */ 27 #define HCLGEVF_MAX_VF_VECTOR_NUM (32 + 1) 28 29 #define HCLGEVF_VECTOR_REG_BASE 0x20000 30 #define HCLGEVF_MISC_VECTOR_REG_BASE 0x20400 31 #define HCLGEVF_VECTOR_REG_OFFSET 0x4 32 #define HCLGEVF_VECTOR_VF_OFFSET 0x100000 33 34 /* bar registers for cmdq */ 35 #define HCLGEVF_CMDQ_TX_ADDR_L_REG 0x27000 36 #define HCLGEVF_CMDQ_TX_ADDR_H_REG 0x27004 37 #define HCLGEVF_CMDQ_TX_DEPTH_REG 0x27008 38 #define HCLGEVF_CMDQ_TX_TAIL_REG 0x27010 39 #define HCLGEVF_CMDQ_TX_HEAD_REG 0x27014 40 #define HCLGEVF_CMDQ_RX_ADDR_L_REG 0x27018 41 #define HCLGEVF_CMDQ_RX_ADDR_H_REG 0x2701C 42 #define HCLGEVF_CMDQ_RX_DEPTH_REG 0x27020 43 #define HCLGEVF_CMDQ_RX_TAIL_REG 0x27024 44 #define HCLGEVF_CMDQ_RX_HEAD_REG 0x27028 45 #define HCLGEVF_CMDQ_INTR_EN_REG 0x27108 46 #define HCLGEVF_CMDQ_INTR_GEN_REG 0x2710C 47 48 /* bar registers for common func */ 49 #define HCLGEVF_GRO_EN_REG 0x28000 50 #define HCLGEVF_RXD_ADV_LAYOUT_EN_REG 0x28008 51 52 /* bar registers for rcb */ 53 #define HCLGEVF_RING_RX_ADDR_L_REG 0x80000 54 #define HCLGEVF_RING_RX_ADDR_H_REG 0x80004 55 #define HCLGEVF_RING_RX_BD_NUM_REG 0x80008 56 #define HCLGEVF_RING_RX_BD_LENGTH_REG 0x8000C 57 #define HCLGEVF_RING_RX_MERGE_EN_REG 0x80014 58 #define HCLGEVF_RING_RX_TAIL_REG 0x80018 59 #define HCLGEVF_RING_RX_HEAD_REG 0x8001C 60 #define HCLGEVF_RING_RX_FBD_NUM_REG 0x80020 61 #define HCLGEVF_RING_RX_OFFSET_REG 0x80024 62 #define HCLGEVF_RING_RX_FBD_OFFSET_REG 0x80028 63 #define HCLGEVF_RING_RX_STASH_REG 0x80030 64 #define HCLGEVF_RING_RX_BD_ERR_REG 0x80034 65 #define HCLGEVF_RING_TX_ADDR_L_REG 0x80040 66 #define HCLGEVF_RING_TX_ADDR_H_REG 0x80044 67 #define HCLGEVF_RING_TX_BD_NUM_REG 0x80048 68 #define HCLGEVF_RING_TX_PRIORITY_REG 0x8004C 69 #define HCLGEVF_RING_TX_TC_REG 0x80050 70 #define HCLGEVF_RING_TX_MERGE_EN_REG 0x80054 71 #define HCLGEVF_RING_TX_TAIL_REG 0x80058 72 #define HCLGEVF_RING_TX_HEAD_REG 0x8005C 73 #define HCLGEVF_RING_TX_FBD_NUM_REG 0x80060 74 #define HCLGEVF_RING_TX_OFFSET_REG 0x80064 75 #define HCLGEVF_RING_TX_EBD_NUM_REG 0x80068 76 #define HCLGEVF_RING_TX_EBD_OFFSET_REG 0x80070 77 #define HCLGEVF_RING_TX_BD_ERR_REG 0x80074 78 #define HCLGEVF_RING_EN_REG 0x80090 79 80 /* bar registers for tqp interrupt */ 81 #define HCLGEVF_TQP_INTR_CTRL_REG 0x20000 82 #define HCLGEVF_TQP_INTR_GL0_REG 0x20100 83 #define HCLGEVF_TQP_INTR_GL1_REG 0x20200 84 #define HCLGEVF_TQP_INTR_GL2_REG 0x20300 85 #define HCLGEVF_TQP_INTR_RL_REG 0x20900 86 87 /* Vector0 interrupt CMDQ event source register(RW) */ 88 #define HCLGEVF_VECTOR0_CMDQ_SRC_REG 0x27100 89 /* Vector0 interrupt CMDQ event status register(RO) */ 90 #define HCLGEVF_VECTOR0_CMDQ_STATE_REG 0x27104 91 /* CMDQ register bits for RX event(=MBX event) */ 92 #define HCLGEVF_VECTOR0_RX_CMDQ_INT_B 1 93 /* RST register bits for RESET event */ 94 #define HCLGEVF_VECTOR0_RST_INT_B 2 95 96 #define HCLGEVF_TQP_RESET_TRY_TIMES 10 97 /* Reset related Registers */ 98 #define HCLGEVF_RST_ING 0x20C00 99 #define HCLGEVF_FUN_RST_ING_BIT BIT(0) 100 #define HCLGEVF_GLOBAL_RST_ING_BIT BIT(5) 101 #define HCLGEVF_CORE_RST_ING_BIT BIT(6) 102 #define HCLGEVF_IMP_RST_ING_BIT BIT(7) 103 #define HCLGEVF_RST_ING_BITS \ 104 (HCLGEVF_FUN_RST_ING_BIT | HCLGEVF_GLOBAL_RST_ING_BIT | \ 105 HCLGEVF_CORE_RST_ING_BIT | HCLGEVF_IMP_RST_ING_BIT) 106 107 #define HCLGEVF_VF_RST_ING 0x07008 108 #define HCLGEVF_VF_RST_ING_BIT BIT(16) 109 110 #define HCLGEVF_RSS_IND_TBL_SIZE 512 111 #define HCLGEVF_RSS_SET_BITMAP_MSK 0xffff 112 #define HCLGEVF_RSS_KEY_SIZE 40 113 #define HCLGEVF_RSS_HASH_ALGO_TOEPLITZ 0 114 #define HCLGEVF_RSS_HASH_ALGO_SIMPLE 1 115 #define HCLGEVF_RSS_HASH_ALGO_SYMMETRIC 2 116 #define HCLGEVF_RSS_HASH_ALGO_MASK 0xf 117 118 #define HCLGEVF_RSS_INPUT_TUPLE_OTHER GENMASK(3, 0) 119 #define HCLGEVF_RSS_INPUT_TUPLE_SCTP GENMASK(4, 0) 120 #define HCLGEVF_D_PORT_BIT BIT(0) 121 #define HCLGEVF_S_PORT_BIT BIT(1) 122 #define HCLGEVF_D_IP_BIT BIT(2) 123 #define HCLGEVF_S_IP_BIT BIT(3) 124 #define HCLGEVF_V_TAG_BIT BIT(4) 125 #define HCLGEVF_RSS_INPUT_TUPLE_SCTP_NO_PORT \ 126 (HCLGEVF_D_IP_BIT | HCLGEVF_S_IP_BIT | HCLGEVF_V_TAG_BIT) 127 128 #define HCLGEVF_MAC_MAX_FRAME 9728 129 130 #define HCLGEVF_STATS_TIMER_INTERVAL 36U 131 132 enum hclgevf_evt_cause { 133 HCLGEVF_VECTOR0_EVENT_RST, 134 HCLGEVF_VECTOR0_EVENT_MBX, 135 HCLGEVF_VECTOR0_EVENT_OTHER, 136 }; 137 138 /* states of hclgevf device & tasks */ 139 enum hclgevf_states { 140 /* device states */ 141 HCLGEVF_STATE_DOWN, 142 HCLGEVF_STATE_DISABLED, 143 HCLGEVF_STATE_IRQ_INITED, 144 HCLGEVF_STATE_REMOVING, 145 HCLGEVF_STATE_NIC_REGISTERED, 146 HCLGEVF_STATE_ROCE_REGISTERED, 147 /* task states */ 148 HCLGEVF_STATE_RST_SERVICE_SCHED, 149 HCLGEVF_STATE_RST_HANDLING, 150 HCLGEVF_STATE_MBX_SERVICE_SCHED, 151 HCLGEVF_STATE_MBX_HANDLING, 152 HCLGEVF_STATE_CMD_DISABLE, 153 HCLGEVF_STATE_LINK_UPDATING, 154 HCLGEVF_STATE_PROMISC_CHANGED, 155 HCLGEVF_STATE_RST_FAIL, 156 HCLGEVF_STATE_PF_PUSH_LINK_STATUS, 157 }; 158 159 struct hclgevf_mac { 160 u8 media_type; 161 u8 module_type; 162 u8 mac_addr[ETH_ALEN]; 163 int link; 164 u8 duplex; 165 u32 speed; 166 u64 supported; 167 u64 advertising; 168 }; 169 170 struct hclgevf_hw { 171 void __iomem *io_base; 172 void __iomem *mem_base; 173 int num_vec; 174 struct hclgevf_cmq cmq; 175 struct hclgevf_mac mac; 176 void *hdev; /* hchgevf device it is part of */ 177 }; 178 179 /* TQP stats */ 180 struct hlcgevf_tqp_stats { 181 /* query_tqp_tx_queue_statistics, opcode id: 0x0B03 */ 182 u64 rcb_tx_ring_pktnum_rcd; /* 32bit */ 183 /* query_tqp_rx_queue_statistics, opcode id: 0x0B13 */ 184 u64 rcb_rx_ring_pktnum_rcd; /* 32bit */ 185 }; 186 187 struct hclgevf_tqp { 188 struct device *dev; /* device for DMA mapping */ 189 struct hnae3_queue q; 190 struct hlcgevf_tqp_stats tqp_stats; 191 u16 index; /* global index in a NIC controller */ 192 193 bool alloced; 194 }; 195 196 struct hclgevf_cfg { 197 u8 tc_num; 198 u16 tqp_desc_num; 199 u16 rx_buf_len; 200 u8 phy_addr; 201 u8 media_type; 202 u8 mac_addr[ETH_ALEN]; 203 u32 numa_node_map; 204 }; 205 206 struct hclgevf_rss_tuple_cfg { 207 u8 ipv4_tcp_en; 208 u8 ipv4_udp_en; 209 u8 ipv4_sctp_en; 210 u8 ipv4_fragment_en; 211 u8 ipv6_tcp_en; 212 u8 ipv6_udp_en; 213 u8 ipv6_sctp_en; 214 u8 ipv6_fragment_en; 215 }; 216 217 struct hclgevf_rss_cfg { 218 u8 rss_hash_key[HCLGEVF_RSS_KEY_SIZE]; /* user configured hash keys */ 219 u32 hash_algo; 220 u32 rss_size; 221 u8 hw_tc_map; 222 /* shadow table */ 223 u8 *rss_indirection_tbl; 224 struct hclgevf_rss_tuple_cfg rss_tuple_sets; 225 }; 226 227 struct hclgevf_misc_vector { 228 u8 __iomem *addr; 229 int vector_irq; 230 char name[HNAE3_INT_NAME_LEN]; 231 }; 232 233 struct hclgevf_rst_stats { 234 u32 rst_cnt; /* the number of reset */ 235 u32 vf_func_rst_cnt; /* the number of VF function reset */ 236 u32 flr_rst_cnt; /* the number of FLR */ 237 u32 vf_rst_cnt; /* the number of VF reset */ 238 u32 rst_done_cnt; /* the number of reset completed */ 239 u32 hw_rst_done_cnt; /* the number of HW reset completed */ 240 u32 rst_fail_cnt; /* the number of VF reset fail */ 241 }; 242 243 enum HCLGEVF_MAC_ADDR_TYPE { 244 HCLGEVF_MAC_ADDR_UC, 245 HCLGEVF_MAC_ADDR_MC 246 }; 247 248 enum HCLGEVF_MAC_NODE_STATE { 249 HCLGEVF_MAC_TO_ADD, 250 HCLGEVF_MAC_TO_DEL, 251 HCLGEVF_MAC_ACTIVE 252 }; 253 254 struct hclgevf_mac_addr_node { 255 struct list_head node; 256 enum HCLGEVF_MAC_NODE_STATE state; 257 u8 mac_addr[ETH_ALEN]; 258 }; 259 260 struct hclgevf_mac_table_cfg { 261 spinlock_t mac_list_lock; /* protect mac address need to add/detele */ 262 struct list_head uc_mac_list; 263 struct list_head mc_mac_list; 264 }; 265 266 struct hclgevf_dev { 267 struct pci_dev *pdev; 268 struct hnae3_ae_dev *ae_dev; 269 struct hclgevf_hw hw; 270 struct hclgevf_misc_vector misc_vector; 271 struct hclgevf_rss_cfg rss_cfg; 272 unsigned long state; 273 unsigned long flr_state; 274 unsigned long default_reset_request; 275 unsigned long last_reset_time; 276 enum hnae3_reset_type reset_level; 277 unsigned long reset_pending; 278 enum hnae3_reset_type reset_type; 279 280 #define HCLGEVF_RESET_REQUESTED 0 281 #define HCLGEVF_RESET_PENDING 1 282 unsigned long reset_state; /* requested, pending */ 283 struct hclgevf_rst_stats rst_stats; 284 u32 reset_attempts; 285 struct semaphore reset_sem; /* protect reset process */ 286 287 u32 fw_version; 288 u16 mbx_api_version; 289 u16 num_tqps; /* num task queue pairs of this VF */ 290 291 u16 alloc_rss_size; /* allocated RSS task queue */ 292 u16 rss_size_max; /* HW defined max RSS task queue */ 293 294 u16 num_alloc_vport; /* num vports this driver supports */ 295 u32 numa_node_mask; 296 u16 rx_buf_len; 297 u16 num_tx_desc; /* desc num of per tx queue */ 298 u16 num_rx_desc; /* desc num of per rx queue */ 299 u8 hw_tc_map; 300 u8 has_pf_mac; 301 302 u16 num_msi; 303 u16 num_msi_left; 304 u16 num_msi_used; 305 u16 num_nic_msix; /* Num of nic vectors for this VF */ 306 u16 num_roce_msix; /* Num of roce vectors for this VF */ 307 u16 roce_base_msix_offset; 308 int roce_base_vector; 309 u32 base_msi_vector; 310 u16 *vector_status; 311 int *vector_irq; 312 313 unsigned long vlan_del_fail_bmap[BITS_TO_LONGS(VLAN_N_VID)]; 314 315 struct hclgevf_mac_table_cfg mac_table; 316 317 bool mbx_event_pending; 318 struct hclgevf_mbx_resp_status mbx_resp; /* mailbox response */ 319 struct hclgevf_mbx_arq_ring arq; /* mailbox async rx queue */ 320 321 struct delayed_work service_task; 322 323 struct hclgevf_tqp *htqp; 324 325 struct hnae3_handle nic; 326 struct hnae3_handle roce; 327 328 struct hnae3_client *nic_client; 329 struct hnae3_client *roce_client; 330 u32 flag; 331 unsigned long serv_processed_cnt; 332 unsigned long last_serv_processed; 333 }; 334 335 static inline bool hclgevf_is_reset_pending(struct hclgevf_dev *hdev) 336 { 337 return !!hdev->reset_pending; 338 } 339 340 int hclgevf_send_mbx_msg(struct hclgevf_dev *hdev, 341 struct hclge_vf_to_pf_msg *send_msg, bool need_resp, 342 u8 *resp_data, u16 resp_len); 343 void hclgevf_mbx_handler(struct hclgevf_dev *hdev); 344 void hclgevf_mbx_async_handler(struct hclgevf_dev *hdev); 345 346 void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state); 347 void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed, 348 u8 duplex); 349 void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev); 350 void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev); 351 void hclgevf_update_port_base_vlan_info(struct hclgevf_dev *hdev, u16 state, 352 u8 *port_base_vlan_info, u8 data_size); 353 #endif 354