1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* Copyright (c) 2016-2017 Hisilicon Limited. */ 3 4 #ifndef __HCLGEVF_MAIN_H 5 #define __HCLGEVF_MAIN_H 6 #include <linux/fs.h> 7 #include <linux/if_vlan.h> 8 #include <linux/types.h> 9 #include "hclge_mbx.h" 10 #include "hclgevf_cmd.h" 11 #include "hnae3.h" 12 13 #define HCLGEVF_MOD_VERSION "1.0" 14 #define HCLGEVF_DRIVER_NAME "hclgevf" 15 16 #define HCLGEVF_MAX_VLAN_ID 4095 17 #define HCLGEVF_MISC_VECTOR_NUM 0 18 19 #define HCLGEVF_INVALID_VPORT 0xffff 20 #define HCLGEVF_GENERAL_TASK_INTERVAL 5 21 #define HCLGEVF_KEEP_ALIVE_TASK_INTERVAL 2 22 23 /* This number in actual depends upon the total number of VFs 24 * created by physical function. But the maximum number of 25 * possible vector-per-VF is {VFn(1-32), VECTn(32 + 1)}. 26 */ 27 #define HCLGEVF_MAX_VF_VECTOR_NUM (32 + 1) 28 29 #define HCLGEVF_VECTOR_REG_BASE 0x20000 30 #define HCLGEVF_MISC_VECTOR_REG_BASE 0x20400 31 #define HCLGEVF_VECTOR_REG_OFFSET 0x4 32 #define HCLGEVF_VECTOR_VF_OFFSET 0x100000 33 34 /* bar registers for cmdq */ 35 #define HCLGEVF_CMDQ_TX_ADDR_L_REG 0x27000 36 #define HCLGEVF_CMDQ_TX_ADDR_H_REG 0x27004 37 #define HCLGEVF_CMDQ_TX_DEPTH_REG 0x27008 38 #define HCLGEVF_CMDQ_TX_TAIL_REG 0x27010 39 #define HCLGEVF_CMDQ_TX_HEAD_REG 0x27014 40 #define HCLGEVF_CMDQ_RX_ADDR_L_REG 0x27018 41 #define HCLGEVF_CMDQ_RX_ADDR_H_REG 0x2701C 42 #define HCLGEVF_CMDQ_RX_DEPTH_REG 0x27020 43 #define HCLGEVF_CMDQ_RX_TAIL_REG 0x27024 44 #define HCLGEVF_CMDQ_RX_HEAD_REG 0x27028 45 #define HCLGEVF_CMDQ_INTR_EN_REG 0x27108 46 #define HCLGEVF_CMDQ_INTR_GEN_REG 0x2710C 47 48 /* bar registers for common func */ 49 #define HCLGEVF_GRO_EN_REG 0x28000 50 51 /* bar registers for rcb */ 52 #define HCLGEVF_RING_RX_ADDR_L_REG 0x80000 53 #define HCLGEVF_RING_RX_ADDR_H_REG 0x80004 54 #define HCLGEVF_RING_RX_BD_NUM_REG 0x80008 55 #define HCLGEVF_RING_RX_BD_LENGTH_REG 0x8000C 56 #define HCLGEVF_RING_RX_MERGE_EN_REG 0x80014 57 #define HCLGEVF_RING_RX_TAIL_REG 0x80018 58 #define HCLGEVF_RING_RX_HEAD_REG 0x8001C 59 #define HCLGEVF_RING_RX_FBD_NUM_REG 0x80020 60 #define HCLGEVF_RING_RX_OFFSET_REG 0x80024 61 #define HCLGEVF_RING_RX_FBD_OFFSET_REG 0x80028 62 #define HCLGEVF_RING_RX_STASH_REG 0x80030 63 #define HCLGEVF_RING_RX_BD_ERR_REG 0x80034 64 #define HCLGEVF_RING_TX_ADDR_L_REG 0x80040 65 #define HCLGEVF_RING_TX_ADDR_H_REG 0x80044 66 #define HCLGEVF_RING_TX_BD_NUM_REG 0x80048 67 #define HCLGEVF_RING_TX_PRIORITY_REG 0x8004C 68 #define HCLGEVF_RING_TX_TC_REG 0x80050 69 #define HCLGEVF_RING_TX_MERGE_EN_REG 0x80054 70 #define HCLGEVF_RING_TX_TAIL_REG 0x80058 71 #define HCLGEVF_RING_TX_HEAD_REG 0x8005C 72 #define HCLGEVF_RING_TX_FBD_NUM_REG 0x80060 73 #define HCLGEVF_RING_TX_OFFSET_REG 0x80064 74 #define HCLGEVF_RING_TX_EBD_NUM_REG 0x80068 75 #define HCLGEVF_RING_TX_EBD_OFFSET_REG 0x80070 76 #define HCLGEVF_RING_TX_BD_ERR_REG 0x80074 77 #define HCLGEVF_RING_EN_REG 0x80090 78 79 /* bar registers for tqp interrupt */ 80 #define HCLGEVF_TQP_INTR_CTRL_REG 0x20000 81 #define HCLGEVF_TQP_INTR_GL0_REG 0x20100 82 #define HCLGEVF_TQP_INTR_GL1_REG 0x20200 83 #define HCLGEVF_TQP_INTR_GL2_REG 0x20300 84 #define HCLGEVF_TQP_INTR_RL_REG 0x20900 85 86 /* Vector0 interrupt CMDQ event source register(RW) */ 87 #define HCLGEVF_VECTOR0_CMDQ_SRC_REG 0x27100 88 /* Vector0 interrupt CMDQ event status register(RO) */ 89 #define HCLGEVF_VECTOR0_CMDQ_STATE_REG 0x27104 90 /* CMDQ register bits for RX event(=MBX event) */ 91 #define HCLGEVF_VECTOR0_RX_CMDQ_INT_B 1 92 /* RST register bits for RESET event */ 93 #define HCLGEVF_VECTOR0_RST_INT_B 2 94 95 #define HCLGEVF_TQP_RESET_TRY_TIMES 10 96 /* Reset related Registers */ 97 #define HCLGEVF_RST_ING 0x20C00 98 #define HCLGEVF_FUN_RST_ING_BIT BIT(0) 99 #define HCLGEVF_GLOBAL_RST_ING_BIT BIT(5) 100 #define HCLGEVF_CORE_RST_ING_BIT BIT(6) 101 #define HCLGEVF_IMP_RST_ING_BIT BIT(7) 102 #define HCLGEVF_RST_ING_BITS \ 103 (HCLGEVF_FUN_RST_ING_BIT | HCLGEVF_GLOBAL_RST_ING_BIT | \ 104 HCLGEVF_CORE_RST_ING_BIT | HCLGEVF_IMP_RST_ING_BIT) 105 106 #define HCLGEVF_VF_RST_ING 0x07008 107 #define HCLGEVF_VF_RST_ING_BIT BIT(16) 108 109 #define HCLGEVF_RSS_IND_TBL_SIZE 512 110 #define HCLGEVF_RSS_SET_BITMAP_MSK 0xffff 111 #define HCLGEVF_RSS_KEY_SIZE 40 112 #define HCLGEVF_RSS_HASH_ALGO_TOEPLITZ 0 113 #define HCLGEVF_RSS_HASH_ALGO_SIMPLE 1 114 #define HCLGEVF_RSS_HASH_ALGO_SYMMETRIC 2 115 #define HCLGEVF_RSS_HASH_ALGO_MASK 0xf 116 #define HCLGEVF_RSS_CFG_TBL_NUM \ 117 (HCLGEVF_RSS_IND_TBL_SIZE / HCLGEVF_RSS_CFG_TBL_SIZE) 118 #define HCLGEVF_RSS_INPUT_TUPLE_OTHER GENMASK(3, 0) 119 #define HCLGEVF_RSS_INPUT_TUPLE_SCTP GENMASK(4, 0) 120 #define HCLGEVF_D_PORT_BIT BIT(0) 121 #define HCLGEVF_S_PORT_BIT BIT(1) 122 #define HCLGEVF_D_IP_BIT BIT(2) 123 #define HCLGEVF_S_IP_BIT BIT(3) 124 #define HCLGEVF_V_TAG_BIT BIT(4) 125 126 #define HCLGEVF_STATS_TIMER_INTERVAL 36U 127 128 enum hclgevf_evt_cause { 129 HCLGEVF_VECTOR0_EVENT_RST, 130 HCLGEVF_VECTOR0_EVENT_MBX, 131 HCLGEVF_VECTOR0_EVENT_OTHER, 132 }; 133 134 /* states of hclgevf device & tasks */ 135 enum hclgevf_states { 136 /* device states */ 137 HCLGEVF_STATE_DOWN, 138 HCLGEVF_STATE_DISABLED, 139 HCLGEVF_STATE_IRQ_INITED, 140 HCLGEVF_STATE_REMOVING, 141 HCLGEVF_STATE_NIC_REGISTERED, 142 HCLGEVF_STATE_ROCE_REGISTERED, 143 /* task states */ 144 HCLGEVF_STATE_RST_SERVICE_SCHED, 145 HCLGEVF_STATE_RST_HANDLING, 146 HCLGEVF_STATE_MBX_SERVICE_SCHED, 147 HCLGEVF_STATE_MBX_HANDLING, 148 HCLGEVF_STATE_CMD_DISABLE, 149 HCLGEVF_STATE_LINK_UPDATING, 150 HCLGEVF_STATE_PROMISC_CHANGED, 151 HCLGEVF_STATE_RST_FAIL, 152 }; 153 154 struct hclgevf_mac { 155 u8 media_type; 156 u8 module_type; 157 u8 mac_addr[ETH_ALEN]; 158 int link; 159 u8 duplex; 160 u32 speed; 161 u64 supported; 162 u64 advertising; 163 }; 164 165 struct hclgevf_hw { 166 void __iomem *io_base; 167 void __iomem *mem_base; 168 int num_vec; 169 struct hclgevf_cmq cmq; 170 struct hclgevf_mac mac; 171 void *hdev; /* hchgevf device it is part of */ 172 }; 173 174 /* TQP stats */ 175 struct hlcgevf_tqp_stats { 176 /* query_tqp_tx_queue_statistics ,opcode id: 0x0B03 */ 177 u64 rcb_tx_ring_pktnum_rcd; /* 32bit */ 178 /* query_tqp_rx_queue_statistics ,opcode id: 0x0B13 */ 179 u64 rcb_rx_ring_pktnum_rcd; /* 32bit */ 180 }; 181 182 struct hclgevf_tqp { 183 struct device *dev; /* device for DMA mapping */ 184 struct hnae3_queue q; 185 struct hlcgevf_tqp_stats tqp_stats; 186 u16 index; /* global index in a NIC controller */ 187 188 bool alloced; 189 }; 190 191 struct hclgevf_cfg { 192 u8 vmdq_vport_num; 193 u8 tc_num; 194 u16 tqp_desc_num; 195 u16 rx_buf_len; 196 u8 phy_addr; 197 u8 media_type; 198 u8 mac_addr[ETH_ALEN]; 199 u32 numa_node_map; 200 }; 201 202 struct hclgevf_rss_tuple_cfg { 203 u8 ipv4_tcp_en; 204 u8 ipv4_udp_en; 205 u8 ipv4_sctp_en; 206 u8 ipv4_fragment_en; 207 u8 ipv6_tcp_en; 208 u8 ipv6_udp_en; 209 u8 ipv6_sctp_en; 210 u8 ipv6_fragment_en; 211 }; 212 213 struct hclgevf_rss_cfg { 214 u8 rss_hash_key[HCLGEVF_RSS_KEY_SIZE]; /* user configured hash keys */ 215 u32 hash_algo; 216 u32 rss_size; 217 u8 hw_tc_map; 218 u8 rss_indirection_tbl[HCLGEVF_RSS_IND_TBL_SIZE]; /* shadow table */ 219 struct hclgevf_rss_tuple_cfg rss_tuple_sets; 220 }; 221 222 struct hclgevf_misc_vector { 223 u8 __iomem *addr; 224 int vector_irq; 225 char name[HNAE3_INT_NAME_LEN]; 226 }; 227 228 struct hclgevf_rst_stats { 229 u32 rst_cnt; /* the number of reset */ 230 u32 vf_func_rst_cnt; /* the number of VF function reset */ 231 u32 flr_rst_cnt; /* the number of FLR */ 232 u32 vf_rst_cnt; /* the number of VF reset */ 233 u32 rst_done_cnt; /* the number of reset completed */ 234 u32 hw_rst_done_cnt; /* the number of HW reset completed */ 235 u32 rst_fail_cnt; /* the number of VF reset fail */ 236 }; 237 238 enum HCLGEVF_MAC_ADDR_TYPE { 239 HCLGEVF_MAC_ADDR_UC, 240 HCLGEVF_MAC_ADDR_MC 241 }; 242 243 enum HCLGEVF_MAC_NODE_STATE { 244 HCLGEVF_MAC_TO_ADD, 245 HCLGEVF_MAC_TO_DEL, 246 HCLGEVF_MAC_ACTIVE 247 }; 248 249 struct hclgevf_mac_addr_node { 250 struct list_head node; 251 enum HCLGEVF_MAC_NODE_STATE state; 252 u8 mac_addr[ETH_ALEN]; 253 }; 254 255 struct hclgevf_mac_table_cfg { 256 spinlock_t mac_list_lock; /* protect mac address need to add/detele */ 257 struct list_head uc_mac_list; 258 struct list_head mc_mac_list; 259 }; 260 261 struct hclgevf_dev { 262 struct pci_dev *pdev; 263 struct hnae3_ae_dev *ae_dev; 264 struct hclgevf_hw hw; 265 struct hclgevf_misc_vector misc_vector; 266 struct hclgevf_rss_cfg rss_cfg; 267 unsigned long state; 268 unsigned long flr_state; 269 unsigned long default_reset_request; 270 unsigned long last_reset_time; 271 enum hnae3_reset_type reset_level; 272 unsigned long reset_pending; 273 enum hnae3_reset_type reset_type; 274 275 #define HCLGEVF_RESET_REQUESTED 0 276 #define HCLGEVF_RESET_PENDING 1 277 unsigned long reset_state; /* requested, pending */ 278 struct hclgevf_rst_stats rst_stats; 279 u32 reset_attempts; 280 struct semaphore reset_sem; /* protect reset process */ 281 282 u32 fw_version; 283 u16 num_tqps; /* num task queue pairs of this VF */ 284 285 u16 alloc_rss_size; /* allocated RSS task queue */ 286 u16 rss_size_max; /* HW defined max RSS task queue */ 287 288 u16 num_alloc_vport; /* num vports this driver supports */ 289 u32 numa_node_mask; 290 u16 rx_buf_len; 291 u16 num_tx_desc; /* desc num of per tx queue */ 292 u16 num_rx_desc; /* desc num of per rx queue */ 293 u8 hw_tc_map; 294 u8 has_pf_mac; 295 296 u16 num_msi; 297 u16 num_msi_left; 298 u16 num_msi_used; 299 u16 num_nic_msix; /* Num of nic vectors for this VF */ 300 u16 num_roce_msix; /* Num of roce vectors for this VF */ 301 u16 roce_base_msix_offset; 302 int roce_base_vector; 303 u32 base_msi_vector; 304 u16 *vector_status; 305 int *vector_irq; 306 307 unsigned long vlan_del_fail_bmap[BITS_TO_LONGS(VLAN_N_VID)]; 308 309 struct hclgevf_mac_table_cfg mac_table; 310 311 bool mbx_event_pending; 312 struct hclgevf_mbx_resp_status mbx_resp; /* mailbox response */ 313 struct hclgevf_mbx_arq_ring arq; /* mailbox async rx queue */ 314 315 struct delayed_work service_task; 316 317 struct hclgevf_tqp *htqp; 318 319 struct hnae3_handle nic; 320 struct hnae3_handle roce; 321 322 struct hnae3_client *nic_client; 323 struct hnae3_client *roce_client; 324 u32 flag; 325 unsigned long serv_processed_cnt; 326 unsigned long last_serv_processed; 327 }; 328 329 static inline bool hclgevf_is_reset_pending(struct hclgevf_dev *hdev) 330 { 331 return !!hdev->reset_pending; 332 } 333 334 int hclgevf_send_mbx_msg(struct hclgevf_dev *hdev, 335 struct hclge_vf_to_pf_msg *send_msg, bool need_resp, 336 u8 *resp_data, u16 resp_len); 337 void hclgevf_mbx_handler(struct hclgevf_dev *hdev); 338 void hclgevf_mbx_async_handler(struct hclgevf_dev *hdev); 339 340 void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state); 341 void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed, 342 u8 duplex); 343 void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev); 344 void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev); 345 void hclgevf_update_port_base_vlan_info(struct hclgevf_dev *hdev, u16 state, 346 u8 *port_base_vlan_info, u8 data_size); 347 #endif 348