1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /* Copyright (c) 2016-2017 Hisilicon Limited. */
3 
4 #ifndef __HCLGEVF_MAIN_H
5 #define __HCLGEVF_MAIN_H
6 #include <linux/fs.h>
7 #include <linux/if_vlan.h>
8 #include <linux/types.h>
9 #include <net/devlink.h>
10 #include "hclge_mbx.h"
11 #include "hclgevf_cmd.h"
12 #include "hnae3.h"
13 #include "hclge_comm_rss.h"
14 #include "hclge_comm_tqp_stats.h"
15 
16 #define HCLGEVF_MOD_VERSION "1.0"
17 #define HCLGEVF_DRIVER_NAME "hclgevf"
18 
19 #define HCLGEVF_MAX_VLAN_ID	4095
20 #define HCLGEVF_MISC_VECTOR_NUM		0
21 
22 #define HCLGEVF_INVALID_VPORT		0xffff
23 #define HCLGEVF_GENERAL_TASK_INTERVAL	  5
24 #define HCLGEVF_KEEP_ALIVE_TASK_INTERVAL  2
25 
26 /* This number in actual depends upon the total number of VFs
27  * created by physical function. But the maximum number of
28  * possible vector-per-VF is {VFn(1-32), VECTn(32 + 1)}.
29  */
30 #define HCLGEVF_MAX_VF_VECTOR_NUM	(32 + 1)
31 
32 #define HCLGEVF_VECTOR_REG_BASE		0x20000
33 #define HCLGEVF_MISC_VECTOR_REG_BASE	0x20400
34 #define HCLGEVF_VECTOR_REG_OFFSET	0x4
35 #define HCLGEVF_VECTOR_VF_OFFSET		0x100000
36 
37 /* bar registers for common func */
38 #define HCLGEVF_GRO_EN_REG			0x28000
39 #define HCLGEVF_RXD_ADV_LAYOUT_EN_REG		0x28008
40 
41 /* bar registers for rcb */
42 #define HCLGEVF_RING_RX_ADDR_L_REG		0x80000
43 #define HCLGEVF_RING_RX_ADDR_H_REG		0x80004
44 #define HCLGEVF_RING_RX_BD_NUM_REG		0x80008
45 #define HCLGEVF_RING_RX_BD_LENGTH_REG		0x8000C
46 #define HCLGEVF_RING_RX_MERGE_EN_REG		0x80014
47 #define HCLGEVF_RING_RX_TAIL_REG		0x80018
48 #define HCLGEVF_RING_RX_HEAD_REG		0x8001C
49 #define HCLGEVF_RING_RX_FBD_NUM_REG		0x80020
50 #define HCLGEVF_RING_RX_OFFSET_REG		0x80024
51 #define HCLGEVF_RING_RX_FBD_OFFSET_REG		0x80028
52 #define HCLGEVF_RING_RX_STASH_REG		0x80030
53 #define HCLGEVF_RING_RX_BD_ERR_REG		0x80034
54 #define HCLGEVF_RING_TX_ADDR_L_REG		0x80040
55 #define HCLGEVF_RING_TX_ADDR_H_REG		0x80044
56 #define HCLGEVF_RING_TX_BD_NUM_REG		0x80048
57 #define HCLGEVF_RING_TX_PRIORITY_REG		0x8004C
58 #define HCLGEVF_RING_TX_TC_REG			0x80050
59 #define HCLGEVF_RING_TX_MERGE_EN_REG		0x80054
60 #define HCLGEVF_RING_TX_TAIL_REG		0x80058
61 #define HCLGEVF_RING_TX_HEAD_REG		0x8005C
62 #define HCLGEVF_RING_TX_FBD_NUM_REG		0x80060
63 #define HCLGEVF_RING_TX_OFFSET_REG		0x80064
64 #define HCLGEVF_RING_TX_EBD_NUM_REG		0x80068
65 #define HCLGEVF_RING_TX_EBD_OFFSET_REG		0x80070
66 #define HCLGEVF_RING_TX_BD_ERR_REG		0x80074
67 #define HCLGEVF_RING_EN_REG			0x80090
68 
69 /* bar registers for tqp interrupt */
70 #define HCLGEVF_TQP_INTR_CTRL_REG		0x20000
71 #define HCLGEVF_TQP_INTR_GL0_REG		0x20100
72 #define HCLGEVF_TQP_INTR_GL1_REG		0x20200
73 #define HCLGEVF_TQP_INTR_GL2_REG		0x20300
74 #define HCLGEVF_TQP_INTR_RL_REG			0x20900
75 
76 /* CMDQ register bits for RX event(=MBX event) */
77 #define HCLGEVF_VECTOR0_RX_CMDQ_INT_B	1
78 /* RST register bits for RESET event */
79 #define HCLGEVF_VECTOR0_RST_INT_B	2
80 
81 #define HCLGEVF_TQP_RESET_TRY_TIMES	10
82 /* Reset related Registers */
83 #define HCLGEVF_RST_ING			0x20C00
84 #define HCLGEVF_FUN_RST_ING_BIT		BIT(0)
85 #define HCLGEVF_GLOBAL_RST_ING_BIT	BIT(5)
86 #define HCLGEVF_CORE_RST_ING_BIT	BIT(6)
87 #define HCLGEVF_IMP_RST_ING_BIT		BIT(7)
88 #define HCLGEVF_RST_ING_BITS \
89 	(HCLGEVF_FUN_RST_ING_BIT | HCLGEVF_GLOBAL_RST_ING_BIT | \
90 	 HCLGEVF_CORE_RST_ING_BIT | HCLGEVF_IMP_RST_ING_BIT)
91 
92 #define HCLGEVF_VF_RST_ING		0x07008
93 #define HCLGEVF_VF_RST_ING_BIT		BIT(16)
94 
95 #define HCLGEVF_WAIT_RESET_DONE		100
96 
97 #define HCLGEVF_RSS_IND_TBL_SIZE		512
98 
99 #define HCLGEVF_TQP_MEM_SIZE		0x10000
100 #define HCLGEVF_MEM_BAR			4
101 /* in the bar4, the first half is for roce, and the second half is for nic */
102 #define HCLGEVF_NIC_MEM_OFFSET(hdev)	\
103 	(pci_resource_len((hdev)->pdev, HCLGEVF_MEM_BAR) >> 1)
104 #define HCLGEVF_TQP_MEM_OFFSET(hdev, i)		\
105 	(HCLGEVF_NIC_MEM_OFFSET(hdev) + HCLGEVF_TQP_MEM_SIZE * (i))
106 
107 #define HCLGEVF_MAC_MAX_FRAME		9728
108 
109 #define HCLGEVF_STATS_TIMER_INTERVAL	36U
110 
111 #define hclgevf_read_dev(a, reg) \
112 	hclge_comm_read_reg((a)->hw.io_base, reg)
113 #define hclgevf_write_dev(a, reg, value) \
114 	hclge_comm_write_reg((a)->hw.io_base, reg, value)
115 
116 enum hclgevf_evt_cause {
117 	HCLGEVF_VECTOR0_EVENT_RST,
118 	HCLGEVF_VECTOR0_EVENT_MBX,
119 	HCLGEVF_VECTOR0_EVENT_OTHER,
120 };
121 
122 /* states of hclgevf device & tasks */
123 enum hclgevf_states {
124 	/* device states */
125 	HCLGEVF_STATE_DOWN,
126 	HCLGEVF_STATE_DISABLED,
127 	HCLGEVF_STATE_IRQ_INITED,
128 	HCLGEVF_STATE_REMOVING,
129 	HCLGEVF_STATE_NIC_REGISTERED,
130 	HCLGEVF_STATE_ROCE_REGISTERED,
131 	HCLGEVF_STATE_SERVICE_INITED,
132 	/* task states */
133 	HCLGEVF_STATE_RST_SERVICE_SCHED,
134 	HCLGEVF_STATE_RST_HANDLING,
135 	HCLGEVF_STATE_MBX_SERVICE_SCHED,
136 	HCLGEVF_STATE_MBX_HANDLING,
137 	HCLGEVF_STATE_LINK_UPDATING,
138 	HCLGEVF_STATE_PROMISC_CHANGED,
139 	HCLGEVF_STATE_RST_FAIL,
140 	HCLGEVF_STATE_PF_PUSH_LINK_STATUS,
141 };
142 
143 struct hclgevf_mac {
144 	u8 media_type;
145 	u8 module_type;
146 	u8 mac_addr[ETH_ALEN];
147 	int link;
148 	u8 duplex;
149 	u32 speed;
150 	u64 supported;
151 	u64 advertising;
152 };
153 
154 struct hclgevf_hw {
155 	struct hclge_comm_hw hw;
156 	int num_vec;
157 	struct hclgevf_mac mac;
158 };
159 
160 struct hclgevf_cfg {
161 	u8 tc_num;
162 	u16 tqp_desc_num;
163 	u16 rx_buf_len;
164 	u8 phy_addr;
165 	u8 media_type;
166 	u8 mac_addr[ETH_ALEN];
167 	u32 numa_node_map;
168 };
169 
170 struct hclgevf_misc_vector {
171 	u8 __iomem *addr;
172 	int vector_irq;
173 	char name[HNAE3_INT_NAME_LEN];
174 };
175 
176 struct hclgevf_rst_stats {
177 	u32 rst_cnt;			/* the number of reset */
178 	u32 vf_func_rst_cnt;		/* the number of VF function reset */
179 	u32 flr_rst_cnt;		/* the number of FLR */
180 	u32 vf_rst_cnt;			/* the number of VF reset */
181 	u32 rst_done_cnt;		/* the number of reset completed */
182 	u32 hw_rst_done_cnt;		/* the number of HW reset completed */
183 	u32 rst_fail_cnt;		/* the number of VF reset fail */
184 };
185 
186 enum HCLGEVF_MAC_ADDR_TYPE {
187 	HCLGEVF_MAC_ADDR_UC,
188 	HCLGEVF_MAC_ADDR_MC
189 };
190 
191 enum HCLGEVF_MAC_NODE_STATE {
192 	HCLGEVF_MAC_TO_ADD,
193 	HCLGEVF_MAC_TO_DEL,
194 	HCLGEVF_MAC_ACTIVE
195 };
196 
197 struct hclgevf_mac_addr_node {
198 	struct list_head node;
199 	enum HCLGEVF_MAC_NODE_STATE state;
200 	u8 mac_addr[ETH_ALEN];
201 };
202 
203 struct hclgevf_mac_table_cfg {
204 	spinlock_t mac_list_lock; /* protect mac address need to add/detele */
205 	struct list_head uc_mac_list;
206 	struct list_head mc_mac_list;
207 };
208 
209 struct hclgevf_dev {
210 	struct pci_dev *pdev;
211 	struct hnae3_ae_dev *ae_dev;
212 	struct hclgevf_hw hw;
213 	struct hclgevf_misc_vector misc_vector;
214 	struct hclge_comm_rss_cfg rss_cfg;
215 	unsigned long state;
216 	unsigned long flr_state;
217 	unsigned long default_reset_request;
218 	unsigned long last_reset_time;
219 	enum hnae3_reset_type reset_level;
220 	unsigned long reset_pending;
221 	enum hnae3_reset_type reset_type;
222 	struct timer_list reset_timer;
223 
224 #define HCLGEVF_RESET_REQUESTED		0
225 #define HCLGEVF_RESET_PENDING		1
226 	unsigned long reset_state;	/* requested, pending */
227 	struct hclgevf_rst_stats rst_stats;
228 	u32 reset_attempts;
229 	struct semaphore reset_sem;	/* protect reset process */
230 
231 	u32 fw_version;
232 	u16 mbx_api_version;
233 	u16 num_tqps;		/* num task queue pairs of this VF */
234 
235 	u16 alloc_rss_size;	/* allocated RSS task queue */
236 	u16 rss_size_max;	/* HW defined max RSS task queue */
237 
238 	u16 num_alloc_vport;	/* num vports this driver supports */
239 	u32 numa_node_mask;
240 	u16 rx_buf_len;
241 	u16 num_tx_desc;	/* desc num of per tx queue */
242 	u16 num_rx_desc;	/* desc num of per rx queue */
243 	u8 hw_tc_map;
244 	u8 has_pf_mac;
245 
246 	u16 num_msi;
247 	u16 num_msi_left;
248 	u16 num_msi_used;
249 	u16 num_nic_msix;	/* Num of nic vectors for this VF */
250 	u16 num_roce_msix;	/* Num of roce vectors for this VF */
251 	u16 roce_base_msix_offset;
252 	u16 *vector_status;
253 	int *vector_irq;
254 
255 	bool gro_en;
256 
257 	unsigned long vlan_del_fail_bmap[BITS_TO_LONGS(VLAN_N_VID)];
258 
259 	struct hclgevf_mac_table_cfg mac_table;
260 
261 	struct hclgevf_mbx_resp_status mbx_resp; /* mailbox response */
262 	struct hclgevf_mbx_arq_ring arq; /* mailbox async rx queue */
263 
264 	struct delayed_work service_task;
265 
266 	struct hclge_comm_tqp *htqp;
267 
268 	struct hnae3_handle nic;
269 	struct hnae3_handle roce;
270 
271 	struct hnae3_client *nic_client;
272 	struct hnae3_client *roce_client;
273 	u32 flag;
274 	unsigned long serv_processed_cnt;
275 	unsigned long last_serv_processed;
276 
277 	struct devlink *devlink;
278 };
279 
280 static inline bool hclgevf_is_reset_pending(struct hclgevf_dev *hdev)
281 {
282 	return !!hdev->reset_pending;
283 }
284 
285 int hclgevf_send_mbx_msg(struct hclgevf_dev *hdev,
286 			 struct hclge_vf_to_pf_msg *send_msg, bool need_resp,
287 			 u8 *resp_data, u16 resp_len);
288 void hclgevf_mbx_handler(struct hclgevf_dev *hdev);
289 void hclgevf_mbx_async_handler(struct hclgevf_dev *hdev);
290 
291 void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state);
292 void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed,
293 				 u8 duplex);
294 void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev);
295 void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev);
296 void hclgevf_update_port_base_vlan_info(struct hclgevf_dev *hdev, u16 state,
297 			struct hclge_mbx_port_base_vlan *port_base_vlan);
298 struct hclgevf_dev *hclgevf_ae_get_hdev(struct hnae3_handle *handle);
299 #endif
300