1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* Copyright (c) 2016-2017 Hisilicon Limited. */ 3 4 #ifndef __HCLGEVF_MAIN_H 5 #define __HCLGEVF_MAIN_H 6 #include <linux/fs.h> 7 #include <linux/types.h> 8 #include "hclge_mbx.h" 9 #include "hclgevf_cmd.h" 10 #include "hnae3.h" 11 12 #define HCLGEVF_MOD_VERSION "v1.0" 13 #define HCLGEVF_DRIVER_NAME "hclgevf" 14 15 #define HCLGEVF_ROCEE_VECTOR_NUM 0 16 #define HCLGEVF_MISC_VECTOR_NUM 0 17 18 #define HCLGEVF_INVALID_VPORT 0xffff 19 20 /* This number in actual depends upon the total number of VFs 21 * created by physical function. But the maximum number of 22 * possible vector-per-VF is {VFn(1-32), VECTn(32 + 1)}. 23 */ 24 #define HCLGEVF_MAX_VF_VECTOR_NUM (32 + 1) 25 26 #define HCLGEVF_VECTOR_REG_BASE 0x20000 27 #define HCLGEVF_MISC_VECTOR_REG_BASE 0x20400 28 #define HCLGEVF_VECTOR_REG_OFFSET 0x4 29 #define HCLGEVF_VECTOR_VF_OFFSET 0x100000 30 31 /* Vector0 interrupt CMDQ event source register(RW) */ 32 #define HCLGEVF_VECTOR0_CMDQ_SRC_REG 0x27100 33 /* CMDQ register bits for RX event(=MBX event) */ 34 #define HCLGEVF_VECTOR0_RX_CMDQ_INT_B 1 35 36 #define HCLGEVF_TQP_RESET_TRY_TIMES 10 37 38 #define HCLGEVF_RSS_IND_TBL_SIZE 512 39 #define HCLGEVF_RSS_SET_BITMAP_MSK 0xffff 40 #define HCLGEVF_RSS_KEY_SIZE 40 41 #define HCLGEVF_RSS_HASH_ALGO_TOEPLITZ 0 42 #define HCLGEVF_RSS_HASH_ALGO_SIMPLE 1 43 #define HCLGEVF_RSS_HASH_ALGO_SYMMETRIC 2 44 #define HCLGEVF_RSS_HASH_ALGO_MASK 0xf 45 #define HCLGEVF_RSS_CFG_TBL_NUM \ 46 (HCLGEVF_RSS_IND_TBL_SIZE / HCLGEVF_RSS_CFG_TBL_SIZE) 47 48 /* states of hclgevf device & tasks */ 49 enum hclgevf_states { 50 /* device states */ 51 HCLGEVF_STATE_DOWN, 52 HCLGEVF_STATE_DISABLED, 53 /* task states */ 54 HCLGEVF_STATE_SERVICE_SCHED, 55 HCLGEVF_STATE_MBX_SERVICE_SCHED, 56 HCLGEVF_STATE_MBX_HANDLING, 57 }; 58 59 #define HCLGEVF_MPF_ENBALE 1 60 61 struct hclgevf_mac { 62 u8 mac_addr[ETH_ALEN]; 63 int link; 64 }; 65 66 struct hclgevf_hw { 67 void __iomem *io_base; 68 int num_vec; 69 struct hclgevf_cmq cmq; 70 struct hclgevf_mac mac; 71 void *hdev; /* hchgevf device it is part of */ 72 }; 73 74 /* TQP stats */ 75 struct hlcgevf_tqp_stats { 76 /* query_tqp_tx_queue_statistics ,opcode id: 0x0B03 */ 77 u64 rcb_tx_ring_pktnum_rcd; /* 32bit */ 78 /* query_tqp_rx_queue_statistics ,opcode id: 0x0B13 */ 79 u64 rcb_rx_ring_pktnum_rcd; /* 32bit */ 80 }; 81 82 struct hclgevf_tqp { 83 struct device *dev; /* device for DMA mapping */ 84 struct hnae3_queue q; 85 struct hlcgevf_tqp_stats tqp_stats; 86 u16 index; /* global index in a NIC controller */ 87 88 bool alloced; 89 }; 90 91 struct hclgevf_cfg { 92 u8 vmdq_vport_num; 93 u8 tc_num; 94 u16 tqp_desc_num; 95 u16 rx_buf_len; 96 u8 phy_addr; 97 u8 media_type; 98 u8 mac_addr[ETH_ALEN]; 99 u32 numa_node_map; 100 }; 101 102 struct hclgevf_rss_cfg { 103 u8 rss_hash_key[HCLGEVF_RSS_KEY_SIZE]; /* user configured hash keys */ 104 u32 hash_algo; 105 u32 rss_size; 106 u8 hw_tc_map; 107 u8 rss_indirection_tbl[HCLGEVF_RSS_IND_TBL_SIZE]; /* shadow table */ 108 }; 109 110 struct hclgevf_misc_vector { 111 u8 __iomem *addr; 112 int vector_irq; 113 }; 114 115 struct hclgevf_dev { 116 struct pci_dev *pdev; 117 struct hnae3_ae_dev *ae_dev; 118 struct hclgevf_hw hw; 119 struct hclgevf_misc_vector misc_vector; 120 struct hclgevf_rss_cfg rss_cfg; 121 unsigned long state; 122 123 u32 fw_version; 124 u16 num_tqps; /* num task queue pairs of this PF */ 125 126 u16 alloc_rss_size; /* allocated RSS task queue */ 127 u16 rss_size_max; /* HW defined max RSS task queue */ 128 129 u16 num_alloc_vport; /* num vports this driver supports */ 130 u32 numa_node_mask; 131 u16 rx_buf_len; 132 u16 num_desc; 133 u8 hw_tc_map; 134 135 u16 num_msi; 136 u16 num_msi_left; 137 u16 num_msi_used; 138 u32 base_msi_vector; 139 u16 *vector_status; 140 int *vector_irq; 141 142 bool accept_mta_mc; /* whether to accept mta filter multicast */ 143 struct hclgevf_mbx_resp_status mbx_resp; /* mailbox response */ 144 145 struct timer_list service_timer; 146 struct work_struct service_task; 147 struct work_struct mbx_service_task; 148 149 struct hclgevf_tqp *htqp; 150 151 struct hnae3_handle nic; 152 struct hnae3_handle roce; 153 154 struct hnae3_client *nic_client; 155 struct hnae3_client *roce_client; 156 u32 flag; 157 }; 158 159 int hclgevf_send_mbx_msg(struct hclgevf_dev *hdev, u16 code, u16 subcode, 160 const u8 *msg_data, u8 msg_len, bool need_resp, 161 u8 *resp_data, u16 resp_len); 162 void hclgevf_mbx_handler(struct hclgevf_dev *hdev); 163 void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state); 164 #endif 165