1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* Copyright (c) 2016-2017 Hisilicon Limited. */ 3 4 #ifndef __HCLGEVF_MAIN_H 5 #define __HCLGEVF_MAIN_H 6 #include <linux/fs.h> 7 #include <linux/types.h> 8 #include "hclge_mbx.h" 9 #include "hclgevf_cmd.h" 10 #include "hnae3.h" 11 12 #define HCLGEVF_MOD_VERSION "1.0" 13 #define HCLGEVF_DRIVER_NAME "hclgevf" 14 15 #define HCLGEVF_MISC_VECTOR_NUM 0 16 17 #define HCLGEVF_INVALID_VPORT 0xffff 18 19 /* This number in actual depends upon the total number of VFs 20 * created by physical function. But the maximum number of 21 * possible vector-per-VF is {VFn(1-32), VECTn(32 + 1)}. 22 */ 23 #define HCLGEVF_MAX_VF_VECTOR_NUM (32 + 1) 24 25 #define HCLGEVF_VECTOR_REG_BASE 0x20000 26 #define HCLGEVF_MISC_VECTOR_REG_BASE 0x20400 27 #define HCLGEVF_VECTOR_REG_OFFSET 0x4 28 #define HCLGEVF_VECTOR_VF_OFFSET 0x100000 29 30 /* bar registers for cmdq */ 31 #define HCLGEVF_CMDQ_TX_ADDR_L_REG 0x27000 32 #define HCLGEVF_CMDQ_TX_ADDR_H_REG 0x27004 33 #define HCLGEVF_CMDQ_TX_DEPTH_REG 0x27008 34 #define HCLGEVF_CMDQ_TX_TAIL_REG 0x27010 35 #define HCLGEVF_CMDQ_TX_HEAD_REG 0x27014 36 #define HCLGEVF_CMDQ_RX_ADDR_L_REG 0x27018 37 #define HCLGEVF_CMDQ_RX_ADDR_H_REG 0x2701C 38 #define HCLGEVF_CMDQ_RX_DEPTH_REG 0x27020 39 #define HCLGEVF_CMDQ_RX_TAIL_REG 0x27024 40 #define HCLGEVF_CMDQ_RX_HEAD_REG 0x27028 41 #define HCLGEVF_CMDQ_INTR_SRC_REG 0x27100 42 #define HCLGEVF_CMDQ_INTR_STS_REG 0x27104 43 #define HCLGEVF_CMDQ_INTR_EN_REG 0x27108 44 #define HCLGEVF_CMDQ_INTR_GEN_REG 0x2710C 45 46 /* bar registers for common func */ 47 #define HCLGEVF_GRO_EN_REG 0x28000 48 49 /* bar registers for rcb */ 50 #define HCLGEVF_RING_RX_ADDR_L_REG 0x80000 51 #define HCLGEVF_RING_RX_ADDR_H_REG 0x80004 52 #define HCLGEVF_RING_RX_BD_NUM_REG 0x80008 53 #define HCLGEVF_RING_RX_BD_LENGTH_REG 0x8000C 54 #define HCLGEVF_RING_RX_MERGE_EN_REG 0x80014 55 #define HCLGEVF_RING_RX_TAIL_REG 0x80018 56 #define HCLGEVF_RING_RX_HEAD_REG 0x8001C 57 #define HCLGEVF_RING_RX_FBD_NUM_REG 0x80020 58 #define HCLGEVF_RING_RX_OFFSET_REG 0x80024 59 #define HCLGEVF_RING_RX_FBD_OFFSET_REG 0x80028 60 #define HCLGEVF_RING_RX_STASH_REG 0x80030 61 #define HCLGEVF_RING_RX_BD_ERR_REG 0x80034 62 #define HCLGEVF_RING_TX_ADDR_L_REG 0x80040 63 #define HCLGEVF_RING_TX_ADDR_H_REG 0x80044 64 #define HCLGEVF_RING_TX_BD_NUM_REG 0x80048 65 #define HCLGEVF_RING_TX_PRIORITY_REG 0x8004C 66 #define HCLGEVF_RING_TX_TC_REG 0x80050 67 #define HCLGEVF_RING_TX_MERGE_EN_REG 0x80054 68 #define HCLGEVF_RING_TX_TAIL_REG 0x80058 69 #define HCLGEVF_RING_TX_HEAD_REG 0x8005C 70 #define HCLGEVF_RING_TX_FBD_NUM_REG 0x80060 71 #define HCLGEVF_RING_TX_OFFSET_REG 0x80064 72 #define HCLGEVF_RING_TX_EBD_NUM_REG 0x80068 73 #define HCLGEVF_RING_TX_EBD_OFFSET_REG 0x80070 74 #define HCLGEVF_RING_TX_BD_ERR_REG 0x80074 75 #define HCLGEVF_RING_EN_REG 0x80090 76 77 /* bar registers for tqp interrupt */ 78 #define HCLGEVF_TQP_INTR_CTRL_REG 0x20000 79 #define HCLGEVF_TQP_INTR_GL0_REG 0x20100 80 #define HCLGEVF_TQP_INTR_GL1_REG 0x20200 81 #define HCLGEVF_TQP_INTR_GL2_REG 0x20300 82 #define HCLGEVF_TQP_INTR_RL_REG 0x20900 83 84 /* Vector0 interrupt CMDQ event source register(RW) */ 85 #define HCLGEVF_VECTOR0_CMDQ_SRC_REG 0x27100 86 /* CMDQ register bits for RX event(=MBX event) */ 87 #define HCLGEVF_VECTOR0_RX_CMDQ_INT_B 1 88 /* RST register bits for RESET event */ 89 #define HCLGEVF_VECTOR0_RST_INT_B 2 90 91 #define HCLGEVF_TQP_RESET_TRY_TIMES 10 92 /* Reset related Registers */ 93 #define HCLGEVF_RST_ING 0x20C00 94 #define HCLGEVF_FUN_RST_ING_BIT BIT(0) 95 #define HCLGEVF_GLOBAL_RST_ING_BIT BIT(5) 96 #define HCLGEVF_CORE_RST_ING_BIT BIT(6) 97 #define HCLGEVF_IMP_RST_ING_BIT BIT(7) 98 #define HCLGEVF_RST_ING_BITS \ 99 (HCLGEVF_FUN_RST_ING_BIT | HCLGEVF_GLOBAL_RST_ING_BIT | \ 100 HCLGEVF_CORE_RST_ING_BIT | HCLGEVF_IMP_RST_ING_BIT) 101 102 #define HCLGEVF_RSS_IND_TBL_SIZE 512 103 #define HCLGEVF_RSS_SET_BITMAP_MSK 0xffff 104 #define HCLGEVF_RSS_KEY_SIZE 40 105 #define HCLGEVF_RSS_HASH_ALGO_TOEPLITZ 0 106 #define HCLGEVF_RSS_HASH_ALGO_SIMPLE 1 107 #define HCLGEVF_RSS_HASH_ALGO_SYMMETRIC 2 108 #define HCLGEVF_RSS_HASH_ALGO_MASK 0xf 109 #define HCLGEVF_RSS_CFG_TBL_NUM \ 110 (HCLGEVF_RSS_IND_TBL_SIZE / HCLGEVF_RSS_CFG_TBL_SIZE) 111 #define HCLGEVF_RSS_INPUT_TUPLE_OTHER GENMASK(3, 0) 112 #define HCLGEVF_RSS_INPUT_TUPLE_SCTP GENMASK(4, 0) 113 #define HCLGEVF_D_PORT_BIT BIT(0) 114 #define HCLGEVF_S_PORT_BIT BIT(1) 115 #define HCLGEVF_D_IP_BIT BIT(2) 116 #define HCLGEVF_S_IP_BIT BIT(3) 117 #define HCLGEVF_V_TAG_BIT BIT(4) 118 119 #define HCLGEVF_STATS_TIMER_INTERVAL (36) 120 121 enum hclgevf_evt_cause { 122 HCLGEVF_VECTOR0_EVENT_RST, 123 HCLGEVF_VECTOR0_EVENT_MBX, 124 HCLGEVF_VECTOR0_EVENT_OTHER, 125 }; 126 127 /* states of hclgevf device & tasks */ 128 enum hclgevf_states { 129 /* device states */ 130 HCLGEVF_STATE_DOWN, 131 HCLGEVF_STATE_DISABLED, 132 HCLGEVF_STATE_IRQ_INITED, 133 /* task states */ 134 HCLGEVF_STATE_SERVICE_SCHED, 135 HCLGEVF_STATE_RST_SERVICE_SCHED, 136 HCLGEVF_STATE_RST_HANDLING, 137 HCLGEVF_STATE_MBX_SERVICE_SCHED, 138 HCLGEVF_STATE_MBX_HANDLING, 139 HCLGEVF_STATE_CMD_DISABLE, 140 }; 141 142 #define HCLGEVF_MPF_ENBALE 1 143 144 struct hclgevf_mac { 145 u8 media_type; 146 u8 module_type; 147 u8 mac_addr[ETH_ALEN]; 148 int link; 149 u8 duplex; 150 u32 speed; 151 u64 supported; 152 u64 advertising; 153 }; 154 155 struct hclgevf_hw { 156 void __iomem *io_base; 157 int num_vec; 158 struct hclgevf_cmq cmq; 159 struct hclgevf_mac mac; 160 void *hdev; /* hchgevf device it is part of */ 161 }; 162 163 /* TQP stats */ 164 struct hlcgevf_tqp_stats { 165 /* query_tqp_tx_queue_statistics ,opcode id: 0x0B03 */ 166 u64 rcb_tx_ring_pktnum_rcd; /* 32bit */ 167 /* query_tqp_rx_queue_statistics ,opcode id: 0x0B13 */ 168 u64 rcb_rx_ring_pktnum_rcd; /* 32bit */ 169 }; 170 171 struct hclgevf_tqp { 172 struct device *dev; /* device for DMA mapping */ 173 struct hnae3_queue q; 174 struct hlcgevf_tqp_stats tqp_stats; 175 u16 index; /* global index in a NIC controller */ 176 177 bool alloced; 178 }; 179 180 struct hclgevf_cfg { 181 u8 vmdq_vport_num; 182 u8 tc_num; 183 u16 tqp_desc_num; 184 u16 rx_buf_len; 185 u8 phy_addr; 186 u8 media_type; 187 u8 mac_addr[ETH_ALEN]; 188 u32 numa_node_map; 189 }; 190 191 struct hclgevf_rss_tuple_cfg { 192 u8 ipv4_tcp_en; 193 u8 ipv4_udp_en; 194 u8 ipv4_sctp_en; 195 u8 ipv4_fragment_en; 196 u8 ipv6_tcp_en; 197 u8 ipv6_udp_en; 198 u8 ipv6_sctp_en; 199 u8 ipv6_fragment_en; 200 }; 201 202 struct hclgevf_rss_cfg { 203 u8 rss_hash_key[HCLGEVF_RSS_KEY_SIZE]; /* user configured hash keys */ 204 u32 hash_algo; 205 u32 rss_size; 206 u8 hw_tc_map; 207 u8 rss_indirection_tbl[HCLGEVF_RSS_IND_TBL_SIZE]; /* shadow table */ 208 struct hclgevf_rss_tuple_cfg rss_tuple_sets; 209 }; 210 211 struct hclgevf_misc_vector { 212 u8 __iomem *addr; 213 int vector_irq; 214 }; 215 216 struct hclgevf_rst_stats { 217 u32 rst_cnt; /* the number of reset */ 218 u32 vf_func_rst_cnt; /* the number of VF function reset */ 219 u32 flr_rst_cnt; /* the number of FLR */ 220 u32 vf_rst_cnt; /* the number of VF reset */ 221 u32 rst_done_cnt; /* the number of reset completed */ 222 u32 hw_rst_done_cnt; /* the number of HW reset completed */ 223 }; 224 225 struct hclgevf_dev { 226 struct pci_dev *pdev; 227 struct hnae3_ae_dev *ae_dev; 228 struct hclgevf_hw hw; 229 struct hclgevf_misc_vector misc_vector; 230 struct hclgevf_rss_cfg rss_cfg; 231 unsigned long state; 232 unsigned long flr_state; 233 unsigned long default_reset_request; 234 unsigned long last_reset_time; 235 enum hnae3_reset_type reset_level; 236 unsigned long reset_pending; 237 enum hnae3_reset_type reset_type; 238 239 #define HCLGEVF_RESET_REQUESTED 0 240 #define HCLGEVF_RESET_PENDING 1 241 unsigned long reset_state; /* requested, pending */ 242 struct hclgevf_rst_stats rst_stats; 243 u32 reset_attempts; 244 245 u32 fw_version; 246 u16 num_tqps; /* num task queue pairs of this PF */ 247 248 u16 alloc_rss_size; /* allocated RSS task queue */ 249 u16 rss_size_max; /* HW defined max RSS task queue */ 250 251 u16 num_alloc_vport; /* num vports this driver supports */ 252 u32 numa_node_mask; 253 u16 rx_buf_len; 254 u16 num_tx_desc; /* desc num of per tx queue */ 255 u16 num_rx_desc; /* desc num of per rx queue */ 256 u8 hw_tc_map; 257 258 u16 num_msi; 259 u16 num_msi_left; 260 u16 num_msi_used; 261 u16 num_roce_msix; /* Num of roce vectors for this VF */ 262 u16 roce_base_msix_offset; 263 int roce_base_vector; 264 u32 base_msi_vector; 265 u16 *vector_status; 266 int *vector_irq; 267 268 bool mbx_event_pending; 269 struct hclgevf_mbx_resp_status mbx_resp; /* mailbox response */ 270 struct hclgevf_mbx_arq_ring arq; /* mailbox async rx queue */ 271 272 struct timer_list service_timer; 273 struct timer_list keep_alive_timer; 274 struct work_struct service_task; 275 struct work_struct keep_alive_task; 276 struct work_struct rst_service_task; 277 struct work_struct mbx_service_task; 278 279 struct hclgevf_tqp *htqp; 280 281 struct hnae3_handle nic; 282 struct hnae3_handle roce; 283 284 struct hnae3_client *nic_client; 285 struct hnae3_client *roce_client; 286 u32 flag; 287 u32 stats_timer; 288 }; 289 290 static inline bool hclgevf_is_reset_pending(struct hclgevf_dev *hdev) 291 { 292 return !!hdev->reset_pending; 293 } 294 295 int hclgevf_send_mbx_msg(struct hclgevf_dev *hdev, u16 code, u16 subcode, 296 const u8 *msg_data, u8 msg_len, bool need_resp, 297 u8 *resp_data, u16 resp_len); 298 void hclgevf_mbx_handler(struct hclgevf_dev *hdev); 299 void hclgevf_mbx_async_handler(struct hclgevf_dev *hdev); 300 301 void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state); 302 void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed, 303 u8 duplex); 304 void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev); 305 void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev); 306 void hclgevf_update_port_base_vlan_info(struct hclgevf_dev *hdev, u16 state, 307 u8 *port_base_vlan_info, u8 data_size); 308 #endif 309