1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /* Copyright (c) 2016-2017 Hisilicon Limited. */
3 
4 #ifndef __HCLGEVF_MAIN_H
5 #define __HCLGEVF_MAIN_H
6 #include <linux/fs.h>
7 #include <linux/if_vlan.h>
8 #include <linux/types.h>
9 #include "hclge_mbx.h"
10 #include "hclgevf_cmd.h"
11 #include "hnae3.h"
12 
13 #define HCLGEVF_MOD_VERSION "1.0"
14 #define HCLGEVF_DRIVER_NAME "hclgevf"
15 
16 #define HCLGEVF_MAX_VLAN_ID	4095
17 #define HCLGEVF_MISC_VECTOR_NUM		0
18 
19 #define HCLGEVF_INVALID_VPORT		0xffff
20 #define HCLGEVF_GENERAL_TASK_INTERVAL	  5
21 #define HCLGEVF_KEEP_ALIVE_TASK_INTERVAL  2
22 
23 /* This number in actual depends upon the total number of VFs
24  * created by physical function. But the maximum number of
25  * possible vector-per-VF is {VFn(1-32), VECTn(32 + 1)}.
26  */
27 #define HCLGEVF_MAX_VF_VECTOR_NUM	(32 + 1)
28 
29 #define HCLGEVF_VECTOR_REG_BASE		0x20000
30 #define HCLGEVF_MISC_VECTOR_REG_BASE	0x20400
31 #define HCLGEVF_VECTOR_REG_OFFSET	0x4
32 #define HCLGEVF_VECTOR_VF_OFFSET		0x100000
33 
34 /* bar registers for cmdq */
35 #define HCLGEVF_CMDQ_TX_ADDR_L_REG		0x27000
36 #define HCLGEVF_CMDQ_TX_ADDR_H_REG		0x27004
37 #define HCLGEVF_CMDQ_TX_DEPTH_REG		0x27008
38 #define HCLGEVF_CMDQ_TX_TAIL_REG		0x27010
39 #define HCLGEVF_CMDQ_TX_HEAD_REG		0x27014
40 #define HCLGEVF_CMDQ_RX_ADDR_L_REG		0x27018
41 #define HCLGEVF_CMDQ_RX_ADDR_H_REG		0x2701C
42 #define HCLGEVF_CMDQ_RX_DEPTH_REG		0x27020
43 #define HCLGEVF_CMDQ_RX_TAIL_REG		0x27024
44 #define HCLGEVF_CMDQ_RX_HEAD_REG		0x27028
45 #define HCLGEVF_CMDQ_INTR_EN_REG		0x27108
46 #define HCLGEVF_CMDQ_INTR_GEN_REG		0x2710C
47 
48 /* bar registers for common func */
49 #define HCLGEVF_GRO_EN_REG			0x28000
50 
51 /* bar registers for rcb */
52 #define HCLGEVF_RING_RX_ADDR_L_REG		0x80000
53 #define HCLGEVF_RING_RX_ADDR_H_REG		0x80004
54 #define HCLGEVF_RING_RX_BD_NUM_REG		0x80008
55 #define HCLGEVF_RING_RX_BD_LENGTH_REG		0x8000C
56 #define HCLGEVF_RING_RX_MERGE_EN_REG		0x80014
57 #define HCLGEVF_RING_RX_TAIL_REG		0x80018
58 #define HCLGEVF_RING_RX_HEAD_REG		0x8001C
59 #define HCLGEVF_RING_RX_FBD_NUM_REG		0x80020
60 #define HCLGEVF_RING_RX_OFFSET_REG		0x80024
61 #define HCLGEVF_RING_RX_FBD_OFFSET_REG		0x80028
62 #define HCLGEVF_RING_RX_STASH_REG		0x80030
63 #define HCLGEVF_RING_RX_BD_ERR_REG		0x80034
64 #define HCLGEVF_RING_TX_ADDR_L_REG		0x80040
65 #define HCLGEVF_RING_TX_ADDR_H_REG		0x80044
66 #define HCLGEVF_RING_TX_BD_NUM_REG		0x80048
67 #define HCLGEVF_RING_TX_PRIORITY_REG		0x8004C
68 #define HCLGEVF_RING_TX_TC_REG			0x80050
69 #define HCLGEVF_RING_TX_MERGE_EN_REG		0x80054
70 #define HCLGEVF_RING_TX_TAIL_REG		0x80058
71 #define HCLGEVF_RING_TX_HEAD_REG		0x8005C
72 #define HCLGEVF_RING_TX_FBD_NUM_REG		0x80060
73 #define HCLGEVF_RING_TX_OFFSET_REG		0x80064
74 #define HCLGEVF_RING_TX_EBD_NUM_REG		0x80068
75 #define HCLGEVF_RING_TX_EBD_OFFSET_REG		0x80070
76 #define HCLGEVF_RING_TX_BD_ERR_REG		0x80074
77 #define HCLGEVF_RING_EN_REG			0x80090
78 
79 /* bar registers for tqp interrupt */
80 #define HCLGEVF_TQP_INTR_CTRL_REG		0x20000
81 #define HCLGEVF_TQP_INTR_GL0_REG		0x20100
82 #define HCLGEVF_TQP_INTR_GL1_REG		0x20200
83 #define HCLGEVF_TQP_INTR_GL2_REG		0x20300
84 #define HCLGEVF_TQP_INTR_RL_REG			0x20900
85 
86 /* Vector0 interrupt CMDQ event source register(RW) */
87 #define HCLGEVF_VECTOR0_CMDQ_SRC_REG	0x27100
88 /* Vector0 interrupt CMDQ event status register(RO) */
89 #define HCLGEVF_VECTOR0_CMDQ_STATE_REG	0x27104
90 /* CMDQ register bits for RX event(=MBX event) */
91 #define HCLGEVF_VECTOR0_RX_CMDQ_INT_B	1
92 /* RST register bits for RESET event */
93 #define HCLGEVF_VECTOR0_RST_INT_B	2
94 
95 #define HCLGEVF_TQP_RESET_TRY_TIMES	10
96 /* Reset related Registers */
97 #define HCLGEVF_RST_ING			0x20C00
98 #define HCLGEVF_FUN_RST_ING_BIT		BIT(0)
99 #define HCLGEVF_GLOBAL_RST_ING_BIT	BIT(5)
100 #define HCLGEVF_CORE_RST_ING_BIT	BIT(6)
101 #define HCLGEVF_IMP_RST_ING_BIT		BIT(7)
102 #define HCLGEVF_RST_ING_BITS \
103 	(HCLGEVF_FUN_RST_ING_BIT | HCLGEVF_GLOBAL_RST_ING_BIT | \
104 	 HCLGEVF_CORE_RST_ING_BIT | HCLGEVF_IMP_RST_ING_BIT)
105 
106 #define HCLGEVF_VF_RST_ING		0x07008
107 #define HCLGEVF_VF_RST_ING_BIT		BIT(16)
108 
109 #define HCLGEVF_RSS_IND_TBL_SIZE		512
110 #define HCLGEVF_RSS_SET_BITMAP_MSK	0xffff
111 #define HCLGEVF_RSS_KEY_SIZE		40
112 #define HCLGEVF_RSS_HASH_ALGO_TOEPLITZ	0
113 #define HCLGEVF_RSS_HASH_ALGO_SIMPLE	1
114 #define HCLGEVF_RSS_HASH_ALGO_SYMMETRIC	2
115 #define HCLGEVF_RSS_HASH_ALGO_MASK	0xf
116 
117 #define HCLGEVF_RSS_INPUT_TUPLE_OTHER	GENMASK(3, 0)
118 #define HCLGEVF_RSS_INPUT_TUPLE_SCTP	GENMASK(4, 0)
119 #define HCLGEVF_D_PORT_BIT		BIT(0)
120 #define HCLGEVF_S_PORT_BIT		BIT(1)
121 #define HCLGEVF_D_IP_BIT		BIT(2)
122 #define HCLGEVF_S_IP_BIT		BIT(3)
123 #define HCLGEVF_V_TAG_BIT		BIT(4)
124 #define HCLGEVF_RSS_INPUT_TUPLE_SCTP_NO_PORT	\
125 	(HCLGEVF_D_IP_BIT | HCLGEVF_S_IP_BIT | HCLGEVF_V_TAG_BIT)
126 
127 #define HCLGEVF_MAC_MAX_FRAME		9728
128 
129 #define HCLGEVF_STATS_TIMER_INTERVAL	36U
130 
131 enum hclgevf_evt_cause {
132 	HCLGEVF_VECTOR0_EVENT_RST,
133 	HCLGEVF_VECTOR0_EVENT_MBX,
134 	HCLGEVF_VECTOR0_EVENT_OTHER,
135 };
136 
137 /* states of hclgevf device & tasks */
138 enum hclgevf_states {
139 	/* device states */
140 	HCLGEVF_STATE_DOWN,
141 	HCLGEVF_STATE_DISABLED,
142 	HCLGEVF_STATE_IRQ_INITED,
143 	HCLGEVF_STATE_REMOVING,
144 	HCLGEVF_STATE_NIC_REGISTERED,
145 	HCLGEVF_STATE_ROCE_REGISTERED,
146 	/* task states */
147 	HCLGEVF_STATE_RST_SERVICE_SCHED,
148 	HCLGEVF_STATE_RST_HANDLING,
149 	HCLGEVF_STATE_MBX_SERVICE_SCHED,
150 	HCLGEVF_STATE_MBX_HANDLING,
151 	HCLGEVF_STATE_CMD_DISABLE,
152 	HCLGEVF_STATE_LINK_UPDATING,
153 	HCLGEVF_STATE_PROMISC_CHANGED,
154 	HCLGEVF_STATE_RST_FAIL,
155 	HCLGEVF_STATE_PF_PUSH_LINK_STATUS,
156 };
157 
158 struct hclgevf_mac {
159 	u8 media_type;
160 	u8 module_type;
161 	u8 mac_addr[ETH_ALEN];
162 	int link;
163 	u8 duplex;
164 	u32 speed;
165 	u64 supported;
166 	u64 advertising;
167 };
168 
169 struct hclgevf_hw {
170 	void __iomem *io_base;
171 	void __iomem *mem_base;
172 	int num_vec;
173 	struct hclgevf_cmq cmq;
174 	struct hclgevf_mac mac;
175 	void *hdev; /* hchgevf device it is part of */
176 };
177 
178 /* TQP stats */
179 struct hlcgevf_tqp_stats {
180 	/* query_tqp_tx_queue_statistics, opcode id: 0x0B03 */
181 	u64 rcb_tx_ring_pktnum_rcd; /* 32bit */
182 	/* query_tqp_rx_queue_statistics, opcode id: 0x0B13 */
183 	u64 rcb_rx_ring_pktnum_rcd; /* 32bit */
184 };
185 
186 struct hclgevf_tqp {
187 	struct device *dev;	/* device for DMA mapping */
188 	struct hnae3_queue q;
189 	struct hlcgevf_tqp_stats tqp_stats;
190 	u16 index;		/* global index in a NIC controller */
191 
192 	bool alloced;
193 };
194 
195 struct hclgevf_cfg {
196 	u8 tc_num;
197 	u16 tqp_desc_num;
198 	u16 rx_buf_len;
199 	u8 phy_addr;
200 	u8 media_type;
201 	u8 mac_addr[ETH_ALEN];
202 	u32 numa_node_map;
203 };
204 
205 struct hclgevf_rss_tuple_cfg {
206 	u8 ipv4_tcp_en;
207 	u8 ipv4_udp_en;
208 	u8 ipv4_sctp_en;
209 	u8 ipv4_fragment_en;
210 	u8 ipv6_tcp_en;
211 	u8 ipv6_udp_en;
212 	u8 ipv6_sctp_en;
213 	u8 ipv6_fragment_en;
214 };
215 
216 struct hclgevf_rss_cfg {
217 	u8  rss_hash_key[HCLGEVF_RSS_KEY_SIZE]; /* user configured hash keys */
218 	u32 hash_algo;
219 	u32 rss_size;
220 	u8 hw_tc_map;
221 	/* shadow table */
222 	u8 *rss_indirection_tbl;
223 	struct hclgevf_rss_tuple_cfg rss_tuple_sets;
224 };
225 
226 struct hclgevf_misc_vector {
227 	u8 __iomem *addr;
228 	int vector_irq;
229 	char name[HNAE3_INT_NAME_LEN];
230 };
231 
232 struct hclgevf_rst_stats {
233 	u32 rst_cnt;			/* the number of reset */
234 	u32 vf_func_rst_cnt;		/* the number of VF function reset */
235 	u32 flr_rst_cnt;		/* the number of FLR */
236 	u32 vf_rst_cnt;			/* the number of VF reset */
237 	u32 rst_done_cnt;		/* the number of reset completed */
238 	u32 hw_rst_done_cnt;		/* the number of HW reset completed */
239 	u32 rst_fail_cnt;		/* the number of VF reset fail */
240 };
241 
242 enum HCLGEVF_MAC_ADDR_TYPE {
243 	HCLGEVF_MAC_ADDR_UC,
244 	HCLGEVF_MAC_ADDR_MC
245 };
246 
247 enum HCLGEVF_MAC_NODE_STATE {
248 	HCLGEVF_MAC_TO_ADD,
249 	HCLGEVF_MAC_TO_DEL,
250 	HCLGEVF_MAC_ACTIVE
251 };
252 
253 struct hclgevf_mac_addr_node {
254 	struct list_head node;
255 	enum HCLGEVF_MAC_NODE_STATE state;
256 	u8 mac_addr[ETH_ALEN];
257 };
258 
259 struct hclgevf_mac_table_cfg {
260 	spinlock_t mac_list_lock; /* protect mac address need to add/detele */
261 	struct list_head uc_mac_list;
262 	struct list_head mc_mac_list;
263 };
264 
265 struct hclgevf_dev {
266 	struct pci_dev *pdev;
267 	struct hnae3_ae_dev *ae_dev;
268 	struct hclgevf_hw hw;
269 	struct hclgevf_misc_vector misc_vector;
270 	struct hclgevf_rss_cfg rss_cfg;
271 	unsigned long state;
272 	unsigned long flr_state;
273 	unsigned long default_reset_request;
274 	unsigned long last_reset_time;
275 	enum hnae3_reset_type reset_level;
276 	unsigned long reset_pending;
277 	enum hnae3_reset_type reset_type;
278 
279 #define HCLGEVF_RESET_REQUESTED		0
280 #define HCLGEVF_RESET_PENDING		1
281 	unsigned long reset_state;	/* requested, pending */
282 	struct hclgevf_rst_stats rst_stats;
283 	u32 reset_attempts;
284 	struct semaphore reset_sem;	/* protect reset process */
285 
286 	u32 fw_version;
287 	u16 num_tqps;		/* num task queue pairs of this VF */
288 
289 	u16 alloc_rss_size;	/* allocated RSS task queue */
290 	u16 rss_size_max;	/* HW defined max RSS task queue */
291 
292 	u16 num_alloc_vport;	/* num vports this driver supports */
293 	u32 numa_node_mask;
294 	u16 rx_buf_len;
295 	u16 num_tx_desc;	/* desc num of per tx queue */
296 	u16 num_rx_desc;	/* desc num of per rx queue */
297 	u8 hw_tc_map;
298 	u8 has_pf_mac;
299 
300 	u16 num_msi;
301 	u16 num_msi_left;
302 	u16 num_msi_used;
303 	u16 num_nic_msix;	/* Num of nic vectors for this VF */
304 	u16 num_roce_msix;	/* Num of roce vectors for this VF */
305 	u16 roce_base_msix_offset;
306 	int roce_base_vector;
307 	u32 base_msi_vector;
308 	u16 *vector_status;
309 	int *vector_irq;
310 
311 	unsigned long vlan_del_fail_bmap[BITS_TO_LONGS(VLAN_N_VID)];
312 
313 	struct hclgevf_mac_table_cfg mac_table;
314 
315 	bool mbx_event_pending;
316 	struct hclgevf_mbx_resp_status mbx_resp; /* mailbox response */
317 	struct hclgevf_mbx_arq_ring arq; /* mailbox async rx queue */
318 
319 	struct delayed_work service_task;
320 
321 	struct hclgevf_tqp *htqp;
322 
323 	struct hnae3_handle nic;
324 	struct hnae3_handle roce;
325 
326 	struct hnae3_client *nic_client;
327 	struct hnae3_client *roce_client;
328 	u32 flag;
329 	unsigned long serv_processed_cnt;
330 	unsigned long last_serv_processed;
331 };
332 
333 static inline bool hclgevf_is_reset_pending(struct hclgevf_dev *hdev)
334 {
335 	return !!hdev->reset_pending;
336 }
337 
338 int hclgevf_send_mbx_msg(struct hclgevf_dev *hdev,
339 			 struct hclge_vf_to_pf_msg *send_msg, bool need_resp,
340 			 u8 *resp_data, u16 resp_len);
341 void hclgevf_mbx_handler(struct hclgevf_dev *hdev);
342 void hclgevf_mbx_async_handler(struct hclgevf_dev *hdev);
343 
344 void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state);
345 void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed,
346 				 u8 duplex);
347 void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev);
348 void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev);
349 void hclgevf_update_port_base_vlan_info(struct hclgevf_dev *hdev, u16 state,
350 					u8 *port_base_vlan_info, u8 data_size);
351 #endif
352