1e2cb1decSSalil Mehta /* SPDX-License-Identifier: GPL-2.0+ */ 2e2cb1decSSalil Mehta /* Copyright (c) 2016-2017 Hisilicon Limited. */ 3e2cb1decSSalil Mehta 4e2cb1decSSalil Mehta #ifndef __HCLGEVF_MAIN_H 5e2cb1decSSalil Mehta #define __HCLGEVF_MAIN_H 6e2cb1decSSalil Mehta #include <linux/fs.h> 7e2cb1decSSalil Mehta #include <linux/types.h> 8e2cb1decSSalil Mehta #include "hclge_mbx.h" 9e2cb1decSSalil Mehta #include "hclgevf_cmd.h" 10e2cb1decSSalil Mehta #include "hnae3.h" 11e2cb1decSSalil Mehta 123c7624d8SXi Wang #define HCLGEVF_MOD_VERSION "1.0" 13e2cb1decSSalil Mehta #define HCLGEVF_DRIVER_NAME "hclgevf" 14e2cb1decSSalil Mehta 15e2cb1decSSalil Mehta #define HCLGEVF_MISC_VECTOR_NUM 0 16e2cb1decSSalil Mehta 17e2cb1decSSalil Mehta #define HCLGEVF_INVALID_VPORT 0xffff 18e2cb1decSSalil Mehta 19e2cb1decSSalil Mehta /* This number in actual depends upon the total number of VFs 20e2cb1decSSalil Mehta * created by physical function. But the maximum number of 21e2cb1decSSalil Mehta * possible vector-per-VF is {VFn(1-32), VECTn(32 + 1)}. 22e2cb1decSSalil Mehta */ 23e2cb1decSSalil Mehta #define HCLGEVF_MAX_VF_VECTOR_NUM (32 + 1) 24e2cb1decSSalil Mehta 25e2cb1decSSalil Mehta #define HCLGEVF_VECTOR_REG_BASE 0x20000 26e2cb1decSSalil Mehta #define HCLGEVF_MISC_VECTOR_REG_BASE 0x20400 27e2cb1decSSalil Mehta #define HCLGEVF_VECTOR_REG_OFFSET 0x4 28e2cb1decSSalil Mehta #define HCLGEVF_VECTOR_VF_OFFSET 0x100000 29e2cb1decSSalil Mehta 30e2cb1decSSalil Mehta /* Vector0 interrupt CMDQ event source register(RW) */ 31e2cb1decSSalil Mehta #define HCLGEVF_VECTOR0_CMDQ_SRC_REG 0x27100 32e2cb1decSSalil Mehta /* CMDQ register bits for RX event(=MBX event) */ 33e2cb1decSSalil Mehta #define HCLGEVF_VECTOR0_RX_CMDQ_INT_B 1 34e2cb1decSSalil Mehta 35e2cb1decSSalil Mehta #define HCLGEVF_TQP_RESET_TRY_TIMES 10 366988eb2aSSalil Mehta /* Reset related Registers */ 376988eb2aSSalil Mehta #define HCLGEVF_FUN_RST_ING 0x20C00 386988eb2aSSalil Mehta #define HCLGEVF_FUN_RST_ING_B 0 39e2cb1decSSalil Mehta 40e2cb1decSSalil Mehta #define HCLGEVF_RSS_IND_TBL_SIZE 512 41e2cb1decSSalil Mehta #define HCLGEVF_RSS_SET_BITMAP_MSK 0xffff 42e2cb1decSSalil Mehta #define HCLGEVF_RSS_KEY_SIZE 40 43e2cb1decSSalil Mehta #define HCLGEVF_RSS_HASH_ALGO_TOEPLITZ 0 44e2cb1decSSalil Mehta #define HCLGEVF_RSS_HASH_ALGO_SIMPLE 1 45e2cb1decSSalil Mehta #define HCLGEVF_RSS_HASH_ALGO_SYMMETRIC 2 46e2cb1decSSalil Mehta #define HCLGEVF_RSS_HASH_ALGO_MASK 0xf 47e2cb1decSSalil Mehta #define HCLGEVF_RSS_CFG_TBL_NUM \ 48e2cb1decSSalil Mehta (HCLGEVF_RSS_IND_TBL_SIZE / HCLGEVF_RSS_CFG_TBL_SIZE) 49d97b3072SJian Shen #define HCLGEVF_RSS_INPUT_TUPLE_OTHER GENMASK(3, 0) 50d97b3072SJian Shen #define HCLGEVF_RSS_INPUT_TUPLE_SCTP GENMASK(4, 0) 51d97b3072SJian Shen #define HCLGEVF_D_PORT_BIT BIT(0) 52d97b3072SJian Shen #define HCLGEVF_S_PORT_BIT BIT(1) 53d97b3072SJian Shen #define HCLGEVF_D_IP_BIT BIT(2) 54d97b3072SJian Shen #define HCLGEVF_S_IP_BIT BIT(3) 55d97b3072SJian Shen #define HCLGEVF_V_TAG_BIT BIT(4) 56e2cb1decSSalil Mehta 57e2cb1decSSalil Mehta /* states of hclgevf device & tasks */ 58e2cb1decSSalil Mehta enum hclgevf_states { 59e2cb1decSSalil Mehta /* device states */ 60e2cb1decSSalil Mehta HCLGEVF_STATE_DOWN, 61e2cb1decSSalil Mehta HCLGEVF_STATE_DISABLED, 62e2cb1decSSalil Mehta /* task states */ 63e2cb1decSSalil Mehta HCLGEVF_STATE_SERVICE_SCHED, 6435a1e503SSalil Mehta HCLGEVF_STATE_RST_SERVICE_SCHED, 6535a1e503SSalil Mehta HCLGEVF_STATE_RST_HANDLING, 66e2cb1decSSalil Mehta HCLGEVF_STATE_MBX_SERVICE_SCHED, 67e2cb1decSSalil Mehta HCLGEVF_STATE_MBX_HANDLING, 68e2cb1decSSalil Mehta }; 69e2cb1decSSalil Mehta 70e2cb1decSSalil Mehta #define HCLGEVF_MPF_ENBALE 1 71e2cb1decSSalil Mehta 72e2cb1decSSalil Mehta struct hclgevf_mac { 73c136b884SPeng Li u8 media_type; 74e2cb1decSSalil Mehta u8 mac_addr[ETH_ALEN]; 75e2cb1decSSalil Mehta int link; 764a152de9SFuyun Liang u8 duplex; 774a152de9SFuyun Liang u32 speed; 78e2cb1decSSalil Mehta }; 79e2cb1decSSalil Mehta 80e2cb1decSSalil Mehta struct hclgevf_hw { 81e2cb1decSSalil Mehta void __iomem *io_base; 82e2cb1decSSalil Mehta int num_vec; 83e2cb1decSSalil Mehta struct hclgevf_cmq cmq; 84e2cb1decSSalil Mehta struct hclgevf_mac mac; 85e2cb1decSSalil Mehta void *hdev; /* hchgevf device it is part of */ 86e2cb1decSSalil Mehta }; 87e2cb1decSSalil Mehta 88e2cb1decSSalil Mehta /* TQP stats */ 89e2cb1decSSalil Mehta struct hlcgevf_tqp_stats { 90e2cb1decSSalil Mehta /* query_tqp_tx_queue_statistics ,opcode id: 0x0B03 */ 91e2cb1decSSalil Mehta u64 rcb_tx_ring_pktnum_rcd; /* 32bit */ 92e2cb1decSSalil Mehta /* query_tqp_rx_queue_statistics ,opcode id: 0x0B13 */ 93e2cb1decSSalil Mehta u64 rcb_rx_ring_pktnum_rcd; /* 32bit */ 94e2cb1decSSalil Mehta }; 95e2cb1decSSalil Mehta 96e2cb1decSSalil Mehta struct hclgevf_tqp { 97e2cb1decSSalil Mehta struct device *dev; /* device for DMA mapping */ 98e2cb1decSSalil Mehta struct hnae3_queue q; 99e2cb1decSSalil Mehta struct hlcgevf_tqp_stats tqp_stats; 100e2cb1decSSalil Mehta u16 index; /* global index in a NIC controller */ 101e2cb1decSSalil Mehta 102e2cb1decSSalil Mehta bool alloced; 103e2cb1decSSalil Mehta }; 104e2cb1decSSalil Mehta 105e2cb1decSSalil Mehta struct hclgevf_cfg { 106e2cb1decSSalil Mehta u8 vmdq_vport_num; 107e2cb1decSSalil Mehta u8 tc_num; 108e2cb1decSSalil Mehta u16 tqp_desc_num; 109e2cb1decSSalil Mehta u16 rx_buf_len; 110e2cb1decSSalil Mehta u8 phy_addr; 111e2cb1decSSalil Mehta u8 media_type; 112e2cb1decSSalil Mehta u8 mac_addr[ETH_ALEN]; 113e2cb1decSSalil Mehta u32 numa_node_map; 114e2cb1decSSalil Mehta }; 115e2cb1decSSalil Mehta 116d97b3072SJian Shen struct hclgevf_rss_tuple_cfg { 117d97b3072SJian Shen u8 ipv4_tcp_en; 118d97b3072SJian Shen u8 ipv4_udp_en; 119d97b3072SJian Shen u8 ipv4_sctp_en; 120d97b3072SJian Shen u8 ipv4_fragment_en; 121d97b3072SJian Shen u8 ipv6_tcp_en; 122d97b3072SJian Shen u8 ipv6_udp_en; 123d97b3072SJian Shen u8 ipv6_sctp_en; 124d97b3072SJian Shen u8 ipv6_fragment_en; 125d97b3072SJian Shen }; 126d97b3072SJian Shen 127e2cb1decSSalil Mehta struct hclgevf_rss_cfg { 128e2cb1decSSalil Mehta u8 rss_hash_key[HCLGEVF_RSS_KEY_SIZE]; /* user configured hash keys */ 129e2cb1decSSalil Mehta u32 hash_algo; 130e2cb1decSSalil Mehta u32 rss_size; 131e2cb1decSSalil Mehta u8 hw_tc_map; 132e2cb1decSSalil Mehta u8 rss_indirection_tbl[HCLGEVF_RSS_IND_TBL_SIZE]; /* shadow table */ 133d97b3072SJian Shen struct hclgevf_rss_tuple_cfg rss_tuple_sets; 134e2cb1decSSalil Mehta }; 135e2cb1decSSalil Mehta 136e2cb1decSSalil Mehta struct hclgevf_misc_vector { 137e2cb1decSSalil Mehta u8 __iomem *addr; 138e2cb1decSSalil Mehta int vector_irq; 139e2cb1decSSalil Mehta }; 140e2cb1decSSalil Mehta 141e2cb1decSSalil Mehta struct hclgevf_dev { 142e2cb1decSSalil Mehta struct pci_dev *pdev; 143e2cb1decSSalil Mehta struct hnae3_ae_dev *ae_dev; 144e2cb1decSSalil Mehta struct hclgevf_hw hw; 145e2cb1decSSalil Mehta struct hclgevf_misc_vector misc_vector; 146e2cb1decSSalil Mehta struct hclgevf_rss_cfg rss_cfg; 147e2cb1decSSalil Mehta unsigned long state; 148e2cb1decSSalil Mehta 149436667d2SSalil Mehta #define HCLGEVF_RESET_REQUESTED 0 150436667d2SSalil Mehta #define HCLGEVF_RESET_PENDING 1 151436667d2SSalil Mehta unsigned long reset_state; /* requested, pending */ 152436667d2SSalil Mehta u32 reset_attempts; 153436667d2SSalil Mehta 154e2cb1decSSalil Mehta u32 fw_version; 155e2cb1decSSalil Mehta u16 num_tqps; /* num task queue pairs of this PF */ 156e2cb1decSSalil Mehta 157e2cb1decSSalil Mehta u16 alloc_rss_size; /* allocated RSS task queue */ 158e2cb1decSSalil Mehta u16 rss_size_max; /* HW defined max RSS task queue */ 159e2cb1decSSalil Mehta 160e2cb1decSSalil Mehta u16 num_alloc_vport; /* num vports this driver supports */ 161e2cb1decSSalil Mehta u32 numa_node_mask; 162e2cb1decSSalil Mehta u16 rx_buf_len; 163e2cb1decSSalil Mehta u16 num_desc; 164e2cb1decSSalil Mehta u8 hw_tc_map; 165e2cb1decSSalil Mehta 166e2cb1decSSalil Mehta u16 num_msi; 167e2cb1decSSalil Mehta u16 num_msi_left; 168e2cb1decSSalil Mehta u16 num_msi_used; 16907acf909SJian Shen u16 num_roce_msix; /* Num of roce vectors for this VF */ 17007acf909SJian Shen u16 roce_base_msix_offset; 17107acf909SJian Shen int roce_base_vector; 172e2cb1decSSalil Mehta u32 base_msi_vector; 173e2cb1decSSalil Mehta u16 *vector_status; 174e2cb1decSSalil Mehta int *vector_irq; 175e2cb1decSSalil Mehta 17607a0556aSSalil Mehta bool mbx_event_pending; 177e2cb1decSSalil Mehta struct hclgevf_mbx_resp_status mbx_resp; /* mailbox response */ 17807a0556aSSalil Mehta struct hclgevf_mbx_arq_ring arq; /* mailbox async rx queue */ 179e2cb1decSSalil Mehta 180e2cb1decSSalil Mehta struct timer_list service_timer; 181e2cb1decSSalil Mehta struct work_struct service_task; 18235a1e503SSalil Mehta struct work_struct rst_service_task; 183e2cb1decSSalil Mehta struct work_struct mbx_service_task; 184e2cb1decSSalil Mehta 185e2cb1decSSalil Mehta struct hclgevf_tqp *htqp; 186e2cb1decSSalil Mehta 187e2cb1decSSalil Mehta struct hnae3_handle nic; 188e2cb1decSSalil Mehta struct hnae3_handle roce; 189e2cb1decSSalil Mehta 190e2cb1decSSalil Mehta struct hnae3_client *nic_client; 191e2cb1decSSalil Mehta struct hnae3_client *roce_client; 192e2cb1decSSalil Mehta u32 flag; 193e2cb1decSSalil Mehta }; 194e2cb1decSSalil Mehta 1957a01c897SSalil Mehta static inline bool hclgevf_dev_ongoing_reset(struct hclgevf_dev *hdev) 1967a01c897SSalil Mehta { 1977a01c897SSalil Mehta return (hdev && 1987a01c897SSalil Mehta (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) && 1997a01c897SSalil Mehta (hdev->nic.reset_level == HNAE3_VF_RESET)); 2007a01c897SSalil Mehta } 2017a01c897SSalil Mehta 2027a01c897SSalil Mehta static inline bool hclgevf_dev_ongoing_full_reset(struct hclgevf_dev *hdev) 2037a01c897SSalil Mehta { 2047a01c897SSalil Mehta return (hdev && 2057a01c897SSalil Mehta (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) && 2067a01c897SSalil Mehta (hdev->nic.reset_level == HNAE3_VF_FULL_RESET)); 2077a01c897SSalil Mehta } 2087a01c897SSalil Mehta 209e2cb1decSSalil Mehta int hclgevf_send_mbx_msg(struct hclgevf_dev *hdev, u16 code, u16 subcode, 210e2cb1decSSalil Mehta const u8 *msg_data, u8 msg_len, bool need_resp, 211e2cb1decSSalil Mehta u8 *resp_data, u16 resp_len); 212e2cb1decSSalil Mehta void hclgevf_mbx_handler(struct hclgevf_dev *hdev); 21307a0556aSSalil Mehta void hclgevf_mbx_async_handler(struct hclgevf_dev *hdev); 21407a0556aSSalil Mehta 215e2cb1decSSalil Mehta void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state); 2164a152de9SFuyun Liang void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed, 2174a152de9SFuyun Liang u8 duplex); 21835a1e503SSalil Mehta void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev); 21907a0556aSSalil Mehta void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev); 220e2cb1decSSalil Mehta #endif 221