1e2cb1decSSalil Mehta /* SPDX-License-Identifier: GPL-2.0+ */ 2e2cb1decSSalil Mehta /* Copyright (c) 2016-2017 Hisilicon Limited. */ 3e2cb1decSSalil Mehta 4e2cb1decSSalil Mehta #ifndef __HCLGEVF_MAIN_H 5e2cb1decSSalil Mehta #define __HCLGEVF_MAIN_H 6e2cb1decSSalil Mehta #include <linux/fs.h> 7fe4144d4SJian Shen #include <linux/if_vlan.h> 8e2cb1decSSalil Mehta #include <linux/types.h> 9e2cb1decSSalil Mehta #include "hclge_mbx.h" 10e2cb1decSSalil Mehta #include "hclgevf_cmd.h" 11e2cb1decSSalil Mehta #include "hnae3.h" 12e2cb1decSSalil Mehta 133c7624d8SXi Wang #define HCLGEVF_MOD_VERSION "1.0" 14e2cb1decSSalil Mehta #define HCLGEVF_DRIVER_NAME "hclgevf" 15e2cb1decSSalil Mehta 16b37ce587SYufeng Mo #define HCLGEVF_MAX_VLAN_ID 4095 17e2cb1decSSalil Mehta #define HCLGEVF_MISC_VECTOR_NUM 0 18e2cb1decSSalil Mehta 19e2cb1decSSalil Mehta #define HCLGEVF_INVALID_VPORT 0xffff 20b37ce587SYufeng Mo #define HCLGEVF_GENERAL_TASK_INTERVAL 5 21b37ce587SYufeng Mo #define HCLGEVF_KEEP_ALIVE_TASK_INTERVAL 2 22e2cb1decSSalil Mehta 23e2cb1decSSalil Mehta /* This number in actual depends upon the total number of VFs 24e2cb1decSSalil Mehta * created by physical function. But the maximum number of 25e2cb1decSSalil Mehta * possible vector-per-VF is {VFn(1-32), VECTn(32 + 1)}. 26e2cb1decSSalil Mehta */ 27e2cb1decSSalil Mehta #define HCLGEVF_MAX_VF_VECTOR_NUM (32 + 1) 28e2cb1decSSalil Mehta 29e2cb1decSSalil Mehta #define HCLGEVF_VECTOR_REG_BASE 0x20000 30e2cb1decSSalil Mehta #define HCLGEVF_MISC_VECTOR_REG_BASE 0x20400 31e2cb1decSSalil Mehta #define HCLGEVF_VECTOR_REG_OFFSET 0x4 32e2cb1decSSalil Mehta #define HCLGEVF_VECTOR_VF_OFFSET 0x100000 33e2cb1decSSalil Mehta 341600c3e5SJian Shen /* bar registers for cmdq */ 351600c3e5SJian Shen #define HCLGEVF_CMDQ_TX_ADDR_L_REG 0x27000 361600c3e5SJian Shen #define HCLGEVF_CMDQ_TX_ADDR_H_REG 0x27004 371600c3e5SJian Shen #define HCLGEVF_CMDQ_TX_DEPTH_REG 0x27008 381600c3e5SJian Shen #define HCLGEVF_CMDQ_TX_TAIL_REG 0x27010 391600c3e5SJian Shen #define HCLGEVF_CMDQ_TX_HEAD_REG 0x27014 401600c3e5SJian Shen #define HCLGEVF_CMDQ_RX_ADDR_L_REG 0x27018 411600c3e5SJian Shen #define HCLGEVF_CMDQ_RX_ADDR_H_REG 0x2701C 421600c3e5SJian Shen #define HCLGEVF_CMDQ_RX_DEPTH_REG 0x27020 431600c3e5SJian Shen #define HCLGEVF_CMDQ_RX_TAIL_REG 0x27024 441600c3e5SJian Shen #define HCLGEVF_CMDQ_RX_HEAD_REG 0x27028 451600c3e5SJian Shen #define HCLGEVF_CMDQ_INTR_EN_REG 0x27108 461600c3e5SJian Shen #define HCLGEVF_CMDQ_INTR_GEN_REG 0x2710C 471600c3e5SJian Shen 481600c3e5SJian Shen /* bar registers for common func */ 491600c3e5SJian Shen #define HCLGEVF_GRO_EN_REG 0x28000 501600c3e5SJian Shen 511600c3e5SJian Shen /* bar registers for rcb */ 521600c3e5SJian Shen #define HCLGEVF_RING_RX_ADDR_L_REG 0x80000 531600c3e5SJian Shen #define HCLGEVF_RING_RX_ADDR_H_REG 0x80004 541600c3e5SJian Shen #define HCLGEVF_RING_RX_BD_NUM_REG 0x80008 551600c3e5SJian Shen #define HCLGEVF_RING_RX_BD_LENGTH_REG 0x8000C 561600c3e5SJian Shen #define HCLGEVF_RING_RX_MERGE_EN_REG 0x80014 571600c3e5SJian Shen #define HCLGEVF_RING_RX_TAIL_REG 0x80018 581600c3e5SJian Shen #define HCLGEVF_RING_RX_HEAD_REG 0x8001C 591600c3e5SJian Shen #define HCLGEVF_RING_RX_FBD_NUM_REG 0x80020 601600c3e5SJian Shen #define HCLGEVF_RING_RX_OFFSET_REG 0x80024 611600c3e5SJian Shen #define HCLGEVF_RING_RX_FBD_OFFSET_REG 0x80028 621600c3e5SJian Shen #define HCLGEVF_RING_RX_STASH_REG 0x80030 631600c3e5SJian Shen #define HCLGEVF_RING_RX_BD_ERR_REG 0x80034 641600c3e5SJian Shen #define HCLGEVF_RING_TX_ADDR_L_REG 0x80040 651600c3e5SJian Shen #define HCLGEVF_RING_TX_ADDR_H_REG 0x80044 661600c3e5SJian Shen #define HCLGEVF_RING_TX_BD_NUM_REG 0x80048 671600c3e5SJian Shen #define HCLGEVF_RING_TX_PRIORITY_REG 0x8004C 681600c3e5SJian Shen #define HCLGEVF_RING_TX_TC_REG 0x80050 691600c3e5SJian Shen #define HCLGEVF_RING_TX_MERGE_EN_REG 0x80054 701600c3e5SJian Shen #define HCLGEVF_RING_TX_TAIL_REG 0x80058 711600c3e5SJian Shen #define HCLGEVF_RING_TX_HEAD_REG 0x8005C 721600c3e5SJian Shen #define HCLGEVF_RING_TX_FBD_NUM_REG 0x80060 731600c3e5SJian Shen #define HCLGEVF_RING_TX_OFFSET_REG 0x80064 741600c3e5SJian Shen #define HCLGEVF_RING_TX_EBD_NUM_REG 0x80068 751600c3e5SJian Shen #define HCLGEVF_RING_TX_EBD_OFFSET_REG 0x80070 761600c3e5SJian Shen #define HCLGEVF_RING_TX_BD_ERR_REG 0x80074 771600c3e5SJian Shen #define HCLGEVF_RING_EN_REG 0x80090 781600c3e5SJian Shen 791600c3e5SJian Shen /* bar registers for tqp interrupt */ 801600c3e5SJian Shen #define HCLGEVF_TQP_INTR_CTRL_REG 0x20000 811600c3e5SJian Shen #define HCLGEVF_TQP_INTR_GL0_REG 0x20100 821600c3e5SJian Shen #define HCLGEVF_TQP_INTR_GL1_REG 0x20200 831600c3e5SJian Shen #define HCLGEVF_TQP_INTR_GL2_REG 0x20300 841600c3e5SJian Shen #define HCLGEVF_TQP_INTR_RL_REG 0x20900 851600c3e5SJian Shen 86e2cb1decSSalil Mehta /* Vector0 interrupt CMDQ event source register(RW) */ 87e2cb1decSSalil Mehta #define HCLGEVF_VECTOR0_CMDQ_SRC_REG 0x27100 8813050921SHuazhong Tan /* Vector0 interrupt CMDQ event status register(RO) */ 899cee2e8dSHuazhong Tan #define HCLGEVF_VECTOR0_CMDQ_STATE_REG 0x27104 90e2cb1decSSalil Mehta /* CMDQ register bits for RX event(=MBX event) */ 91e2cb1decSSalil Mehta #define HCLGEVF_VECTOR0_RX_CMDQ_INT_B 1 92b90fcc5bSHuazhong Tan /* RST register bits for RESET event */ 93b90fcc5bSHuazhong Tan #define HCLGEVF_VECTOR0_RST_INT_B 2 94e2cb1decSSalil Mehta 95e2cb1decSSalil Mehta #define HCLGEVF_TQP_RESET_TRY_TIMES 10 966988eb2aSSalil Mehta /* Reset related Registers */ 97aa5c4f17SHuazhong Tan #define HCLGEVF_RST_ING 0x20C00 98aa5c4f17SHuazhong Tan #define HCLGEVF_FUN_RST_ING_BIT BIT(0) 99aa5c4f17SHuazhong Tan #define HCLGEVF_GLOBAL_RST_ING_BIT BIT(5) 100aa5c4f17SHuazhong Tan #define HCLGEVF_CORE_RST_ING_BIT BIT(6) 101aa5c4f17SHuazhong Tan #define HCLGEVF_IMP_RST_ING_BIT BIT(7) 102aa5c4f17SHuazhong Tan #define HCLGEVF_RST_ING_BITS \ 103aa5c4f17SHuazhong Tan (HCLGEVF_FUN_RST_ING_BIT | HCLGEVF_GLOBAL_RST_ING_BIT | \ 104aa5c4f17SHuazhong Tan HCLGEVF_CORE_RST_ING_BIT | HCLGEVF_IMP_RST_ING_BIT) 105e2cb1decSSalil Mehta 10672e2fb07SHuazhong Tan #define HCLGEVF_VF_RST_ING 0x07008 10772e2fb07SHuazhong Tan #define HCLGEVF_VF_RST_ING_BIT BIT(16) 10872e2fb07SHuazhong Tan 109e2cb1decSSalil Mehta #define HCLGEVF_RSS_IND_TBL_SIZE 512 110e2cb1decSSalil Mehta #define HCLGEVF_RSS_SET_BITMAP_MSK 0xffff 111e2cb1decSSalil Mehta #define HCLGEVF_RSS_KEY_SIZE 40 112e2cb1decSSalil Mehta #define HCLGEVF_RSS_HASH_ALGO_TOEPLITZ 0 113e2cb1decSSalil Mehta #define HCLGEVF_RSS_HASH_ALGO_SIMPLE 1 114e2cb1decSSalil Mehta #define HCLGEVF_RSS_HASH_ALGO_SYMMETRIC 2 115e2cb1decSSalil Mehta #define HCLGEVF_RSS_HASH_ALGO_MASK 0xf 116e2cb1decSSalil Mehta #define HCLGEVF_RSS_CFG_TBL_NUM \ 117e2cb1decSSalil Mehta (HCLGEVF_RSS_IND_TBL_SIZE / HCLGEVF_RSS_CFG_TBL_SIZE) 118d97b3072SJian Shen #define HCLGEVF_RSS_INPUT_TUPLE_OTHER GENMASK(3, 0) 119d97b3072SJian Shen #define HCLGEVF_RSS_INPUT_TUPLE_SCTP GENMASK(4, 0) 120d97b3072SJian Shen #define HCLGEVF_D_PORT_BIT BIT(0) 121d97b3072SJian Shen #define HCLGEVF_S_PORT_BIT BIT(1) 122d97b3072SJian Shen #define HCLGEVF_D_IP_BIT BIT(2) 123d97b3072SJian Shen #define HCLGEVF_S_IP_BIT BIT(3) 124d97b3072SJian Shen #define HCLGEVF_V_TAG_BIT BIT(4) 125*ab6e32d2SJian Shen #define HCLGEVF_RSS_INPUT_TUPLE_SCTP_NO_PORT \ 126*ab6e32d2SJian Shen (HCLGEVF_D_IP_BIT | HCLGEVF_S_IP_BIT | HCLGEVF_V_TAG_BIT) 127e2cb1decSSalil Mehta 128eddd9860SGuojia Liao #define HCLGEVF_STATS_TIMER_INTERVAL 36U 129db01afebSliuzhongzhu 130b90fcc5bSHuazhong Tan enum hclgevf_evt_cause { 131b90fcc5bSHuazhong Tan HCLGEVF_VECTOR0_EVENT_RST, 132b90fcc5bSHuazhong Tan HCLGEVF_VECTOR0_EVENT_MBX, 133b90fcc5bSHuazhong Tan HCLGEVF_VECTOR0_EVENT_OTHER, 134b90fcc5bSHuazhong Tan }; 135b90fcc5bSHuazhong Tan 136e2cb1decSSalil Mehta /* states of hclgevf device & tasks */ 137e2cb1decSSalil Mehta enum hclgevf_states { 138e2cb1decSSalil Mehta /* device states */ 139e2cb1decSSalil Mehta HCLGEVF_STATE_DOWN, 140e2cb1decSSalil Mehta HCLGEVF_STATE_DISABLED, 141862d969aSHuazhong Tan HCLGEVF_STATE_IRQ_INITED, 142acfc3d55SHuazhong Tan HCLGEVF_STATE_REMOVING, 14325d1817cSHuazhong Tan HCLGEVF_STATE_NIC_REGISTERED, 144fe735c84SHuazhong Tan HCLGEVF_STATE_ROCE_REGISTERED, 145e2cb1decSSalil Mehta /* task states */ 14635a1e503SSalil Mehta HCLGEVF_STATE_RST_SERVICE_SCHED, 14735a1e503SSalil Mehta HCLGEVF_STATE_RST_HANDLING, 148e2cb1decSSalil Mehta HCLGEVF_STATE_MBX_SERVICE_SCHED, 149e2cb1decSSalil Mehta HCLGEVF_STATE_MBX_HANDLING, 150ef5f8e50SHuazhong Tan HCLGEVF_STATE_CMD_DISABLE, 151ff200099SYunsheng Lin HCLGEVF_STATE_LINK_UPDATING, 152c631c696SJian Shen HCLGEVF_STATE_PROMISC_CHANGED, 153d5432455SGuojia Liao HCLGEVF_STATE_RST_FAIL, 154e2cb1decSSalil Mehta }; 155e2cb1decSSalil Mehta 156e2cb1decSSalil Mehta struct hclgevf_mac { 157c136b884SPeng Li u8 media_type; 15888d10bd6SJian Shen u8 module_type; 159e2cb1decSSalil Mehta u8 mac_addr[ETH_ALEN]; 160e2cb1decSSalil Mehta int link; 1614a152de9SFuyun Liang u8 duplex; 1624a152de9SFuyun Liang u32 speed; 1639194d18bSliuzhongzhu u64 supported; 1649194d18bSliuzhongzhu u64 advertising; 165e2cb1decSSalil Mehta }; 166e2cb1decSSalil Mehta 167e2cb1decSSalil Mehta struct hclgevf_hw { 168e2cb1decSSalil Mehta void __iomem *io_base; 16930ae7f8aSHuazhong Tan void __iomem *mem_base; 170e2cb1decSSalil Mehta int num_vec; 171e2cb1decSSalil Mehta struct hclgevf_cmq cmq; 172e2cb1decSSalil Mehta struct hclgevf_mac mac; 173e2cb1decSSalil Mehta void *hdev; /* hchgevf device it is part of */ 174e2cb1decSSalil Mehta }; 175e2cb1decSSalil Mehta 176e2cb1decSSalil Mehta /* TQP stats */ 177e2cb1decSSalil Mehta struct hlcgevf_tqp_stats { 178e2cb1decSSalil Mehta /* query_tqp_tx_queue_statistics ,opcode id: 0x0B03 */ 179e2cb1decSSalil Mehta u64 rcb_tx_ring_pktnum_rcd; /* 32bit */ 180e2cb1decSSalil Mehta /* query_tqp_rx_queue_statistics ,opcode id: 0x0B13 */ 181e2cb1decSSalil Mehta u64 rcb_rx_ring_pktnum_rcd; /* 32bit */ 182e2cb1decSSalil Mehta }; 183e2cb1decSSalil Mehta 184e2cb1decSSalil Mehta struct hclgevf_tqp { 185e2cb1decSSalil Mehta struct device *dev; /* device for DMA mapping */ 186e2cb1decSSalil Mehta struct hnae3_queue q; 187e2cb1decSSalil Mehta struct hlcgevf_tqp_stats tqp_stats; 188e2cb1decSSalil Mehta u16 index; /* global index in a NIC controller */ 189e2cb1decSSalil Mehta 190e2cb1decSSalil Mehta bool alloced; 191e2cb1decSSalil Mehta }; 192e2cb1decSSalil Mehta 193e2cb1decSSalil Mehta struct hclgevf_cfg { 194e2cb1decSSalil Mehta u8 vmdq_vport_num; 195e2cb1decSSalil Mehta u8 tc_num; 196e2cb1decSSalil Mehta u16 tqp_desc_num; 197e2cb1decSSalil Mehta u16 rx_buf_len; 198e2cb1decSSalil Mehta u8 phy_addr; 199e2cb1decSSalil Mehta u8 media_type; 200e2cb1decSSalil Mehta u8 mac_addr[ETH_ALEN]; 201e2cb1decSSalil Mehta u32 numa_node_map; 202e2cb1decSSalil Mehta }; 203e2cb1decSSalil Mehta 204d97b3072SJian Shen struct hclgevf_rss_tuple_cfg { 205d97b3072SJian Shen u8 ipv4_tcp_en; 206d97b3072SJian Shen u8 ipv4_udp_en; 207d97b3072SJian Shen u8 ipv4_sctp_en; 208d97b3072SJian Shen u8 ipv4_fragment_en; 209d97b3072SJian Shen u8 ipv6_tcp_en; 210d97b3072SJian Shen u8 ipv6_udp_en; 211d97b3072SJian Shen u8 ipv6_sctp_en; 212d97b3072SJian Shen u8 ipv6_fragment_en; 213d97b3072SJian Shen }; 214d97b3072SJian Shen 215e2cb1decSSalil Mehta struct hclgevf_rss_cfg { 216e2cb1decSSalil Mehta u8 rss_hash_key[HCLGEVF_RSS_KEY_SIZE]; /* user configured hash keys */ 217e2cb1decSSalil Mehta u32 hash_algo; 218e2cb1decSSalil Mehta u32 rss_size; 219e2cb1decSSalil Mehta u8 hw_tc_map; 220e2cb1decSSalil Mehta u8 rss_indirection_tbl[HCLGEVF_RSS_IND_TBL_SIZE]; /* shadow table */ 221d97b3072SJian Shen struct hclgevf_rss_tuple_cfg rss_tuple_sets; 222e2cb1decSSalil Mehta }; 223e2cb1decSSalil Mehta 224e2cb1decSSalil Mehta struct hclgevf_misc_vector { 225e2cb1decSSalil Mehta u8 __iomem *addr; 226e2cb1decSSalil Mehta int vector_irq; 227f97c4d82SYonglong Liu char name[HNAE3_INT_NAME_LEN]; 228e2cb1decSSalil Mehta }; 229e2cb1decSSalil Mehta 230c88a6e7dSHuazhong Tan struct hclgevf_rst_stats { 231c88a6e7dSHuazhong Tan u32 rst_cnt; /* the number of reset */ 232c88a6e7dSHuazhong Tan u32 vf_func_rst_cnt; /* the number of VF function reset */ 233c88a6e7dSHuazhong Tan u32 flr_rst_cnt; /* the number of FLR */ 234c88a6e7dSHuazhong Tan u32 vf_rst_cnt; /* the number of VF reset */ 235c88a6e7dSHuazhong Tan u32 rst_done_cnt; /* the number of reset completed */ 236c88a6e7dSHuazhong Tan u32 hw_rst_done_cnt; /* the number of HW reset completed */ 237bbe6540eSHuazhong Tan u32 rst_fail_cnt; /* the number of VF reset fail */ 238c88a6e7dSHuazhong Tan }; 239c88a6e7dSHuazhong Tan 240ee4bcd3bSJian Shen enum HCLGEVF_MAC_ADDR_TYPE { 241ee4bcd3bSJian Shen HCLGEVF_MAC_ADDR_UC, 242ee4bcd3bSJian Shen HCLGEVF_MAC_ADDR_MC 243ee4bcd3bSJian Shen }; 244ee4bcd3bSJian Shen 245ee4bcd3bSJian Shen enum HCLGEVF_MAC_NODE_STATE { 246ee4bcd3bSJian Shen HCLGEVF_MAC_TO_ADD, 247ee4bcd3bSJian Shen HCLGEVF_MAC_TO_DEL, 248ee4bcd3bSJian Shen HCLGEVF_MAC_ACTIVE 249ee4bcd3bSJian Shen }; 250ee4bcd3bSJian Shen 251ee4bcd3bSJian Shen struct hclgevf_mac_addr_node { 252ee4bcd3bSJian Shen struct list_head node; 253ee4bcd3bSJian Shen enum HCLGEVF_MAC_NODE_STATE state; 254ee4bcd3bSJian Shen u8 mac_addr[ETH_ALEN]; 255ee4bcd3bSJian Shen }; 256ee4bcd3bSJian Shen 257ee4bcd3bSJian Shen struct hclgevf_mac_table_cfg { 258ee4bcd3bSJian Shen spinlock_t mac_list_lock; /* protect mac address need to add/detele */ 259ee4bcd3bSJian Shen struct list_head uc_mac_list; 260ee4bcd3bSJian Shen struct list_head mc_mac_list; 261ee4bcd3bSJian Shen }; 262ee4bcd3bSJian Shen 263e2cb1decSSalil Mehta struct hclgevf_dev { 264e2cb1decSSalil Mehta struct pci_dev *pdev; 265e2cb1decSSalil Mehta struct hnae3_ae_dev *ae_dev; 266e2cb1decSSalil Mehta struct hclgevf_hw hw; 267e2cb1decSSalil Mehta struct hclgevf_misc_vector misc_vector; 268e2cb1decSSalil Mehta struct hclgevf_rss_cfg rss_cfg; 269e2cb1decSSalil Mehta unsigned long state; 2706ff3cf07SHuazhong Tan unsigned long flr_state; 271720bd583SHuazhong Tan unsigned long default_reset_request; 2720742ed7cSHuazhong Tan unsigned long last_reset_time; 2730742ed7cSHuazhong Tan enum hnae3_reset_type reset_level; 274dea846e8SHuazhong Tan unsigned long reset_pending; 275dea846e8SHuazhong Tan enum hnae3_reset_type reset_type; 276e2cb1decSSalil Mehta 277436667d2SSalil Mehta #define HCLGEVF_RESET_REQUESTED 0 278436667d2SSalil Mehta #define HCLGEVF_RESET_PENDING 1 279436667d2SSalil Mehta unsigned long reset_state; /* requested, pending */ 280c88a6e7dSHuazhong Tan struct hclgevf_rst_stats rst_stats; 281436667d2SSalil Mehta u32 reset_attempts; 282f28368bbSHuazhong Tan struct semaphore reset_sem; /* protect reset process */ 283436667d2SSalil Mehta 284e2cb1decSSalil Mehta u32 fw_version; 285ec4d9392SHuazhong Tan u16 num_tqps; /* num task queue pairs of this VF */ 286e2cb1decSSalil Mehta 287e2cb1decSSalil Mehta u16 alloc_rss_size; /* allocated RSS task queue */ 288e2cb1decSSalil Mehta u16 rss_size_max; /* HW defined max RSS task queue */ 289e2cb1decSSalil Mehta 290e2cb1decSSalil Mehta u16 num_alloc_vport; /* num vports this driver supports */ 291e2cb1decSSalil Mehta u32 numa_node_mask; 292e2cb1decSSalil Mehta u16 rx_buf_len; 293c0425944SPeng Li u16 num_tx_desc; /* desc num of per tx queue */ 294c0425944SPeng Li u16 num_rx_desc; /* desc num of per rx queue */ 295e2cb1decSSalil Mehta u8 hw_tc_map; 2968e6de441SHuazhong Tan u8 has_pf_mac; 297e2cb1decSSalil Mehta 298e2cb1decSSalil Mehta u16 num_msi; 299e2cb1decSSalil Mehta u16 num_msi_left; 300e2cb1decSSalil Mehta u16 num_msi_used; 301580a05f9SYonglong Liu u16 num_nic_msix; /* Num of nic vectors for this VF */ 30207acf909SJian Shen u16 num_roce_msix; /* Num of roce vectors for this VF */ 30307acf909SJian Shen u16 roce_base_msix_offset; 30407acf909SJian Shen int roce_base_vector; 305e2cb1decSSalil Mehta u32 base_msi_vector; 306e2cb1decSSalil Mehta u16 *vector_status; 307e2cb1decSSalil Mehta int *vector_irq; 308e2cb1decSSalil Mehta 309fe4144d4SJian Shen unsigned long vlan_del_fail_bmap[BITS_TO_LONGS(VLAN_N_VID)]; 310fe4144d4SJian Shen 311ee4bcd3bSJian Shen struct hclgevf_mac_table_cfg mac_table; 312ee4bcd3bSJian Shen 31307a0556aSSalil Mehta bool mbx_event_pending; 314e2cb1decSSalil Mehta struct hclgevf_mbx_resp_status mbx_resp; /* mailbox response */ 31507a0556aSSalil Mehta struct hclgevf_mbx_arq_ring arq; /* mailbox async rx queue */ 316e2cb1decSSalil Mehta 317b3c3fe8eSYunsheng Lin struct delayed_work service_task; 318e2cb1decSSalil Mehta 319e2cb1decSSalil Mehta struct hclgevf_tqp *htqp; 320e2cb1decSSalil Mehta 321e2cb1decSSalil Mehta struct hnae3_handle nic; 322e2cb1decSSalil Mehta struct hnae3_handle roce; 323e2cb1decSSalil Mehta 324e2cb1decSSalil Mehta struct hnae3_client *nic_client; 325e2cb1decSSalil Mehta struct hnae3_client *roce_client; 326e2cb1decSSalil Mehta u32 flag; 327ff200099SYunsheng Lin unsigned long serv_processed_cnt; 328ff200099SYunsheng Lin unsigned long last_serv_processed; 329e2cb1decSSalil Mehta }; 330e2cb1decSSalil Mehta 331ef5f8e50SHuazhong Tan static inline bool hclgevf_is_reset_pending(struct hclgevf_dev *hdev) 332ef5f8e50SHuazhong Tan { 333ef5f8e50SHuazhong Tan return !!hdev->reset_pending; 334ef5f8e50SHuazhong Tan } 335ef5f8e50SHuazhong Tan 336d3410018SYufeng Mo int hclgevf_send_mbx_msg(struct hclgevf_dev *hdev, 337d3410018SYufeng Mo struct hclge_vf_to_pf_msg *send_msg, bool need_resp, 338e2cb1decSSalil Mehta u8 *resp_data, u16 resp_len); 339e2cb1decSSalil Mehta void hclgevf_mbx_handler(struct hclgevf_dev *hdev); 34007a0556aSSalil Mehta void hclgevf_mbx_async_handler(struct hclgevf_dev *hdev); 34107a0556aSSalil Mehta 342e2cb1decSSalil Mehta void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state); 3434a152de9SFuyun Liang void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed, 3444a152de9SFuyun Liang u8 duplex); 34535a1e503SSalil Mehta void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev); 34607a0556aSSalil Mehta void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev); 34792f11ea1SJian Shen void hclgevf_update_port_base_vlan_info(struct hclgevf_dev *hdev, u16 state, 34892f11ea1SJian Shen u8 *port_base_vlan_info, u8 data_size); 349e2cb1decSSalil Mehta #endif 350