1e2cb1decSSalil Mehta /* SPDX-License-Identifier: GPL-2.0+ */ 2e2cb1decSSalil Mehta /* Copyright (c) 2016-2017 Hisilicon Limited. */ 3e2cb1decSSalil Mehta 4e2cb1decSSalil Mehta #ifndef __HCLGEVF_MAIN_H 5e2cb1decSSalil Mehta #define __HCLGEVF_MAIN_H 6e2cb1decSSalil Mehta #include <linux/fs.h> 7e2cb1decSSalil Mehta #include <linux/types.h> 8e2cb1decSSalil Mehta #include "hclge_mbx.h" 9e2cb1decSSalil Mehta #include "hclgevf_cmd.h" 10e2cb1decSSalil Mehta #include "hnae3.h" 11e2cb1decSSalil Mehta 123c7624d8SXi Wang #define HCLGEVF_MOD_VERSION "1.0" 13e2cb1decSSalil Mehta #define HCLGEVF_DRIVER_NAME "hclgevf" 14e2cb1decSSalil Mehta 15e2cb1decSSalil Mehta #define HCLGEVF_MISC_VECTOR_NUM 0 16e2cb1decSSalil Mehta 17e2cb1decSSalil Mehta #define HCLGEVF_INVALID_VPORT 0xffff 18e2cb1decSSalil Mehta 19e2cb1decSSalil Mehta /* This number in actual depends upon the total number of VFs 20e2cb1decSSalil Mehta * created by physical function. But the maximum number of 21e2cb1decSSalil Mehta * possible vector-per-VF is {VFn(1-32), VECTn(32 + 1)}. 22e2cb1decSSalil Mehta */ 23e2cb1decSSalil Mehta #define HCLGEVF_MAX_VF_VECTOR_NUM (32 + 1) 24e2cb1decSSalil Mehta 25e2cb1decSSalil Mehta #define HCLGEVF_VECTOR_REG_BASE 0x20000 26e2cb1decSSalil Mehta #define HCLGEVF_MISC_VECTOR_REG_BASE 0x20400 27e2cb1decSSalil Mehta #define HCLGEVF_VECTOR_REG_OFFSET 0x4 28e2cb1decSSalil Mehta #define HCLGEVF_VECTOR_VF_OFFSET 0x100000 29e2cb1decSSalil Mehta 30e2cb1decSSalil Mehta /* Vector0 interrupt CMDQ event source register(RW) */ 31e2cb1decSSalil Mehta #define HCLGEVF_VECTOR0_CMDQ_SRC_REG 0x27100 32e2cb1decSSalil Mehta /* CMDQ register bits for RX event(=MBX event) */ 33e2cb1decSSalil Mehta #define HCLGEVF_VECTOR0_RX_CMDQ_INT_B 1 34b90fcc5bSHuazhong Tan /* RST register bits for RESET event */ 35b90fcc5bSHuazhong Tan #define HCLGEVF_VECTOR0_RST_INT_B 2 36e2cb1decSSalil Mehta 37e2cb1decSSalil Mehta #define HCLGEVF_TQP_RESET_TRY_TIMES 10 386988eb2aSSalil Mehta /* Reset related Registers */ 39aa5c4f17SHuazhong Tan #define HCLGEVF_RST_ING 0x20C00 40aa5c4f17SHuazhong Tan #define HCLGEVF_FUN_RST_ING_BIT BIT(0) 41aa5c4f17SHuazhong Tan #define HCLGEVF_GLOBAL_RST_ING_BIT BIT(5) 42aa5c4f17SHuazhong Tan #define HCLGEVF_CORE_RST_ING_BIT BIT(6) 43aa5c4f17SHuazhong Tan #define HCLGEVF_IMP_RST_ING_BIT BIT(7) 44aa5c4f17SHuazhong Tan #define HCLGEVF_RST_ING_BITS \ 45aa5c4f17SHuazhong Tan (HCLGEVF_FUN_RST_ING_BIT | HCLGEVF_GLOBAL_RST_ING_BIT | \ 46aa5c4f17SHuazhong Tan HCLGEVF_CORE_RST_ING_BIT | HCLGEVF_IMP_RST_ING_BIT) 47e2cb1decSSalil Mehta 48e2cb1decSSalil Mehta #define HCLGEVF_RSS_IND_TBL_SIZE 512 49e2cb1decSSalil Mehta #define HCLGEVF_RSS_SET_BITMAP_MSK 0xffff 50e2cb1decSSalil Mehta #define HCLGEVF_RSS_KEY_SIZE 40 51e2cb1decSSalil Mehta #define HCLGEVF_RSS_HASH_ALGO_TOEPLITZ 0 52e2cb1decSSalil Mehta #define HCLGEVF_RSS_HASH_ALGO_SIMPLE 1 53e2cb1decSSalil Mehta #define HCLGEVF_RSS_HASH_ALGO_SYMMETRIC 2 54e2cb1decSSalil Mehta #define HCLGEVF_RSS_HASH_ALGO_MASK 0xf 55e2cb1decSSalil Mehta #define HCLGEVF_RSS_CFG_TBL_NUM \ 56e2cb1decSSalil Mehta (HCLGEVF_RSS_IND_TBL_SIZE / HCLGEVF_RSS_CFG_TBL_SIZE) 57d97b3072SJian Shen #define HCLGEVF_RSS_INPUT_TUPLE_OTHER GENMASK(3, 0) 58d97b3072SJian Shen #define HCLGEVF_RSS_INPUT_TUPLE_SCTP GENMASK(4, 0) 59d97b3072SJian Shen #define HCLGEVF_D_PORT_BIT BIT(0) 60d97b3072SJian Shen #define HCLGEVF_S_PORT_BIT BIT(1) 61d97b3072SJian Shen #define HCLGEVF_D_IP_BIT BIT(2) 62d97b3072SJian Shen #define HCLGEVF_S_IP_BIT BIT(3) 63d97b3072SJian Shen #define HCLGEVF_V_TAG_BIT BIT(4) 64e2cb1decSSalil Mehta 65b90fcc5bSHuazhong Tan enum hclgevf_evt_cause { 66b90fcc5bSHuazhong Tan HCLGEVF_VECTOR0_EVENT_RST, 67b90fcc5bSHuazhong Tan HCLGEVF_VECTOR0_EVENT_MBX, 68b90fcc5bSHuazhong Tan HCLGEVF_VECTOR0_EVENT_OTHER, 69b90fcc5bSHuazhong Tan }; 70b90fcc5bSHuazhong Tan 71e2cb1decSSalil Mehta /* states of hclgevf device & tasks */ 72e2cb1decSSalil Mehta enum hclgevf_states { 73e2cb1decSSalil Mehta /* device states */ 74e2cb1decSSalil Mehta HCLGEVF_STATE_DOWN, 75e2cb1decSSalil Mehta HCLGEVF_STATE_DISABLED, 76862d969aSHuazhong Tan HCLGEVF_STATE_IRQ_INITED, 77e2cb1decSSalil Mehta /* task states */ 78e2cb1decSSalil Mehta HCLGEVF_STATE_SERVICE_SCHED, 7935a1e503SSalil Mehta HCLGEVF_STATE_RST_SERVICE_SCHED, 8035a1e503SSalil Mehta HCLGEVF_STATE_RST_HANDLING, 81e2cb1decSSalil Mehta HCLGEVF_STATE_MBX_SERVICE_SCHED, 82e2cb1decSSalil Mehta HCLGEVF_STATE_MBX_HANDLING, 83ef5f8e50SHuazhong Tan HCLGEVF_STATE_CMD_DISABLE, 84e2cb1decSSalil Mehta }; 85e2cb1decSSalil Mehta 86e2cb1decSSalil Mehta #define HCLGEVF_MPF_ENBALE 1 87e2cb1decSSalil Mehta 88e2cb1decSSalil Mehta struct hclgevf_mac { 89c136b884SPeng Li u8 media_type; 90e2cb1decSSalil Mehta u8 mac_addr[ETH_ALEN]; 91e2cb1decSSalil Mehta int link; 924a152de9SFuyun Liang u8 duplex; 934a152de9SFuyun Liang u32 speed; 94e2cb1decSSalil Mehta }; 95e2cb1decSSalil Mehta 96e2cb1decSSalil Mehta struct hclgevf_hw { 97e2cb1decSSalil Mehta void __iomem *io_base; 98e2cb1decSSalil Mehta int num_vec; 99e2cb1decSSalil Mehta struct hclgevf_cmq cmq; 100e2cb1decSSalil Mehta struct hclgevf_mac mac; 101e2cb1decSSalil Mehta void *hdev; /* hchgevf device it is part of */ 102e2cb1decSSalil Mehta }; 103e2cb1decSSalil Mehta 104e2cb1decSSalil Mehta /* TQP stats */ 105e2cb1decSSalil Mehta struct hlcgevf_tqp_stats { 106e2cb1decSSalil Mehta /* query_tqp_tx_queue_statistics ,opcode id: 0x0B03 */ 107e2cb1decSSalil Mehta u64 rcb_tx_ring_pktnum_rcd; /* 32bit */ 108e2cb1decSSalil Mehta /* query_tqp_rx_queue_statistics ,opcode id: 0x0B13 */ 109e2cb1decSSalil Mehta u64 rcb_rx_ring_pktnum_rcd; /* 32bit */ 110e2cb1decSSalil Mehta }; 111e2cb1decSSalil Mehta 112e2cb1decSSalil Mehta struct hclgevf_tqp { 113e2cb1decSSalil Mehta struct device *dev; /* device for DMA mapping */ 114e2cb1decSSalil Mehta struct hnae3_queue q; 115e2cb1decSSalil Mehta struct hlcgevf_tqp_stats tqp_stats; 116e2cb1decSSalil Mehta u16 index; /* global index in a NIC controller */ 117e2cb1decSSalil Mehta 118e2cb1decSSalil Mehta bool alloced; 119e2cb1decSSalil Mehta }; 120e2cb1decSSalil Mehta 121e2cb1decSSalil Mehta struct hclgevf_cfg { 122e2cb1decSSalil Mehta u8 vmdq_vport_num; 123e2cb1decSSalil Mehta u8 tc_num; 124e2cb1decSSalil Mehta u16 tqp_desc_num; 125e2cb1decSSalil Mehta u16 rx_buf_len; 126e2cb1decSSalil Mehta u8 phy_addr; 127e2cb1decSSalil Mehta u8 media_type; 128e2cb1decSSalil Mehta u8 mac_addr[ETH_ALEN]; 129e2cb1decSSalil Mehta u32 numa_node_map; 130e2cb1decSSalil Mehta }; 131e2cb1decSSalil Mehta 132d97b3072SJian Shen struct hclgevf_rss_tuple_cfg { 133d97b3072SJian Shen u8 ipv4_tcp_en; 134d97b3072SJian Shen u8 ipv4_udp_en; 135d97b3072SJian Shen u8 ipv4_sctp_en; 136d97b3072SJian Shen u8 ipv4_fragment_en; 137d97b3072SJian Shen u8 ipv6_tcp_en; 138d97b3072SJian Shen u8 ipv6_udp_en; 139d97b3072SJian Shen u8 ipv6_sctp_en; 140d97b3072SJian Shen u8 ipv6_fragment_en; 141d97b3072SJian Shen }; 142d97b3072SJian Shen 143e2cb1decSSalil Mehta struct hclgevf_rss_cfg { 144e2cb1decSSalil Mehta u8 rss_hash_key[HCLGEVF_RSS_KEY_SIZE]; /* user configured hash keys */ 145e2cb1decSSalil Mehta u32 hash_algo; 146e2cb1decSSalil Mehta u32 rss_size; 147e2cb1decSSalil Mehta u8 hw_tc_map; 148e2cb1decSSalil Mehta u8 rss_indirection_tbl[HCLGEVF_RSS_IND_TBL_SIZE]; /* shadow table */ 149d97b3072SJian Shen struct hclgevf_rss_tuple_cfg rss_tuple_sets; 150e2cb1decSSalil Mehta }; 151e2cb1decSSalil Mehta 152e2cb1decSSalil Mehta struct hclgevf_misc_vector { 153e2cb1decSSalil Mehta u8 __iomem *addr; 154e2cb1decSSalil Mehta int vector_irq; 155e2cb1decSSalil Mehta }; 156e2cb1decSSalil Mehta 157e2cb1decSSalil Mehta struct hclgevf_dev { 158e2cb1decSSalil Mehta struct pci_dev *pdev; 159e2cb1decSSalil Mehta struct hnae3_ae_dev *ae_dev; 160e2cb1decSSalil Mehta struct hclgevf_hw hw; 161e2cb1decSSalil Mehta struct hclgevf_misc_vector misc_vector; 162e2cb1decSSalil Mehta struct hclgevf_rss_cfg rss_cfg; 163e2cb1decSSalil Mehta unsigned long state; 1646ff3cf07SHuazhong Tan unsigned long flr_state; 165720bd583SHuazhong Tan unsigned long default_reset_request; 1660742ed7cSHuazhong Tan unsigned long last_reset_time; 1670742ed7cSHuazhong Tan enum hnae3_reset_type reset_level; 168dea846e8SHuazhong Tan unsigned long reset_pending; 169dea846e8SHuazhong Tan enum hnae3_reset_type reset_type; 170e2cb1decSSalil Mehta 171436667d2SSalil Mehta #define HCLGEVF_RESET_REQUESTED 0 172436667d2SSalil Mehta #define HCLGEVF_RESET_PENDING 1 173436667d2SSalil Mehta unsigned long reset_state; /* requested, pending */ 1744d60291bSHuazhong Tan unsigned long reset_count; /* the number of reset has been done */ 175436667d2SSalil Mehta u32 reset_attempts; 176436667d2SSalil Mehta 177e2cb1decSSalil Mehta u32 fw_version; 178e2cb1decSSalil Mehta u16 num_tqps; /* num task queue pairs of this PF */ 179e2cb1decSSalil Mehta 180e2cb1decSSalil Mehta u16 alloc_rss_size; /* allocated RSS task queue */ 181e2cb1decSSalil Mehta u16 rss_size_max; /* HW defined max RSS task queue */ 182e2cb1decSSalil Mehta 183e2cb1decSSalil Mehta u16 num_alloc_vport; /* num vports this driver supports */ 184e2cb1decSSalil Mehta u32 numa_node_mask; 185e2cb1decSSalil Mehta u16 rx_buf_len; 186e2cb1decSSalil Mehta u16 num_desc; 187e2cb1decSSalil Mehta u8 hw_tc_map; 188e2cb1decSSalil Mehta 189e2cb1decSSalil Mehta u16 num_msi; 190e2cb1decSSalil Mehta u16 num_msi_left; 191e2cb1decSSalil Mehta u16 num_msi_used; 19207acf909SJian Shen u16 num_roce_msix; /* Num of roce vectors for this VF */ 19307acf909SJian Shen u16 roce_base_msix_offset; 19407acf909SJian Shen int roce_base_vector; 195e2cb1decSSalil Mehta u32 base_msi_vector; 196e2cb1decSSalil Mehta u16 *vector_status; 197e2cb1decSSalil Mehta int *vector_irq; 198e2cb1decSSalil Mehta 19907a0556aSSalil Mehta bool mbx_event_pending; 200e2cb1decSSalil Mehta struct hclgevf_mbx_resp_status mbx_resp; /* mailbox response */ 20107a0556aSSalil Mehta struct hclgevf_mbx_arq_ring arq; /* mailbox async rx queue */ 202e2cb1decSSalil Mehta 203e2cb1decSSalil Mehta struct timer_list service_timer; 204a6d818e3SYunsheng Lin struct timer_list keep_alive_timer; 205e2cb1decSSalil Mehta struct work_struct service_task; 206a6d818e3SYunsheng Lin struct work_struct keep_alive_task; 20735a1e503SSalil Mehta struct work_struct rst_service_task; 208e2cb1decSSalil Mehta struct work_struct mbx_service_task; 209e2cb1decSSalil Mehta 210e2cb1decSSalil Mehta struct hclgevf_tqp *htqp; 211e2cb1decSSalil Mehta 212e2cb1decSSalil Mehta struct hnae3_handle nic; 213e2cb1decSSalil Mehta struct hnae3_handle roce; 214e2cb1decSSalil Mehta 215e2cb1decSSalil Mehta struct hnae3_client *nic_client; 216e2cb1decSSalil Mehta struct hnae3_client *roce_client; 217e2cb1decSSalil Mehta u32 flag; 218e2cb1decSSalil Mehta }; 219e2cb1decSSalil Mehta 220ef5f8e50SHuazhong Tan static inline bool hclgevf_is_reset_pending(struct hclgevf_dev *hdev) 221ef5f8e50SHuazhong Tan { 222ef5f8e50SHuazhong Tan return !!hdev->reset_pending; 223ef5f8e50SHuazhong Tan } 224ef5f8e50SHuazhong Tan 225e2cb1decSSalil Mehta int hclgevf_send_mbx_msg(struct hclgevf_dev *hdev, u16 code, u16 subcode, 226e2cb1decSSalil Mehta const u8 *msg_data, u8 msg_len, bool need_resp, 227e2cb1decSSalil Mehta u8 *resp_data, u16 resp_len); 228e2cb1decSSalil Mehta void hclgevf_mbx_handler(struct hclgevf_dev *hdev); 22907a0556aSSalil Mehta void hclgevf_mbx_async_handler(struct hclgevf_dev *hdev); 23007a0556aSSalil Mehta 231e2cb1decSSalil Mehta void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state); 2324a152de9SFuyun Liang void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed, 2334a152de9SFuyun Liang u8 duplex); 23435a1e503SSalil Mehta void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev); 23507a0556aSSalil Mehta void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev); 236e2cb1decSSalil Mehta #endif 237