1e2cb1decSSalil Mehta /* SPDX-License-Identifier: GPL-2.0+ */ 2e2cb1decSSalil Mehta /* Copyright (c) 2016-2017 Hisilicon Limited. */ 3e2cb1decSSalil Mehta 4e2cb1decSSalil Mehta #ifndef __HCLGEVF_MAIN_H 5e2cb1decSSalil Mehta #define __HCLGEVF_MAIN_H 6e2cb1decSSalil Mehta #include <linux/fs.h> 7e2cb1decSSalil Mehta #include <linux/types.h> 8e2cb1decSSalil Mehta #include "hclge_mbx.h" 9e2cb1decSSalil Mehta #include "hclgevf_cmd.h" 10e2cb1decSSalil Mehta #include "hnae3.h" 11e2cb1decSSalil Mehta 12e2cb1decSSalil Mehta #define HCLGEVF_MOD_VERSION "v1.0" 13e2cb1decSSalil Mehta #define HCLGEVF_DRIVER_NAME "hclgevf" 14e2cb1decSSalil Mehta 15e2cb1decSSalil Mehta #define HCLGEVF_ROCEE_VECTOR_NUM 0 16e2cb1decSSalil Mehta #define HCLGEVF_MISC_VECTOR_NUM 0 17e2cb1decSSalil Mehta 18e2cb1decSSalil Mehta #define HCLGEVF_INVALID_VPORT 0xffff 19e2cb1decSSalil Mehta 20e2cb1decSSalil Mehta /* This number in actual depends upon the total number of VFs 21e2cb1decSSalil Mehta * created by physical function. But the maximum number of 22e2cb1decSSalil Mehta * possible vector-per-VF is {VFn(1-32), VECTn(32 + 1)}. 23e2cb1decSSalil Mehta */ 24e2cb1decSSalil Mehta #define HCLGEVF_MAX_VF_VECTOR_NUM (32 + 1) 25e2cb1decSSalil Mehta 26e2cb1decSSalil Mehta #define HCLGEVF_VECTOR_REG_BASE 0x20000 27e2cb1decSSalil Mehta #define HCLGEVF_MISC_VECTOR_REG_BASE 0x20400 28e2cb1decSSalil Mehta #define HCLGEVF_VECTOR_REG_OFFSET 0x4 29e2cb1decSSalil Mehta #define HCLGEVF_VECTOR_VF_OFFSET 0x100000 30e2cb1decSSalil Mehta 31e2cb1decSSalil Mehta /* Vector0 interrupt CMDQ event source register(RW) */ 32e2cb1decSSalil Mehta #define HCLGEVF_VECTOR0_CMDQ_SRC_REG 0x27100 33e2cb1decSSalil Mehta /* CMDQ register bits for RX event(=MBX event) */ 34e2cb1decSSalil Mehta #define HCLGEVF_VECTOR0_RX_CMDQ_INT_B 1 35e2cb1decSSalil Mehta 36e2cb1decSSalil Mehta #define HCLGEVF_TQP_RESET_TRY_TIMES 10 376988eb2aSSalil Mehta /* Reset related Registers */ 386988eb2aSSalil Mehta #define HCLGEVF_FUN_RST_ING 0x20C00 396988eb2aSSalil Mehta #define HCLGEVF_FUN_RST_ING_B 0 40e2cb1decSSalil Mehta 41e2cb1decSSalil Mehta #define HCLGEVF_RSS_IND_TBL_SIZE 512 42e2cb1decSSalil Mehta #define HCLGEVF_RSS_SET_BITMAP_MSK 0xffff 43e2cb1decSSalil Mehta #define HCLGEVF_RSS_KEY_SIZE 40 44e2cb1decSSalil Mehta #define HCLGEVF_RSS_HASH_ALGO_TOEPLITZ 0 45e2cb1decSSalil Mehta #define HCLGEVF_RSS_HASH_ALGO_SIMPLE 1 46e2cb1decSSalil Mehta #define HCLGEVF_RSS_HASH_ALGO_SYMMETRIC 2 47e2cb1decSSalil Mehta #define HCLGEVF_RSS_HASH_ALGO_MASK 0xf 48e2cb1decSSalil Mehta #define HCLGEVF_RSS_CFG_TBL_NUM \ 49e2cb1decSSalil Mehta (HCLGEVF_RSS_IND_TBL_SIZE / HCLGEVF_RSS_CFG_TBL_SIZE) 50e2cb1decSSalil Mehta 51e2cb1decSSalil Mehta /* states of hclgevf device & tasks */ 52e2cb1decSSalil Mehta enum hclgevf_states { 53e2cb1decSSalil Mehta /* device states */ 54e2cb1decSSalil Mehta HCLGEVF_STATE_DOWN, 55e2cb1decSSalil Mehta HCLGEVF_STATE_DISABLED, 56e2cb1decSSalil Mehta /* task states */ 57e2cb1decSSalil Mehta HCLGEVF_STATE_SERVICE_SCHED, 5835a1e503SSalil Mehta HCLGEVF_STATE_RST_SERVICE_SCHED, 5935a1e503SSalil Mehta HCLGEVF_STATE_RST_HANDLING, 60e2cb1decSSalil Mehta HCLGEVF_STATE_MBX_SERVICE_SCHED, 61e2cb1decSSalil Mehta HCLGEVF_STATE_MBX_HANDLING, 62e2cb1decSSalil Mehta }; 63e2cb1decSSalil Mehta 64e2cb1decSSalil Mehta #define HCLGEVF_MPF_ENBALE 1 65e2cb1decSSalil Mehta 66e2cb1decSSalil Mehta struct hclgevf_mac { 67e2cb1decSSalil Mehta u8 mac_addr[ETH_ALEN]; 68e2cb1decSSalil Mehta int link; 694a152de9SFuyun Liang u8 duplex; 704a152de9SFuyun Liang u32 speed; 71e2cb1decSSalil Mehta }; 72e2cb1decSSalil Mehta 73e2cb1decSSalil Mehta struct hclgevf_hw { 74e2cb1decSSalil Mehta void __iomem *io_base; 75e2cb1decSSalil Mehta int num_vec; 76e2cb1decSSalil Mehta struct hclgevf_cmq cmq; 77e2cb1decSSalil Mehta struct hclgevf_mac mac; 78e2cb1decSSalil Mehta void *hdev; /* hchgevf device it is part of */ 79e2cb1decSSalil Mehta }; 80e2cb1decSSalil Mehta 81e2cb1decSSalil Mehta /* TQP stats */ 82e2cb1decSSalil Mehta struct hlcgevf_tqp_stats { 83e2cb1decSSalil Mehta /* query_tqp_tx_queue_statistics ,opcode id: 0x0B03 */ 84e2cb1decSSalil Mehta u64 rcb_tx_ring_pktnum_rcd; /* 32bit */ 85e2cb1decSSalil Mehta /* query_tqp_rx_queue_statistics ,opcode id: 0x0B13 */ 86e2cb1decSSalil Mehta u64 rcb_rx_ring_pktnum_rcd; /* 32bit */ 87e2cb1decSSalil Mehta }; 88e2cb1decSSalil Mehta 89e2cb1decSSalil Mehta struct hclgevf_tqp { 90e2cb1decSSalil Mehta struct device *dev; /* device for DMA mapping */ 91e2cb1decSSalil Mehta struct hnae3_queue q; 92e2cb1decSSalil Mehta struct hlcgevf_tqp_stats tqp_stats; 93e2cb1decSSalil Mehta u16 index; /* global index in a NIC controller */ 94e2cb1decSSalil Mehta 95e2cb1decSSalil Mehta bool alloced; 96e2cb1decSSalil Mehta }; 97e2cb1decSSalil Mehta 98e2cb1decSSalil Mehta struct hclgevf_cfg { 99e2cb1decSSalil Mehta u8 vmdq_vport_num; 100e2cb1decSSalil Mehta u8 tc_num; 101e2cb1decSSalil Mehta u16 tqp_desc_num; 102e2cb1decSSalil Mehta u16 rx_buf_len; 103e2cb1decSSalil Mehta u8 phy_addr; 104e2cb1decSSalil Mehta u8 media_type; 105e2cb1decSSalil Mehta u8 mac_addr[ETH_ALEN]; 106e2cb1decSSalil Mehta u32 numa_node_map; 107e2cb1decSSalil Mehta }; 108e2cb1decSSalil Mehta 109e2cb1decSSalil Mehta struct hclgevf_rss_cfg { 110e2cb1decSSalil Mehta u8 rss_hash_key[HCLGEVF_RSS_KEY_SIZE]; /* user configured hash keys */ 111e2cb1decSSalil Mehta u32 hash_algo; 112e2cb1decSSalil Mehta u32 rss_size; 113e2cb1decSSalil Mehta u8 hw_tc_map; 114e2cb1decSSalil Mehta u8 rss_indirection_tbl[HCLGEVF_RSS_IND_TBL_SIZE]; /* shadow table */ 115e2cb1decSSalil Mehta }; 116e2cb1decSSalil Mehta 117e2cb1decSSalil Mehta struct hclgevf_misc_vector { 118e2cb1decSSalil Mehta u8 __iomem *addr; 119e2cb1decSSalil Mehta int vector_irq; 120e2cb1decSSalil Mehta }; 121e2cb1decSSalil Mehta 122e2cb1decSSalil Mehta struct hclgevf_dev { 123e2cb1decSSalil Mehta struct pci_dev *pdev; 124e2cb1decSSalil Mehta struct hnae3_ae_dev *ae_dev; 125e2cb1decSSalil Mehta struct hclgevf_hw hw; 126e2cb1decSSalil Mehta struct hclgevf_misc_vector misc_vector; 127e2cb1decSSalil Mehta struct hclgevf_rss_cfg rss_cfg; 128e2cb1decSSalil Mehta unsigned long state; 129e2cb1decSSalil Mehta 130436667d2SSalil Mehta #define HCLGEVF_RESET_REQUESTED 0 131436667d2SSalil Mehta #define HCLGEVF_RESET_PENDING 1 132436667d2SSalil Mehta unsigned long reset_state; /* requested, pending */ 133436667d2SSalil Mehta u32 reset_attempts; 134436667d2SSalil Mehta 135e2cb1decSSalil Mehta u32 fw_version; 136e2cb1decSSalil Mehta u16 num_tqps; /* num task queue pairs of this PF */ 137e2cb1decSSalil Mehta 138e2cb1decSSalil Mehta u16 alloc_rss_size; /* allocated RSS task queue */ 139e2cb1decSSalil Mehta u16 rss_size_max; /* HW defined max RSS task queue */ 140e2cb1decSSalil Mehta 141e2cb1decSSalil Mehta u16 num_alloc_vport; /* num vports this driver supports */ 142e2cb1decSSalil Mehta u32 numa_node_mask; 143e2cb1decSSalil Mehta u16 rx_buf_len; 144e2cb1decSSalil Mehta u16 num_desc; 145e2cb1decSSalil Mehta u8 hw_tc_map; 146e2cb1decSSalil Mehta 147e2cb1decSSalil Mehta u16 num_msi; 148e2cb1decSSalil Mehta u16 num_msi_left; 149e2cb1decSSalil Mehta u16 num_msi_used; 150e2cb1decSSalil Mehta u32 base_msi_vector; 151e2cb1decSSalil Mehta u16 *vector_status; 152e2cb1decSSalil Mehta int *vector_irq; 153e2cb1decSSalil Mehta 154e2cb1decSSalil Mehta bool accept_mta_mc; /* whether to accept mta filter multicast */ 155e2cb1decSSalil Mehta struct hclgevf_mbx_resp_status mbx_resp; /* mailbox response */ 156e2cb1decSSalil Mehta 157e2cb1decSSalil Mehta struct timer_list service_timer; 158e2cb1decSSalil Mehta struct work_struct service_task; 15935a1e503SSalil Mehta struct work_struct rst_service_task; 160e2cb1decSSalil Mehta struct work_struct mbx_service_task; 161e2cb1decSSalil Mehta 162e2cb1decSSalil Mehta struct hclgevf_tqp *htqp; 163e2cb1decSSalil Mehta 164e2cb1decSSalil Mehta struct hnae3_handle nic; 165e2cb1decSSalil Mehta struct hnae3_handle roce; 166e2cb1decSSalil Mehta 167e2cb1decSSalil Mehta struct hnae3_client *nic_client; 168e2cb1decSSalil Mehta struct hnae3_client *roce_client; 169e2cb1decSSalil Mehta u32 flag; 170e2cb1decSSalil Mehta }; 171e2cb1decSSalil Mehta 1727a01c897SSalil Mehta static inline bool hclgevf_dev_ongoing_reset(struct hclgevf_dev *hdev) 1737a01c897SSalil Mehta { 1747a01c897SSalil Mehta return (hdev && 1757a01c897SSalil Mehta (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) && 1767a01c897SSalil Mehta (hdev->nic.reset_level == HNAE3_VF_RESET)); 1777a01c897SSalil Mehta } 1787a01c897SSalil Mehta 1797a01c897SSalil Mehta static inline bool hclgevf_dev_ongoing_full_reset(struct hclgevf_dev *hdev) 1807a01c897SSalil Mehta { 1817a01c897SSalil Mehta return (hdev && 1827a01c897SSalil Mehta (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) && 1837a01c897SSalil Mehta (hdev->nic.reset_level == HNAE3_VF_FULL_RESET)); 1847a01c897SSalil Mehta } 1857a01c897SSalil Mehta 186e2cb1decSSalil Mehta int hclgevf_send_mbx_msg(struct hclgevf_dev *hdev, u16 code, u16 subcode, 187e2cb1decSSalil Mehta const u8 *msg_data, u8 msg_len, bool need_resp, 188e2cb1decSSalil Mehta u8 *resp_data, u16 resp_len); 189e2cb1decSSalil Mehta void hclgevf_mbx_handler(struct hclgevf_dev *hdev); 190e2cb1decSSalil Mehta void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state); 1914a152de9SFuyun Liang void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed, 1924a152de9SFuyun Liang u8 duplex); 19335a1e503SSalil Mehta void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev); 194e2cb1decSSalil Mehta #endif 195