1e2cb1decSSalil Mehta /* SPDX-License-Identifier: GPL-2.0+ */ 2e2cb1decSSalil Mehta /* Copyright (c) 2016-2017 Hisilicon Limited. */ 3e2cb1decSSalil Mehta 4e2cb1decSSalil Mehta #ifndef __HCLGEVF_MAIN_H 5e2cb1decSSalil Mehta #define __HCLGEVF_MAIN_H 6e2cb1decSSalil Mehta #include <linux/fs.h> 7fe4144d4SJian Shen #include <linux/if_vlan.h> 8e2cb1decSSalil Mehta #include <linux/types.h> 9e2cb1decSSalil Mehta #include "hclge_mbx.h" 10e2cb1decSSalil Mehta #include "hclgevf_cmd.h" 11e2cb1decSSalil Mehta #include "hnae3.h" 12e2cb1decSSalil Mehta 133c7624d8SXi Wang #define HCLGEVF_MOD_VERSION "1.0" 14e2cb1decSSalil Mehta #define HCLGEVF_DRIVER_NAME "hclgevf" 15e2cb1decSSalil Mehta 16b37ce587SYufeng Mo #define HCLGEVF_MAX_VLAN_ID 4095 17e2cb1decSSalil Mehta #define HCLGEVF_MISC_VECTOR_NUM 0 18e2cb1decSSalil Mehta 19e2cb1decSSalil Mehta #define HCLGEVF_INVALID_VPORT 0xffff 20b37ce587SYufeng Mo #define HCLGEVF_GENERAL_TASK_INTERVAL 5 21b37ce587SYufeng Mo #define HCLGEVF_KEEP_ALIVE_TASK_INTERVAL 2 22e2cb1decSSalil Mehta 23e2cb1decSSalil Mehta /* This number in actual depends upon the total number of VFs 24e2cb1decSSalil Mehta * created by physical function. But the maximum number of 25e2cb1decSSalil Mehta * possible vector-per-VF is {VFn(1-32), VECTn(32 + 1)}. 26e2cb1decSSalil Mehta */ 27e2cb1decSSalil Mehta #define HCLGEVF_MAX_VF_VECTOR_NUM (32 + 1) 28e2cb1decSSalil Mehta 29e2cb1decSSalil Mehta #define HCLGEVF_VECTOR_REG_BASE 0x20000 30e2cb1decSSalil Mehta #define HCLGEVF_MISC_VECTOR_REG_BASE 0x20400 31e2cb1decSSalil Mehta #define HCLGEVF_VECTOR_REG_OFFSET 0x4 32e2cb1decSSalil Mehta #define HCLGEVF_VECTOR_VF_OFFSET 0x100000 33e2cb1decSSalil Mehta 341600c3e5SJian Shen /* bar registers for cmdq */ 351600c3e5SJian Shen #define HCLGEVF_CMDQ_TX_ADDR_L_REG 0x27000 361600c3e5SJian Shen #define HCLGEVF_CMDQ_TX_ADDR_H_REG 0x27004 371600c3e5SJian Shen #define HCLGEVF_CMDQ_TX_DEPTH_REG 0x27008 381600c3e5SJian Shen #define HCLGEVF_CMDQ_TX_TAIL_REG 0x27010 391600c3e5SJian Shen #define HCLGEVF_CMDQ_TX_HEAD_REG 0x27014 401600c3e5SJian Shen #define HCLGEVF_CMDQ_RX_ADDR_L_REG 0x27018 411600c3e5SJian Shen #define HCLGEVF_CMDQ_RX_ADDR_H_REG 0x2701C 421600c3e5SJian Shen #define HCLGEVF_CMDQ_RX_DEPTH_REG 0x27020 431600c3e5SJian Shen #define HCLGEVF_CMDQ_RX_TAIL_REG 0x27024 441600c3e5SJian Shen #define HCLGEVF_CMDQ_RX_HEAD_REG 0x27028 451600c3e5SJian Shen #define HCLGEVF_CMDQ_INTR_EN_REG 0x27108 461600c3e5SJian Shen #define HCLGEVF_CMDQ_INTR_GEN_REG 0x2710C 471600c3e5SJian Shen 481600c3e5SJian Shen /* bar registers for common func */ 491600c3e5SJian Shen #define HCLGEVF_GRO_EN_REG 0x28000 5079664077SHuazhong Tan #define HCLGEVF_RXD_ADV_LAYOUT_EN_REG 0x28008 511600c3e5SJian Shen 521600c3e5SJian Shen /* bar registers for rcb */ 531600c3e5SJian Shen #define HCLGEVF_RING_RX_ADDR_L_REG 0x80000 541600c3e5SJian Shen #define HCLGEVF_RING_RX_ADDR_H_REG 0x80004 551600c3e5SJian Shen #define HCLGEVF_RING_RX_BD_NUM_REG 0x80008 561600c3e5SJian Shen #define HCLGEVF_RING_RX_BD_LENGTH_REG 0x8000C 571600c3e5SJian Shen #define HCLGEVF_RING_RX_MERGE_EN_REG 0x80014 581600c3e5SJian Shen #define HCLGEVF_RING_RX_TAIL_REG 0x80018 591600c3e5SJian Shen #define HCLGEVF_RING_RX_HEAD_REG 0x8001C 601600c3e5SJian Shen #define HCLGEVF_RING_RX_FBD_NUM_REG 0x80020 611600c3e5SJian Shen #define HCLGEVF_RING_RX_OFFSET_REG 0x80024 621600c3e5SJian Shen #define HCLGEVF_RING_RX_FBD_OFFSET_REG 0x80028 631600c3e5SJian Shen #define HCLGEVF_RING_RX_STASH_REG 0x80030 641600c3e5SJian Shen #define HCLGEVF_RING_RX_BD_ERR_REG 0x80034 651600c3e5SJian Shen #define HCLGEVF_RING_TX_ADDR_L_REG 0x80040 661600c3e5SJian Shen #define HCLGEVF_RING_TX_ADDR_H_REG 0x80044 671600c3e5SJian Shen #define HCLGEVF_RING_TX_BD_NUM_REG 0x80048 681600c3e5SJian Shen #define HCLGEVF_RING_TX_PRIORITY_REG 0x8004C 691600c3e5SJian Shen #define HCLGEVF_RING_TX_TC_REG 0x80050 701600c3e5SJian Shen #define HCLGEVF_RING_TX_MERGE_EN_REG 0x80054 711600c3e5SJian Shen #define HCLGEVF_RING_TX_TAIL_REG 0x80058 721600c3e5SJian Shen #define HCLGEVF_RING_TX_HEAD_REG 0x8005C 731600c3e5SJian Shen #define HCLGEVF_RING_TX_FBD_NUM_REG 0x80060 741600c3e5SJian Shen #define HCLGEVF_RING_TX_OFFSET_REG 0x80064 751600c3e5SJian Shen #define HCLGEVF_RING_TX_EBD_NUM_REG 0x80068 761600c3e5SJian Shen #define HCLGEVF_RING_TX_EBD_OFFSET_REG 0x80070 771600c3e5SJian Shen #define HCLGEVF_RING_TX_BD_ERR_REG 0x80074 781600c3e5SJian Shen #define HCLGEVF_RING_EN_REG 0x80090 791600c3e5SJian Shen 801600c3e5SJian Shen /* bar registers for tqp interrupt */ 811600c3e5SJian Shen #define HCLGEVF_TQP_INTR_CTRL_REG 0x20000 821600c3e5SJian Shen #define HCLGEVF_TQP_INTR_GL0_REG 0x20100 831600c3e5SJian Shen #define HCLGEVF_TQP_INTR_GL1_REG 0x20200 841600c3e5SJian Shen #define HCLGEVF_TQP_INTR_GL2_REG 0x20300 851600c3e5SJian Shen #define HCLGEVF_TQP_INTR_RL_REG 0x20900 861600c3e5SJian Shen 87e2cb1decSSalil Mehta /* Vector0 interrupt CMDQ event source register(RW) */ 88e2cb1decSSalil Mehta #define HCLGEVF_VECTOR0_CMDQ_SRC_REG 0x27100 8913050921SHuazhong Tan /* Vector0 interrupt CMDQ event status register(RO) */ 909cee2e8dSHuazhong Tan #define HCLGEVF_VECTOR0_CMDQ_STATE_REG 0x27104 91e2cb1decSSalil Mehta /* CMDQ register bits for RX event(=MBX event) */ 92e2cb1decSSalil Mehta #define HCLGEVF_VECTOR0_RX_CMDQ_INT_B 1 93b90fcc5bSHuazhong Tan /* RST register bits for RESET event */ 94b90fcc5bSHuazhong Tan #define HCLGEVF_VECTOR0_RST_INT_B 2 95e2cb1decSSalil Mehta 96e2cb1decSSalil Mehta #define HCLGEVF_TQP_RESET_TRY_TIMES 10 976988eb2aSSalil Mehta /* Reset related Registers */ 98aa5c4f17SHuazhong Tan #define HCLGEVF_RST_ING 0x20C00 99aa5c4f17SHuazhong Tan #define HCLGEVF_FUN_RST_ING_BIT BIT(0) 100aa5c4f17SHuazhong Tan #define HCLGEVF_GLOBAL_RST_ING_BIT BIT(5) 101aa5c4f17SHuazhong Tan #define HCLGEVF_CORE_RST_ING_BIT BIT(6) 102aa5c4f17SHuazhong Tan #define HCLGEVF_IMP_RST_ING_BIT BIT(7) 103aa5c4f17SHuazhong Tan #define HCLGEVF_RST_ING_BITS \ 104aa5c4f17SHuazhong Tan (HCLGEVF_FUN_RST_ING_BIT | HCLGEVF_GLOBAL_RST_ING_BIT | \ 105aa5c4f17SHuazhong Tan HCLGEVF_CORE_RST_ING_BIT | HCLGEVF_IMP_RST_ING_BIT) 106e2cb1decSSalil Mehta 10772e2fb07SHuazhong Tan #define HCLGEVF_VF_RST_ING 0x07008 10872e2fb07SHuazhong Tan #define HCLGEVF_VF_RST_ING_BIT BIT(16) 10972e2fb07SHuazhong Tan 110e2cb1decSSalil Mehta #define HCLGEVF_RSS_IND_TBL_SIZE 512 111e2cb1decSSalil Mehta #define HCLGEVF_RSS_SET_BITMAP_MSK 0xffff 112e2cb1decSSalil Mehta #define HCLGEVF_RSS_KEY_SIZE 40 113e2cb1decSSalil Mehta #define HCLGEVF_RSS_HASH_ALGO_TOEPLITZ 0 114e2cb1decSSalil Mehta #define HCLGEVF_RSS_HASH_ALGO_SIMPLE 1 115e2cb1decSSalil Mehta #define HCLGEVF_RSS_HASH_ALGO_SYMMETRIC 2 116e2cb1decSSalil Mehta #define HCLGEVF_RSS_HASH_ALGO_MASK 0xf 11787ce161eSGuangbin Huang 118d97b3072SJian Shen #define HCLGEVF_RSS_INPUT_TUPLE_OTHER GENMASK(3, 0) 119d97b3072SJian Shen #define HCLGEVF_RSS_INPUT_TUPLE_SCTP GENMASK(4, 0) 120d97b3072SJian Shen #define HCLGEVF_D_PORT_BIT BIT(0) 121d97b3072SJian Shen #define HCLGEVF_S_PORT_BIT BIT(1) 122d97b3072SJian Shen #define HCLGEVF_D_IP_BIT BIT(2) 123d97b3072SJian Shen #define HCLGEVF_S_IP_BIT BIT(3) 124d97b3072SJian Shen #define HCLGEVF_V_TAG_BIT BIT(4) 125ab6e32d2SJian Shen #define HCLGEVF_RSS_INPUT_TUPLE_SCTP_NO_PORT \ 126ab6e32d2SJian Shen (HCLGEVF_D_IP_BIT | HCLGEVF_S_IP_BIT | HCLGEVF_V_TAG_BIT) 127e2cb1decSSalil Mehta 128e070c8b9SYufeng Mo #define HCLGEVF_MAC_MAX_FRAME 9728 129e070c8b9SYufeng Mo 130eddd9860SGuojia Liao #define HCLGEVF_STATS_TIMER_INTERVAL 36U 131db01afebSliuzhongzhu 132b90fcc5bSHuazhong Tan enum hclgevf_evt_cause { 133b90fcc5bSHuazhong Tan HCLGEVF_VECTOR0_EVENT_RST, 134b90fcc5bSHuazhong Tan HCLGEVF_VECTOR0_EVENT_MBX, 135b90fcc5bSHuazhong Tan HCLGEVF_VECTOR0_EVENT_OTHER, 136b90fcc5bSHuazhong Tan }; 137b90fcc5bSHuazhong Tan 138e2cb1decSSalil Mehta /* states of hclgevf device & tasks */ 139e2cb1decSSalil Mehta enum hclgevf_states { 140e2cb1decSSalil Mehta /* device states */ 141e2cb1decSSalil Mehta HCLGEVF_STATE_DOWN, 142e2cb1decSSalil Mehta HCLGEVF_STATE_DISABLED, 143862d969aSHuazhong Tan HCLGEVF_STATE_IRQ_INITED, 144acfc3d55SHuazhong Tan HCLGEVF_STATE_REMOVING, 14525d1817cSHuazhong Tan HCLGEVF_STATE_NIC_REGISTERED, 146fe735c84SHuazhong Tan HCLGEVF_STATE_ROCE_REGISTERED, 147e2cb1decSSalil Mehta /* task states */ 14835a1e503SSalil Mehta HCLGEVF_STATE_RST_SERVICE_SCHED, 14935a1e503SSalil Mehta HCLGEVF_STATE_RST_HANDLING, 150e2cb1decSSalil Mehta HCLGEVF_STATE_MBX_SERVICE_SCHED, 151e2cb1decSSalil Mehta HCLGEVF_STATE_MBX_HANDLING, 152ef5f8e50SHuazhong Tan HCLGEVF_STATE_CMD_DISABLE, 153ff200099SYunsheng Lin HCLGEVF_STATE_LINK_UPDATING, 154c631c696SJian Shen HCLGEVF_STATE_PROMISC_CHANGED, 155d5432455SGuojia Liao HCLGEVF_STATE_RST_FAIL, 15601305e16SGuangbin Huang HCLGEVF_STATE_PF_PUSH_LINK_STATUS, 157e2cb1decSSalil Mehta }; 158e2cb1decSSalil Mehta 159e2cb1decSSalil Mehta struct hclgevf_mac { 160c136b884SPeng Li u8 media_type; 16188d10bd6SJian Shen u8 module_type; 162e2cb1decSSalil Mehta u8 mac_addr[ETH_ALEN]; 163e2cb1decSSalil Mehta int link; 1644a152de9SFuyun Liang u8 duplex; 1654a152de9SFuyun Liang u32 speed; 1669194d18bSliuzhongzhu u64 supported; 1679194d18bSliuzhongzhu u64 advertising; 168e2cb1decSSalil Mehta }; 169e2cb1decSSalil Mehta 170e2cb1decSSalil Mehta struct hclgevf_hw { 171e2cb1decSSalil Mehta void __iomem *io_base; 17230ae7f8aSHuazhong Tan void __iomem *mem_base; 173e2cb1decSSalil Mehta int num_vec; 174e2cb1decSSalil Mehta struct hclgevf_cmq cmq; 175e2cb1decSSalil Mehta struct hclgevf_mac mac; 176e2cb1decSSalil Mehta void *hdev; /* hchgevf device it is part of */ 177e2cb1decSSalil Mehta }; 178e2cb1decSSalil Mehta 179e2cb1decSSalil Mehta /* TQP stats */ 180e2cb1decSSalil Mehta struct hlcgevf_tqp_stats { 181e2cb1decSSalil Mehta /* query_tqp_tx_queue_statistics, opcode id: 0x0B03 */ 182e2cb1decSSalil Mehta u64 rcb_tx_ring_pktnum_rcd; /* 32bit */ 183e2cb1decSSalil Mehta /* query_tqp_rx_queue_statistics, opcode id: 0x0B13 */ 184e2cb1decSSalil Mehta u64 rcb_rx_ring_pktnum_rcd; /* 32bit */ 185e2cb1decSSalil Mehta }; 186e2cb1decSSalil Mehta 187e2cb1decSSalil Mehta struct hclgevf_tqp { 188e2cb1decSSalil Mehta struct device *dev; /* device for DMA mapping */ 189e2cb1decSSalil Mehta struct hnae3_queue q; 190e2cb1decSSalil Mehta struct hlcgevf_tqp_stats tqp_stats; 191e2cb1decSSalil Mehta u16 index; /* global index in a NIC controller */ 192e2cb1decSSalil Mehta 193e2cb1decSSalil Mehta bool alloced; 194e2cb1decSSalil Mehta }; 195e2cb1decSSalil Mehta 196e2cb1decSSalil Mehta struct hclgevf_cfg { 197e2cb1decSSalil Mehta u8 tc_num; 198e2cb1decSSalil Mehta u16 tqp_desc_num; 199e2cb1decSSalil Mehta u16 rx_buf_len; 200e2cb1decSSalil Mehta u8 phy_addr; 201e2cb1decSSalil Mehta u8 media_type; 202e2cb1decSSalil Mehta u8 mac_addr[ETH_ALEN]; 203e2cb1decSSalil Mehta u32 numa_node_map; 204e2cb1decSSalil Mehta }; 205e2cb1decSSalil Mehta 206d97b3072SJian Shen struct hclgevf_rss_tuple_cfg { 207d97b3072SJian Shen u8 ipv4_tcp_en; 208d97b3072SJian Shen u8 ipv4_udp_en; 209d97b3072SJian Shen u8 ipv4_sctp_en; 210d97b3072SJian Shen u8 ipv4_fragment_en; 211d97b3072SJian Shen u8 ipv6_tcp_en; 212d97b3072SJian Shen u8 ipv6_udp_en; 213d97b3072SJian Shen u8 ipv6_sctp_en; 214d97b3072SJian Shen u8 ipv6_fragment_en; 215d97b3072SJian Shen }; 216d97b3072SJian Shen 217e2cb1decSSalil Mehta struct hclgevf_rss_cfg { 218e2cb1decSSalil Mehta u8 rss_hash_key[HCLGEVF_RSS_KEY_SIZE]; /* user configured hash keys */ 219e2cb1decSSalil Mehta u32 hash_algo; 220e2cb1decSSalil Mehta u32 rss_size; 221e2cb1decSSalil Mehta u8 hw_tc_map; 22287ce161eSGuangbin Huang /* shadow table */ 22387ce161eSGuangbin Huang u8 *rss_indirection_tbl; 224d97b3072SJian Shen struct hclgevf_rss_tuple_cfg rss_tuple_sets; 225e2cb1decSSalil Mehta }; 226e2cb1decSSalil Mehta 227e2cb1decSSalil Mehta struct hclgevf_misc_vector { 228e2cb1decSSalil Mehta u8 __iomem *addr; 229e2cb1decSSalil Mehta int vector_irq; 230f97c4d82SYonglong Liu char name[HNAE3_INT_NAME_LEN]; 231e2cb1decSSalil Mehta }; 232e2cb1decSSalil Mehta 233c88a6e7dSHuazhong Tan struct hclgevf_rst_stats { 234c88a6e7dSHuazhong Tan u32 rst_cnt; /* the number of reset */ 235c88a6e7dSHuazhong Tan u32 vf_func_rst_cnt; /* the number of VF function reset */ 236c88a6e7dSHuazhong Tan u32 flr_rst_cnt; /* the number of FLR */ 237c88a6e7dSHuazhong Tan u32 vf_rst_cnt; /* the number of VF reset */ 238c88a6e7dSHuazhong Tan u32 rst_done_cnt; /* the number of reset completed */ 239c88a6e7dSHuazhong Tan u32 hw_rst_done_cnt; /* the number of HW reset completed */ 240bbe6540eSHuazhong Tan u32 rst_fail_cnt; /* the number of VF reset fail */ 241c88a6e7dSHuazhong Tan }; 242c88a6e7dSHuazhong Tan 243ee4bcd3bSJian Shen enum HCLGEVF_MAC_ADDR_TYPE { 244ee4bcd3bSJian Shen HCLGEVF_MAC_ADDR_UC, 245ee4bcd3bSJian Shen HCLGEVF_MAC_ADDR_MC 246ee4bcd3bSJian Shen }; 247ee4bcd3bSJian Shen 248ee4bcd3bSJian Shen enum HCLGEVF_MAC_NODE_STATE { 249ee4bcd3bSJian Shen HCLGEVF_MAC_TO_ADD, 250ee4bcd3bSJian Shen HCLGEVF_MAC_TO_DEL, 251ee4bcd3bSJian Shen HCLGEVF_MAC_ACTIVE 252ee4bcd3bSJian Shen }; 253ee4bcd3bSJian Shen 254ee4bcd3bSJian Shen struct hclgevf_mac_addr_node { 255ee4bcd3bSJian Shen struct list_head node; 256ee4bcd3bSJian Shen enum HCLGEVF_MAC_NODE_STATE state; 257ee4bcd3bSJian Shen u8 mac_addr[ETH_ALEN]; 258ee4bcd3bSJian Shen }; 259ee4bcd3bSJian Shen 260ee4bcd3bSJian Shen struct hclgevf_mac_table_cfg { 261ee4bcd3bSJian Shen spinlock_t mac_list_lock; /* protect mac address need to add/detele */ 262ee4bcd3bSJian Shen struct list_head uc_mac_list; 263ee4bcd3bSJian Shen struct list_head mc_mac_list; 264ee4bcd3bSJian Shen }; 265ee4bcd3bSJian Shen 266e2cb1decSSalil Mehta struct hclgevf_dev { 267e2cb1decSSalil Mehta struct pci_dev *pdev; 268e2cb1decSSalil Mehta struct hnae3_ae_dev *ae_dev; 269e2cb1decSSalil Mehta struct hclgevf_hw hw; 270e2cb1decSSalil Mehta struct hclgevf_misc_vector misc_vector; 271e2cb1decSSalil Mehta struct hclgevf_rss_cfg rss_cfg; 272e2cb1decSSalil Mehta unsigned long state; 2736ff3cf07SHuazhong Tan unsigned long flr_state; 274720bd583SHuazhong Tan unsigned long default_reset_request; 2750742ed7cSHuazhong Tan unsigned long last_reset_time; 2760742ed7cSHuazhong Tan enum hnae3_reset_type reset_level; 277dea846e8SHuazhong Tan unsigned long reset_pending; 278dea846e8SHuazhong Tan enum hnae3_reset_type reset_type; 279e2cb1decSSalil Mehta 280436667d2SSalil Mehta #define HCLGEVF_RESET_REQUESTED 0 281436667d2SSalil Mehta #define HCLGEVF_RESET_PENDING 1 282436667d2SSalil Mehta unsigned long reset_state; /* requested, pending */ 283c88a6e7dSHuazhong Tan struct hclgevf_rst_stats rst_stats; 284436667d2SSalil Mehta u32 reset_attempts; 285f28368bbSHuazhong Tan struct semaphore reset_sem; /* protect reset process */ 286436667d2SSalil Mehta 287e2cb1decSSalil Mehta u32 fw_version; 28832e6d104SJian Shen u16 mbx_api_version; 289ec4d9392SHuazhong Tan u16 num_tqps; /* num task queue pairs of this VF */ 290e2cb1decSSalil Mehta 291e2cb1decSSalil Mehta u16 alloc_rss_size; /* allocated RSS task queue */ 292e2cb1decSSalil Mehta u16 rss_size_max; /* HW defined max RSS task queue */ 293e2cb1decSSalil Mehta 294e2cb1decSSalil Mehta u16 num_alloc_vport; /* num vports this driver supports */ 295e2cb1decSSalil Mehta u32 numa_node_mask; 296e2cb1decSSalil Mehta u16 rx_buf_len; 297c0425944SPeng Li u16 num_tx_desc; /* desc num of per tx queue */ 298c0425944SPeng Li u16 num_rx_desc; /* desc num of per rx queue */ 299e2cb1decSSalil Mehta u8 hw_tc_map; 3008e6de441SHuazhong Tan u8 has_pf_mac; 301e2cb1decSSalil Mehta 302e2cb1decSSalil Mehta u16 num_msi; 303e2cb1decSSalil Mehta u16 num_msi_left; 304e2cb1decSSalil Mehta u16 num_msi_used; 305580a05f9SYonglong Liu u16 num_nic_msix; /* Num of nic vectors for this VF */ 30607acf909SJian Shen u16 num_roce_msix; /* Num of roce vectors for this VF */ 30707acf909SJian Shen u16 roce_base_msix_offset; 30807acf909SJian Shen int roce_base_vector; 309e2cb1decSSalil Mehta u32 base_msi_vector; 310e2cb1decSSalil Mehta u16 *vector_status; 311e2cb1decSSalil Mehta int *vector_irq; 312e2cb1decSSalil Mehta 313*3462207dSYufeng Mo bool gro_en; 314*3462207dSYufeng Mo 315fe4144d4SJian Shen unsigned long vlan_del_fail_bmap[BITS_TO_LONGS(VLAN_N_VID)]; 316fe4144d4SJian Shen 317ee4bcd3bSJian Shen struct hclgevf_mac_table_cfg mac_table; 318ee4bcd3bSJian Shen 31907a0556aSSalil Mehta bool mbx_event_pending; 320e2cb1decSSalil Mehta struct hclgevf_mbx_resp_status mbx_resp; /* mailbox response */ 32107a0556aSSalil Mehta struct hclgevf_mbx_arq_ring arq; /* mailbox async rx queue */ 322e2cb1decSSalil Mehta 323b3c3fe8eSYunsheng Lin struct delayed_work service_task; 324e2cb1decSSalil Mehta 325e2cb1decSSalil Mehta struct hclgevf_tqp *htqp; 326e2cb1decSSalil Mehta 327e2cb1decSSalil Mehta struct hnae3_handle nic; 328e2cb1decSSalil Mehta struct hnae3_handle roce; 329e2cb1decSSalil Mehta 330e2cb1decSSalil Mehta struct hnae3_client *nic_client; 331e2cb1decSSalil Mehta struct hnae3_client *roce_client; 332e2cb1decSSalil Mehta u32 flag; 333ff200099SYunsheng Lin unsigned long serv_processed_cnt; 334ff200099SYunsheng Lin unsigned long last_serv_processed; 335e2cb1decSSalil Mehta }; 336e2cb1decSSalil Mehta 337ef5f8e50SHuazhong Tan static inline bool hclgevf_is_reset_pending(struct hclgevf_dev *hdev) 338ef5f8e50SHuazhong Tan { 339ef5f8e50SHuazhong Tan return !!hdev->reset_pending; 340ef5f8e50SHuazhong Tan } 341ef5f8e50SHuazhong Tan 342d3410018SYufeng Mo int hclgevf_send_mbx_msg(struct hclgevf_dev *hdev, 343d3410018SYufeng Mo struct hclge_vf_to_pf_msg *send_msg, bool need_resp, 344e2cb1decSSalil Mehta u8 *resp_data, u16 resp_len); 345e2cb1decSSalil Mehta void hclgevf_mbx_handler(struct hclgevf_dev *hdev); 34607a0556aSSalil Mehta void hclgevf_mbx_async_handler(struct hclgevf_dev *hdev); 34707a0556aSSalil Mehta 348e2cb1decSSalil Mehta void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state); 3494a152de9SFuyun Liang void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed, 3504a152de9SFuyun Liang u8 duplex); 35135a1e503SSalil Mehta void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev); 35207a0556aSSalil Mehta void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev); 35392f11ea1SJian Shen void hclgevf_update_port_base_vlan_info(struct hclgevf_dev *hdev, u16 state, 35492f11ea1SJian Shen u8 *port_base_vlan_info, u8 data_size); 355e2cb1decSSalil Mehta #endif 356