1e2cb1decSSalil Mehta /* SPDX-License-Identifier: GPL-2.0+ */ 2e2cb1decSSalil Mehta /* Copyright (c) 2016-2017 Hisilicon Limited. */ 3e2cb1decSSalil Mehta 4e2cb1decSSalil Mehta #ifndef __HCLGEVF_MAIN_H 5e2cb1decSSalil Mehta #define __HCLGEVF_MAIN_H 6e2cb1decSSalil Mehta #include <linux/fs.h> 7e2cb1decSSalil Mehta #include <linux/types.h> 8e2cb1decSSalil Mehta #include "hclge_mbx.h" 9e2cb1decSSalil Mehta #include "hclgevf_cmd.h" 10e2cb1decSSalil Mehta #include "hnae3.h" 11e2cb1decSSalil Mehta 123c7624d8SXi Wang #define HCLGEVF_MOD_VERSION "1.0" 13e2cb1decSSalil Mehta #define HCLGEVF_DRIVER_NAME "hclgevf" 14e2cb1decSSalil Mehta 15e2cb1decSSalil Mehta #define HCLGEVF_MISC_VECTOR_NUM 0 16e2cb1decSSalil Mehta 17e2cb1decSSalil Mehta #define HCLGEVF_INVALID_VPORT 0xffff 18e2cb1decSSalil Mehta 19e2cb1decSSalil Mehta /* This number in actual depends upon the total number of VFs 20e2cb1decSSalil Mehta * created by physical function. But the maximum number of 21e2cb1decSSalil Mehta * possible vector-per-VF is {VFn(1-32), VECTn(32 + 1)}. 22e2cb1decSSalil Mehta */ 23e2cb1decSSalil Mehta #define HCLGEVF_MAX_VF_VECTOR_NUM (32 + 1) 24e2cb1decSSalil Mehta 25e2cb1decSSalil Mehta #define HCLGEVF_VECTOR_REG_BASE 0x20000 26e2cb1decSSalil Mehta #define HCLGEVF_MISC_VECTOR_REG_BASE 0x20400 27e2cb1decSSalil Mehta #define HCLGEVF_VECTOR_REG_OFFSET 0x4 28e2cb1decSSalil Mehta #define HCLGEVF_VECTOR_VF_OFFSET 0x100000 29e2cb1decSSalil Mehta 301600c3e5SJian Shen /* bar registers for cmdq */ 311600c3e5SJian Shen #define HCLGEVF_CMDQ_TX_ADDR_L_REG 0x27000 321600c3e5SJian Shen #define HCLGEVF_CMDQ_TX_ADDR_H_REG 0x27004 331600c3e5SJian Shen #define HCLGEVF_CMDQ_TX_DEPTH_REG 0x27008 341600c3e5SJian Shen #define HCLGEVF_CMDQ_TX_TAIL_REG 0x27010 351600c3e5SJian Shen #define HCLGEVF_CMDQ_TX_HEAD_REG 0x27014 361600c3e5SJian Shen #define HCLGEVF_CMDQ_RX_ADDR_L_REG 0x27018 371600c3e5SJian Shen #define HCLGEVF_CMDQ_RX_ADDR_H_REG 0x2701C 381600c3e5SJian Shen #define HCLGEVF_CMDQ_RX_DEPTH_REG 0x27020 391600c3e5SJian Shen #define HCLGEVF_CMDQ_RX_TAIL_REG 0x27024 401600c3e5SJian Shen #define HCLGEVF_CMDQ_RX_HEAD_REG 0x27028 411600c3e5SJian Shen #define HCLGEVF_CMDQ_INTR_SRC_REG 0x27100 421600c3e5SJian Shen #define HCLGEVF_CMDQ_INTR_STS_REG 0x27104 431600c3e5SJian Shen #define HCLGEVF_CMDQ_INTR_EN_REG 0x27108 441600c3e5SJian Shen #define HCLGEVF_CMDQ_INTR_GEN_REG 0x2710C 451600c3e5SJian Shen 461600c3e5SJian Shen /* bar registers for common func */ 471600c3e5SJian Shen #define HCLGEVF_GRO_EN_REG 0x28000 481600c3e5SJian Shen 491600c3e5SJian Shen /* bar registers for rcb */ 501600c3e5SJian Shen #define HCLGEVF_RING_RX_ADDR_L_REG 0x80000 511600c3e5SJian Shen #define HCLGEVF_RING_RX_ADDR_H_REG 0x80004 521600c3e5SJian Shen #define HCLGEVF_RING_RX_BD_NUM_REG 0x80008 531600c3e5SJian Shen #define HCLGEVF_RING_RX_BD_LENGTH_REG 0x8000C 541600c3e5SJian Shen #define HCLGEVF_RING_RX_MERGE_EN_REG 0x80014 551600c3e5SJian Shen #define HCLGEVF_RING_RX_TAIL_REG 0x80018 561600c3e5SJian Shen #define HCLGEVF_RING_RX_HEAD_REG 0x8001C 571600c3e5SJian Shen #define HCLGEVF_RING_RX_FBD_NUM_REG 0x80020 581600c3e5SJian Shen #define HCLGEVF_RING_RX_OFFSET_REG 0x80024 591600c3e5SJian Shen #define HCLGEVF_RING_RX_FBD_OFFSET_REG 0x80028 601600c3e5SJian Shen #define HCLGEVF_RING_RX_STASH_REG 0x80030 611600c3e5SJian Shen #define HCLGEVF_RING_RX_BD_ERR_REG 0x80034 621600c3e5SJian Shen #define HCLGEVF_RING_TX_ADDR_L_REG 0x80040 631600c3e5SJian Shen #define HCLGEVF_RING_TX_ADDR_H_REG 0x80044 641600c3e5SJian Shen #define HCLGEVF_RING_TX_BD_NUM_REG 0x80048 651600c3e5SJian Shen #define HCLGEVF_RING_TX_PRIORITY_REG 0x8004C 661600c3e5SJian Shen #define HCLGEVF_RING_TX_TC_REG 0x80050 671600c3e5SJian Shen #define HCLGEVF_RING_TX_MERGE_EN_REG 0x80054 681600c3e5SJian Shen #define HCLGEVF_RING_TX_TAIL_REG 0x80058 691600c3e5SJian Shen #define HCLGEVF_RING_TX_HEAD_REG 0x8005C 701600c3e5SJian Shen #define HCLGEVF_RING_TX_FBD_NUM_REG 0x80060 711600c3e5SJian Shen #define HCLGEVF_RING_TX_OFFSET_REG 0x80064 721600c3e5SJian Shen #define HCLGEVF_RING_TX_EBD_NUM_REG 0x80068 731600c3e5SJian Shen #define HCLGEVF_RING_TX_EBD_OFFSET_REG 0x80070 741600c3e5SJian Shen #define HCLGEVF_RING_TX_BD_ERR_REG 0x80074 751600c3e5SJian Shen #define HCLGEVF_RING_EN_REG 0x80090 761600c3e5SJian Shen 771600c3e5SJian Shen /* bar registers for tqp interrupt */ 781600c3e5SJian Shen #define HCLGEVF_TQP_INTR_CTRL_REG 0x20000 791600c3e5SJian Shen #define HCLGEVF_TQP_INTR_GL0_REG 0x20100 801600c3e5SJian Shen #define HCLGEVF_TQP_INTR_GL1_REG 0x20200 811600c3e5SJian Shen #define HCLGEVF_TQP_INTR_GL2_REG 0x20300 821600c3e5SJian Shen #define HCLGEVF_TQP_INTR_RL_REG 0x20900 831600c3e5SJian Shen 84e2cb1decSSalil Mehta /* Vector0 interrupt CMDQ event source register(RW) */ 85e2cb1decSSalil Mehta #define HCLGEVF_VECTOR0_CMDQ_SRC_REG 0x27100 86e2cb1decSSalil Mehta /* CMDQ register bits for RX event(=MBX event) */ 87e2cb1decSSalil Mehta #define HCLGEVF_VECTOR0_RX_CMDQ_INT_B 1 88b90fcc5bSHuazhong Tan /* RST register bits for RESET event */ 89b90fcc5bSHuazhong Tan #define HCLGEVF_VECTOR0_RST_INT_B 2 90e2cb1decSSalil Mehta 91e2cb1decSSalil Mehta #define HCLGEVF_TQP_RESET_TRY_TIMES 10 926988eb2aSSalil Mehta /* Reset related Registers */ 93aa5c4f17SHuazhong Tan #define HCLGEVF_RST_ING 0x20C00 94aa5c4f17SHuazhong Tan #define HCLGEVF_FUN_RST_ING_BIT BIT(0) 95aa5c4f17SHuazhong Tan #define HCLGEVF_GLOBAL_RST_ING_BIT BIT(5) 96aa5c4f17SHuazhong Tan #define HCLGEVF_CORE_RST_ING_BIT BIT(6) 97aa5c4f17SHuazhong Tan #define HCLGEVF_IMP_RST_ING_BIT BIT(7) 98aa5c4f17SHuazhong Tan #define HCLGEVF_RST_ING_BITS \ 99aa5c4f17SHuazhong Tan (HCLGEVF_FUN_RST_ING_BIT | HCLGEVF_GLOBAL_RST_ING_BIT | \ 100aa5c4f17SHuazhong Tan HCLGEVF_CORE_RST_ING_BIT | HCLGEVF_IMP_RST_ING_BIT) 101e2cb1decSSalil Mehta 102e2cb1decSSalil Mehta #define HCLGEVF_RSS_IND_TBL_SIZE 512 103e2cb1decSSalil Mehta #define HCLGEVF_RSS_SET_BITMAP_MSK 0xffff 104e2cb1decSSalil Mehta #define HCLGEVF_RSS_KEY_SIZE 40 105e2cb1decSSalil Mehta #define HCLGEVF_RSS_HASH_ALGO_TOEPLITZ 0 106e2cb1decSSalil Mehta #define HCLGEVF_RSS_HASH_ALGO_SIMPLE 1 107e2cb1decSSalil Mehta #define HCLGEVF_RSS_HASH_ALGO_SYMMETRIC 2 108e2cb1decSSalil Mehta #define HCLGEVF_RSS_HASH_ALGO_MASK 0xf 109e2cb1decSSalil Mehta #define HCLGEVF_RSS_CFG_TBL_NUM \ 110e2cb1decSSalil Mehta (HCLGEVF_RSS_IND_TBL_SIZE / HCLGEVF_RSS_CFG_TBL_SIZE) 111d97b3072SJian Shen #define HCLGEVF_RSS_INPUT_TUPLE_OTHER GENMASK(3, 0) 112d97b3072SJian Shen #define HCLGEVF_RSS_INPUT_TUPLE_SCTP GENMASK(4, 0) 113d97b3072SJian Shen #define HCLGEVF_D_PORT_BIT BIT(0) 114d97b3072SJian Shen #define HCLGEVF_S_PORT_BIT BIT(1) 115d97b3072SJian Shen #define HCLGEVF_D_IP_BIT BIT(2) 116d97b3072SJian Shen #define HCLGEVF_S_IP_BIT BIT(3) 117d97b3072SJian Shen #define HCLGEVF_V_TAG_BIT BIT(4) 118e2cb1decSSalil Mehta 119b90fcc5bSHuazhong Tan enum hclgevf_evt_cause { 120b90fcc5bSHuazhong Tan HCLGEVF_VECTOR0_EVENT_RST, 121b90fcc5bSHuazhong Tan HCLGEVF_VECTOR0_EVENT_MBX, 122b90fcc5bSHuazhong Tan HCLGEVF_VECTOR0_EVENT_OTHER, 123b90fcc5bSHuazhong Tan }; 124b90fcc5bSHuazhong Tan 125e2cb1decSSalil Mehta /* states of hclgevf device & tasks */ 126e2cb1decSSalil Mehta enum hclgevf_states { 127e2cb1decSSalil Mehta /* device states */ 128e2cb1decSSalil Mehta HCLGEVF_STATE_DOWN, 129e2cb1decSSalil Mehta HCLGEVF_STATE_DISABLED, 130862d969aSHuazhong Tan HCLGEVF_STATE_IRQ_INITED, 131e2cb1decSSalil Mehta /* task states */ 132e2cb1decSSalil Mehta HCLGEVF_STATE_SERVICE_SCHED, 13335a1e503SSalil Mehta HCLGEVF_STATE_RST_SERVICE_SCHED, 13435a1e503SSalil Mehta HCLGEVF_STATE_RST_HANDLING, 135e2cb1decSSalil Mehta HCLGEVF_STATE_MBX_SERVICE_SCHED, 136e2cb1decSSalil Mehta HCLGEVF_STATE_MBX_HANDLING, 137ef5f8e50SHuazhong Tan HCLGEVF_STATE_CMD_DISABLE, 138e2cb1decSSalil Mehta }; 139e2cb1decSSalil Mehta 140e2cb1decSSalil Mehta #define HCLGEVF_MPF_ENBALE 1 141e2cb1decSSalil Mehta 142e2cb1decSSalil Mehta struct hclgevf_mac { 143c136b884SPeng Li u8 media_type; 144e2cb1decSSalil Mehta u8 mac_addr[ETH_ALEN]; 145e2cb1decSSalil Mehta int link; 1464a152de9SFuyun Liang u8 duplex; 1474a152de9SFuyun Liang u32 speed; 148e2cb1decSSalil Mehta }; 149e2cb1decSSalil Mehta 150e2cb1decSSalil Mehta struct hclgevf_hw { 151e2cb1decSSalil Mehta void __iomem *io_base; 152e2cb1decSSalil Mehta int num_vec; 153e2cb1decSSalil Mehta struct hclgevf_cmq cmq; 154e2cb1decSSalil Mehta struct hclgevf_mac mac; 155e2cb1decSSalil Mehta void *hdev; /* hchgevf device it is part of */ 156e2cb1decSSalil Mehta }; 157e2cb1decSSalil Mehta 158e2cb1decSSalil Mehta /* TQP stats */ 159e2cb1decSSalil Mehta struct hlcgevf_tqp_stats { 160e2cb1decSSalil Mehta /* query_tqp_tx_queue_statistics ,opcode id: 0x0B03 */ 161e2cb1decSSalil Mehta u64 rcb_tx_ring_pktnum_rcd; /* 32bit */ 162e2cb1decSSalil Mehta /* query_tqp_rx_queue_statistics ,opcode id: 0x0B13 */ 163e2cb1decSSalil Mehta u64 rcb_rx_ring_pktnum_rcd; /* 32bit */ 164e2cb1decSSalil Mehta }; 165e2cb1decSSalil Mehta 166e2cb1decSSalil Mehta struct hclgevf_tqp { 167e2cb1decSSalil Mehta struct device *dev; /* device for DMA mapping */ 168e2cb1decSSalil Mehta struct hnae3_queue q; 169e2cb1decSSalil Mehta struct hlcgevf_tqp_stats tqp_stats; 170e2cb1decSSalil Mehta u16 index; /* global index in a NIC controller */ 171e2cb1decSSalil Mehta 172e2cb1decSSalil Mehta bool alloced; 173e2cb1decSSalil Mehta }; 174e2cb1decSSalil Mehta 175e2cb1decSSalil Mehta struct hclgevf_cfg { 176e2cb1decSSalil Mehta u8 vmdq_vport_num; 177e2cb1decSSalil Mehta u8 tc_num; 178e2cb1decSSalil Mehta u16 tqp_desc_num; 179e2cb1decSSalil Mehta u16 rx_buf_len; 180e2cb1decSSalil Mehta u8 phy_addr; 181e2cb1decSSalil Mehta u8 media_type; 182e2cb1decSSalil Mehta u8 mac_addr[ETH_ALEN]; 183e2cb1decSSalil Mehta u32 numa_node_map; 184e2cb1decSSalil Mehta }; 185e2cb1decSSalil Mehta 186d97b3072SJian Shen struct hclgevf_rss_tuple_cfg { 187d97b3072SJian Shen u8 ipv4_tcp_en; 188d97b3072SJian Shen u8 ipv4_udp_en; 189d97b3072SJian Shen u8 ipv4_sctp_en; 190d97b3072SJian Shen u8 ipv4_fragment_en; 191d97b3072SJian Shen u8 ipv6_tcp_en; 192d97b3072SJian Shen u8 ipv6_udp_en; 193d97b3072SJian Shen u8 ipv6_sctp_en; 194d97b3072SJian Shen u8 ipv6_fragment_en; 195d97b3072SJian Shen }; 196d97b3072SJian Shen 197e2cb1decSSalil Mehta struct hclgevf_rss_cfg { 198e2cb1decSSalil Mehta u8 rss_hash_key[HCLGEVF_RSS_KEY_SIZE]; /* user configured hash keys */ 199e2cb1decSSalil Mehta u32 hash_algo; 200e2cb1decSSalil Mehta u32 rss_size; 201e2cb1decSSalil Mehta u8 hw_tc_map; 202e2cb1decSSalil Mehta u8 rss_indirection_tbl[HCLGEVF_RSS_IND_TBL_SIZE]; /* shadow table */ 203d97b3072SJian Shen struct hclgevf_rss_tuple_cfg rss_tuple_sets; 204e2cb1decSSalil Mehta }; 205e2cb1decSSalil Mehta 206e2cb1decSSalil Mehta struct hclgevf_misc_vector { 207e2cb1decSSalil Mehta u8 __iomem *addr; 208e2cb1decSSalil Mehta int vector_irq; 209e2cb1decSSalil Mehta }; 210e2cb1decSSalil Mehta 211e2cb1decSSalil Mehta struct hclgevf_dev { 212e2cb1decSSalil Mehta struct pci_dev *pdev; 213e2cb1decSSalil Mehta struct hnae3_ae_dev *ae_dev; 214e2cb1decSSalil Mehta struct hclgevf_hw hw; 215e2cb1decSSalil Mehta struct hclgevf_misc_vector misc_vector; 216e2cb1decSSalil Mehta struct hclgevf_rss_cfg rss_cfg; 217e2cb1decSSalil Mehta unsigned long state; 2186ff3cf07SHuazhong Tan unsigned long flr_state; 219720bd583SHuazhong Tan unsigned long default_reset_request; 2200742ed7cSHuazhong Tan unsigned long last_reset_time; 2210742ed7cSHuazhong Tan enum hnae3_reset_type reset_level; 222dea846e8SHuazhong Tan unsigned long reset_pending; 223dea846e8SHuazhong Tan enum hnae3_reset_type reset_type; 224e2cb1decSSalil Mehta 225436667d2SSalil Mehta #define HCLGEVF_RESET_REQUESTED 0 226436667d2SSalil Mehta #define HCLGEVF_RESET_PENDING 1 227436667d2SSalil Mehta unsigned long reset_state; /* requested, pending */ 2284d60291bSHuazhong Tan unsigned long reset_count; /* the number of reset has been done */ 229436667d2SSalil Mehta u32 reset_attempts; 230436667d2SSalil Mehta 231e2cb1decSSalil Mehta u32 fw_version; 232e2cb1decSSalil Mehta u16 num_tqps; /* num task queue pairs of this PF */ 233e2cb1decSSalil Mehta 234e2cb1decSSalil Mehta u16 alloc_rss_size; /* allocated RSS task queue */ 235e2cb1decSSalil Mehta u16 rss_size_max; /* HW defined max RSS task queue */ 236e2cb1decSSalil Mehta 237e2cb1decSSalil Mehta u16 num_alloc_vport; /* num vports this driver supports */ 238e2cb1decSSalil Mehta u32 numa_node_mask; 239e2cb1decSSalil Mehta u16 rx_buf_len; 240e2cb1decSSalil Mehta u16 num_desc; 241e2cb1decSSalil Mehta u8 hw_tc_map; 242e2cb1decSSalil Mehta 243e2cb1decSSalil Mehta u16 num_msi; 244e2cb1decSSalil Mehta u16 num_msi_left; 245e2cb1decSSalil Mehta u16 num_msi_used; 24607acf909SJian Shen u16 num_roce_msix; /* Num of roce vectors for this VF */ 24707acf909SJian Shen u16 roce_base_msix_offset; 24807acf909SJian Shen int roce_base_vector; 249e2cb1decSSalil Mehta u32 base_msi_vector; 250e2cb1decSSalil Mehta u16 *vector_status; 251e2cb1decSSalil Mehta int *vector_irq; 252e2cb1decSSalil Mehta 25307a0556aSSalil Mehta bool mbx_event_pending; 254e2cb1decSSalil Mehta struct hclgevf_mbx_resp_status mbx_resp; /* mailbox response */ 25507a0556aSSalil Mehta struct hclgevf_mbx_arq_ring arq; /* mailbox async rx queue */ 256e2cb1decSSalil Mehta 257e2cb1decSSalil Mehta struct timer_list service_timer; 258a6d818e3SYunsheng Lin struct timer_list keep_alive_timer; 259e2cb1decSSalil Mehta struct work_struct service_task; 260a6d818e3SYunsheng Lin struct work_struct keep_alive_task; 26135a1e503SSalil Mehta struct work_struct rst_service_task; 262e2cb1decSSalil Mehta struct work_struct mbx_service_task; 263e2cb1decSSalil Mehta 264e2cb1decSSalil Mehta struct hclgevf_tqp *htqp; 265e2cb1decSSalil Mehta 266e2cb1decSSalil Mehta struct hnae3_handle nic; 267e2cb1decSSalil Mehta struct hnae3_handle roce; 268e2cb1decSSalil Mehta 269e2cb1decSSalil Mehta struct hnae3_client *nic_client; 270e2cb1decSSalil Mehta struct hnae3_client *roce_client; 271e2cb1decSSalil Mehta u32 flag; 272e2cb1decSSalil Mehta }; 273e2cb1decSSalil Mehta 274ef5f8e50SHuazhong Tan static inline bool hclgevf_is_reset_pending(struct hclgevf_dev *hdev) 275ef5f8e50SHuazhong Tan { 276ef5f8e50SHuazhong Tan return !!hdev->reset_pending; 277ef5f8e50SHuazhong Tan } 278ef5f8e50SHuazhong Tan 279e2cb1decSSalil Mehta int hclgevf_send_mbx_msg(struct hclgevf_dev *hdev, u16 code, u16 subcode, 280e2cb1decSSalil Mehta const u8 *msg_data, u8 msg_len, bool need_resp, 281e2cb1decSSalil Mehta u8 *resp_data, u16 resp_len); 282e2cb1decSSalil Mehta void hclgevf_mbx_handler(struct hclgevf_dev *hdev); 28307a0556aSSalil Mehta void hclgevf_mbx_async_handler(struct hclgevf_dev *hdev); 28407a0556aSSalil Mehta 285e2cb1decSSalil Mehta void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state); 2864a152de9SFuyun Liang void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed, 2874a152de9SFuyun Liang u8 duplex); 28835a1e503SSalil Mehta void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev); 28907a0556aSSalil Mehta void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev); 290e2cb1decSSalil Mehta #endif 291