1e2cb1decSSalil Mehta /* SPDX-License-Identifier: GPL-2.0+ */ 2e2cb1decSSalil Mehta /* Copyright (c) 2016-2017 Hisilicon Limited. */ 3e2cb1decSSalil Mehta 4e2cb1decSSalil Mehta #ifndef __HCLGEVF_MAIN_H 5e2cb1decSSalil Mehta #define __HCLGEVF_MAIN_H 6e2cb1decSSalil Mehta #include <linux/fs.h> 7fe4144d4SJian Shen #include <linux/if_vlan.h> 8e2cb1decSSalil Mehta #include <linux/types.h> 9e2cb1decSSalil Mehta #include "hclge_mbx.h" 10e2cb1decSSalil Mehta #include "hclgevf_cmd.h" 11e2cb1decSSalil Mehta #include "hnae3.h" 12e2cb1decSSalil Mehta 133c7624d8SXi Wang #define HCLGEVF_MOD_VERSION "1.0" 14e2cb1decSSalil Mehta #define HCLGEVF_DRIVER_NAME "hclgevf" 15e2cb1decSSalil Mehta 16b37ce587SYufeng Mo #define HCLGEVF_MAX_VLAN_ID 4095 17e2cb1decSSalil Mehta #define HCLGEVF_MISC_VECTOR_NUM 0 18e2cb1decSSalil Mehta 19e2cb1decSSalil Mehta #define HCLGEVF_INVALID_VPORT 0xffff 20b37ce587SYufeng Mo #define HCLGEVF_GENERAL_TASK_INTERVAL 5 21b37ce587SYufeng Mo #define HCLGEVF_KEEP_ALIVE_TASK_INTERVAL 2 22e2cb1decSSalil Mehta 23e2cb1decSSalil Mehta /* This number in actual depends upon the total number of VFs 24e2cb1decSSalil Mehta * created by physical function. But the maximum number of 25e2cb1decSSalil Mehta * possible vector-per-VF is {VFn(1-32), VECTn(32 + 1)}. 26e2cb1decSSalil Mehta */ 27e2cb1decSSalil Mehta #define HCLGEVF_MAX_VF_VECTOR_NUM (32 + 1) 28e2cb1decSSalil Mehta 29e2cb1decSSalil Mehta #define HCLGEVF_VECTOR_REG_BASE 0x20000 30e2cb1decSSalil Mehta #define HCLGEVF_MISC_VECTOR_REG_BASE 0x20400 31e2cb1decSSalil Mehta #define HCLGEVF_VECTOR_REG_OFFSET 0x4 32e2cb1decSSalil Mehta #define HCLGEVF_VECTOR_VF_OFFSET 0x100000 33e2cb1decSSalil Mehta 341600c3e5SJian Shen /* bar registers for cmdq */ 351600c3e5SJian Shen #define HCLGEVF_CMDQ_TX_ADDR_L_REG 0x27000 361600c3e5SJian Shen #define HCLGEVF_CMDQ_TX_ADDR_H_REG 0x27004 371600c3e5SJian Shen #define HCLGEVF_CMDQ_TX_DEPTH_REG 0x27008 381600c3e5SJian Shen #define HCLGEVF_CMDQ_TX_TAIL_REG 0x27010 391600c3e5SJian Shen #define HCLGEVF_CMDQ_TX_HEAD_REG 0x27014 401600c3e5SJian Shen #define HCLGEVF_CMDQ_RX_ADDR_L_REG 0x27018 411600c3e5SJian Shen #define HCLGEVF_CMDQ_RX_ADDR_H_REG 0x2701C 421600c3e5SJian Shen #define HCLGEVF_CMDQ_RX_DEPTH_REG 0x27020 431600c3e5SJian Shen #define HCLGEVF_CMDQ_RX_TAIL_REG 0x27024 441600c3e5SJian Shen #define HCLGEVF_CMDQ_RX_HEAD_REG 0x27028 451600c3e5SJian Shen #define HCLGEVF_CMDQ_INTR_SRC_REG 0x27100 461600c3e5SJian Shen #define HCLGEVF_CMDQ_INTR_STS_REG 0x27104 471600c3e5SJian Shen #define HCLGEVF_CMDQ_INTR_EN_REG 0x27108 481600c3e5SJian Shen #define HCLGEVF_CMDQ_INTR_GEN_REG 0x2710C 491600c3e5SJian Shen 501600c3e5SJian Shen /* bar registers for common func */ 511600c3e5SJian Shen #define HCLGEVF_GRO_EN_REG 0x28000 521600c3e5SJian Shen 531600c3e5SJian Shen /* bar registers for rcb */ 541600c3e5SJian Shen #define HCLGEVF_RING_RX_ADDR_L_REG 0x80000 551600c3e5SJian Shen #define HCLGEVF_RING_RX_ADDR_H_REG 0x80004 561600c3e5SJian Shen #define HCLGEVF_RING_RX_BD_NUM_REG 0x80008 571600c3e5SJian Shen #define HCLGEVF_RING_RX_BD_LENGTH_REG 0x8000C 581600c3e5SJian Shen #define HCLGEVF_RING_RX_MERGE_EN_REG 0x80014 591600c3e5SJian Shen #define HCLGEVF_RING_RX_TAIL_REG 0x80018 601600c3e5SJian Shen #define HCLGEVF_RING_RX_HEAD_REG 0x8001C 611600c3e5SJian Shen #define HCLGEVF_RING_RX_FBD_NUM_REG 0x80020 621600c3e5SJian Shen #define HCLGEVF_RING_RX_OFFSET_REG 0x80024 631600c3e5SJian Shen #define HCLGEVF_RING_RX_FBD_OFFSET_REG 0x80028 641600c3e5SJian Shen #define HCLGEVF_RING_RX_STASH_REG 0x80030 651600c3e5SJian Shen #define HCLGEVF_RING_RX_BD_ERR_REG 0x80034 661600c3e5SJian Shen #define HCLGEVF_RING_TX_ADDR_L_REG 0x80040 671600c3e5SJian Shen #define HCLGEVF_RING_TX_ADDR_H_REG 0x80044 681600c3e5SJian Shen #define HCLGEVF_RING_TX_BD_NUM_REG 0x80048 691600c3e5SJian Shen #define HCLGEVF_RING_TX_PRIORITY_REG 0x8004C 701600c3e5SJian Shen #define HCLGEVF_RING_TX_TC_REG 0x80050 711600c3e5SJian Shen #define HCLGEVF_RING_TX_MERGE_EN_REG 0x80054 721600c3e5SJian Shen #define HCLGEVF_RING_TX_TAIL_REG 0x80058 731600c3e5SJian Shen #define HCLGEVF_RING_TX_HEAD_REG 0x8005C 741600c3e5SJian Shen #define HCLGEVF_RING_TX_FBD_NUM_REG 0x80060 751600c3e5SJian Shen #define HCLGEVF_RING_TX_OFFSET_REG 0x80064 761600c3e5SJian Shen #define HCLGEVF_RING_TX_EBD_NUM_REG 0x80068 771600c3e5SJian Shen #define HCLGEVF_RING_TX_EBD_OFFSET_REG 0x80070 781600c3e5SJian Shen #define HCLGEVF_RING_TX_BD_ERR_REG 0x80074 791600c3e5SJian Shen #define HCLGEVF_RING_EN_REG 0x80090 801600c3e5SJian Shen 811600c3e5SJian Shen /* bar registers for tqp interrupt */ 821600c3e5SJian Shen #define HCLGEVF_TQP_INTR_CTRL_REG 0x20000 831600c3e5SJian Shen #define HCLGEVF_TQP_INTR_GL0_REG 0x20100 841600c3e5SJian Shen #define HCLGEVF_TQP_INTR_GL1_REG 0x20200 851600c3e5SJian Shen #define HCLGEVF_TQP_INTR_GL2_REG 0x20300 861600c3e5SJian Shen #define HCLGEVF_TQP_INTR_RL_REG 0x20900 871600c3e5SJian Shen 88e2cb1decSSalil Mehta /* Vector0 interrupt CMDQ event source register(RW) */ 89e2cb1decSSalil Mehta #define HCLGEVF_VECTOR0_CMDQ_SRC_REG 0x27100 9013050921SHuazhong Tan /* Vector0 interrupt CMDQ event status register(RO) */ 9113050921SHuazhong Tan #define HCLGEVF_VECTOR0_CMDQ_STAT_REG 0x27104 92e2cb1decSSalil Mehta /* CMDQ register bits for RX event(=MBX event) */ 93e2cb1decSSalil Mehta #define HCLGEVF_VECTOR0_RX_CMDQ_INT_B 1 94b90fcc5bSHuazhong Tan /* RST register bits for RESET event */ 95b90fcc5bSHuazhong Tan #define HCLGEVF_VECTOR0_RST_INT_B 2 96e2cb1decSSalil Mehta 97e2cb1decSSalil Mehta #define HCLGEVF_TQP_RESET_TRY_TIMES 10 986988eb2aSSalil Mehta /* Reset related Registers */ 99aa5c4f17SHuazhong Tan #define HCLGEVF_RST_ING 0x20C00 100aa5c4f17SHuazhong Tan #define HCLGEVF_FUN_RST_ING_BIT BIT(0) 101aa5c4f17SHuazhong Tan #define HCLGEVF_GLOBAL_RST_ING_BIT BIT(5) 102aa5c4f17SHuazhong Tan #define HCLGEVF_CORE_RST_ING_BIT BIT(6) 103aa5c4f17SHuazhong Tan #define HCLGEVF_IMP_RST_ING_BIT BIT(7) 104aa5c4f17SHuazhong Tan #define HCLGEVF_RST_ING_BITS \ 105aa5c4f17SHuazhong Tan (HCLGEVF_FUN_RST_ING_BIT | HCLGEVF_GLOBAL_RST_ING_BIT | \ 106aa5c4f17SHuazhong Tan HCLGEVF_CORE_RST_ING_BIT | HCLGEVF_IMP_RST_ING_BIT) 107e2cb1decSSalil Mehta 10872e2fb07SHuazhong Tan #define HCLGEVF_VF_RST_ING 0x07008 10972e2fb07SHuazhong Tan #define HCLGEVF_VF_RST_ING_BIT BIT(16) 11072e2fb07SHuazhong Tan 111e2cb1decSSalil Mehta #define HCLGEVF_RSS_IND_TBL_SIZE 512 112e2cb1decSSalil Mehta #define HCLGEVF_RSS_SET_BITMAP_MSK 0xffff 113e2cb1decSSalil Mehta #define HCLGEVF_RSS_KEY_SIZE 40 114e2cb1decSSalil Mehta #define HCLGEVF_RSS_HASH_ALGO_TOEPLITZ 0 115e2cb1decSSalil Mehta #define HCLGEVF_RSS_HASH_ALGO_SIMPLE 1 116e2cb1decSSalil Mehta #define HCLGEVF_RSS_HASH_ALGO_SYMMETRIC 2 117e2cb1decSSalil Mehta #define HCLGEVF_RSS_HASH_ALGO_MASK 0xf 118e2cb1decSSalil Mehta #define HCLGEVF_RSS_CFG_TBL_NUM \ 119e2cb1decSSalil Mehta (HCLGEVF_RSS_IND_TBL_SIZE / HCLGEVF_RSS_CFG_TBL_SIZE) 120d97b3072SJian Shen #define HCLGEVF_RSS_INPUT_TUPLE_OTHER GENMASK(3, 0) 121d97b3072SJian Shen #define HCLGEVF_RSS_INPUT_TUPLE_SCTP GENMASK(4, 0) 122d97b3072SJian Shen #define HCLGEVF_D_PORT_BIT BIT(0) 123d97b3072SJian Shen #define HCLGEVF_S_PORT_BIT BIT(1) 124d97b3072SJian Shen #define HCLGEVF_D_IP_BIT BIT(2) 125d97b3072SJian Shen #define HCLGEVF_S_IP_BIT BIT(3) 126d97b3072SJian Shen #define HCLGEVF_V_TAG_BIT BIT(4) 127e2cb1decSSalil Mehta 128db01afebSliuzhongzhu #define HCLGEVF_STATS_TIMER_INTERVAL (36) 129db01afebSliuzhongzhu 130b90fcc5bSHuazhong Tan enum hclgevf_evt_cause { 131b90fcc5bSHuazhong Tan HCLGEVF_VECTOR0_EVENT_RST, 132b90fcc5bSHuazhong Tan HCLGEVF_VECTOR0_EVENT_MBX, 133b90fcc5bSHuazhong Tan HCLGEVF_VECTOR0_EVENT_OTHER, 134b90fcc5bSHuazhong Tan }; 135b90fcc5bSHuazhong Tan 136e2cb1decSSalil Mehta /* states of hclgevf device & tasks */ 137e2cb1decSSalil Mehta enum hclgevf_states { 138e2cb1decSSalil Mehta /* device states */ 139e2cb1decSSalil Mehta HCLGEVF_STATE_DOWN, 140e2cb1decSSalil Mehta HCLGEVF_STATE_DISABLED, 141862d969aSHuazhong Tan HCLGEVF_STATE_IRQ_INITED, 142acfc3d55SHuazhong Tan HCLGEVF_STATE_REMOVING, 14325d1817cSHuazhong Tan HCLGEVF_STATE_NIC_REGISTERED, 144e2cb1decSSalil Mehta /* task states */ 145e2cb1decSSalil Mehta HCLGEVF_STATE_SERVICE_SCHED, 14635a1e503SSalil Mehta HCLGEVF_STATE_RST_SERVICE_SCHED, 14735a1e503SSalil Mehta HCLGEVF_STATE_RST_HANDLING, 148e2cb1decSSalil Mehta HCLGEVF_STATE_MBX_SERVICE_SCHED, 149e2cb1decSSalil Mehta HCLGEVF_STATE_MBX_HANDLING, 150ef5f8e50SHuazhong Tan HCLGEVF_STATE_CMD_DISABLE, 151e2cb1decSSalil Mehta }; 152e2cb1decSSalil Mehta 153e2cb1decSSalil Mehta #define HCLGEVF_MPF_ENBALE 1 154e2cb1decSSalil Mehta 155e2cb1decSSalil Mehta struct hclgevf_mac { 156c136b884SPeng Li u8 media_type; 15788d10bd6SJian Shen u8 module_type; 158e2cb1decSSalil Mehta u8 mac_addr[ETH_ALEN]; 159e2cb1decSSalil Mehta int link; 1604a152de9SFuyun Liang u8 duplex; 1614a152de9SFuyun Liang u32 speed; 1629194d18bSliuzhongzhu u64 supported; 1639194d18bSliuzhongzhu u64 advertising; 164e2cb1decSSalil Mehta }; 165e2cb1decSSalil Mehta 166e2cb1decSSalil Mehta struct hclgevf_hw { 167e2cb1decSSalil Mehta void __iomem *io_base; 168e2cb1decSSalil Mehta int num_vec; 169e2cb1decSSalil Mehta struct hclgevf_cmq cmq; 170e2cb1decSSalil Mehta struct hclgevf_mac mac; 171e2cb1decSSalil Mehta void *hdev; /* hchgevf device it is part of */ 172e2cb1decSSalil Mehta }; 173e2cb1decSSalil Mehta 174e2cb1decSSalil Mehta /* TQP stats */ 175e2cb1decSSalil Mehta struct hlcgevf_tqp_stats { 176e2cb1decSSalil Mehta /* query_tqp_tx_queue_statistics ,opcode id: 0x0B03 */ 177e2cb1decSSalil Mehta u64 rcb_tx_ring_pktnum_rcd; /* 32bit */ 178e2cb1decSSalil Mehta /* query_tqp_rx_queue_statistics ,opcode id: 0x0B13 */ 179e2cb1decSSalil Mehta u64 rcb_rx_ring_pktnum_rcd; /* 32bit */ 180e2cb1decSSalil Mehta }; 181e2cb1decSSalil Mehta 182e2cb1decSSalil Mehta struct hclgevf_tqp { 183e2cb1decSSalil Mehta struct device *dev; /* device for DMA mapping */ 184e2cb1decSSalil Mehta struct hnae3_queue q; 185e2cb1decSSalil Mehta struct hlcgevf_tqp_stats tqp_stats; 186e2cb1decSSalil Mehta u16 index; /* global index in a NIC controller */ 187e2cb1decSSalil Mehta 188e2cb1decSSalil Mehta bool alloced; 189e2cb1decSSalil Mehta }; 190e2cb1decSSalil Mehta 191e2cb1decSSalil Mehta struct hclgevf_cfg { 192e2cb1decSSalil Mehta u8 vmdq_vport_num; 193e2cb1decSSalil Mehta u8 tc_num; 194e2cb1decSSalil Mehta u16 tqp_desc_num; 195e2cb1decSSalil Mehta u16 rx_buf_len; 196e2cb1decSSalil Mehta u8 phy_addr; 197e2cb1decSSalil Mehta u8 media_type; 198e2cb1decSSalil Mehta u8 mac_addr[ETH_ALEN]; 199e2cb1decSSalil Mehta u32 numa_node_map; 200e2cb1decSSalil Mehta }; 201e2cb1decSSalil Mehta 202d97b3072SJian Shen struct hclgevf_rss_tuple_cfg { 203d97b3072SJian Shen u8 ipv4_tcp_en; 204d97b3072SJian Shen u8 ipv4_udp_en; 205d97b3072SJian Shen u8 ipv4_sctp_en; 206d97b3072SJian Shen u8 ipv4_fragment_en; 207d97b3072SJian Shen u8 ipv6_tcp_en; 208d97b3072SJian Shen u8 ipv6_udp_en; 209d97b3072SJian Shen u8 ipv6_sctp_en; 210d97b3072SJian Shen u8 ipv6_fragment_en; 211d97b3072SJian Shen }; 212d97b3072SJian Shen 213e2cb1decSSalil Mehta struct hclgevf_rss_cfg { 214e2cb1decSSalil Mehta u8 rss_hash_key[HCLGEVF_RSS_KEY_SIZE]; /* user configured hash keys */ 215e2cb1decSSalil Mehta u32 hash_algo; 216e2cb1decSSalil Mehta u32 rss_size; 217e2cb1decSSalil Mehta u8 hw_tc_map; 218e2cb1decSSalil Mehta u8 rss_indirection_tbl[HCLGEVF_RSS_IND_TBL_SIZE]; /* shadow table */ 219d97b3072SJian Shen struct hclgevf_rss_tuple_cfg rss_tuple_sets; 220e2cb1decSSalil Mehta }; 221e2cb1decSSalil Mehta 222e2cb1decSSalil Mehta struct hclgevf_misc_vector { 223e2cb1decSSalil Mehta u8 __iomem *addr; 224e2cb1decSSalil Mehta int vector_irq; 225e2cb1decSSalil Mehta }; 226e2cb1decSSalil Mehta 227c88a6e7dSHuazhong Tan struct hclgevf_rst_stats { 228c88a6e7dSHuazhong Tan u32 rst_cnt; /* the number of reset */ 229c88a6e7dSHuazhong Tan u32 vf_func_rst_cnt; /* the number of VF function reset */ 230c88a6e7dSHuazhong Tan u32 flr_rst_cnt; /* the number of FLR */ 231c88a6e7dSHuazhong Tan u32 vf_rst_cnt; /* the number of VF reset */ 232c88a6e7dSHuazhong Tan u32 rst_done_cnt; /* the number of reset completed */ 233c88a6e7dSHuazhong Tan u32 hw_rst_done_cnt; /* the number of HW reset completed */ 234bbe6540eSHuazhong Tan u32 rst_fail_cnt; /* the number of VF reset fail */ 235c88a6e7dSHuazhong Tan }; 236c88a6e7dSHuazhong Tan 237e2cb1decSSalil Mehta struct hclgevf_dev { 238e2cb1decSSalil Mehta struct pci_dev *pdev; 239e2cb1decSSalil Mehta struct hnae3_ae_dev *ae_dev; 240e2cb1decSSalil Mehta struct hclgevf_hw hw; 241e2cb1decSSalil Mehta struct hclgevf_misc_vector misc_vector; 242e2cb1decSSalil Mehta struct hclgevf_rss_cfg rss_cfg; 243e2cb1decSSalil Mehta unsigned long state; 2446ff3cf07SHuazhong Tan unsigned long flr_state; 245720bd583SHuazhong Tan unsigned long default_reset_request; 2460742ed7cSHuazhong Tan unsigned long last_reset_time; 2470742ed7cSHuazhong Tan enum hnae3_reset_type reset_level; 248dea846e8SHuazhong Tan unsigned long reset_pending; 249dea846e8SHuazhong Tan enum hnae3_reset_type reset_type; 250e2cb1decSSalil Mehta 251436667d2SSalil Mehta #define HCLGEVF_RESET_REQUESTED 0 252436667d2SSalil Mehta #define HCLGEVF_RESET_PENDING 1 253436667d2SSalil Mehta unsigned long reset_state; /* requested, pending */ 254c88a6e7dSHuazhong Tan struct hclgevf_rst_stats rst_stats; 255436667d2SSalil Mehta u32 reset_attempts; 256436667d2SSalil Mehta 257e2cb1decSSalil Mehta u32 fw_version; 258e2cb1decSSalil Mehta u16 num_tqps; /* num task queue pairs of this PF */ 259e2cb1decSSalil Mehta 260e2cb1decSSalil Mehta u16 alloc_rss_size; /* allocated RSS task queue */ 261e2cb1decSSalil Mehta u16 rss_size_max; /* HW defined max RSS task queue */ 262e2cb1decSSalil Mehta 263e2cb1decSSalil Mehta u16 num_alloc_vport; /* num vports this driver supports */ 264e2cb1decSSalil Mehta u32 numa_node_mask; 265e2cb1decSSalil Mehta u16 rx_buf_len; 266c0425944SPeng Li u16 num_tx_desc; /* desc num of per tx queue */ 267c0425944SPeng Li u16 num_rx_desc; /* desc num of per rx queue */ 268e2cb1decSSalil Mehta u8 hw_tc_map; 269e2cb1decSSalil Mehta 270e2cb1decSSalil Mehta u16 num_msi; 271e2cb1decSSalil Mehta u16 num_msi_left; 272e2cb1decSSalil Mehta u16 num_msi_used; 27307acf909SJian Shen u16 num_roce_msix; /* Num of roce vectors for this VF */ 27407acf909SJian Shen u16 roce_base_msix_offset; 27507acf909SJian Shen int roce_base_vector; 276e2cb1decSSalil Mehta u32 base_msi_vector; 277e2cb1decSSalil Mehta u16 *vector_status; 278e2cb1decSSalil Mehta int *vector_irq; 279e2cb1decSSalil Mehta 280fe4144d4SJian Shen unsigned long vlan_del_fail_bmap[BITS_TO_LONGS(VLAN_N_VID)]; 281fe4144d4SJian Shen 28207a0556aSSalil Mehta bool mbx_event_pending; 283e2cb1decSSalil Mehta struct hclgevf_mbx_resp_status mbx_resp; /* mailbox response */ 28407a0556aSSalil Mehta struct hclgevf_mbx_arq_ring arq; /* mailbox async rx queue */ 285e2cb1decSSalil Mehta 286e2cb1decSSalil Mehta struct timer_list service_timer; 287a6d818e3SYunsheng Lin struct timer_list keep_alive_timer; 288e2cb1decSSalil Mehta struct work_struct service_task; 289a6d818e3SYunsheng Lin struct work_struct keep_alive_task; 29035a1e503SSalil Mehta struct work_struct rst_service_task; 291e2cb1decSSalil Mehta struct work_struct mbx_service_task; 292e2cb1decSSalil Mehta 293e2cb1decSSalil Mehta struct hclgevf_tqp *htqp; 294e2cb1decSSalil Mehta 295e2cb1decSSalil Mehta struct hnae3_handle nic; 296e2cb1decSSalil Mehta struct hnae3_handle roce; 297e2cb1decSSalil Mehta 298e2cb1decSSalil Mehta struct hnae3_client *nic_client; 299e2cb1decSSalil Mehta struct hnae3_client *roce_client; 300e2cb1decSSalil Mehta u32 flag; 301db01afebSliuzhongzhu u32 stats_timer; 302e2cb1decSSalil Mehta }; 303e2cb1decSSalil Mehta 304ef5f8e50SHuazhong Tan static inline bool hclgevf_is_reset_pending(struct hclgevf_dev *hdev) 305ef5f8e50SHuazhong Tan { 306ef5f8e50SHuazhong Tan return !!hdev->reset_pending; 307ef5f8e50SHuazhong Tan } 308ef5f8e50SHuazhong Tan 309e2cb1decSSalil Mehta int hclgevf_send_mbx_msg(struct hclgevf_dev *hdev, u16 code, u16 subcode, 310e2cb1decSSalil Mehta const u8 *msg_data, u8 msg_len, bool need_resp, 311e2cb1decSSalil Mehta u8 *resp_data, u16 resp_len); 312e2cb1decSSalil Mehta void hclgevf_mbx_handler(struct hclgevf_dev *hdev); 31307a0556aSSalil Mehta void hclgevf_mbx_async_handler(struct hclgevf_dev *hdev); 31407a0556aSSalil Mehta 315e2cb1decSSalil Mehta void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state); 3164a152de9SFuyun Liang void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed, 3174a152de9SFuyun Liang u8 duplex); 31835a1e503SSalil Mehta void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev); 31907a0556aSSalil Mehta void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev); 32092f11ea1SJian Shen void hclgevf_update_port_base_vlan_info(struct hclgevf_dev *hdev, u16 state, 32192f11ea1SJian Shen u8 *port_base_vlan_info, u8 data_size); 322e2cb1decSSalil Mehta #endif 323