1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/etherdevice.h> 5 #include <linux/iopoll.h> 6 #include <net/rtnetlink.h> 7 #include "hclgevf_cmd.h" 8 #include "hclgevf_main.h" 9 #include "hclge_mbx.h" 10 #include "hnae3.h" 11 12 #define HCLGEVF_NAME "hclgevf" 13 14 #define HCLGEVF_RESET_MAX_FAIL_CNT 5 15 16 static int hclgevf_reset_hdev(struct hclgevf_dev *hdev); 17 static struct hnae3_ae_algo ae_algovf; 18 19 static const struct pci_device_id ae_algovf_pci_tbl[] = { 20 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0}, 21 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF), 0}, 22 /* required last entry */ 23 {0, } 24 }; 25 26 static const u8 hclgevf_hash_key[] = { 27 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2, 28 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0, 29 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4, 30 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C, 31 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA 32 }; 33 34 MODULE_DEVICE_TABLE(pci, ae_algovf_pci_tbl); 35 36 static const u32 cmdq_reg_addr_list[] = {HCLGEVF_CMDQ_TX_ADDR_L_REG, 37 HCLGEVF_CMDQ_TX_ADDR_H_REG, 38 HCLGEVF_CMDQ_TX_DEPTH_REG, 39 HCLGEVF_CMDQ_TX_TAIL_REG, 40 HCLGEVF_CMDQ_TX_HEAD_REG, 41 HCLGEVF_CMDQ_RX_ADDR_L_REG, 42 HCLGEVF_CMDQ_RX_ADDR_H_REG, 43 HCLGEVF_CMDQ_RX_DEPTH_REG, 44 HCLGEVF_CMDQ_RX_TAIL_REG, 45 HCLGEVF_CMDQ_RX_HEAD_REG, 46 HCLGEVF_VECTOR0_CMDQ_SRC_REG, 47 HCLGEVF_CMDQ_INTR_STS_REG, 48 HCLGEVF_CMDQ_INTR_EN_REG, 49 HCLGEVF_CMDQ_INTR_GEN_REG}; 50 51 static const u32 common_reg_addr_list[] = {HCLGEVF_MISC_VECTOR_REG_BASE, 52 HCLGEVF_RST_ING, 53 HCLGEVF_GRO_EN_REG}; 54 55 static const u32 ring_reg_addr_list[] = {HCLGEVF_RING_RX_ADDR_L_REG, 56 HCLGEVF_RING_RX_ADDR_H_REG, 57 HCLGEVF_RING_RX_BD_NUM_REG, 58 HCLGEVF_RING_RX_BD_LENGTH_REG, 59 HCLGEVF_RING_RX_MERGE_EN_REG, 60 HCLGEVF_RING_RX_TAIL_REG, 61 HCLGEVF_RING_RX_HEAD_REG, 62 HCLGEVF_RING_RX_FBD_NUM_REG, 63 HCLGEVF_RING_RX_OFFSET_REG, 64 HCLGEVF_RING_RX_FBD_OFFSET_REG, 65 HCLGEVF_RING_RX_STASH_REG, 66 HCLGEVF_RING_RX_BD_ERR_REG, 67 HCLGEVF_RING_TX_ADDR_L_REG, 68 HCLGEVF_RING_TX_ADDR_H_REG, 69 HCLGEVF_RING_TX_BD_NUM_REG, 70 HCLGEVF_RING_TX_PRIORITY_REG, 71 HCLGEVF_RING_TX_TC_REG, 72 HCLGEVF_RING_TX_MERGE_EN_REG, 73 HCLGEVF_RING_TX_TAIL_REG, 74 HCLGEVF_RING_TX_HEAD_REG, 75 HCLGEVF_RING_TX_FBD_NUM_REG, 76 HCLGEVF_RING_TX_OFFSET_REG, 77 HCLGEVF_RING_TX_EBD_NUM_REG, 78 HCLGEVF_RING_TX_EBD_OFFSET_REG, 79 HCLGEVF_RING_TX_BD_ERR_REG, 80 HCLGEVF_RING_EN_REG}; 81 82 static const u32 tqp_intr_reg_addr_list[] = {HCLGEVF_TQP_INTR_CTRL_REG, 83 HCLGEVF_TQP_INTR_GL0_REG, 84 HCLGEVF_TQP_INTR_GL1_REG, 85 HCLGEVF_TQP_INTR_GL2_REG, 86 HCLGEVF_TQP_INTR_RL_REG}; 87 88 static struct hclgevf_dev *hclgevf_ae_get_hdev(struct hnae3_handle *handle) 89 { 90 if (!handle->client) 91 return container_of(handle, struct hclgevf_dev, nic); 92 else if (handle->client->type == HNAE3_CLIENT_ROCE) 93 return container_of(handle, struct hclgevf_dev, roce); 94 else 95 return container_of(handle, struct hclgevf_dev, nic); 96 } 97 98 static int hclgevf_tqps_update_stats(struct hnae3_handle *handle) 99 { 100 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 101 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 102 struct hclgevf_desc desc; 103 struct hclgevf_tqp *tqp; 104 int status; 105 int i; 106 107 for (i = 0; i < kinfo->num_tqps; i++) { 108 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 109 hclgevf_cmd_setup_basic_desc(&desc, 110 HCLGEVF_OPC_QUERY_RX_STATUS, 111 true); 112 113 desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 114 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 115 if (status) { 116 dev_err(&hdev->pdev->dev, 117 "Query tqp stat fail, status = %d,queue = %d\n", 118 status, i); 119 return status; 120 } 121 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd += 122 le32_to_cpu(desc.data[1]); 123 124 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_TX_STATUS, 125 true); 126 127 desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 128 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 129 if (status) { 130 dev_err(&hdev->pdev->dev, 131 "Query tqp stat fail, status = %d,queue = %d\n", 132 status, i); 133 return status; 134 } 135 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd += 136 le32_to_cpu(desc.data[1]); 137 } 138 139 return 0; 140 } 141 142 static u64 *hclgevf_tqps_get_stats(struct hnae3_handle *handle, u64 *data) 143 { 144 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 145 struct hclgevf_tqp *tqp; 146 u64 *buff = data; 147 int i; 148 149 for (i = 0; i < kinfo->num_tqps; i++) { 150 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 151 *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd; 152 } 153 for (i = 0; i < kinfo->num_tqps; i++) { 154 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 155 *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd; 156 } 157 158 return buff; 159 } 160 161 static int hclgevf_tqps_get_sset_count(struct hnae3_handle *handle, int strset) 162 { 163 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 164 165 return kinfo->num_tqps * 2; 166 } 167 168 static u8 *hclgevf_tqps_get_strings(struct hnae3_handle *handle, u8 *data) 169 { 170 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 171 u8 *buff = data; 172 int i = 0; 173 174 for (i = 0; i < kinfo->num_tqps; i++) { 175 struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 176 struct hclgevf_tqp, q); 177 snprintf(buff, ETH_GSTRING_LEN, "txq%d_pktnum_rcd", 178 tqp->index); 179 buff += ETH_GSTRING_LEN; 180 } 181 182 for (i = 0; i < kinfo->num_tqps; i++) { 183 struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 184 struct hclgevf_tqp, q); 185 snprintf(buff, ETH_GSTRING_LEN, "rxq%d_pktnum_rcd", 186 tqp->index); 187 buff += ETH_GSTRING_LEN; 188 } 189 190 return buff; 191 } 192 193 static void hclgevf_update_stats(struct hnae3_handle *handle, 194 struct net_device_stats *net_stats) 195 { 196 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 197 int status; 198 199 status = hclgevf_tqps_update_stats(handle); 200 if (status) 201 dev_err(&hdev->pdev->dev, 202 "VF update of TQPS stats fail, status = %d.\n", 203 status); 204 } 205 206 static int hclgevf_get_sset_count(struct hnae3_handle *handle, int strset) 207 { 208 if (strset == ETH_SS_TEST) 209 return -EOPNOTSUPP; 210 else if (strset == ETH_SS_STATS) 211 return hclgevf_tqps_get_sset_count(handle, strset); 212 213 return 0; 214 } 215 216 static void hclgevf_get_strings(struct hnae3_handle *handle, u32 strset, 217 u8 *data) 218 { 219 u8 *p = (char *)data; 220 221 if (strset == ETH_SS_STATS) 222 p = hclgevf_tqps_get_strings(handle, p); 223 } 224 225 static void hclgevf_get_stats(struct hnae3_handle *handle, u64 *data) 226 { 227 hclgevf_tqps_get_stats(handle, data); 228 } 229 230 static int hclgevf_get_tc_info(struct hclgevf_dev *hdev) 231 { 232 u8 resp_msg; 233 int status; 234 235 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_TCINFO, 0, NULL, 0, 236 true, &resp_msg, sizeof(resp_msg)); 237 if (status) { 238 dev_err(&hdev->pdev->dev, 239 "VF request to get TC info from PF failed %d", 240 status); 241 return status; 242 } 243 244 hdev->hw_tc_map = resp_msg; 245 246 return 0; 247 } 248 249 static int hclgevf_get_port_base_vlan_filter_state(struct hclgevf_dev *hdev) 250 { 251 struct hnae3_handle *nic = &hdev->nic; 252 u8 resp_msg; 253 int ret; 254 255 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 256 HCLGE_MBX_GET_PORT_BASE_VLAN_STATE, 257 NULL, 0, true, &resp_msg, sizeof(u8)); 258 if (ret) { 259 dev_err(&hdev->pdev->dev, 260 "VF request to get port based vlan state failed %d", 261 ret); 262 return ret; 263 } 264 265 nic->port_base_vlan_state = resp_msg; 266 267 return 0; 268 } 269 270 static int hclgevf_get_queue_info(struct hclgevf_dev *hdev) 271 { 272 #define HCLGEVF_TQPS_RSS_INFO_LEN 6 273 u8 resp_msg[HCLGEVF_TQPS_RSS_INFO_LEN]; 274 int status; 275 276 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QINFO, 0, NULL, 0, 277 true, resp_msg, 278 HCLGEVF_TQPS_RSS_INFO_LEN); 279 if (status) { 280 dev_err(&hdev->pdev->dev, 281 "VF request to get tqp info from PF failed %d", 282 status); 283 return status; 284 } 285 286 memcpy(&hdev->num_tqps, &resp_msg[0], sizeof(u16)); 287 memcpy(&hdev->rss_size_max, &resp_msg[2], sizeof(u16)); 288 memcpy(&hdev->rx_buf_len, &resp_msg[4], sizeof(u16)); 289 290 return 0; 291 } 292 293 static int hclgevf_get_queue_depth(struct hclgevf_dev *hdev) 294 { 295 #define HCLGEVF_TQPS_DEPTH_INFO_LEN 4 296 u8 resp_msg[HCLGEVF_TQPS_DEPTH_INFO_LEN]; 297 int ret; 298 299 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QDEPTH, 0, NULL, 0, 300 true, resp_msg, 301 HCLGEVF_TQPS_DEPTH_INFO_LEN); 302 if (ret) { 303 dev_err(&hdev->pdev->dev, 304 "VF request to get tqp depth info from PF failed %d", 305 ret); 306 return ret; 307 } 308 309 memcpy(&hdev->num_tx_desc, &resp_msg[0], sizeof(u16)); 310 memcpy(&hdev->num_rx_desc, &resp_msg[2], sizeof(u16)); 311 312 return 0; 313 } 314 315 static u16 hclgevf_get_qid_global(struct hnae3_handle *handle, u16 queue_id) 316 { 317 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 318 u8 msg_data[2], resp_data[2]; 319 u16 qid_in_pf = 0; 320 int ret; 321 322 memcpy(&msg_data[0], &queue_id, sizeof(queue_id)); 323 324 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QID_IN_PF, 0, msg_data, 325 sizeof(msg_data), true, resp_data, 326 sizeof(resp_data)); 327 if (!ret) 328 qid_in_pf = *(u16 *)resp_data; 329 330 return qid_in_pf; 331 } 332 333 static int hclgevf_get_pf_media_type(struct hclgevf_dev *hdev) 334 { 335 u8 resp_msg[2]; 336 int ret; 337 338 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_MEDIA_TYPE, 0, NULL, 0, 339 true, resp_msg, sizeof(resp_msg)); 340 if (ret) { 341 dev_err(&hdev->pdev->dev, 342 "VF request to get the pf port media type failed %d", 343 ret); 344 return ret; 345 } 346 347 hdev->hw.mac.media_type = resp_msg[0]; 348 hdev->hw.mac.module_type = resp_msg[1]; 349 350 return 0; 351 } 352 353 static int hclgevf_alloc_tqps(struct hclgevf_dev *hdev) 354 { 355 struct hclgevf_tqp *tqp; 356 int i; 357 358 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 359 sizeof(struct hclgevf_tqp), GFP_KERNEL); 360 if (!hdev->htqp) 361 return -ENOMEM; 362 363 tqp = hdev->htqp; 364 365 for (i = 0; i < hdev->num_tqps; i++) { 366 tqp->dev = &hdev->pdev->dev; 367 tqp->index = i; 368 369 tqp->q.ae_algo = &ae_algovf; 370 tqp->q.buf_size = hdev->rx_buf_len; 371 tqp->q.tx_desc_num = hdev->num_tx_desc; 372 tqp->q.rx_desc_num = hdev->num_rx_desc; 373 tqp->q.io_base = hdev->hw.io_base + HCLGEVF_TQP_REG_OFFSET + 374 i * HCLGEVF_TQP_REG_SIZE; 375 376 tqp++; 377 } 378 379 return 0; 380 } 381 382 static int hclgevf_knic_setup(struct hclgevf_dev *hdev) 383 { 384 struct hnae3_handle *nic = &hdev->nic; 385 struct hnae3_knic_private_info *kinfo; 386 u16 new_tqps = hdev->num_tqps; 387 unsigned int i; 388 389 kinfo = &nic->kinfo; 390 kinfo->num_tc = 0; 391 kinfo->num_tx_desc = hdev->num_tx_desc; 392 kinfo->num_rx_desc = hdev->num_rx_desc; 393 kinfo->rx_buf_len = hdev->rx_buf_len; 394 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) 395 if (hdev->hw_tc_map & BIT(i)) 396 kinfo->num_tc++; 397 398 kinfo->rss_size 399 = min_t(u16, hdev->rss_size_max, new_tqps / kinfo->num_tc); 400 new_tqps = kinfo->rss_size * kinfo->num_tc; 401 kinfo->num_tqps = min(new_tqps, hdev->num_tqps); 402 403 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps, 404 sizeof(struct hnae3_queue *), GFP_KERNEL); 405 if (!kinfo->tqp) 406 return -ENOMEM; 407 408 for (i = 0; i < kinfo->num_tqps; i++) { 409 hdev->htqp[i].q.handle = &hdev->nic; 410 hdev->htqp[i].q.tqp_index = i; 411 kinfo->tqp[i] = &hdev->htqp[i].q; 412 } 413 414 /* after init the max rss_size and tqps, adjust the default tqp numbers 415 * and rss size with the actual vector numbers 416 */ 417 kinfo->num_tqps = min_t(u16, hdev->num_nic_msix - 1, kinfo->num_tqps); 418 kinfo->rss_size = min_t(u16, kinfo->num_tqps / kinfo->num_tc, 419 kinfo->rss_size); 420 421 return 0; 422 } 423 424 static void hclgevf_request_link_info(struct hclgevf_dev *hdev) 425 { 426 int status; 427 u8 resp_msg; 428 429 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_STATUS, 0, NULL, 430 0, false, &resp_msg, sizeof(resp_msg)); 431 if (status) 432 dev_err(&hdev->pdev->dev, 433 "VF failed to fetch link status(%d) from PF", status); 434 } 435 436 void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state) 437 { 438 struct hnae3_handle *rhandle = &hdev->roce; 439 struct hnae3_handle *handle = &hdev->nic; 440 struct hnae3_client *rclient; 441 struct hnae3_client *client; 442 443 if (test_and_set_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state)) 444 return; 445 446 client = handle->client; 447 rclient = hdev->roce_client; 448 449 link_state = 450 test_bit(HCLGEVF_STATE_DOWN, &hdev->state) ? 0 : link_state; 451 452 if (link_state != hdev->hw.mac.link) { 453 client->ops->link_status_change(handle, !!link_state); 454 if (rclient && rclient->ops->link_status_change) 455 rclient->ops->link_status_change(rhandle, !!link_state); 456 hdev->hw.mac.link = link_state; 457 } 458 459 clear_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state); 460 } 461 462 static void hclgevf_update_link_mode(struct hclgevf_dev *hdev) 463 { 464 #define HCLGEVF_ADVERTISING 0 465 #define HCLGEVF_SUPPORTED 1 466 u8 send_msg; 467 u8 resp_msg; 468 469 send_msg = HCLGEVF_ADVERTISING; 470 hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_MODE, 0, 471 &send_msg, sizeof(send_msg), false, 472 &resp_msg, sizeof(resp_msg)); 473 send_msg = HCLGEVF_SUPPORTED; 474 hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_MODE, 0, 475 &send_msg, sizeof(send_msg), false, 476 &resp_msg, sizeof(resp_msg)); 477 } 478 479 static int hclgevf_set_handle_info(struct hclgevf_dev *hdev) 480 { 481 struct hnae3_handle *nic = &hdev->nic; 482 int ret; 483 484 nic->ae_algo = &ae_algovf; 485 nic->pdev = hdev->pdev; 486 nic->numa_node_mask = hdev->numa_node_mask; 487 nic->flags |= HNAE3_SUPPORT_VF; 488 489 ret = hclgevf_knic_setup(hdev); 490 if (ret) 491 dev_err(&hdev->pdev->dev, "VF knic setup failed %d\n", 492 ret); 493 return ret; 494 } 495 496 static void hclgevf_free_vector(struct hclgevf_dev *hdev, int vector_id) 497 { 498 if (hdev->vector_status[vector_id] == HCLGEVF_INVALID_VPORT) { 499 dev_warn(&hdev->pdev->dev, 500 "vector(vector_id %d) has been freed.\n", vector_id); 501 return; 502 } 503 504 hdev->vector_status[vector_id] = HCLGEVF_INVALID_VPORT; 505 hdev->num_msi_left += 1; 506 hdev->num_msi_used -= 1; 507 } 508 509 static int hclgevf_get_vector(struct hnae3_handle *handle, u16 vector_num, 510 struct hnae3_vector_info *vector_info) 511 { 512 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 513 struct hnae3_vector_info *vector = vector_info; 514 int alloc = 0; 515 int i, j; 516 517 vector_num = min_t(u16, hdev->num_nic_msix - 1, vector_num); 518 vector_num = min(hdev->num_msi_left, vector_num); 519 520 for (j = 0; j < vector_num; j++) { 521 for (i = HCLGEVF_MISC_VECTOR_NUM + 1; i < hdev->num_msi; i++) { 522 if (hdev->vector_status[i] == HCLGEVF_INVALID_VPORT) { 523 vector->vector = pci_irq_vector(hdev->pdev, i); 524 vector->io_addr = hdev->hw.io_base + 525 HCLGEVF_VECTOR_REG_BASE + 526 (i - 1) * HCLGEVF_VECTOR_REG_OFFSET; 527 hdev->vector_status[i] = 0; 528 hdev->vector_irq[i] = vector->vector; 529 530 vector++; 531 alloc++; 532 533 break; 534 } 535 } 536 } 537 hdev->num_msi_left -= alloc; 538 hdev->num_msi_used += alloc; 539 540 return alloc; 541 } 542 543 static int hclgevf_get_vector_index(struct hclgevf_dev *hdev, int vector) 544 { 545 int i; 546 547 for (i = 0; i < hdev->num_msi; i++) 548 if (vector == hdev->vector_irq[i]) 549 return i; 550 551 return -EINVAL; 552 } 553 554 static int hclgevf_set_rss_algo_key(struct hclgevf_dev *hdev, 555 const u8 hfunc, const u8 *key) 556 { 557 struct hclgevf_rss_config_cmd *req; 558 unsigned int key_offset = 0; 559 struct hclgevf_desc desc; 560 int key_counts; 561 int key_size; 562 int ret; 563 564 key_counts = HCLGEVF_RSS_KEY_SIZE; 565 req = (struct hclgevf_rss_config_cmd *)desc.data; 566 567 while (key_counts) { 568 hclgevf_cmd_setup_basic_desc(&desc, 569 HCLGEVF_OPC_RSS_GENERIC_CONFIG, 570 false); 571 572 req->hash_config |= (hfunc & HCLGEVF_RSS_HASH_ALGO_MASK); 573 req->hash_config |= 574 (key_offset << HCLGEVF_RSS_HASH_KEY_OFFSET_B); 575 576 key_size = min(HCLGEVF_RSS_HASH_KEY_NUM, key_counts); 577 memcpy(req->hash_key, 578 key + key_offset * HCLGEVF_RSS_HASH_KEY_NUM, key_size); 579 580 key_counts -= key_size; 581 key_offset++; 582 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 583 if (ret) { 584 dev_err(&hdev->pdev->dev, 585 "Configure RSS config fail, status = %d\n", 586 ret); 587 return ret; 588 } 589 } 590 591 return 0; 592 } 593 594 static u32 hclgevf_get_rss_key_size(struct hnae3_handle *handle) 595 { 596 return HCLGEVF_RSS_KEY_SIZE; 597 } 598 599 static u32 hclgevf_get_rss_indir_size(struct hnae3_handle *handle) 600 { 601 return HCLGEVF_RSS_IND_TBL_SIZE; 602 } 603 604 static int hclgevf_set_rss_indir_table(struct hclgevf_dev *hdev) 605 { 606 const u8 *indir = hdev->rss_cfg.rss_indirection_tbl; 607 struct hclgevf_rss_indirection_table_cmd *req; 608 struct hclgevf_desc desc; 609 int status; 610 int i, j; 611 612 req = (struct hclgevf_rss_indirection_table_cmd *)desc.data; 613 614 for (i = 0; i < HCLGEVF_RSS_CFG_TBL_NUM; i++) { 615 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INDIR_TABLE, 616 false); 617 req->start_table_index = i * HCLGEVF_RSS_CFG_TBL_SIZE; 618 req->rss_set_bitmap = HCLGEVF_RSS_SET_BITMAP_MSK; 619 for (j = 0; j < HCLGEVF_RSS_CFG_TBL_SIZE; j++) 620 req->rss_result[j] = 621 indir[i * HCLGEVF_RSS_CFG_TBL_SIZE + j]; 622 623 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 624 if (status) { 625 dev_err(&hdev->pdev->dev, 626 "VF failed(=%d) to set RSS indirection table\n", 627 status); 628 return status; 629 } 630 } 631 632 return 0; 633 } 634 635 static int hclgevf_set_rss_tc_mode(struct hclgevf_dev *hdev, u16 rss_size) 636 { 637 struct hclgevf_rss_tc_mode_cmd *req; 638 u16 tc_offset[HCLGEVF_MAX_TC_NUM]; 639 u16 tc_valid[HCLGEVF_MAX_TC_NUM]; 640 u16 tc_size[HCLGEVF_MAX_TC_NUM]; 641 struct hclgevf_desc desc; 642 u16 roundup_size; 643 int status; 644 unsigned int i; 645 646 req = (struct hclgevf_rss_tc_mode_cmd *)desc.data; 647 648 roundup_size = roundup_pow_of_two(rss_size); 649 roundup_size = ilog2(roundup_size); 650 651 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 652 tc_valid[i] = !!(hdev->hw_tc_map & BIT(i)); 653 tc_size[i] = roundup_size; 654 tc_offset[i] = rss_size * i; 655 } 656 657 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_TC_MODE, false); 658 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 659 hnae3_set_bit(req->rss_tc_mode[i], HCLGEVF_RSS_TC_VALID_B, 660 (tc_valid[i] & 0x1)); 661 hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_SIZE_M, 662 HCLGEVF_RSS_TC_SIZE_S, tc_size[i]); 663 hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_OFFSET_M, 664 HCLGEVF_RSS_TC_OFFSET_S, tc_offset[i]); 665 } 666 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 667 if (status) 668 dev_err(&hdev->pdev->dev, 669 "VF failed(=%d) to set rss tc mode\n", status); 670 671 return status; 672 } 673 674 /* for revision 0x20, vf shared the same rss config with pf */ 675 static int hclgevf_get_rss_hash_key(struct hclgevf_dev *hdev) 676 { 677 #define HCLGEVF_RSS_MBX_RESP_LEN 8 678 679 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 680 u8 resp_msg[HCLGEVF_RSS_MBX_RESP_LEN]; 681 u16 msg_num, hash_key_index; 682 u8 index; 683 int ret; 684 685 msg_num = (HCLGEVF_RSS_KEY_SIZE + HCLGEVF_RSS_MBX_RESP_LEN - 1) / 686 HCLGEVF_RSS_MBX_RESP_LEN; 687 for (index = 0; index < msg_num; index++) { 688 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_RSS_KEY, 0, 689 &index, sizeof(index), 690 true, resp_msg, 691 HCLGEVF_RSS_MBX_RESP_LEN); 692 if (ret) { 693 dev_err(&hdev->pdev->dev, 694 "VF get rss hash key from PF failed, ret=%d", 695 ret); 696 return ret; 697 } 698 699 hash_key_index = HCLGEVF_RSS_MBX_RESP_LEN * index; 700 if (index == msg_num - 1) 701 memcpy(&rss_cfg->rss_hash_key[hash_key_index], 702 &resp_msg[0], 703 HCLGEVF_RSS_KEY_SIZE - hash_key_index); 704 else 705 memcpy(&rss_cfg->rss_hash_key[hash_key_index], 706 &resp_msg[0], HCLGEVF_RSS_MBX_RESP_LEN); 707 } 708 709 return 0; 710 } 711 712 static int hclgevf_get_rss(struct hnae3_handle *handle, u32 *indir, u8 *key, 713 u8 *hfunc) 714 { 715 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 716 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 717 int i, ret; 718 719 if (handle->pdev->revision >= 0x21) { 720 /* Get hash algorithm */ 721 if (hfunc) { 722 switch (rss_cfg->hash_algo) { 723 case HCLGEVF_RSS_HASH_ALGO_TOEPLITZ: 724 *hfunc = ETH_RSS_HASH_TOP; 725 break; 726 case HCLGEVF_RSS_HASH_ALGO_SIMPLE: 727 *hfunc = ETH_RSS_HASH_XOR; 728 break; 729 default: 730 *hfunc = ETH_RSS_HASH_UNKNOWN; 731 break; 732 } 733 } 734 735 /* Get the RSS Key required by the user */ 736 if (key) 737 memcpy(key, rss_cfg->rss_hash_key, 738 HCLGEVF_RSS_KEY_SIZE); 739 } else { 740 if (hfunc) 741 *hfunc = ETH_RSS_HASH_TOP; 742 if (key) { 743 ret = hclgevf_get_rss_hash_key(hdev); 744 if (ret) 745 return ret; 746 memcpy(key, rss_cfg->rss_hash_key, 747 HCLGEVF_RSS_KEY_SIZE); 748 } 749 } 750 751 if (indir) 752 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 753 indir[i] = rss_cfg->rss_indirection_tbl[i]; 754 755 return 0; 756 } 757 758 static int hclgevf_set_rss(struct hnae3_handle *handle, const u32 *indir, 759 const u8 *key, const u8 hfunc) 760 { 761 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 762 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 763 int ret, i; 764 765 if (handle->pdev->revision >= 0x21) { 766 /* Set the RSS Hash Key if specififed by the user */ 767 if (key) { 768 switch (hfunc) { 769 case ETH_RSS_HASH_TOP: 770 rss_cfg->hash_algo = 771 HCLGEVF_RSS_HASH_ALGO_TOEPLITZ; 772 break; 773 case ETH_RSS_HASH_XOR: 774 rss_cfg->hash_algo = 775 HCLGEVF_RSS_HASH_ALGO_SIMPLE; 776 break; 777 case ETH_RSS_HASH_NO_CHANGE: 778 break; 779 default: 780 return -EINVAL; 781 } 782 783 ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 784 key); 785 if (ret) 786 return ret; 787 788 /* Update the shadow RSS key with user specified qids */ 789 memcpy(rss_cfg->rss_hash_key, key, 790 HCLGEVF_RSS_KEY_SIZE); 791 } 792 } 793 794 /* update the shadow RSS table with user specified qids */ 795 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 796 rss_cfg->rss_indirection_tbl[i] = indir[i]; 797 798 /* update the hardware */ 799 return hclgevf_set_rss_indir_table(hdev); 800 } 801 802 static u8 hclgevf_get_rss_hash_bits(struct ethtool_rxnfc *nfc) 803 { 804 u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGEVF_S_PORT_BIT : 0; 805 806 if (nfc->data & RXH_L4_B_2_3) 807 hash_sets |= HCLGEVF_D_PORT_BIT; 808 else 809 hash_sets &= ~HCLGEVF_D_PORT_BIT; 810 811 if (nfc->data & RXH_IP_SRC) 812 hash_sets |= HCLGEVF_S_IP_BIT; 813 else 814 hash_sets &= ~HCLGEVF_S_IP_BIT; 815 816 if (nfc->data & RXH_IP_DST) 817 hash_sets |= HCLGEVF_D_IP_BIT; 818 else 819 hash_sets &= ~HCLGEVF_D_IP_BIT; 820 821 if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW) 822 hash_sets |= HCLGEVF_V_TAG_BIT; 823 824 return hash_sets; 825 } 826 827 static int hclgevf_set_rss_tuple(struct hnae3_handle *handle, 828 struct ethtool_rxnfc *nfc) 829 { 830 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 831 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 832 struct hclgevf_rss_input_tuple_cmd *req; 833 struct hclgevf_desc desc; 834 u8 tuple_sets; 835 int ret; 836 837 if (handle->pdev->revision == 0x20) 838 return -EOPNOTSUPP; 839 840 if (nfc->data & 841 ~(RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3)) 842 return -EINVAL; 843 844 req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 845 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 846 847 req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 848 req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 849 req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 850 req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 851 req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 852 req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 853 req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 854 req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 855 856 tuple_sets = hclgevf_get_rss_hash_bits(nfc); 857 switch (nfc->flow_type) { 858 case TCP_V4_FLOW: 859 req->ipv4_tcp_en = tuple_sets; 860 break; 861 case TCP_V6_FLOW: 862 req->ipv6_tcp_en = tuple_sets; 863 break; 864 case UDP_V4_FLOW: 865 req->ipv4_udp_en = tuple_sets; 866 break; 867 case UDP_V6_FLOW: 868 req->ipv6_udp_en = tuple_sets; 869 break; 870 case SCTP_V4_FLOW: 871 req->ipv4_sctp_en = tuple_sets; 872 break; 873 case SCTP_V6_FLOW: 874 if ((nfc->data & RXH_L4_B_0_1) || 875 (nfc->data & RXH_L4_B_2_3)) 876 return -EINVAL; 877 878 req->ipv6_sctp_en = tuple_sets; 879 break; 880 case IPV4_FLOW: 881 req->ipv4_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 882 break; 883 case IPV6_FLOW: 884 req->ipv6_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 885 break; 886 default: 887 return -EINVAL; 888 } 889 890 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 891 if (ret) { 892 dev_err(&hdev->pdev->dev, 893 "Set rss tuple fail, status = %d\n", ret); 894 return ret; 895 } 896 897 rss_cfg->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en; 898 rss_cfg->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en; 899 rss_cfg->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en; 900 rss_cfg->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en; 901 rss_cfg->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en; 902 rss_cfg->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en; 903 rss_cfg->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en; 904 rss_cfg->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en; 905 return 0; 906 } 907 908 static int hclgevf_get_rss_tuple(struct hnae3_handle *handle, 909 struct ethtool_rxnfc *nfc) 910 { 911 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 912 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 913 u8 tuple_sets; 914 915 if (handle->pdev->revision == 0x20) 916 return -EOPNOTSUPP; 917 918 nfc->data = 0; 919 920 switch (nfc->flow_type) { 921 case TCP_V4_FLOW: 922 tuple_sets = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 923 break; 924 case UDP_V4_FLOW: 925 tuple_sets = rss_cfg->rss_tuple_sets.ipv4_udp_en; 926 break; 927 case TCP_V6_FLOW: 928 tuple_sets = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 929 break; 930 case UDP_V6_FLOW: 931 tuple_sets = rss_cfg->rss_tuple_sets.ipv6_udp_en; 932 break; 933 case SCTP_V4_FLOW: 934 tuple_sets = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 935 break; 936 case SCTP_V6_FLOW: 937 tuple_sets = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 938 break; 939 case IPV4_FLOW: 940 case IPV6_FLOW: 941 tuple_sets = HCLGEVF_S_IP_BIT | HCLGEVF_D_IP_BIT; 942 break; 943 default: 944 return -EINVAL; 945 } 946 947 if (!tuple_sets) 948 return 0; 949 950 if (tuple_sets & HCLGEVF_D_PORT_BIT) 951 nfc->data |= RXH_L4_B_2_3; 952 if (tuple_sets & HCLGEVF_S_PORT_BIT) 953 nfc->data |= RXH_L4_B_0_1; 954 if (tuple_sets & HCLGEVF_D_IP_BIT) 955 nfc->data |= RXH_IP_DST; 956 if (tuple_sets & HCLGEVF_S_IP_BIT) 957 nfc->data |= RXH_IP_SRC; 958 959 return 0; 960 } 961 962 static int hclgevf_set_rss_input_tuple(struct hclgevf_dev *hdev, 963 struct hclgevf_rss_cfg *rss_cfg) 964 { 965 struct hclgevf_rss_input_tuple_cmd *req; 966 struct hclgevf_desc desc; 967 int ret; 968 969 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 970 971 req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 972 973 req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 974 req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 975 req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 976 req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 977 req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 978 req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 979 req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 980 req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 981 982 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 983 if (ret) 984 dev_err(&hdev->pdev->dev, 985 "Configure rss input fail, status = %d\n", ret); 986 return ret; 987 } 988 989 static int hclgevf_get_tc_size(struct hnae3_handle *handle) 990 { 991 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 992 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 993 994 return rss_cfg->rss_size; 995 } 996 997 static int hclgevf_bind_ring_to_vector(struct hnae3_handle *handle, bool en, 998 int vector_id, 999 struct hnae3_ring_chain_node *ring_chain) 1000 { 1001 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1002 struct hnae3_ring_chain_node *node; 1003 struct hclge_mbx_vf_to_pf_cmd *req; 1004 struct hclgevf_desc desc; 1005 int i = 0; 1006 int status; 1007 u8 type; 1008 1009 req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data; 1010 type = en ? HCLGE_MBX_MAP_RING_TO_VECTOR : 1011 HCLGE_MBX_UNMAP_RING_TO_VECTOR; 1012 1013 for (node = ring_chain; node; node = node->next) { 1014 int idx_offset = HCLGE_MBX_RING_MAP_BASIC_MSG_NUM + 1015 HCLGE_MBX_RING_NODE_VARIABLE_NUM * i; 1016 1017 if (i == 0) { 1018 hclgevf_cmd_setup_basic_desc(&desc, 1019 HCLGEVF_OPC_MBX_VF_TO_PF, 1020 false); 1021 req->msg[0] = type; 1022 req->msg[1] = vector_id; 1023 } 1024 1025 req->msg[idx_offset] = 1026 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B); 1027 req->msg[idx_offset + 1] = node->tqp_index; 1028 req->msg[idx_offset + 2] = hnae3_get_field(node->int_gl_idx, 1029 HNAE3_RING_GL_IDX_M, 1030 HNAE3_RING_GL_IDX_S); 1031 1032 i++; 1033 if ((i == (HCLGE_MBX_VF_MSG_DATA_NUM - 1034 HCLGE_MBX_RING_MAP_BASIC_MSG_NUM) / 1035 HCLGE_MBX_RING_NODE_VARIABLE_NUM) || 1036 !node->next) { 1037 req->msg[2] = i; 1038 1039 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1040 if (status) { 1041 dev_err(&hdev->pdev->dev, 1042 "Map TQP fail, status is %d.\n", 1043 status); 1044 return status; 1045 } 1046 i = 0; 1047 hclgevf_cmd_setup_basic_desc(&desc, 1048 HCLGEVF_OPC_MBX_VF_TO_PF, 1049 false); 1050 req->msg[0] = type; 1051 req->msg[1] = vector_id; 1052 } 1053 } 1054 1055 return 0; 1056 } 1057 1058 static int hclgevf_map_ring_to_vector(struct hnae3_handle *handle, int vector, 1059 struct hnae3_ring_chain_node *ring_chain) 1060 { 1061 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1062 int vector_id; 1063 1064 vector_id = hclgevf_get_vector_index(hdev, vector); 1065 if (vector_id < 0) { 1066 dev_err(&handle->pdev->dev, 1067 "Get vector index fail. ret =%d\n", vector_id); 1068 return vector_id; 1069 } 1070 1071 return hclgevf_bind_ring_to_vector(handle, true, vector_id, ring_chain); 1072 } 1073 1074 static int hclgevf_unmap_ring_from_vector( 1075 struct hnae3_handle *handle, 1076 int vector, 1077 struct hnae3_ring_chain_node *ring_chain) 1078 { 1079 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1080 int ret, vector_id; 1081 1082 if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 1083 return 0; 1084 1085 vector_id = hclgevf_get_vector_index(hdev, vector); 1086 if (vector_id < 0) { 1087 dev_err(&handle->pdev->dev, 1088 "Get vector index fail. ret =%d\n", vector_id); 1089 return vector_id; 1090 } 1091 1092 ret = hclgevf_bind_ring_to_vector(handle, false, vector_id, ring_chain); 1093 if (ret) 1094 dev_err(&handle->pdev->dev, 1095 "Unmap ring from vector fail. vector=%d, ret =%d\n", 1096 vector_id, 1097 ret); 1098 1099 return ret; 1100 } 1101 1102 static int hclgevf_put_vector(struct hnae3_handle *handle, int vector) 1103 { 1104 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1105 int vector_id; 1106 1107 vector_id = hclgevf_get_vector_index(hdev, vector); 1108 if (vector_id < 0) { 1109 dev_err(&handle->pdev->dev, 1110 "hclgevf_put_vector get vector index fail. ret =%d\n", 1111 vector_id); 1112 return vector_id; 1113 } 1114 1115 hclgevf_free_vector(hdev, vector_id); 1116 1117 return 0; 1118 } 1119 1120 static int hclgevf_cmd_set_promisc_mode(struct hclgevf_dev *hdev, 1121 bool en_uc_pmc, bool en_mc_pmc, 1122 bool en_bc_pmc) 1123 { 1124 struct hclge_mbx_vf_to_pf_cmd *req; 1125 struct hclgevf_desc desc; 1126 int ret; 1127 1128 req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data; 1129 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_MBX_VF_TO_PF, false); 1130 req->msg[0] = HCLGE_MBX_SET_PROMISC_MODE; 1131 req->msg[1] = en_bc_pmc ? 1 : 0; 1132 req->msg[2] = en_uc_pmc ? 1 : 0; 1133 req->msg[3] = en_mc_pmc ? 1 : 0; 1134 1135 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1136 if (ret) 1137 dev_err(&hdev->pdev->dev, 1138 "Set promisc mode fail, status is %d.\n", ret); 1139 1140 return ret; 1141 } 1142 1143 static int hclgevf_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc, 1144 bool en_mc_pmc) 1145 { 1146 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1147 struct pci_dev *pdev = hdev->pdev; 1148 bool en_bc_pmc; 1149 1150 en_bc_pmc = pdev->revision != 0x20; 1151 1152 return hclgevf_cmd_set_promisc_mode(hdev, en_uc_pmc, en_mc_pmc, 1153 en_bc_pmc); 1154 } 1155 1156 static int hclgevf_tqp_enable(struct hclgevf_dev *hdev, unsigned int tqp_id, 1157 int stream_id, bool enable) 1158 { 1159 struct hclgevf_cfg_com_tqp_queue_cmd *req; 1160 struct hclgevf_desc desc; 1161 int status; 1162 1163 req = (struct hclgevf_cfg_com_tqp_queue_cmd *)desc.data; 1164 1165 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_CFG_COM_TQP_QUEUE, 1166 false); 1167 req->tqp_id = cpu_to_le16(tqp_id & HCLGEVF_RING_ID_MASK); 1168 req->stream_id = cpu_to_le16(stream_id); 1169 if (enable) 1170 req->enable |= 1U << HCLGEVF_TQP_ENABLE_B; 1171 1172 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1173 if (status) 1174 dev_err(&hdev->pdev->dev, 1175 "TQP enable fail, status =%d.\n", status); 1176 1177 return status; 1178 } 1179 1180 static void hclgevf_reset_tqp_stats(struct hnae3_handle *handle) 1181 { 1182 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 1183 struct hclgevf_tqp *tqp; 1184 int i; 1185 1186 for (i = 0; i < kinfo->num_tqps; i++) { 1187 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 1188 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats)); 1189 } 1190 } 1191 1192 static int hclgevf_get_host_mac_addr(struct hclgevf_dev *hdev, u8 *p) 1193 { 1194 u8 host_mac[ETH_ALEN]; 1195 int status; 1196 1197 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_MAC_ADDR, 0, NULL, 0, 1198 true, host_mac, ETH_ALEN); 1199 if (status) { 1200 dev_err(&hdev->pdev->dev, 1201 "fail to get VF MAC from host %d", status); 1202 return status; 1203 } 1204 1205 ether_addr_copy(p, host_mac); 1206 1207 return 0; 1208 } 1209 1210 static void hclgevf_get_mac_addr(struct hnae3_handle *handle, u8 *p) 1211 { 1212 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1213 u8 host_mac_addr[ETH_ALEN]; 1214 1215 if (hclgevf_get_host_mac_addr(hdev, host_mac_addr)) 1216 return; 1217 1218 hdev->has_pf_mac = !is_zero_ether_addr(host_mac_addr); 1219 if (hdev->has_pf_mac) 1220 ether_addr_copy(p, host_mac_addr); 1221 else 1222 ether_addr_copy(p, hdev->hw.mac.mac_addr); 1223 } 1224 1225 static int hclgevf_set_mac_addr(struct hnae3_handle *handle, void *p, 1226 bool is_first) 1227 { 1228 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1229 u8 *old_mac_addr = (u8 *)hdev->hw.mac.mac_addr; 1230 u8 *new_mac_addr = (u8 *)p; 1231 u8 msg_data[ETH_ALEN * 2]; 1232 u16 subcode; 1233 int status; 1234 1235 ether_addr_copy(msg_data, new_mac_addr); 1236 ether_addr_copy(&msg_data[ETH_ALEN], old_mac_addr); 1237 1238 subcode = is_first ? HCLGE_MBX_MAC_VLAN_UC_ADD : 1239 HCLGE_MBX_MAC_VLAN_UC_MODIFY; 1240 1241 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 1242 subcode, msg_data, sizeof(msg_data), 1243 true, NULL, 0); 1244 if (!status) 1245 ether_addr_copy(hdev->hw.mac.mac_addr, new_mac_addr); 1246 1247 return status; 1248 } 1249 1250 static int hclgevf_add_uc_addr(struct hnae3_handle *handle, 1251 const unsigned char *addr) 1252 { 1253 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1254 1255 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 1256 HCLGE_MBX_MAC_VLAN_UC_ADD, 1257 addr, ETH_ALEN, false, NULL, 0); 1258 } 1259 1260 static int hclgevf_rm_uc_addr(struct hnae3_handle *handle, 1261 const unsigned char *addr) 1262 { 1263 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1264 1265 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 1266 HCLGE_MBX_MAC_VLAN_UC_REMOVE, 1267 addr, ETH_ALEN, false, NULL, 0); 1268 } 1269 1270 static int hclgevf_add_mc_addr(struct hnae3_handle *handle, 1271 const unsigned char *addr) 1272 { 1273 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1274 1275 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 1276 HCLGE_MBX_MAC_VLAN_MC_ADD, 1277 addr, ETH_ALEN, false, NULL, 0); 1278 } 1279 1280 static int hclgevf_rm_mc_addr(struct hnae3_handle *handle, 1281 const unsigned char *addr) 1282 { 1283 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1284 1285 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 1286 HCLGE_MBX_MAC_VLAN_MC_REMOVE, 1287 addr, ETH_ALEN, false, NULL, 0); 1288 } 1289 1290 static int hclgevf_set_vlan_filter(struct hnae3_handle *handle, 1291 __be16 proto, u16 vlan_id, 1292 bool is_kill) 1293 { 1294 #define HCLGEVF_VLAN_MBX_MSG_LEN 5 1295 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1296 u8 msg_data[HCLGEVF_VLAN_MBX_MSG_LEN]; 1297 int ret; 1298 1299 if (vlan_id > HCLGEVF_MAX_VLAN_ID) 1300 return -EINVAL; 1301 1302 if (proto != htons(ETH_P_8021Q)) 1303 return -EPROTONOSUPPORT; 1304 1305 /* When device is resetting, firmware is unable to handle 1306 * mailbox. Just record the vlan id, and remove it after 1307 * reset finished. 1308 */ 1309 if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) && is_kill) { 1310 set_bit(vlan_id, hdev->vlan_del_fail_bmap); 1311 return -EBUSY; 1312 } 1313 1314 msg_data[0] = is_kill; 1315 memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id)); 1316 memcpy(&msg_data[3], &proto, sizeof(proto)); 1317 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 1318 HCLGE_MBX_VLAN_FILTER, msg_data, 1319 HCLGEVF_VLAN_MBX_MSG_LEN, true, NULL, 0); 1320 1321 /* when remove hw vlan filter failed, record the vlan id, 1322 * and try to remove it from hw later, to be consistence 1323 * with stack. 1324 */ 1325 if (is_kill && ret) 1326 set_bit(vlan_id, hdev->vlan_del_fail_bmap); 1327 1328 return ret; 1329 } 1330 1331 static void hclgevf_sync_vlan_filter(struct hclgevf_dev *hdev) 1332 { 1333 #define HCLGEVF_MAX_SYNC_COUNT 60 1334 struct hnae3_handle *handle = &hdev->nic; 1335 int ret, sync_cnt = 0; 1336 u16 vlan_id; 1337 1338 vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID); 1339 while (vlan_id != VLAN_N_VID) { 1340 ret = hclgevf_set_vlan_filter(handle, htons(ETH_P_8021Q), 1341 vlan_id, true); 1342 if (ret) 1343 return; 1344 1345 clear_bit(vlan_id, hdev->vlan_del_fail_bmap); 1346 sync_cnt++; 1347 if (sync_cnt >= HCLGEVF_MAX_SYNC_COUNT) 1348 return; 1349 1350 vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID); 1351 } 1352 } 1353 1354 static int hclgevf_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) 1355 { 1356 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1357 u8 msg_data; 1358 1359 msg_data = enable ? 1 : 0; 1360 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 1361 HCLGE_MBX_VLAN_RX_OFF_CFG, &msg_data, 1362 1, false, NULL, 0); 1363 } 1364 1365 static int hclgevf_reset_tqp(struct hnae3_handle *handle, u16 queue_id) 1366 { 1367 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1368 u8 msg_data[2]; 1369 int ret; 1370 1371 memcpy(msg_data, &queue_id, sizeof(queue_id)); 1372 1373 /* disable vf queue before send queue reset msg to PF */ 1374 ret = hclgevf_tqp_enable(hdev, queue_id, 0, false); 1375 if (ret) 1376 return ret; 1377 1378 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_QUEUE_RESET, 0, msg_data, 1379 sizeof(msg_data), true, NULL, 0); 1380 } 1381 1382 static int hclgevf_set_mtu(struct hnae3_handle *handle, int new_mtu) 1383 { 1384 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1385 1386 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MTU, 0, (u8 *)&new_mtu, 1387 sizeof(new_mtu), true, NULL, 0); 1388 } 1389 1390 static int hclgevf_notify_client(struct hclgevf_dev *hdev, 1391 enum hnae3_reset_notify_type type) 1392 { 1393 struct hnae3_client *client = hdev->nic_client; 1394 struct hnae3_handle *handle = &hdev->nic; 1395 int ret; 1396 1397 if (!test_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state) || 1398 !client) 1399 return 0; 1400 1401 if (!client->ops->reset_notify) 1402 return -EOPNOTSUPP; 1403 1404 ret = client->ops->reset_notify(handle, type); 1405 if (ret) 1406 dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n", 1407 type, ret); 1408 1409 return ret; 1410 } 1411 1412 static void hclgevf_flr_done(struct hnae3_ae_dev *ae_dev) 1413 { 1414 struct hclgevf_dev *hdev = ae_dev->priv; 1415 1416 set_bit(HNAE3_FLR_DONE, &hdev->flr_state); 1417 } 1418 1419 static int hclgevf_flr_poll_timeout(struct hclgevf_dev *hdev, 1420 unsigned long delay_us, 1421 unsigned long wait_cnt) 1422 { 1423 unsigned long cnt = 0; 1424 1425 while (!test_bit(HNAE3_FLR_DONE, &hdev->flr_state) && 1426 cnt++ < wait_cnt) 1427 usleep_range(delay_us, delay_us * 2); 1428 1429 if (!test_bit(HNAE3_FLR_DONE, &hdev->flr_state)) { 1430 dev_err(&hdev->pdev->dev, 1431 "flr wait timeout\n"); 1432 return -ETIMEDOUT; 1433 } 1434 1435 return 0; 1436 } 1437 1438 static int hclgevf_reset_wait(struct hclgevf_dev *hdev) 1439 { 1440 #define HCLGEVF_RESET_WAIT_US 20000 1441 #define HCLGEVF_RESET_WAIT_CNT 2000 1442 #define HCLGEVF_RESET_WAIT_TIMEOUT_US \ 1443 (HCLGEVF_RESET_WAIT_US * HCLGEVF_RESET_WAIT_CNT) 1444 1445 u32 val; 1446 int ret; 1447 1448 if (hdev->reset_type == HNAE3_FLR_RESET) 1449 return hclgevf_flr_poll_timeout(hdev, 1450 HCLGEVF_RESET_WAIT_US, 1451 HCLGEVF_RESET_WAIT_CNT); 1452 else if (hdev->reset_type == HNAE3_VF_RESET) 1453 ret = readl_poll_timeout(hdev->hw.io_base + 1454 HCLGEVF_VF_RST_ING, val, 1455 !(val & HCLGEVF_VF_RST_ING_BIT), 1456 HCLGEVF_RESET_WAIT_US, 1457 HCLGEVF_RESET_WAIT_TIMEOUT_US); 1458 else 1459 ret = readl_poll_timeout(hdev->hw.io_base + 1460 HCLGEVF_RST_ING, val, 1461 !(val & HCLGEVF_RST_ING_BITS), 1462 HCLGEVF_RESET_WAIT_US, 1463 HCLGEVF_RESET_WAIT_TIMEOUT_US); 1464 1465 /* hardware completion status should be available by this time */ 1466 if (ret) { 1467 dev_err(&hdev->pdev->dev, 1468 "could'nt get reset done status from h/w, timeout!\n"); 1469 return ret; 1470 } 1471 1472 /* we will wait a bit more to let reset of the stack to complete. This 1473 * might happen in case reset assertion was made by PF. Yes, this also 1474 * means we might end up waiting bit more even for VF reset. 1475 */ 1476 msleep(5000); 1477 1478 return 0; 1479 } 1480 1481 static void hclgevf_reset_handshake(struct hclgevf_dev *hdev, bool enable) 1482 { 1483 u32 reg_val; 1484 1485 reg_val = hclgevf_read_dev(&hdev->hw, HCLGEVF_NIC_CSQ_DEPTH_REG); 1486 if (enable) 1487 reg_val |= HCLGEVF_NIC_SW_RST_RDY; 1488 else 1489 reg_val &= ~HCLGEVF_NIC_SW_RST_RDY; 1490 1491 hclgevf_write_dev(&hdev->hw, HCLGEVF_NIC_CSQ_DEPTH_REG, 1492 reg_val); 1493 } 1494 1495 static int hclgevf_reset_stack(struct hclgevf_dev *hdev) 1496 { 1497 int ret; 1498 1499 /* uninitialize the nic client */ 1500 ret = hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT); 1501 if (ret) 1502 return ret; 1503 1504 /* re-initialize the hclge device */ 1505 ret = hclgevf_reset_hdev(hdev); 1506 if (ret) { 1507 dev_err(&hdev->pdev->dev, 1508 "hclge device re-init failed, VF is disabled!\n"); 1509 return ret; 1510 } 1511 1512 /* bring up the nic client again */ 1513 ret = hclgevf_notify_client(hdev, HNAE3_INIT_CLIENT); 1514 if (ret) 1515 return ret; 1516 1517 ret = hclgevf_notify_client(hdev, HNAE3_RESTORE_CLIENT); 1518 if (ret) 1519 return ret; 1520 1521 /* clear handshake status with IMP */ 1522 hclgevf_reset_handshake(hdev, false); 1523 1524 return 0; 1525 } 1526 1527 static int hclgevf_reset_prepare_wait(struct hclgevf_dev *hdev) 1528 { 1529 #define HCLGEVF_RESET_SYNC_TIME 100 1530 1531 int ret = 0; 1532 1533 switch (hdev->reset_type) { 1534 case HNAE3_VF_FUNC_RESET: 1535 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_RESET, 0, NULL, 1536 0, true, NULL, sizeof(u8)); 1537 hdev->rst_stats.vf_func_rst_cnt++; 1538 break; 1539 case HNAE3_FLR_RESET: 1540 set_bit(HNAE3_FLR_DOWN, &hdev->flr_state); 1541 hdev->rst_stats.flr_rst_cnt++; 1542 break; 1543 default: 1544 break; 1545 } 1546 1547 set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 1548 /* inform hardware that preparatory work is done */ 1549 msleep(HCLGEVF_RESET_SYNC_TIME); 1550 hclgevf_reset_handshake(hdev, true); 1551 dev_info(&hdev->pdev->dev, "prepare reset(%d) wait done, ret:%d\n", 1552 hdev->reset_type, ret); 1553 1554 return ret; 1555 } 1556 1557 static void hclgevf_dump_rst_info(struct hclgevf_dev *hdev) 1558 { 1559 dev_info(&hdev->pdev->dev, "VF function reset count: %u\n", 1560 hdev->rst_stats.vf_func_rst_cnt); 1561 dev_info(&hdev->pdev->dev, "FLR reset count: %u\n", 1562 hdev->rst_stats.flr_rst_cnt); 1563 dev_info(&hdev->pdev->dev, "VF reset count: %u\n", 1564 hdev->rst_stats.vf_rst_cnt); 1565 dev_info(&hdev->pdev->dev, "reset done count: %u\n", 1566 hdev->rst_stats.rst_done_cnt); 1567 dev_info(&hdev->pdev->dev, "HW reset done count: %u\n", 1568 hdev->rst_stats.hw_rst_done_cnt); 1569 dev_info(&hdev->pdev->dev, "reset count: %u\n", 1570 hdev->rst_stats.rst_cnt); 1571 dev_info(&hdev->pdev->dev, "reset fail count: %u\n", 1572 hdev->rst_stats.rst_fail_cnt); 1573 dev_info(&hdev->pdev->dev, "vector0 interrupt enable status: 0x%x\n", 1574 hclgevf_read_dev(&hdev->hw, HCLGEVF_MISC_VECTOR_REG_BASE)); 1575 dev_info(&hdev->pdev->dev, "vector0 interrupt status: 0x%x\n", 1576 hclgevf_read_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_STAT_REG)); 1577 dev_info(&hdev->pdev->dev, "handshake status: 0x%x\n", 1578 hclgevf_read_dev(&hdev->hw, HCLGEVF_CMDQ_TX_DEPTH_REG)); 1579 dev_info(&hdev->pdev->dev, "function reset status: 0x%x\n", 1580 hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING)); 1581 dev_info(&hdev->pdev->dev, "hdev state: 0x%lx\n", hdev->state); 1582 } 1583 1584 static void hclgevf_reset_err_handle(struct hclgevf_dev *hdev) 1585 { 1586 /* recover handshake status with IMP when reset fail */ 1587 hclgevf_reset_handshake(hdev, true); 1588 hdev->rst_stats.rst_fail_cnt++; 1589 dev_err(&hdev->pdev->dev, "failed to reset VF(%u)\n", 1590 hdev->rst_stats.rst_fail_cnt); 1591 1592 if (hdev->rst_stats.rst_fail_cnt < HCLGEVF_RESET_MAX_FAIL_CNT) 1593 set_bit(hdev->reset_type, &hdev->reset_pending); 1594 1595 if (hclgevf_is_reset_pending(hdev)) { 1596 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1597 hclgevf_reset_task_schedule(hdev); 1598 } else { 1599 hclgevf_dump_rst_info(hdev); 1600 } 1601 } 1602 1603 static int hclgevf_reset(struct hclgevf_dev *hdev) 1604 { 1605 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1606 int ret; 1607 1608 /* Initialize ae_dev reset status as well, in case enet layer wants to 1609 * know if device is undergoing reset 1610 */ 1611 ae_dev->reset_type = hdev->reset_type; 1612 hdev->rst_stats.rst_cnt++; 1613 rtnl_lock(); 1614 1615 /* bring down the nic to stop any ongoing TX/RX */ 1616 ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 1617 if (ret) 1618 goto err_reset_lock; 1619 1620 rtnl_unlock(); 1621 1622 ret = hclgevf_reset_prepare_wait(hdev); 1623 if (ret) 1624 goto err_reset; 1625 1626 /* check if VF could successfully fetch the hardware reset completion 1627 * status from the hardware 1628 */ 1629 ret = hclgevf_reset_wait(hdev); 1630 if (ret) { 1631 /* can't do much in this situation, will disable VF */ 1632 dev_err(&hdev->pdev->dev, 1633 "VF failed(=%d) to fetch H/W reset completion status\n", 1634 ret); 1635 goto err_reset; 1636 } 1637 1638 hdev->rst_stats.hw_rst_done_cnt++; 1639 1640 rtnl_lock(); 1641 1642 /* now, re-initialize the nic client and ae device */ 1643 ret = hclgevf_reset_stack(hdev); 1644 if (ret) { 1645 dev_err(&hdev->pdev->dev, "failed to reset VF stack\n"); 1646 goto err_reset_lock; 1647 } 1648 1649 /* bring up the nic to enable TX/RX again */ 1650 ret = hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 1651 if (ret) 1652 goto err_reset_lock; 1653 1654 rtnl_unlock(); 1655 1656 hdev->last_reset_time = jiffies; 1657 ae_dev->reset_type = HNAE3_NONE_RESET; 1658 hdev->rst_stats.rst_done_cnt++; 1659 hdev->rst_stats.rst_fail_cnt = 0; 1660 1661 return ret; 1662 err_reset_lock: 1663 rtnl_unlock(); 1664 err_reset: 1665 hclgevf_reset_err_handle(hdev); 1666 1667 return ret; 1668 } 1669 1670 static enum hnae3_reset_type hclgevf_get_reset_level(struct hclgevf_dev *hdev, 1671 unsigned long *addr) 1672 { 1673 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; 1674 1675 /* return the highest priority reset level amongst all */ 1676 if (test_bit(HNAE3_VF_RESET, addr)) { 1677 rst_level = HNAE3_VF_RESET; 1678 clear_bit(HNAE3_VF_RESET, addr); 1679 clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1680 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1681 } else if (test_bit(HNAE3_VF_FULL_RESET, addr)) { 1682 rst_level = HNAE3_VF_FULL_RESET; 1683 clear_bit(HNAE3_VF_FULL_RESET, addr); 1684 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1685 } else if (test_bit(HNAE3_VF_PF_FUNC_RESET, addr)) { 1686 rst_level = HNAE3_VF_PF_FUNC_RESET; 1687 clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1688 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1689 } else if (test_bit(HNAE3_VF_FUNC_RESET, addr)) { 1690 rst_level = HNAE3_VF_FUNC_RESET; 1691 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1692 } else if (test_bit(HNAE3_FLR_RESET, addr)) { 1693 rst_level = HNAE3_FLR_RESET; 1694 clear_bit(HNAE3_FLR_RESET, addr); 1695 } 1696 1697 return rst_level; 1698 } 1699 1700 static void hclgevf_reset_event(struct pci_dev *pdev, 1701 struct hnae3_handle *handle) 1702 { 1703 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 1704 struct hclgevf_dev *hdev = ae_dev->priv; 1705 1706 dev_info(&hdev->pdev->dev, "received reset request from VF enet\n"); 1707 1708 if (hdev->default_reset_request) 1709 hdev->reset_level = 1710 hclgevf_get_reset_level(hdev, 1711 &hdev->default_reset_request); 1712 else 1713 hdev->reset_level = HNAE3_VF_FUNC_RESET; 1714 1715 /* reset of this VF requested */ 1716 set_bit(HCLGEVF_RESET_REQUESTED, &hdev->reset_state); 1717 hclgevf_reset_task_schedule(hdev); 1718 1719 hdev->last_reset_time = jiffies; 1720 } 1721 1722 static void hclgevf_set_def_reset_request(struct hnae3_ae_dev *ae_dev, 1723 enum hnae3_reset_type rst_type) 1724 { 1725 struct hclgevf_dev *hdev = ae_dev->priv; 1726 1727 set_bit(rst_type, &hdev->default_reset_request); 1728 } 1729 1730 static void hclgevf_flr_prepare(struct hnae3_ae_dev *ae_dev) 1731 { 1732 #define HCLGEVF_FLR_WAIT_MS 100 1733 #define HCLGEVF_FLR_WAIT_CNT 50 1734 struct hclgevf_dev *hdev = ae_dev->priv; 1735 int cnt = 0; 1736 1737 clear_bit(HNAE3_FLR_DOWN, &hdev->flr_state); 1738 clear_bit(HNAE3_FLR_DONE, &hdev->flr_state); 1739 set_bit(HNAE3_FLR_RESET, &hdev->default_reset_request); 1740 hclgevf_reset_event(hdev->pdev, NULL); 1741 1742 while (!test_bit(HNAE3_FLR_DOWN, &hdev->flr_state) && 1743 cnt++ < HCLGEVF_FLR_WAIT_CNT) 1744 msleep(HCLGEVF_FLR_WAIT_MS); 1745 1746 if (!test_bit(HNAE3_FLR_DOWN, &hdev->flr_state)) 1747 dev_err(&hdev->pdev->dev, 1748 "flr wait down timeout: %d\n", cnt); 1749 } 1750 1751 static u32 hclgevf_get_fw_version(struct hnae3_handle *handle) 1752 { 1753 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1754 1755 return hdev->fw_version; 1756 } 1757 1758 static void hclgevf_get_misc_vector(struct hclgevf_dev *hdev) 1759 { 1760 struct hclgevf_misc_vector *vector = &hdev->misc_vector; 1761 1762 vector->vector_irq = pci_irq_vector(hdev->pdev, 1763 HCLGEVF_MISC_VECTOR_NUM); 1764 vector->addr = hdev->hw.io_base + HCLGEVF_MISC_VECTOR_REG_BASE; 1765 /* vector status always valid for Vector 0 */ 1766 hdev->vector_status[HCLGEVF_MISC_VECTOR_NUM] = 0; 1767 hdev->vector_irq[HCLGEVF_MISC_VECTOR_NUM] = vector->vector_irq; 1768 1769 hdev->num_msi_left -= 1; 1770 hdev->num_msi_used += 1; 1771 } 1772 1773 void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev) 1774 { 1775 if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) && 1776 !test_and_set_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, 1777 &hdev->state)) 1778 mod_delayed_work(system_wq, &hdev->service_task, 0); 1779 } 1780 1781 void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev) 1782 { 1783 if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) && 1784 !test_and_set_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, 1785 &hdev->state)) 1786 mod_delayed_work(system_wq, &hdev->service_task, 0); 1787 } 1788 1789 static void hclgevf_task_schedule(struct hclgevf_dev *hdev, 1790 unsigned long delay) 1791 { 1792 if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state)) 1793 mod_delayed_work(system_wq, &hdev->service_task, delay); 1794 } 1795 1796 static void hclgevf_reset_service_task(struct hclgevf_dev *hdev) 1797 { 1798 #define HCLGEVF_MAX_RESET_ATTEMPTS_CNT 3 1799 1800 int ret; 1801 1802 if (!test_and_clear_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state)) 1803 return; 1804 1805 if (test_and_set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 1806 return; 1807 1808 if (test_and_clear_bit(HCLGEVF_RESET_PENDING, 1809 &hdev->reset_state)) { 1810 /* PF has initmated that it is about to reset the hardware. 1811 * We now have to poll & check if hardware has actually 1812 * completed the reset sequence. On hardware reset completion, 1813 * VF needs to reset the client and ae device. 1814 */ 1815 hdev->reset_attempts = 0; 1816 1817 hdev->last_reset_time = jiffies; 1818 while ((hdev->reset_type = 1819 hclgevf_get_reset_level(hdev, &hdev->reset_pending)) 1820 != HNAE3_NONE_RESET) { 1821 ret = hclgevf_reset(hdev); 1822 if (ret) 1823 dev_err(&hdev->pdev->dev, 1824 "VF stack reset failed %d.\n", ret); 1825 } 1826 } else if (test_and_clear_bit(HCLGEVF_RESET_REQUESTED, 1827 &hdev->reset_state)) { 1828 /* we could be here when either of below happens: 1829 * 1. reset was initiated due to watchdog timeout caused by 1830 * a. IMP was earlier reset and our TX got choked down and 1831 * which resulted in watchdog reacting and inducing VF 1832 * reset. This also means our cmdq would be unreliable. 1833 * b. problem in TX due to other lower layer(example link 1834 * layer not functioning properly etc.) 1835 * 2. VF reset might have been initiated due to some config 1836 * change. 1837 * 1838 * NOTE: Theres no clear way to detect above cases than to react 1839 * to the response of PF for this reset request. PF will ack the 1840 * 1b and 2. cases but we will not get any intimation about 1a 1841 * from PF as cmdq would be in unreliable state i.e. mailbox 1842 * communication between PF and VF would be broken. 1843 * 1844 * if we are never geting into pending state it means either: 1845 * 1. PF is not receiving our request which could be due to IMP 1846 * reset 1847 * 2. PF is screwed 1848 * We cannot do much for 2. but to check first we can try reset 1849 * our PCIe + stack and see if it alleviates the problem. 1850 */ 1851 if (hdev->reset_attempts > HCLGEVF_MAX_RESET_ATTEMPTS_CNT) { 1852 /* prepare for full reset of stack + pcie interface */ 1853 set_bit(HNAE3_VF_FULL_RESET, &hdev->reset_pending); 1854 1855 /* "defer" schedule the reset task again */ 1856 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1857 } else { 1858 hdev->reset_attempts++; 1859 1860 set_bit(hdev->reset_level, &hdev->reset_pending); 1861 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1862 } 1863 hclgevf_reset_task_schedule(hdev); 1864 } 1865 1866 clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 1867 } 1868 1869 static void hclgevf_mailbox_service_task(struct hclgevf_dev *hdev) 1870 { 1871 if (!test_and_clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state)) 1872 return; 1873 1874 if (test_and_set_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) 1875 return; 1876 1877 hclgevf_mbx_async_handler(hdev); 1878 1879 clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 1880 } 1881 1882 static void hclgevf_keep_alive(struct hclgevf_dev *hdev) 1883 { 1884 u8 respmsg; 1885 int ret; 1886 1887 if (test_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state)) 1888 return; 1889 1890 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_KEEP_ALIVE, 0, NULL, 1891 0, false, &respmsg, sizeof(respmsg)); 1892 if (ret) 1893 dev_err(&hdev->pdev->dev, 1894 "VF sends keep alive cmd failed(=%d)\n", ret); 1895 } 1896 1897 static void hclgevf_periodic_service_task(struct hclgevf_dev *hdev) 1898 { 1899 unsigned long delta = round_jiffies_relative(HZ); 1900 struct hnae3_handle *handle = &hdev->nic; 1901 1902 if (time_is_after_jiffies(hdev->last_serv_processed + HZ)) { 1903 delta = jiffies - hdev->last_serv_processed; 1904 1905 if (delta < round_jiffies_relative(HZ)) { 1906 delta = round_jiffies_relative(HZ) - delta; 1907 goto out; 1908 } 1909 } 1910 1911 hdev->serv_processed_cnt++; 1912 if (!(hdev->serv_processed_cnt % HCLGEVF_KEEP_ALIVE_TASK_INTERVAL)) 1913 hclgevf_keep_alive(hdev); 1914 1915 if (test_bit(HCLGEVF_STATE_DOWN, &hdev->state)) { 1916 hdev->last_serv_processed = jiffies; 1917 goto out; 1918 } 1919 1920 if (!(hdev->serv_processed_cnt % HCLGEVF_STATS_TIMER_INTERVAL)) 1921 hclgevf_tqps_update_stats(handle); 1922 1923 /* request the link status from the PF. PF would be able to tell VF 1924 * about such updates in future so we might remove this later 1925 */ 1926 hclgevf_request_link_info(hdev); 1927 1928 hclgevf_update_link_mode(hdev); 1929 1930 hclgevf_sync_vlan_filter(hdev); 1931 1932 hdev->last_serv_processed = jiffies; 1933 1934 out: 1935 hclgevf_task_schedule(hdev, delta); 1936 } 1937 1938 static void hclgevf_service_task(struct work_struct *work) 1939 { 1940 struct hclgevf_dev *hdev = container_of(work, struct hclgevf_dev, 1941 service_task.work); 1942 1943 hclgevf_reset_service_task(hdev); 1944 hclgevf_mailbox_service_task(hdev); 1945 hclgevf_periodic_service_task(hdev); 1946 1947 /* Handle reset and mbx again in case periodical task delays the 1948 * handling by calling hclgevf_task_schedule() in 1949 * hclgevf_periodic_service_task() 1950 */ 1951 hclgevf_reset_service_task(hdev); 1952 hclgevf_mailbox_service_task(hdev); 1953 } 1954 1955 static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regclr) 1956 { 1957 hclgevf_write_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_SRC_REG, regclr); 1958 } 1959 1960 static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev, 1961 u32 *clearval) 1962 { 1963 u32 val, cmdq_stat_reg, rst_ing_reg; 1964 1965 /* fetch the events from their corresponding regs */ 1966 cmdq_stat_reg = hclgevf_read_dev(&hdev->hw, 1967 HCLGEVF_VECTOR0_CMDQ_STAT_REG); 1968 1969 if (BIT(HCLGEVF_VECTOR0_RST_INT_B) & cmdq_stat_reg) { 1970 rst_ing_reg = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 1971 dev_info(&hdev->pdev->dev, 1972 "receive reset interrupt 0x%x!\n", rst_ing_reg); 1973 set_bit(HNAE3_VF_RESET, &hdev->reset_pending); 1974 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1975 set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 1976 *clearval = ~(1U << HCLGEVF_VECTOR0_RST_INT_B); 1977 hdev->rst_stats.vf_rst_cnt++; 1978 /* set up VF hardware reset status, its PF will clear 1979 * this status when PF has initialized done. 1980 */ 1981 val = hclgevf_read_dev(&hdev->hw, HCLGEVF_VF_RST_ING); 1982 hclgevf_write_dev(&hdev->hw, HCLGEVF_VF_RST_ING, 1983 val | HCLGEVF_VF_RST_ING_BIT); 1984 return HCLGEVF_VECTOR0_EVENT_RST; 1985 } 1986 1987 /* check for vector0 mailbox(=CMDQ RX) event source */ 1988 if (BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) { 1989 /* for revision 0x21, clearing interrupt is writing bit 0 1990 * to the clear register, writing bit 1 means to keep the 1991 * old value. 1992 * for revision 0x20, the clear register is a read & write 1993 * register, so we should just write 0 to the bit we are 1994 * handling, and keep other bits as cmdq_stat_reg. 1995 */ 1996 if (hdev->pdev->revision >= 0x21) 1997 *clearval = ~(1U << HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 1998 else 1999 *clearval = cmdq_stat_reg & 2000 ~BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 2001 2002 return HCLGEVF_VECTOR0_EVENT_MBX; 2003 } 2004 2005 dev_dbg(&hdev->pdev->dev, "vector 0 interrupt from unknown source\n"); 2006 2007 return HCLGEVF_VECTOR0_EVENT_OTHER; 2008 } 2009 2010 static void hclgevf_enable_vector(struct hclgevf_misc_vector *vector, bool en) 2011 { 2012 writel(en ? 1 : 0, vector->addr); 2013 } 2014 2015 static irqreturn_t hclgevf_misc_irq_handle(int irq, void *data) 2016 { 2017 enum hclgevf_evt_cause event_cause; 2018 struct hclgevf_dev *hdev = data; 2019 u32 clearval; 2020 2021 hclgevf_enable_vector(&hdev->misc_vector, false); 2022 event_cause = hclgevf_check_evt_cause(hdev, &clearval); 2023 2024 switch (event_cause) { 2025 case HCLGEVF_VECTOR0_EVENT_RST: 2026 hclgevf_reset_task_schedule(hdev); 2027 break; 2028 case HCLGEVF_VECTOR0_EVENT_MBX: 2029 hclgevf_mbx_handler(hdev); 2030 break; 2031 default: 2032 break; 2033 } 2034 2035 if (event_cause != HCLGEVF_VECTOR0_EVENT_OTHER) { 2036 hclgevf_clear_event_cause(hdev, clearval); 2037 hclgevf_enable_vector(&hdev->misc_vector, true); 2038 } 2039 2040 return IRQ_HANDLED; 2041 } 2042 2043 static int hclgevf_configure(struct hclgevf_dev *hdev) 2044 { 2045 int ret; 2046 2047 /* get current port based vlan state from PF */ 2048 ret = hclgevf_get_port_base_vlan_filter_state(hdev); 2049 if (ret) 2050 return ret; 2051 2052 /* get queue configuration from PF */ 2053 ret = hclgevf_get_queue_info(hdev); 2054 if (ret) 2055 return ret; 2056 2057 /* get queue depth info from PF */ 2058 ret = hclgevf_get_queue_depth(hdev); 2059 if (ret) 2060 return ret; 2061 2062 ret = hclgevf_get_pf_media_type(hdev); 2063 if (ret) 2064 return ret; 2065 2066 /* get tc configuration from PF */ 2067 return hclgevf_get_tc_info(hdev); 2068 } 2069 2070 static int hclgevf_alloc_hdev(struct hnae3_ae_dev *ae_dev) 2071 { 2072 struct pci_dev *pdev = ae_dev->pdev; 2073 struct hclgevf_dev *hdev; 2074 2075 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 2076 if (!hdev) 2077 return -ENOMEM; 2078 2079 hdev->pdev = pdev; 2080 hdev->ae_dev = ae_dev; 2081 ae_dev->priv = hdev; 2082 2083 return 0; 2084 } 2085 2086 static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev) 2087 { 2088 struct hnae3_handle *roce = &hdev->roce; 2089 struct hnae3_handle *nic = &hdev->nic; 2090 2091 roce->rinfo.num_vectors = hdev->num_roce_msix; 2092 2093 if (hdev->num_msi_left < roce->rinfo.num_vectors || 2094 hdev->num_msi_left == 0) 2095 return -EINVAL; 2096 2097 roce->rinfo.base_vector = hdev->roce_base_vector; 2098 2099 roce->rinfo.netdev = nic->kinfo.netdev; 2100 roce->rinfo.roce_io_base = hdev->hw.io_base; 2101 2102 roce->pdev = nic->pdev; 2103 roce->ae_algo = nic->ae_algo; 2104 roce->numa_node_mask = nic->numa_node_mask; 2105 2106 return 0; 2107 } 2108 2109 static int hclgevf_config_gro(struct hclgevf_dev *hdev, bool en) 2110 { 2111 struct hclgevf_cfg_gro_status_cmd *req; 2112 struct hclgevf_desc desc; 2113 int ret; 2114 2115 if (!hnae3_dev_gro_supported(hdev)) 2116 return 0; 2117 2118 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_GRO_GENERIC_CONFIG, 2119 false); 2120 req = (struct hclgevf_cfg_gro_status_cmd *)desc.data; 2121 2122 req->gro_en = cpu_to_le16(en ? 1 : 0); 2123 2124 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 2125 if (ret) 2126 dev_err(&hdev->pdev->dev, 2127 "VF GRO hardware config cmd failed, ret = %d.\n", ret); 2128 2129 return ret; 2130 } 2131 2132 static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev) 2133 { 2134 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 2135 int ret; 2136 u32 i; 2137 2138 rss_cfg->rss_size = hdev->nic.kinfo.rss_size; 2139 2140 if (hdev->pdev->revision >= 0x21) { 2141 rss_cfg->hash_algo = HCLGEVF_RSS_HASH_ALGO_SIMPLE; 2142 memcpy(rss_cfg->rss_hash_key, hclgevf_hash_key, 2143 HCLGEVF_RSS_KEY_SIZE); 2144 2145 ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 2146 rss_cfg->rss_hash_key); 2147 if (ret) 2148 return ret; 2149 2150 rss_cfg->rss_tuple_sets.ipv4_tcp_en = 2151 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2152 rss_cfg->rss_tuple_sets.ipv4_udp_en = 2153 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2154 rss_cfg->rss_tuple_sets.ipv4_sctp_en = 2155 HCLGEVF_RSS_INPUT_TUPLE_SCTP; 2156 rss_cfg->rss_tuple_sets.ipv4_fragment_en = 2157 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2158 rss_cfg->rss_tuple_sets.ipv6_tcp_en = 2159 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2160 rss_cfg->rss_tuple_sets.ipv6_udp_en = 2161 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2162 rss_cfg->rss_tuple_sets.ipv6_sctp_en = 2163 HCLGEVF_RSS_INPUT_TUPLE_SCTP; 2164 rss_cfg->rss_tuple_sets.ipv6_fragment_en = 2165 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2166 2167 ret = hclgevf_set_rss_input_tuple(hdev, rss_cfg); 2168 if (ret) 2169 return ret; 2170 } 2171 2172 /* Initialize RSS indirect table */ 2173 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 2174 rss_cfg->rss_indirection_tbl[i] = i % rss_cfg->rss_size; 2175 2176 ret = hclgevf_set_rss_indir_table(hdev); 2177 if (ret) 2178 return ret; 2179 2180 return hclgevf_set_rss_tc_mode(hdev, rss_cfg->rss_size); 2181 } 2182 2183 static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev) 2184 { 2185 return hclgevf_set_vlan_filter(&hdev->nic, htons(ETH_P_8021Q), 0, 2186 false); 2187 } 2188 2189 static void hclgevf_flush_link_update(struct hclgevf_dev *hdev) 2190 { 2191 #define HCLGEVF_FLUSH_LINK_TIMEOUT 100000 2192 2193 unsigned long last = hdev->serv_processed_cnt; 2194 int i = 0; 2195 2196 while (test_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state) && 2197 i++ < HCLGEVF_FLUSH_LINK_TIMEOUT && 2198 last == hdev->serv_processed_cnt) 2199 usleep_range(1, 1); 2200 } 2201 2202 static void hclgevf_set_timer_task(struct hnae3_handle *handle, bool enable) 2203 { 2204 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2205 2206 if (enable) { 2207 hclgevf_task_schedule(hdev, 0); 2208 } else { 2209 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2210 2211 /* flush memory to make sure DOWN is seen by service task */ 2212 smp_mb__before_atomic(); 2213 hclgevf_flush_link_update(hdev); 2214 } 2215 } 2216 2217 static int hclgevf_ae_start(struct hnae3_handle *handle) 2218 { 2219 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2220 2221 hclgevf_reset_tqp_stats(handle); 2222 2223 hclgevf_request_link_info(hdev); 2224 2225 hclgevf_update_link_mode(hdev); 2226 2227 clear_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2228 2229 return 0; 2230 } 2231 2232 static void hclgevf_ae_stop(struct hnae3_handle *handle) 2233 { 2234 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2235 int i; 2236 2237 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2238 2239 if (hdev->reset_type != HNAE3_VF_RESET) 2240 for (i = 0; i < handle->kinfo.num_tqps; i++) 2241 if (hclgevf_reset_tqp(handle, i)) 2242 break; 2243 2244 hclgevf_reset_tqp_stats(handle); 2245 hclgevf_update_link_status(hdev, 0); 2246 } 2247 2248 static int hclgevf_set_alive(struct hnae3_handle *handle, bool alive) 2249 { 2250 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2251 u8 msg_data; 2252 2253 msg_data = alive ? 1 : 0; 2254 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_ALIVE, 2255 0, &msg_data, 1, false, NULL, 0); 2256 } 2257 2258 static int hclgevf_client_start(struct hnae3_handle *handle) 2259 { 2260 int ret; 2261 2262 ret = hclgevf_set_alive(handle, true); 2263 if (ret) 2264 return ret; 2265 2266 return 0; 2267 } 2268 2269 static void hclgevf_client_stop(struct hnae3_handle *handle) 2270 { 2271 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2272 int ret; 2273 2274 ret = hclgevf_set_alive(handle, false); 2275 if (ret) 2276 dev_warn(&hdev->pdev->dev, 2277 "%s failed %d\n", __func__, ret); 2278 } 2279 2280 static void hclgevf_state_init(struct hclgevf_dev *hdev) 2281 { 2282 clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 2283 clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 2284 2285 INIT_DELAYED_WORK(&hdev->service_task, hclgevf_service_task); 2286 2287 mutex_init(&hdev->mbx_resp.mbx_mutex); 2288 2289 /* bring the device down */ 2290 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2291 } 2292 2293 static void hclgevf_state_uninit(struct hclgevf_dev *hdev) 2294 { 2295 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2296 set_bit(HCLGEVF_STATE_REMOVING, &hdev->state); 2297 2298 if (hdev->service_task.work.func) 2299 cancel_delayed_work_sync(&hdev->service_task); 2300 2301 mutex_destroy(&hdev->mbx_resp.mbx_mutex); 2302 } 2303 2304 static int hclgevf_init_msi(struct hclgevf_dev *hdev) 2305 { 2306 struct pci_dev *pdev = hdev->pdev; 2307 int vectors; 2308 int i; 2309 2310 if (hnae3_dev_roce_supported(hdev)) 2311 vectors = pci_alloc_irq_vectors(pdev, 2312 hdev->roce_base_msix_offset + 1, 2313 hdev->num_msi, 2314 PCI_IRQ_MSIX); 2315 else 2316 vectors = pci_alloc_irq_vectors(pdev, HNAE3_MIN_VECTOR_NUM, 2317 hdev->num_msi, 2318 PCI_IRQ_MSI | PCI_IRQ_MSIX); 2319 2320 if (vectors < 0) { 2321 dev_err(&pdev->dev, 2322 "failed(%d) to allocate MSI/MSI-X vectors\n", 2323 vectors); 2324 return vectors; 2325 } 2326 if (vectors < hdev->num_msi) 2327 dev_warn(&hdev->pdev->dev, 2328 "requested %u MSI/MSI-X, but allocated %d MSI/MSI-X\n", 2329 hdev->num_msi, vectors); 2330 2331 hdev->num_msi = vectors; 2332 hdev->num_msi_left = vectors; 2333 2334 hdev->base_msi_vector = pdev->irq; 2335 hdev->roce_base_vector = pdev->irq + hdev->roce_base_msix_offset; 2336 2337 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 2338 sizeof(u16), GFP_KERNEL); 2339 if (!hdev->vector_status) { 2340 pci_free_irq_vectors(pdev); 2341 return -ENOMEM; 2342 } 2343 2344 for (i = 0; i < hdev->num_msi; i++) 2345 hdev->vector_status[i] = HCLGEVF_INVALID_VPORT; 2346 2347 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 2348 sizeof(int), GFP_KERNEL); 2349 if (!hdev->vector_irq) { 2350 devm_kfree(&pdev->dev, hdev->vector_status); 2351 pci_free_irq_vectors(pdev); 2352 return -ENOMEM; 2353 } 2354 2355 return 0; 2356 } 2357 2358 static void hclgevf_uninit_msi(struct hclgevf_dev *hdev) 2359 { 2360 struct pci_dev *pdev = hdev->pdev; 2361 2362 devm_kfree(&pdev->dev, hdev->vector_status); 2363 devm_kfree(&pdev->dev, hdev->vector_irq); 2364 pci_free_irq_vectors(pdev); 2365 } 2366 2367 static int hclgevf_misc_irq_init(struct hclgevf_dev *hdev) 2368 { 2369 int ret; 2370 2371 hclgevf_get_misc_vector(hdev); 2372 2373 ret = request_irq(hdev->misc_vector.vector_irq, hclgevf_misc_irq_handle, 2374 0, "hclgevf_cmd", hdev); 2375 if (ret) { 2376 dev_err(&hdev->pdev->dev, "VF failed to request misc irq(%d)\n", 2377 hdev->misc_vector.vector_irq); 2378 return ret; 2379 } 2380 2381 hclgevf_clear_event_cause(hdev, 0); 2382 2383 /* enable misc. vector(vector 0) */ 2384 hclgevf_enable_vector(&hdev->misc_vector, true); 2385 2386 return ret; 2387 } 2388 2389 static void hclgevf_misc_irq_uninit(struct hclgevf_dev *hdev) 2390 { 2391 /* disable misc vector(vector 0) */ 2392 hclgevf_enable_vector(&hdev->misc_vector, false); 2393 synchronize_irq(hdev->misc_vector.vector_irq); 2394 free_irq(hdev->misc_vector.vector_irq, hdev); 2395 hclgevf_free_vector(hdev, 0); 2396 } 2397 2398 static void hclgevf_info_show(struct hclgevf_dev *hdev) 2399 { 2400 struct device *dev = &hdev->pdev->dev; 2401 2402 dev_info(dev, "VF info begin:\n"); 2403 2404 dev_info(dev, "Task queue pairs numbers: %u\n", hdev->num_tqps); 2405 dev_info(dev, "Desc num per TX queue: %u\n", hdev->num_tx_desc); 2406 dev_info(dev, "Desc num per RX queue: %u\n", hdev->num_rx_desc); 2407 dev_info(dev, "Numbers of vports: %u\n", hdev->num_alloc_vport); 2408 dev_info(dev, "HW tc map: 0x%x\n", hdev->hw_tc_map); 2409 dev_info(dev, "PF media type of this VF: %u\n", 2410 hdev->hw.mac.media_type); 2411 2412 dev_info(dev, "VF info end.\n"); 2413 } 2414 2415 static int hclgevf_init_nic_client_instance(struct hnae3_ae_dev *ae_dev, 2416 struct hnae3_client *client) 2417 { 2418 struct hclgevf_dev *hdev = ae_dev->priv; 2419 int ret; 2420 2421 ret = client->ops->init_instance(&hdev->nic); 2422 if (ret) 2423 return ret; 2424 2425 set_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 2426 hnae3_set_client_init_flag(client, ae_dev, 1); 2427 2428 if (netif_msg_drv(&hdev->nic)) 2429 hclgevf_info_show(hdev); 2430 2431 return 0; 2432 } 2433 2434 static int hclgevf_init_roce_client_instance(struct hnae3_ae_dev *ae_dev, 2435 struct hnae3_client *client) 2436 { 2437 struct hclgevf_dev *hdev = ae_dev->priv; 2438 int ret; 2439 2440 if (!hnae3_dev_roce_supported(hdev) || !hdev->roce_client || 2441 !hdev->nic_client) 2442 return 0; 2443 2444 ret = hclgevf_init_roce_base_info(hdev); 2445 if (ret) 2446 return ret; 2447 2448 ret = client->ops->init_instance(&hdev->roce); 2449 if (ret) 2450 return ret; 2451 2452 hnae3_set_client_init_flag(client, ae_dev, 1); 2453 2454 return 0; 2455 } 2456 2457 static int hclgevf_init_client_instance(struct hnae3_client *client, 2458 struct hnae3_ae_dev *ae_dev) 2459 { 2460 struct hclgevf_dev *hdev = ae_dev->priv; 2461 int ret; 2462 2463 switch (client->type) { 2464 case HNAE3_CLIENT_KNIC: 2465 hdev->nic_client = client; 2466 hdev->nic.client = client; 2467 2468 ret = hclgevf_init_nic_client_instance(ae_dev, client); 2469 if (ret) 2470 goto clear_nic; 2471 2472 ret = hclgevf_init_roce_client_instance(ae_dev, 2473 hdev->roce_client); 2474 if (ret) 2475 goto clear_roce; 2476 2477 break; 2478 case HNAE3_CLIENT_ROCE: 2479 if (hnae3_dev_roce_supported(hdev)) { 2480 hdev->roce_client = client; 2481 hdev->roce.client = client; 2482 } 2483 2484 ret = hclgevf_init_roce_client_instance(ae_dev, client); 2485 if (ret) 2486 goto clear_roce; 2487 2488 break; 2489 default: 2490 return -EINVAL; 2491 } 2492 2493 return 0; 2494 2495 clear_nic: 2496 hdev->nic_client = NULL; 2497 hdev->nic.client = NULL; 2498 return ret; 2499 clear_roce: 2500 hdev->roce_client = NULL; 2501 hdev->roce.client = NULL; 2502 return ret; 2503 } 2504 2505 static void hclgevf_uninit_client_instance(struct hnae3_client *client, 2506 struct hnae3_ae_dev *ae_dev) 2507 { 2508 struct hclgevf_dev *hdev = ae_dev->priv; 2509 2510 /* un-init roce, if it exists */ 2511 if (hdev->roce_client) { 2512 hdev->roce_client->ops->uninit_instance(&hdev->roce, 0); 2513 hdev->roce_client = NULL; 2514 hdev->roce.client = NULL; 2515 } 2516 2517 /* un-init nic/unic, if this was not called by roce client */ 2518 if (client->ops->uninit_instance && hdev->nic_client && 2519 client->type != HNAE3_CLIENT_ROCE) { 2520 clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 2521 2522 client->ops->uninit_instance(&hdev->nic, 0); 2523 hdev->nic_client = NULL; 2524 hdev->nic.client = NULL; 2525 } 2526 } 2527 2528 static int hclgevf_pci_init(struct hclgevf_dev *hdev) 2529 { 2530 struct pci_dev *pdev = hdev->pdev; 2531 struct hclgevf_hw *hw; 2532 int ret; 2533 2534 ret = pci_enable_device(pdev); 2535 if (ret) { 2536 dev_err(&pdev->dev, "failed to enable PCI device\n"); 2537 return ret; 2538 } 2539 2540 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 2541 if (ret) { 2542 dev_err(&pdev->dev, "can't set consistent PCI DMA, exiting"); 2543 goto err_disable_device; 2544 } 2545 2546 ret = pci_request_regions(pdev, HCLGEVF_DRIVER_NAME); 2547 if (ret) { 2548 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 2549 goto err_disable_device; 2550 } 2551 2552 pci_set_master(pdev); 2553 hw = &hdev->hw; 2554 hw->hdev = hdev; 2555 hw->io_base = pci_iomap(pdev, 2, 0); 2556 if (!hw->io_base) { 2557 dev_err(&pdev->dev, "can't map configuration register space\n"); 2558 ret = -ENOMEM; 2559 goto err_clr_master; 2560 } 2561 2562 return 0; 2563 2564 err_clr_master: 2565 pci_clear_master(pdev); 2566 pci_release_regions(pdev); 2567 err_disable_device: 2568 pci_disable_device(pdev); 2569 2570 return ret; 2571 } 2572 2573 static void hclgevf_pci_uninit(struct hclgevf_dev *hdev) 2574 { 2575 struct pci_dev *pdev = hdev->pdev; 2576 2577 pci_iounmap(pdev, hdev->hw.io_base); 2578 pci_clear_master(pdev); 2579 pci_release_regions(pdev); 2580 pci_disable_device(pdev); 2581 } 2582 2583 static int hclgevf_query_vf_resource(struct hclgevf_dev *hdev) 2584 { 2585 struct hclgevf_query_res_cmd *req; 2586 struct hclgevf_desc desc; 2587 int ret; 2588 2589 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_VF_RSRC, true); 2590 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 2591 if (ret) { 2592 dev_err(&hdev->pdev->dev, 2593 "query vf resource failed, ret = %d.\n", ret); 2594 return ret; 2595 } 2596 2597 req = (struct hclgevf_query_res_cmd *)desc.data; 2598 2599 if (hnae3_dev_roce_supported(hdev)) { 2600 hdev->roce_base_msix_offset = 2601 hnae3_get_field(__le16_to_cpu(req->msixcap_localid_ba_rocee), 2602 HCLGEVF_MSIX_OFT_ROCEE_M, 2603 HCLGEVF_MSIX_OFT_ROCEE_S); 2604 hdev->num_roce_msix = 2605 hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number), 2606 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 2607 2608 /* nic's msix numbers is always equals to the roce's. */ 2609 hdev->num_nic_msix = hdev->num_roce_msix; 2610 2611 /* VF should have NIC vectors and Roce vectors, NIC vectors 2612 * are queued before Roce vectors. The offset is fixed to 64. 2613 */ 2614 hdev->num_msi = hdev->num_roce_msix + 2615 hdev->roce_base_msix_offset; 2616 } else { 2617 hdev->num_msi = 2618 hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number), 2619 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 2620 2621 hdev->num_nic_msix = hdev->num_msi; 2622 } 2623 2624 if (hdev->num_nic_msix < HNAE3_MIN_VECTOR_NUM) { 2625 dev_err(&hdev->pdev->dev, 2626 "Just %u msi resources, not enough for vf(min:2).\n", 2627 hdev->num_nic_msix); 2628 return -EINVAL; 2629 } 2630 2631 return 0; 2632 } 2633 2634 static int hclgevf_pci_reset(struct hclgevf_dev *hdev) 2635 { 2636 struct pci_dev *pdev = hdev->pdev; 2637 int ret = 0; 2638 2639 if (hdev->reset_type == HNAE3_VF_FULL_RESET && 2640 test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2641 hclgevf_misc_irq_uninit(hdev); 2642 hclgevf_uninit_msi(hdev); 2643 clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2644 } 2645 2646 if (!test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2647 pci_set_master(pdev); 2648 ret = hclgevf_init_msi(hdev); 2649 if (ret) { 2650 dev_err(&pdev->dev, 2651 "failed(%d) to init MSI/MSI-X\n", ret); 2652 return ret; 2653 } 2654 2655 ret = hclgevf_misc_irq_init(hdev); 2656 if (ret) { 2657 hclgevf_uninit_msi(hdev); 2658 dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 2659 ret); 2660 return ret; 2661 } 2662 2663 set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2664 } 2665 2666 return ret; 2667 } 2668 2669 static int hclgevf_reset_hdev(struct hclgevf_dev *hdev) 2670 { 2671 struct pci_dev *pdev = hdev->pdev; 2672 int ret; 2673 2674 ret = hclgevf_pci_reset(hdev); 2675 if (ret) { 2676 dev_err(&pdev->dev, "pci reset failed %d\n", ret); 2677 return ret; 2678 } 2679 2680 ret = hclgevf_cmd_init(hdev); 2681 if (ret) { 2682 dev_err(&pdev->dev, "cmd failed %d\n", ret); 2683 return ret; 2684 } 2685 2686 ret = hclgevf_rss_init_hw(hdev); 2687 if (ret) { 2688 dev_err(&hdev->pdev->dev, 2689 "failed(%d) to initialize RSS\n", ret); 2690 return ret; 2691 } 2692 2693 ret = hclgevf_config_gro(hdev, true); 2694 if (ret) 2695 return ret; 2696 2697 ret = hclgevf_init_vlan_config(hdev); 2698 if (ret) { 2699 dev_err(&hdev->pdev->dev, 2700 "failed(%d) to initialize VLAN config\n", ret); 2701 return ret; 2702 } 2703 2704 dev_info(&hdev->pdev->dev, "Reset done\n"); 2705 2706 return 0; 2707 } 2708 2709 static int hclgevf_init_hdev(struct hclgevf_dev *hdev) 2710 { 2711 struct pci_dev *pdev = hdev->pdev; 2712 int ret; 2713 2714 ret = hclgevf_pci_init(hdev); 2715 if (ret) { 2716 dev_err(&pdev->dev, "PCI initialization failed\n"); 2717 return ret; 2718 } 2719 2720 ret = hclgevf_cmd_queue_init(hdev); 2721 if (ret) { 2722 dev_err(&pdev->dev, "Cmd queue init failed: %d\n", ret); 2723 goto err_cmd_queue_init; 2724 } 2725 2726 ret = hclgevf_cmd_init(hdev); 2727 if (ret) 2728 goto err_cmd_init; 2729 2730 /* Get vf resource */ 2731 ret = hclgevf_query_vf_resource(hdev); 2732 if (ret) { 2733 dev_err(&hdev->pdev->dev, 2734 "Query vf status error, ret = %d.\n", ret); 2735 goto err_cmd_init; 2736 } 2737 2738 ret = hclgevf_init_msi(hdev); 2739 if (ret) { 2740 dev_err(&pdev->dev, "failed(%d) to init MSI/MSI-X\n", ret); 2741 goto err_cmd_init; 2742 } 2743 2744 hclgevf_state_init(hdev); 2745 hdev->reset_level = HNAE3_VF_FUNC_RESET; 2746 2747 ret = hclgevf_misc_irq_init(hdev); 2748 if (ret) { 2749 dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 2750 ret); 2751 goto err_misc_irq_init; 2752 } 2753 2754 set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2755 2756 ret = hclgevf_configure(hdev); 2757 if (ret) { 2758 dev_err(&pdev->dev, "failed(%d) to fetch configuration\n", ret); 2759 goto err_config; 2760 } 2761 2762 ret = hclgevf_alloc_tqps(hdev); 2763 if (ret) { 2764 dev_err(&pdev->dev, "failed(%d) to allocate TQPs\n", ret); 2765 goto err_config; 2766 } 2767 2768 ret = hclgevf_set_handle_info(hdev); 2769 if (ret) { 2770 dev_err(&pdev->dev, "failed(%d) to set handle info\n", ret); 2771 goto err_config; 2772 } 2773 2774 ret = hclgevf_config_gro(hdev, true); 2775 if (ret) 2776 goto err_config; 2777 2778 /* Initialize RSS for this VF */ 2779 ret = hclgevf_rss_init_hw(hdev); 2780 if (ret) { 2781 dev_err(&hdev->pdev->dev, 2782 "failed(%d) to initialize RSS\n", ret); 2783 goto err_config; 2784 } 2785 2786 ret = hclgevf_init_vlan_config(hdev); 2787 if (ret) { 2788 dev_err(&hdev->pdev->dev, 2789 "failed(%d) to initialize VLAN config\n", ret); 2790 goto err_config; 2791 } 2792 2793 hdev->last_reset_time = jiffies; 2794 dev_info(&hdev->pdev->dev, "finished initializing %s driver\n", 2795 HCLGEVF_DRIVER_NAME); 2796 2797 hclgevf_task_schedule(hdev, round_jiffies_relative(HZ)); 2798 2799 return 0; 2800 2801 err_config: 2802 hclgevf_misc_irq_uninit(hdev); 2803 err_misc_irq_init: 2804 hclgevf_state_uninit(hdev); 2805 hclgevf_uninit_msi(hdev); 2806 err_cmd_init: 2807 hclgevf_cmd_uninit(hdev); 2808 err_cmd_queue_init: 2809 hclgevf_pci_uninit(hdev); 2810 clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2811 return ret; 2812 } 2813 2814 static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev) 2815 { 2816 hclgevf_state_uninit(hdev); 2817 2818 if (test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2819 hclgevf_misc_irq_uninit(hdev); 2820 hclgevf_uninit_msi(hdev); 2821 } 2822 2823 hclgevf_pci_uninit(hdev); 2824 hclgevf_cmd_uninit(hdev); 2825 } 2826 2827 static int hclgevf_init_ae_dev(struct hnae3_ae_dev *ae_dev) 2828 { 2829 struct pci_dev *pdev = ae_dev->pdev; 2830 int ret; 2831 2832 ret = hclgevf_alloc_hdev(ae_dev); 2833 if (ret) { 2834 dev_err(&pdev->dev, "hclge device allocation failed\n"); 2835 return ret; 2836 } 2837 2838 ret = hclgevf_init_hdev(ae_dev->priv); 2839 if (ret) { 2840 dev_err(&pdev->dev, "hclge device initialization failed\n"); 2841 return ret; 2842 } 2843 2844 return 0; 2845 } 2846 2847 static void hclgevf_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 2848 { 2849 struct hclgevf_dev *hdev = ae_dev->priv; 2850 2851 hclgevf_uninit_hdev(hdev); 2852 ae_dev->priv = NULL; 2853 } 2854 2855 static u32 hclgevf_get_max_channels(struct hclgevf_dev *hdev) 2856 { 2857 struct hnae3_handle *nic = &hdev->nic; 2858 struct hnae3_knic_private_info *kinfo = &nic->kinfo; 2859 2860 return min_t(u32, hdev->rss_size_max, 2861 hdev->num_tqps / kinfo->num_tc); 2862 } 2863 2864 /** 2865 * hclgevf_get_channels - Get the current channels enabled and max supported. 2866 * @handle: hardware information for network interface 2867 * @ch: ethtool channels structure 2868 * 2869 * We don't support separate tx and rx queues as channels. The other count 2870 * represents how many queues are being used for control. max_combined counts 2871 * how many queue pairs we can support. They may not be mapped 1 to 1 with 2872 * q_vectors since we support a lot more queue pairs than q_vectors. 2873 **/ 2874 static void hclgevf_get_channels(struct hnae3_handle *handle, 2875 struct ethtool_channels *ch) 2876 { 2877 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2878 2879 ch->max_combined = hclgevf_get_max_channels(hdev); 2880 ch->other_count = 0; 2881 ch->max_other = 0; 2882 ch->combined_count = handle->kinfo.rss_size; 2883 } 2884 2885 static void hclgevf_get_tqps_and_rss_info(struct hnae3_handle *handle, 2886 u16 *alloc_tqps, u16 *max_rss_size) 2887 { 2888 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2889 2890 *alloc_tqps = hdev->num_tqps; 2891 *max_rss_size = hdev->rss_size_max; 2892 } 2893 2894 static void hclgevf_update_rss_size(struct hnae3_handle *handle, 2895 u32 new_tqps_num) 2896 { 2897 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 2898 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2899 u16 max_rss_size; 2900 2901 kinfo->req_rss_size = new_tqps_num; 2902 2903 max_rss_size = min_t(u16, hdev->rss_size_max, 2904 hdev->num_tqps / kinfo->num_tc); 2905 2906 /* Use the user's configuration when it is not larger than 2907 * max_rss_size, otherwise, use the maximum specification value. 2908 */ 2909 if (kinfo->req_rss_size != kinfo->rss_size && kinfo->req_rss_size && 2910 kinfo->req_rss_size <= max_rss_size) 2911 kinfo->rss_size = kinfo->req_rss_size; 2912 else if (kinfo->rss_size > max_rss_size || 2913 (!kinfo->req_rss_size && kinfo->rss_size < max_rss_size)) 2914 kinfo->rss_size = max_rss_size; 2915 2916 kinfo->num_tqps = kinfo->num_tc * kinfo->rss_size; 2917 } 2918 2919 static int hclgevf_set_channels(struct hnae3_handle *handle, u32 new_tqps_num, 2920 bool rxfh_configured) 2921 { 2922 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2923 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 2924 u16 cur_rss_size = kinfo->rss_size; 2925 u16 cur_tqps = kinfo->num_tqps; 2926 u32 *rss_indir; 2927 unsigned int i; 2928 int ret; 2929 2930 hclgevf_update_rss_size(handle, new_tqps_num); 2931 2932 ret = hclgevf_set_rss_tc_mode(hdev, kinfo->rss_size); 2933 if (ret) 2934 return ret; 2935 2936 /* RSS indirection table has been configuared by user */ 2937 if (rxfh_configured) 2938 goto out; 2939 2940 /* Reinitializes the rss indirect table according to the new RSS size */ 2941 rss_indir = kcalloc(HCLGEVF_RSS_IND_TBL_SIZE, sizeof(u32), GFP_KERNEL); 2942 if (!rss_indir) 2943 return -ENOMEM; 2944 2945 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 2946 rss_indir[i] = i % kinfo->rss_size; 2947 2948 ret = hclgevf_set_rss(handle, rss_indir, NULL, 0); 2949 if (ret) 2950 dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n", 2951 ret); 2952 2953 kfree(rss_indir); 2954 2955 out: 2956 if (!ret) 2957 dev_info(&hdev->pdev->dev, 2958 "Channels changed, rss_size from %u to %u, tqps from %u to %u", 2959 cur_rss_size, kinfo->rss_size, 2960 cur_tqps, kinfo->rss_size * kinfo->num_tc); 2961 2962 return ret; 2963 } 2964 2965 static int hclgevf_get_status(struct hnae3_handle *handle) 2966 { 2967 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2968 2969 return hdev->hw.mac.link; 2970 } 2971 2972 static void hclgevf_get_ksettings_an_result(struct hnae3_handle *handle, 2973 u8 *auto_neg, u32 *speed, 2974 u8 *duplex) 2975 { 2976 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2977 2978 if (speed) 2979 *speed = hdev->hw.mac.speed; 2980 if (duplex) 2981 *duplex = hdev->hw.mac.duplex; 2982 if (auto_neg) 2983 *auto_neg = AUTONEG_DISABLE; 2984 } 2985 2986 void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed, 2987 u8 duplex) 2988 { 2989 hdev->hw.mac.speed = speed; 2990 hdev->hw.mac.duplex = duplex; 2991 } 2992 2993 static int hclgevf_gro_en(struct hnae3_handle *handle, bool enable) 2994 { 2995 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2996 2997 return hclgevf_config_gro(hdev, enable); 2998 } 2999 3000 static void hclgevf_get_media_type(struct hnae3_handle *handle, u8 *media_type, 3001 u8 *module_type) 3002 { 3003 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3004 3005 if (media_type) 3006 *media_type = hdev->hw.mac.media_type; 3007 3008 if (module_type) 3009 *module_type = hdev->hw.mac.module_type; 3010 } 3011 3012 static bool hclgevf_get_hw_reset_stat(struct hnae3_handle *handle) 3013 { 3014 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3015 3016 return !!hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 3017 } 3018 3019 static bool hclgevf_ae_dev_resetting(struct hnae3_handle *handle) 3020 { 3021 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3022 3023 return test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 3024 } 3025 3026 static unsigned long hclgevf_ae_dev_reset_cnt(struct hnae3_handle *handle) 3027 { 3028 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3029 3030 return hdev->rst_stats.hw_rst_done_cnt; 3031 } 3032 3033 static void hclgevf_get_link_mode(struct hnae3_handle *handle, 3034 unsigned long *supported, 3035 unsigned long *advertising) 3036 { 3037 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3038 3039 *supported = hdev->hw.mac.supported; 3040 *advertising = hdev->hw.mac.advertising; 3041 } 3042 3043 #define MAX_SEPARATE_NUM 4 3044 #define SEPARATOR_VALUE 0xFFFFFFFF 3045 #define REG_NUM_PER_LINE 4 3046 #define REG_LEN_PER_LINE (REG_NUM_PER_LINE * sizeof(u32)) 3047 3048 static int hclgevf_get_regs_len(struct hnae3_handle *handle) 3049 { 3050 int cmdq_lines, common_lines, ring_lines, tqp_intr_lines; 3051 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3052 3053 cmdq_lines = sizeof(cmdq_reg_addr_list) / REG_LEN_PER_LINE + 1; 3054 common_lines = sizeof(common_reg_addr_list) / REG_LEN_PER_LINE + 1; 3055 ring_lines = sizeof(ring_reg_addr_list) / REG_LEN_PER_LINE + 1; 3056 tqp_intr_lines = sizeof(tqp_intr_reg_addr_list) / REG_LEN_PER_LINE + 1; 3057 3058 return (cmdq_lines + common_lines + ring_lines * hdev->num_tqps + 3059 tqp_intr_lines * (hdev->num_msi_used - 1)) * REG_LEN_PER_LINE; 3060 } 3061 3062 static void hclgevf_get_regs(struct hnae3_handle *handle, u32 *version, 3063 void *data) 3064 { 3065 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3066 int i, j, reg_um, separator_num; 3067 u32 *reg = data; 3068 3069 *version = hdev->fw_version; 3070 3071 /* fetching per-VF registers values from VF PCIe register space */ 3072 reg_um = sizeof(cmdq_reg_addr_list) / sizeof(u32); 3073 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 3074 for (i = 0; i < reg_um; i++) 3075 *reg++ = hclgevf_read_dev(&hdev->hw, cmdq_reg_addr_list[i]); 3076 for (i = 0; i < separator_num; i++) 3077 *reg++ = SEPARATOR_VALUE; 3078 3079 reg_um = sizeof(common_reg_addr_list) / sizeof(u32); 3080 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 3081 for (i = 0; i < reg_um; i++) 3082 *reg++ = hclgevf_read_dev(&hdev->hw, common_reg_addr_list[i]); 3083 for (i = 0; i < separator_num; i++) 3084 *reg++ = SEPARATOR_VALUE; 3085 3086 reg_um = sizeof(ring_reg_addr_list) / sizeof(u32); 3087 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 3088 for (j = 0; j < hdev->num_tqps; j++) { 3089 for (i = 0; i < reg_um; i++) 3090 *reg++ = hclgevf_read_dev(&hdev->hw, 3091 ring_reg_addr_list[i] + 3092 0x200 * j); 3093 for (i = 0; i < separator_num; i++) 3094 *reg++ = SEPARATOR_VALUE; 3095 } 3096 3097 reg_um = sizeof(tqp_intr_reg_addr_list) / sizeof(u32); 3098 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 3099 for (j = 0; j < hdev->num_msi_used - 1; j++) { 3100 for (i = 0; i < reg_um; i++) 3101 *reg++ = hclgevf_read_dev(&hdev->hw, 3102 tqp_intr_reg_addr_list[i] + 3103 4 * j); 3104 for (i = 0; i < separator_num; i++) 3105 *reg++ = SEPARATOR_VALUE; 3106 } 3107 } 3108 3109 void hclgevf_update_port_base_vlan_info(struct hclgevf_dev *hdev, u16 state, 3110 u8 *port_base_vlan_info, u8 data_size) 3111 { 3112 struct hnae3_handle *nic = &hdev->nic; 3113 3114 rtnl_lock(); 3115 hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 3116 rtnl_unlock(); 3117 3118 /* send msg to PF and wait update port based vlan info */ 3119 hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 3120 HCLGE_MBX_PORT_BASE_VLAN_CFG, 3121 port_base_vlan_info, data_size, 3122 false, NULL, 0); 3123 3124 if (state == HNAE3_PORT_BASE_VLAN_DISABLE) 3125 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_DISABLE; 3126 else 3127 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_ENABLE; 3128 3129 rtnl_lock(); 3130 hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 3131 rtnl_unlock(); 3132 } 3133 3134 static const struct hnae3_ae_ops hclgevf_ops = { 3135 .init_ae_dev = hclgevf_init_ae_dev, 3136 .uninit_ae_dev = hclgevf_uninit_ae_dev, 3137 .flr_prepare = hclgevf_flr_prepare, 3138 .flr_done = hclgevf_flr_done, 3139 .init_client_instance = hclgevf_init_client_instance, 3140 .uninit_client_instance = hclgevf_uninit_client_instance, 3141 .start = hclgevf_ae_start, 3142 .stop = hclgevf_ae_stop, 3143 .client_start = hclgevf_client_start, 3144 .client_stop = hclgevf_client_stop, 3145 .map_ring_to_vector = hclgevf_map_ring_to_vector, 3146 .unmap_ring_from_vector = hclgevf_unmap_ring_from_vector, 3147 .get_vector = hclgevf_get_vector, 3148 .put_vector = hclgevf_put_vector, 3149 .reset_queue = hclgevf_reset_tqp, 3150 .get_mac_addr = hclgevf_get_mac_addr, 3151 .set_mac_addr = hclgevf_set_mac_addr, 3152 .add_uc_addr = hclgevf_add_uc_addr, 3153 .rm_uc_addr = hclgevf_rm_uc_addr, 3154 .add_mc_addr = hclgevf_add_mc_addr, 3155 .rm_mc_addr = hclgevf_rm_mc_addr, 3156 .get_stats = hclgevf_get_stats, 3157 .update_stats = hclgevf_update_stats, 3158 .get_strings = hclgevf_get_strings, 3159 .get_sset_count = hclgevf_get_sset_count, 3160 .get_rss_key_size = hclgevf_get_rss_key_size, 3161 .get_rss_indir_size = hclgevf_get_rss_indir_size, 3162 .get_rss = hclgevf_get_rss, 3163 .set_rss = hclgevf_set_rss, 3164 .get_rss_tuple = hclgevf_get_rss_tuple, 3165 .set_rss_tuple = hclgevf_set_rss_tuple, 3166 .get_tc_size = hclgevf_get_tc_size, 3167 .get_fw_version = hclgevf_get_fw_version, 3168 .set_vlan_filter = hclgevf_set_vlan_filter, 3169 .enable_hw_strip_rxvtag = hclgevf_en_hw_strip_rxvtag, 3170 .reset_event = hclgevf_reset_event, 3171 .set_default_reset_request = hclgevf_set_def_reset_request, 3172 .set_channels = hclgevf_set_channels, 3173 .get_channels = hclgevf_get_channels, 3174 .get_tqps_and_rss_info = hclgevf_get_tqps_and_rss_info, 3175 .get_regs_len = hclgevf_get_regs_len, 3176 .get_regs = hclgevf_get_regs, 3177 .get_status = hclgevf_get_status, 3178 .get_ksettings_an_result = hclgevf_get_ksettings_an_result, 3179 .get_media_type = hclgevf_get_media_type, 3180 .get_hw_reset_stat = hclgevf_get_hw_reset_stat, 3181 .ae_dev_resetting = hclgevf_ae_dev_resetting, 3182 .ae_dev_reset_cnt = hclgevf_ae_dev_reset_cnt, 3183 .set_gro_en = hclgevf_gro_en, 3184 .set_mtu = hclgevf_set_mtu, 3185 .get_global_queue_id = hclgevf_get_qid_global, 3186 .set_timer_task = hclgevf_set_timer_task, 3187 .get_link_mode = hclgevf_get_link_mode, 3188 .set_promisc_mode = hclgevf_set_promisc_mode, 3189 }; 3190 3191 static struct hnae3_ae_algo ae_algovf = { 3192 .ops = &hclgevf_ops, 3193 .pdev_id_table = ae_algovf_pci_tbl, 3194 }; 3195 3196 static int hclgevf_init(void) 3197 { 3198 pr_info("%s is initializing\n", HCLGEVF_NAME); 3199 3200 hnae3_register_ae_algo(&ae_algovf); 3201 3202 return 0; 3203 } 3204 3205 static void hclgevf_exit(void) 3206 { 3207 hnae3_unregister_ae_algo(&ae_algovf); 3208 } 3209 module_init(hclgevf_init); 3210 module_exit(hclgevf_exit); 3211 3212 MODULE_LICENSE("GPL"); 3213 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 3214 MODULE_DESCRIPTION("HCLGEVF Driver"); 3215 MODULE_VERSION(HCLGEVF_MOD_VERSION); 3216