1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/etherdevice.h> 5 #include <linux/iopoll.h> 6 #include <net/rtnetlink.h> 7 #include "hclgevf_cmd.h" 8 #include "hclgevf_main.h" 9 #include "hclge_mbx.h" 10 #include "hnae3.h" 11 12 #define HCLGEVF_NAME "hclgevf" 13 14 static int hclgevf_reset_hdev(struct hclgevf_dev *hdev); 15 static struct hnae3_ae_algo ae_algovf; 16 17 static const struct pci_device_id ae_algovf_pci_tbl[] = { 18 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0}, 19 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF), 0}, 20 /* required last entry */ 21 {0, } 22 }; 23 24 static const u8 hclgevf_hash_key[] = { 25 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2, 26 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0, 27 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4, 28 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C, 29 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA 30 }; 31 32 MODULE_DEVICE_TABLE(pci, ae_algovf_pci_tbl); 33 34 static const u32 cmdq_reg_addr_list[] = {HCLGEVF_CMDQ_TX_ADDR_L_REG, 35 HCLGEVF_CMDQ_TX_ADDR_H_REG, 36 HCLGEVF_CMDQ_TX_DEPTH_REG, 37 HCLGEVF_CMDQ_TX_TAIL_REG, 38 HCLGEVF_CMDQ_TX_HEAD_REG, 39 HCLGEVF_CMDQ_RX_ADDR_L_REG, 40 HCLGEVF_CMDQ_RX_ADDR_H_REG, 41 HCLGEVF_CMDQ_RX_DEPTH_REG, 42 HCLGEVF_CMDQ_RX_TAIL_REG, 43 HCLGEVF_CMDQ_RX_HEAD_REG, 44 HCLGEVF_VECTOR0_CMDQ_SRC_REG, 45 HCLGEVF_CMDQ_INTR_STS_REG, 46 HCLGEVF_CMDQ_INTR_EN_REG, 47 HCLGEVF_CMDQ_INTR_GEN_REG}; 48 49 static const u32 common_reg_addr_list[] = {HCLGEVF_MISC_VECTOR_REG_BASE, 50 HCLGEVF_RST_ING, 51 HCLGEVF_GRO_EN_REG}; 52 53 static const u32 ring_reg_addr_list[] = {HCLGEVF_RING_RX_ADDR_L_REG, 54 HCLGEVF_RING_RX_ADDR_H_REG, 55 HCLGEVF_RING_RX_BD_NUM_REG, 56 HCLGEVF_RING_RX_BD_LENGTH_REG, 57 HCLGEVF_RING_RX_MERGE_EN_REG, 58 HCLGEVF_RING_RX_TAIL_REG, 59 HCLGEVF_RING_RX_HEAD_REG, 60 HCLGEVF_RING_RX_FBD_NUM_REG, 61 HCLGEVF_RING_RX_OFFSET_REG, 62 HCLGEVF_RING_RX_FBD_OFFSET_REG, 63 HCLGEVF_RING_RX_STASH_REG, 64 HCLGEVF_RING_RX_BD_ERR_REG, 65 HCLGEVF_RING_TX_ADDR_L_REG, 66 HCLGEVF_RING_TX_ADDR_H_REG, 67 HCLGEVF_RING_TX_BD_NUM_REG, 68 HCLGEVF_RING_TX_PRIORITY_REG, 69 HCLGEVF_RING_TX_TC_REG, 70 HCLGEVF_RING_TX_MERGE_EN_REG, 71 HCLGEVF_RING_TX_TAIL_REG, 72 HCLGEVF_RING_TX_HEAD_REG, 73 HCLGEVF_RING_TX_FBD_NUM_REG, 74 HCLGEVF_RING_TX_OFFSET_REG, 75 HCLGEVF_RING_TX_EBD_NUM_REG, 76 HCLGEVF_RING_TX_EBD_OFFSET_REG, 77 HCLGEVF_RING_TX_BD_ERR_REG, 78 HCLGEVF_RING_EN_REG}; 79 80 static const u32 tqp_intr_reg_addr_list[] = {HCLGEVF_TQP_INTR_CTRL_REG, 81 HCLGEVF_TQP_INTR_GL0_REG, 82 HCLGEVF_TQP_INTR_GL1_REG, 83 HCLGEVF_TQP_INTR_GL2_REG, 84 HCLGEVF_TQP_INTR_RL_REG}; 85 86 static inline struct hclgevf_dev *hclgevf_ae_get_hdev( 87 struct hnae3_handle *handle) 88 { 89 if (!handle->client) 90 return container_of(handle, struct hclgevf_dev, nic); 91 else if (handle->client->type == HNAE3_CLIENT_ROCE) 92 return container_of(handle, struct hclgevf_dev, roce); 93 else 94 return container_of(handle, struct hclgevf_dev, nic); 95 } 96 97 static int hclgevf_tqps_update_stats(struct hnae3_handle *handle) 98 { 99 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 100 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 101 struct hclgevf_desc desc; 102 struct hclgevf_tqp *tqp; 103 int status; 104 int i; 105 106 for (i = 0; i < kinfo->num_tqps; i++) { 107 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 108 hclgevf_cmd_setup_basic_desc(&desc, 109 HCLGEVF_OPC_QUERY_RX_STATUS, 110 true); 111 112 desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 113 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 114 if (status) { 115 dev_err(&hdev->pdev->dev, 116 "Query tqp stat fail, status = %d,queue = %d\n", 117 status, i); 118 return status; 119 } 120 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd += 121 le32_to_cpu(desc.data[1]); 122 123 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_TX_STATUS, 124 true); 125 126 desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 127 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 128 if (status) { 129 dev_err(&hdev->pdev->dev, 130 "Query tqp stat fail, status = %d,queue = %d\n", 131 status, i); 132 return status; 133 } 134 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd += 135 le32_to_cpu(desc.data[1]); 136 } 137 138 return 0; 139 } 140 141 static u64 *hclgevf_tqps_get_stats(struct hnae3_handle *handle, u64 *data) 142 { 143 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 144 struct hclgevf_tqp *tqp; 145 u64 *buff = data; 146 int i; 147 148 for (i = 0; i < kinfo->num_tqps; i++) { 149 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 150 *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd; 151 } 152 for (i = 0; i < kinfo->num_tqps; i++) { 153 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 154 *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd; 155 } 156 157 return buff; 158 } 159 160 static int hclgevf_tqps_get_sset_count(struct hnae3_handle *handle, int strset) 161 { 162 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 163 164 return kinfo->num_tqps * 2; 165 } 166 167 static u8 *hclgevf_tqps_get_strings(struct hnae3_handle *handle, u8 *data) 168 { 169 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 170 u8 *buff = data; 171 int i = 0; 172 173 for (i = 0; i < kinfo->num_tqps; i++) { 174 struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 175 struct hclgevf_tqp, q); 176 snprintf(buff, ETH_GSTRING_LEN, "txq%d_pktnum_rcd", 177 tqp->index); 178 buff += ETH_GSTRING_LEN; 179 } 180 181 for (i = 0; i < kinfo->num_tqps; i++) { 182 struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 183 struct hclgevf_tqp, q); 184 snprintf(buff, ETH_GSTRING_LEN, "rxq%d_pktnum_rcd", 185 tqp->index); 186 buff += ETH_GSTRING_LEN; 187 } 188 189 return buff; 190 } 191 192 static void hclgevf_update_stats(struct hnae3_handle *handle, 193 struct net_device_stats *net_stats) 194 { 195 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 196 int status; 197 198 status = hclgevf_tqps_update_stats(handle); 199 if (status) 200 dev_err(&hdev->pdev->dev, 201 "VF update of TQPS stats fail, status = %d.\n", 202 status); 203 } 204 205 static int hclgevf_get_sset_count(struct hnae3_handle *handle, int strset) 206 { 207 if (strset == ETH_SS_TEST) 208 return -EOPNOTSUPP; 209 else if (strset == ETH_SS_STATS) 210 return hclgevf_tqps_get_sset_count(handle, strset); 211 212 return 0; 213 } 214 215 static void hclgevf_get_strings(struct hnae3_handle *handle, u32 strset, 216 u8 *data) 217 { 218 u8 *p = (char *)data; 219 220 if (strset == ETH_SS_STATS) 221 p = hclgevf_tqps_get_strings(handle, p); 222 } 223 224 static void hclgevf_get_stats(struct hnae3_handle *handle, u64 *data) 225 { 226 hclgevf_tqps_get_stats(handle, data); 227 } 228 229 static int hclgevf_get_tc_info(struct hclgevf_dev *hdev) 230 { 231 u8 resp_msg; 232 int status; 233 234 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_TCINFO, 0, NULL, 0, 235 true, &resp_msg, sizeof(u8)); 236 if (status) { 237 dev_err(&hdev->pdev->dev, 238 "VF request to get TC info from PF failed %d", 239 status); 240 return status; 241 } 242 243 hdev->hw_tc_map = resp_msg; 244 245 return 0; 246 } 247 248 static int hclgevf_get_queue_info(struct hclgevf_dev *hdev) 249 { 250 #define HCLGEVF_TQPS_RSS_INFO_LEN 8 251 u8 resp_msg[HCLGEVF_TQPS_RSS_INFO_LEN]; 252 int status; 253 254 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QINFO, 0, NULL, 0, 255 true, resp_msg, 256 HCLGEVF_TQPS_RSS_INFO_LEN); 257 if (status) { 258 dev_err(&hdev->pdev->dev, 259 "VF request to get tqp info from PF failed %d", 260 status); 261 return status; 262 } 263 264 memcpy(&hdev->num_tqps, &resp_msg[0], sizeof(u16)); 265 memcpy(&hdev->rss_size_max, &resp_msg[2], sizeof(u16)); 266 memcpy(&hdev->num_desc, &resp_msg[4], sizeof(u16)); 267 memcpy(&hdev->rx_buf_len, &resp_msg[6], sizeof(u16)); 268 269 return 0; 270 } 271 272 static u16 hclgevf_get_qid_global(struct hnae3_handle *handle, u16 queue_id) 273 { 274 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 275 u8 msg_data[2], resp_data[2]; 276 u16 qid_in_pf = 0; 277 int ret; 278 279 memcpy(&msg_data[0], &queue_id, sizeof(queue_id)); 280 281 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QID_IN_PF, 0, msg_data, 282 2, true, resp_data, 2); 283 if (!ret) 284 qid_in_pf = *(u16 *)resp_data; 285 286 return qid_in_pf; 287 } 288 289 static int hclgevf_alloc_tqps(struct hclgevf_dev *hdev) 290 { 291 struct hclgevf_tqp *tqp; 292 int i; 293 294 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 295 sizeof(struct hclgevf_tqp), GFP_KERNEL); 296 if (!hdev->htqp) 297 return -ENOMEM; 298 299 tqp = hdev->htqp; 300 301 for (i = 0; i < hdev->num_tqps; i++) { 302 tqp->dev = &hdev->pdev->dev; 303 tqp->index = i; 304 305 tqp->q.ae_algo = &ae_algovf; 306 tqp->q.buf_size = hdev->rx_buf_len; 307 tqp->q.desc_num = hdev->num_desc; 308 tqp->q.io_base = hdev->hw.io_base + HCLGEVF_TQP_REG_OFFSET + 309 i * HCLGEVF_TQP_REG_SIZE; 310 311 tqp++; 312 } 313 314 return 0; 315 } 316 317 static int hclgevf_knic_setup(struct hclgevf_dev *hdev) 318 { 319 struct hnae3_handle *nic = &hdev->nic; 320 struct hnae3_knic_private_info *kinfo; 321 u16 new_tqps = hdev->num_tqps; 322 int i; 323 324 kinfo = &nic->kinfo; 325 kinfo->num_tc = 0; 326 kinfo->num_desc = hdev->num_desc; 327 kinfo->rx_buf_len = hdev->rx_buf_len; 328 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) 329 if (hdev->hw_tc_map & BIT(i)) 330 kinfo->num_tc++; 331 332 kinfo->rss_size 333 = min_t(u16, hdev->rss_size_max, new_tqps / kinfo->num_tc); 334 new_tqps = kinfo->rss_size * kinfo->num_tc; 335 kinfo->num_tqps = min(new_tqps, hdev->num_tqps); 336 337 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps, 338 sizeof(struct hnae3_queue *), GFP_KERNEL); 339 if (!kinfo->tqp) 340 return -ENOMEM; 341 342 for (i = 0; i < kinfo->num_tqps; i++) { 343 hdev->htqp[i].q.handle = &hdev->nic; 344 hdev->htqp[i].q.tqp_index = i; 345 kinfo->tqp[i] = &hdev->htqp[i].q; 346 } 347 348 return 0; 349 } 350 351 static void hclgevf_request_link_info(struct hclgevf_dev *hdev) 352 { 353 int status; 354 u8 resp_msg; 355 356 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_STATUS, 0, NULL, 357 0, false, &resp_msg, sizeof(u8)); 358 if (status) 359 dev_err(&hdev->pdev->dev, 360 "VF failed to fetch link status(%d) from PF", status); 361 } 362 363 void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state) 364 { 365 struct hnae3_handle *rhandle = &hdev->roce; 366 struct hnae3_handle *handle = &hdev->nic; 367 struct hnae3_client *rclient; 368 struct hnae3_client *client; 369 370 client = handle->client; 371 rclient = hdev->roce_client; 372 373 link_state = 374 test_bit(HCLGEVF_STATE_DOWN, &hdev->state) ? 0 : link_state; 375 376 if (link_state != hdev->hw.mac.link) { 377 client->ops->link_status_change(handle, !!link_state); 378 if (rclient && rclient->ops->link_status_change) 379 rclient->ops->link_status_change(rhandle, !!link_state); 380 hdev->hw.mac.link = link_state; 381 } 382 } 383 384 static int hclgevf_set_handle_info(struct hclgevf_dev *hdev) 385 { 386 struct hnae3_handle *nic = &hdev->nic; 387 int ret; 388 389 nic->ae_algo = &ae_algovf; 390 nic->pdev = hdev->pdev; 391 nic->numa_node_mask = hdev->numa_node_mask; 392 nic->flags |= HNAE3_SUPPORT_VF; 393 394 if (hdev->ae_dev->dev_type != HNAE3_DEV_KNIC) { 395 dev_err(&hdev->pdev->dev, "unsupported device type %d\n", 396 hdev->ae_dev->dev_type); 397 return -EINVAL; 398 } 399 400 ret = hclgevf_knic_setup(hdev); 401 if (ret) 402 dev_err(&hdev->pdev->dev, "VF knic setup failed %d\n", 403 ret); 404 return ret; 405 } 406 407 static void hclgevf_free_vector(struct hclgevf_dev *hdev, int vector_id) 408 { 409 if (hdev->vector_status[vector_id] == HCLGEVF_INVALID_VPORT) { 410 dev_warn(&hdev->pdev->dev, 411 "vector(vector_id %d) has been freed.\n", vector_id); 412 return; 413 } 414 415 hdev->vector_status[vector_id] = HCLGEVF_INVALID_VPORT; 416 hdev->num_msi_left += 1; 417 hdev->num_msi_used -= 1; 418 } 419 420 static int hclgevf_get_vector(struct hnae3_handle *handle, u16 vector_num, 421 struct hnae3_vector_info *vector_info) 422 { 423 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 424 struct hnae3_vector_info *vector = vector_info; 425 int alloc = 0; 426 int i, j; 427 428 vector_num = min(hdev->num_msi_left, vector_num); 429 430 for (j = 0; j < vector_num; j++) { 431 for (i = HCLGEVF_MISC_VECTOR_NUM + 1; i < hdev->num_msi; i++) { 432 if (hdev->vector_status[i] == HCLGEVF_INVALID_VPORT) { 433 vector->vector = pci_irq_vector(hdev->pdev, i); 434 vector->io_addr = hdev->hw.io_base + 435 HCLGEVF_VECTOR_REG_BASE + 436 (i - 1) * HCLGEVF_VECTOR_REG_OFFSET; 437 hdev->vector_status[i] = 0; 438 hdev->vector_irq[i] = vector->vector; 439 440 vector++; 441 alloc++; 442 443 break; 444 } 445 } 446 } 447 hdev->num_msi_left -= alloc; 448 hdev->num_msi_used += alloc; 449 450 return alloc; 451 } 452 453 static int hclgevf_get_vector_index(struct hclgevf_dev *hdev, int vector) 454 { 455 int i; 456 457 for (i = 0; i < hdev->num_msi; i++) 458 if (vector == hdev->vector_irq[i]) 459 return i; 460 461 return -EINVAL; 462 } 463 464 static int hclgevf_set_rss_algo_key(struct hclgevf_dev *hdev, 465 const u8 hfunc, const u8 *key) 466 { 467 struct hclgevf_rss_config_cmd *req; 468 struct hclgevf_desc desc; 469 int key_offset; 470 int key_size; 471 int ret; 472 473 req = (struct hclgevf_rss_config_cmd *)desc.data; 474 475 for (key_offset = 0; key_offset < 3; key_offset++) { 476 hclgevf_cmd_setup_basic_desc(&desc, 477 HCLGEVF_OPC_RSS_GENERIC_CONFIG, 478 false); 479 480 req->hash_config |= (hfunc & HCLGEVF_RSS_HASH_ALGO_MASK); 481 req->hash_config |= 482 (key_offset << HCLGEVF_RSS_HASH_KEY_OFFSET_B); 483 484 if (key_offset == 2) 485 key_size = 486 HCLGEVF_RSS_KEY_SIZE - HCLGEVF_RSS_HASH_KEY_NUM * 2; 487 else 488 key_size = HCLGEVF_RSS_HASH_KEY_NUM; 489 490 memcpy(req->hash_key, 491 key + key_offset * HCLGEVF_RSS_HASH_KEY_NUM, key_size); 492 493 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 494 if (ret) { 495 dev_err(&hdev->pdev->dev, 496 "Configure RSS config fail, status = %d\n", 497 ret); 498 return ret; 499 } 500 } 501 502 return 0; 503 } 504 505 static u32 hclgevf_get_rss_key_size(struct hnae3_handle *handle) 506 { 507 return HCLGEVF_RSS_KEY_SIZE; 508 } 509 510 static u32 hclgevf_get_rss_indir_size(struct hnae3_handle *handle) 511 { 512 return HCLGEVF_RSS_IND_TBL_SIZE; 513 } 514 515 static int hclgevf_set_rss_indir_table(struct hclgevf_dev *hdev) 516 { 517 const u8 *indir = hdev->rss_cfg.rss_indirection_tbl; 518 struct hclgevf_rss_indirection_table_cmd *req; 519 struct hclgevf_desc desc; 520 int status; 521 int i, j; 522 523 req = (struct hclgevf_rss_indirection_table_cmd *)desc.data; 524 525 for (i = 0; i < HCLGEVF_RSS_CFG_TBL_NUM; i++) { 526 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INDIR_TABLE, 527 false); 528 req->start_table_index = i * HCLGEVF_RSS_CFG_TBL_SIZE; 529 req->rss_set_bitmap = HCLGEVF_RSS_SET_BITMAP_MSK; 530 for (j = 0; j < HCLGEVF_RSS_CFG_TBL_SIZE; j++) 531 req->rss_result[j] = 532 indir[i * HCLGEVF_RSS_CFG_TBL_SIZE + j]; 533 534 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 535 if (status) { 536 dev_err(&hdev->pdev->dev, 537 "VF failed(=%d) to set RSS indirection table\n", 538 status); 539 return status; 540 } 541 } 542 543 return 0; 544 } 545 546 static int hclgevf_set_rss_tc_mode(struct hclgevf_dev *hdev, u16 rss_size) 547 { 548 struct hclgevf_rss_tc_mode_cmd *req; 549 u16 tc_offset[HCLGEVF_MAX_TC_NUM]; 550 u16 tc_valid[HCLGEVF_MAX_TC_NUM]; 551 u16 tc_size[HCLGEVF_MAX_TC_NUM]; 552 struct hclgevf_desc desc; 553 u16 roundup_size; 554 int status; 555 int i; 556 557 req = (struct hclgevf_rss_tc_mode_cmd *)desc.data; 558 559 roundup_size = roundup_pow_of_two(rss_size); 560 roundup_size = ilog2(roundup_size); 561 562 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 563 tc_valid[i] = !!(hdev->hw_tc_map & BIT(i)); 564 tc_size[i] = roundup_size; 565 tc_offset[i] = rss_size * i; 566 } 567 568 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_TC_MODE, false); 569 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 570 hnae3_set_bit(req->rss_tc_mode[i], HCLGEVF_RSS_TC_VALID_B, 571 (tc_valid[i] & 0x1)); 572 hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_SIZE_M, 573 HCLGEVF_RSS_TC_SIZE_S, tc_size[i]); 574 hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_OFFSET_M, 575 HCLGEVF_RSS_TC_OFFSET_S, tc_offset[i]); 576 } 577 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 578 if (status) 579 dev_err(&hdev->pdev->dev, 580 "VF failed(=%d) to set rss tc mode\n", status); 581 582 return status; 583 } 584 585 static int hclgevf_get_rss(struct hnae3_handle *handle, u32 *indir, u8 *key, 586 u8 *hfunc) 587 { 588 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 589 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 590 int i; 591 592 if (handle->pdev->revision >= 0x21) { 593 /* Get hash algorithm */ 594 if (hfunc) { 595 switch (rss_cfg->hash_algo) { 596 case HCLGEVF_RSS_HASH_ALGO_TOEPLITZ: 597 *hfunc = ETH_RSS_HASH_TOP; 598 break; 599 case HCLGEVF_RSS_HASH_ALGO_SIMPLE: 600 *hfunc = ETH_RSS_HASH_XOR; 601 break; 602 default: 603 *hfunc = ETH_RSS_HASH_UNKNOWN; 604 break; 605 } 606 } 607 608 /* Get the RSS Key required by the user */ 609 if (key) 610 memcpy(key, rss_cfg->rss_hash_key, 611 HCLGEVF_RSS_KEY_SIZE); 612 } 613 614 if (indir) 615 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 616 indir[i] = rss_cfg->rss_indirection_tbl[i]; 617 618 return 0; 619 } 620 621 static int hclgevf_set_rss(struct hnae3_handle *handle, const u32 *indir, 622 const u8 *key, const u8 hfunc) 623 { 624 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 625 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 626 int ret, i; 627 628 if (handle->pdev->revision >= 0x21) { 629 /* Set the RSS Hash Key if specififed by the user */ 630 if (key) { 631 switch (hfunc) { 632 case ETH_RSS_HASH_TOP: 633 rss_cfg->hash_algo = 634 HCLGEVF_RSS_HASH_ALGO_TOEPLITZ; 635 break; 636 case ETH_RSS_HASH_XOR: 637 rss_cfg->hash_algo = 638 HCLGEVF_RSS_HASH_ALGO_SIMPLE; 639 break; 640 case ETH_RSS_HASH_NO_CHANGE: 641 break; 642 default: 643 return -EINVAL; 644 } 645 646 ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 647 key); 648 if (ret) 649 return ret; 650 651 /* Update the shadow RSS key with user specified qids */ 652 memcpy(rss_cfg->rss_hash_key, key, 653 HCLGEVF_RSS_KEY_SIZE); 654 } 655 } 656 657 /* update the shadow RSS table with user specified qids */ 658 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 659 rss_cfg->rss_indirection_tbl[i] = indir[i]; 660 661 /* update the hardware */ 662 return hclgevf_set_rss_indir_table(hdev); 663 } 664 665 static u8 hclgevf_get_rss_hash_bits(struct ethtool_rxnfc *nfc) 666 { 667 u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGEVF_S_PORT_BIT : 0; 668 669 if (nfc->data & RXH_L4_B_2_3) 670 hash_sets |= HCLGEVF_D_PORT_BIT; 671 else 672 hash_sets &= ~HCLGEVF_D_PORT_BIT; 673 674 if (nfc->data & RXH_IP_SRC) 675 hash_sets |= HCLGEVF_S_IP_BIT; 676 else 677 hash_sets &= ~HCLGEVF_S_IP_BIT; 678 679 if (nfc->data & RXH_IP_DST) 680 hash_sets |= HCLGEVF_D_IP_BIT; 681 else 682 hash_sets &= ~HCLGEVF_D_IP_BIT; 683 684 if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW) 685 hash_sets |= HCLGEVF_V_TAG_BIT; 686 687 return hash_sets; 688 } 689 690 static int hclgevf_set_rss_tuple(struct hnae3_handle *handle, 691 struct ethtool_rxnfc *nfc) 692 { 693 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 694 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 695 struct hclgevf_rss_input_tuple_cmd *req; 696 struct hclgevf_desc desc; 697 u8 tuple_sets; 698 int ret; 699 700 if (handle->pdev->revision == 0x20) 701 return -EOPNOTSUPP; 702 703 if (nfc->data & 704 ~(RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3)) 705 return -EINVAL; 706 707 req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 708 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 709 710 req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 711 req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 712 req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 713 req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 714 req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 715 req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 716 req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 717 req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 718 719 tuple_sets = hclgevf_get_rss_hash_bits(nfc); 720 switch (nfc->flow_type) { 721 case TCP_V4_FLOW: 722 req->ipv4_tcp_en = tuple_sets; 723 break; 724 case TCP_V6_FLOW: 725 req->ipv6_tcp_en = tuple_sets; 726 break; 727 case UDP_V4_FLOW: 728 req->ipv4_udp_en = tuple_sets; 729 break; 730 case UDP_V6_FLOW: 731 req->ipv6_udp_en = tuple_sets; 732 break; 733 case SCTP_V4_FLOW: 734 req->ipv4_sctp_en = tuple_sets; 735 break; 736 case SCTP_V6_FLOW: 737 if ((nfc->data & RXH_L4_B_0_1) || 738 (nfc->data & RXH_L4_B_2_3)) 739 return -EINVAL; 740 741 req->ipv6_sctp_en = tuple_sets; 742 break; 743 case IPV4_FLOW: 744 req->ipv4_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 745 break; 746 case IPV6_FLOW: 747 req->ipv6_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 748 break; 749 default: 750 return -EINVAL; 751 } 752 753 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 754 if (ret) { 755 dev_err(&hdev->pdev->dev, 756 "Set rss tuple fail, status = %d\n", ret); 757 return ret; 758 } 759 760 rss_cfg->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en; 761 rss_cfg->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en; 762 rss_cfg->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en; 763 rss_cfg->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en; 764 rss_cfg->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en; 765 rss_cfg->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en; 766 rss_cfg->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en; 767 rss_cfg->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en; 768 return 0; 769 } 770 771 static int hclgevf_get_rss_tuple(struct hnae3_handle *handle, 772 struct ethtool_rxnfc *nfc) 773 { 774 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 775 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 776 u8 tuple_sets; 777 778 if (handle->pdev->revision == 0x20) 779 return -EOPNOTSUPP; 780 781 nfc->data = 0; 782 783 switch (nfc->flow_type) { 784 case TCP_V4_FLOW: 785 tuple_sets = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 786 break; 787 case UDP_V4_FLOW: 788 tuple_sets = rss_cfg->rss_tuple_sets.ipv4_udp_en; 789 break; 790 case TCP_V6_FLOW: 791 tuple_sets = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 792 break; 793 case UDP_V6_FLOW: 794 tuple_sets = rss_cfg->rss_tuple_sets.ipv6_udp_en; 795 break; 796 case SCTP_V4_FLOW: 797 tuple_sets = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 798 break; 799 case SCTP_V6_FLOW: 800 tuple_sets = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 801 break; 802 case IPV4_FLOW: 803 case IPV6_FLOW: 804 tuple_sets = HCLGEVF_S_IP_BIT | HCLGEVF_D_IP_BIT; 805 break; 806 default: 807 return -EINVAL; 808 } 809 810 if (!tuple_sets) 811 return 0; 812 813 if (tuple_sets & HCLGEVF_D_PORT_BIT) 814 nfc->data |= RXH_L4_B_2_3; 815 if (tuple_sets & HCLGEVF_S_PORT_BIT) 816 nfc->data |= RXH_L4_B_0_1; 817 if (tuple_sets & HCLGEVF_D_IP_BIT) 818 nfc->data |= RXH_IP_DST; 819 if (tuple_sets & HCLGEVF_S_IP_BIT) 820 nfc->data |= RXH_IP_SRC; 821 822 return 0; 823 } 824 825 static int hclgevf_set_rss_input_tuple(struct hclgevf_dev *hdev, 826 struct hclgevf_rss_cfg *rss_cfg) 827 { 828 struct hclgevf_rss_input_tuple_cmd *req; 829 struct hclgevf_desc desc; 830 int ret; 831 832 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 833 834 req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 835 836 req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 837 req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 838 req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 839 req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 840 req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 841 req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 842 req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 843 req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 844 845 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 846 if (ret) 847 dev_err(&hdev->pdev->dev, 848 "Configure rss input fail, status = %d\n", ret); 849 return ret; 850 } 851 852 static int hclgevf_get_tc_size(struct hnae3_handle *handle) 853 { 854 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 855 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 856 857 return rss_cfg->rss_size; 858 } 859 860 static int hclgevf_bind_ring_to_vector(struct hnae3_handle *handle, bool en, 861 int vector_id, 862 struct hnae3_ring_chain_node *ring_chain) 863 { 864 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 865 struct hnae3_ring_chain_node *node; 866 struct hclge_mbx_vf_to_pf_cmd *req; 867 struct hclgevf_desc desc; 868 int i = 0; 869 int status; 870 u8 type; 871 872 req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data; 873 874 for (node = ring_chain; node; node = node->next) { 875 int idx_offset = HCLGE_MBX_RING_MAP_BASIC_MSG_NUM + 876 HCLGE_MBX_RING_NODE_VARIABLE_NUM * i; 877 878 if (i == 0) { 879 hclgevf_cmd_setup_basic_desc(&desc, 880 HCLGEVF_OPC_MBX_VF_TO_PF, 881 false); 882 type = en ? 883 HCLGE_MBX_MAP_RING_TO_VECTOR : 884 HCLGE_MBX_UNMAP_RING_TO_VECTOR; 885 req->msg[0] = type; 886 req->msg[1] = vector_id; 887 } 888 889 req->msg[idx_offset] = 890 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B); 891 req->msg[idx_offset + 1] = node->tqp_index; 892 req->msg[idx_offset + 2] = hnae3_get_field(node->int_gl_idx, 893 HNAE3_RING_GL_IDX_M, 894 HNAE3_RING_GL_IDX_S); 895 896 i++; 897 if ((i == (HCLGE_MBX_VF_MSG_DATA_NUM - 898 HCLGE_MBX_RING_MAP_BASIC_MSG_NUM) / 899 HCLGE_MBX_RING_NODE_VARIABLE_NUM) || 900 !node->next) { 901 req->msg[2] = i; 902 903 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 904 if (status) { 905 dev_err(&hdev->pdev->dev, 906 "Map TQP fail, status is %d.\n", 907 status); 908 return status; 909 } 910 i = 0; 911 hclgevf_cmd_setup_basic_desc(&desc, 912 HCLGEVF_OPC_MBX_VF_TO_PF, 913 false); 914 req->msg[0] = type; 915 req->msg[1] = vector_id; 916 } 917 } 918 919 return 0; 920 } 921 922 static int hclgevf_map_ring_to_vector(struct hnae3_handle *handle, int vector, 923 struct hnae3_ring_chain_node *ring_chain) 924 { 925 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 926 int vector_id; 927 928 vector_id = hclgevf_get_vector_index(hdev, vector); 929 if (vector_id < 0) { 930 dev_err(&handle->pdev->dev, 931 "Get vector index fail. ret =%d\n", vector_id); 932 return vector_id; 933 } 934 935 return hclgevf_bind_ring_to_vector(handle, true, vector_id, ring_chain); 936 } 937 938 static int hclgevf_unmap_ring_from_vector( 939 struct hnae3_handle *handle, 940 int vector, 941 struct hnae3_ring_chain_node *ring_chain) 942 { 943 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 944 int ret, vector_id; 945 946 if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 947 return 0; 948 949 vector_id = hclgevf_get_vector_index(hdev, vector); 950 if (vector_id < 0) { 951 dev_err(&handle->pdev->dev, 952 "Get vector index fail. ret =%d\n", vector_id); 953 return vector_id; 954 } 955 956 ret = hclgevf_bind_ring_to_vector(handle, false, vector_id, ring_chain); 957 if (ret) 958 dev_err(&handle->pdev->dev, 959 "Unmap ring from vector fail. vector=%d, ret =%d\n", 960 vector_id, 961 ret); 962 963 return ret; 964 } 965 966 static int hclgevf_put_vector(struct hnae3_handle *handle, int vector) 967 { 968 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 969 int vector_id; 970 971 vector_id = hclgevf_get_vector_index(hdev, vector); 972 if (vector_id < 0) { 973 dev_err(&handle->pdev->dev, 974 "hclgevf_put_vector get vector index fail. ret =%d\n", 975 vector_id); 976 return vector_id; 977 } 978 979 hclgevf_free_vector(hdev, vector_id); 980 981 return 0; 982 } 983 984 static int hclgevf_cmd_set_promisc_mode(struct hclgevf_dev *hdev, 985 bool en_bc_pmc) 986 { 987 struct hclge_mbx_vf_to_pf_cmd *req; 988 struct hclgevf_desc desc; 989 int ret; 990 991 req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data; 992 993 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_MBX_VF_TO_PF, false); 994 req->msg[0] = HCLGE_MBX_SET_PROMISC_MODE; 995 req->msg[1] = en_bc_pmc ? 1 : 0; 996 997 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 998 if (ret) 999 dev_err(&hdev->pdev->dev, 1000 "Set promisc mode fail, status is %d.\n", ret); 1001 1002 return ret; 1003 } 1004 1005 static int hclgevf_set_promisc_mode(struct hclgevf_dev *hdev, bool en_bc_pmc) 1006 { 1007 return hclgevf_cmd_set_promisc_mode(hdev, en_bc_pmc); 1008 } 1009 1010 static int hclgevf_tqp_enable(struct hclgevf_dev *hdev, int tqp_id, 1011 int stream_id, bool enable) 1012 { 1013 struct hclgevf_cfg_com_tqp_queue_cmd *req; 1014 struct hclgevf_desc desc; 1015 int status; 1016 1017 req = (struct hclgevf_cfg_com_tqp_queue_cmd *)desc.data; 1018 1019 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_CFG_COM_TQP_QUEUE, 1020 false); 1021 req->tqp_id = cpu_to_le16(tqp_id & HCLGEVF_RING_ID_MASK); 1022 req->stream_id = cpu_to_le16(stream_id); 1023 req->enable |= enable << HCLGEVF_TQP_ENABLE_B; 1024 1025 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1026 if (status) 1027 dev_err(&hdev->pdev->dev, 1028 "TQP enable fail, status =%d.\n", status); 1029 1030 return status; 1031 } 1032 1033 static void hclgevf_reset_tqp_stats(struct hnae3_handle *handle) 1034 { 1035 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 1036 struct hclgevf_tqp *tqp; 1037 int i; 1038 1039 for (i = 0; i < kinfo->num_tqps; i++) { 1040 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 1041 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats)); 1042 } 1043 } 1044 1045 static void hclgevf_get_mac_addr(struct hnae3_handle *handle, u8 *p) 1046 { 1047 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1048 1049 ether_addr_copy(p, hdev->hw.mac.mac_addr); 1050 } 1051 1052 static int hclgevf_set_mac_addr(struct hnae3_handle *handle, void *p, 1053 bool is_first) 1054 { 1055 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1056 u8 *old_mac_addr = (u8 *)hdev->hw.mac.mac_addr; 1057 u8 *new_mac_addr = (u8 *)p; 1058 u8 msg_data[ETH_ALEN * 2]; 1059 u16 subcode; 1060 int status; 1061 1062 ether_addr_copy(msg_data, new_mac_addr); 1063 ether_addr_copy(&msg_data[ETH_ALEN], old_mac_addr); 1064 1065 subcode = is_first ? HCLGE_MBX_MAC_VLAN_UC_ADD : 1066 HCLGE_MBX_MAC_VLAN_UC_MODIFY; 1067 1068 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 1069 subcode, msg_data, ETH_ALEN * 2, 1070 true, NULL, 0); 1071 if (!status) 1072 ether_addr_copy(hdev->hw.mac.mac_addr, new_mac_addr); 1073 1074 return status; 1075 } 1076 1077 static int hclgevf_add_uc_addr(struct hnae3_handle *handle, 1078 const unsigned char *addr) 1079 { 1080 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1081 1082 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 1083 HCLGE_MBX_MAC_VLAN_UC_ADD, 1084 addr, ETH_ALEN, false, NULL, 0); 1085 } 1086 1087 static int hclgevf_rm_uc_addr(struct hnae3_handle *handle, 1088 const unsigned char *addr) 1089 { 1090 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1091 1092 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 1093 HCLGE_MBX_MAC_VLAN_UC_REMOVE, 1094 addr, ETH_ALEN, false, NULL, 0); 1095 } 1096 1097 static int hclgevf_add_mc_addr(struct hnae3_handle *handle, 1098 const unsigned char *addr) 1099 { 1100 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1101 1102 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 1103 HCLGE_MBX_MAC_VLAN_MC_ADD, 1104 addr, ETH_ALEN, false, NULL, 0); 1105 } 1106 1107 static int hclgevf_rm_mc_addr(struct hnae3_handle *handle, 1108 const unsigned char *addr) 1109 { 1110 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1111 1112 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 1113 HCLGE_MBX_MAC_VLAN_MC_REMOVE, 1114 addr, ETH_ALEN, false, NULL, 0); 1115 } 1116 1117 static int hclgevf_set_vlan_filter(struct hnae3_handle *handle, 1118 __be16 proto, u16 vlan_id, 1119 bool is_kill) 1120 { 1121 #define HCLGEVF_VLAN_MBX_MSG_LEN 5 1122 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1123 u8 msg_data[HCLGEVF_VLAN_MBX_MSG_LEN]; 1124 1125 if (vlan_id > 4095) 1126 return -EINVAL; 1127 1128 if (proto != htons(ETH_P_8021Q)) 1129 return -EPROTONOSUPPORT; 1130 1131 msg_data[0] = is_kill; 1132 memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id)); 1133 memcpy(&msg_data[3], &proto, sizeof(proto)); 1134 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 1135 HCLGE_MBX_VLAN_FILTER, msg_data, 1136 HCLGEVF_VLAN_MBX_MSG_LEN, false, NULL, 0); 1137 } 1138 1139 static int hclgevf_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) 1140 { 1141 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1142 u8 msg_data; 1143 1144 msg_data = enable ? 1 : 0; 1145 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 1146 HCLGE_MBX_VLAN_RX_OFF_CFG, &msg_data, 1147 1, false, NULL, 0); 1148 } 1149 1150 static int hclgevf_reset_tqp(struct hnae3_handle *handle, u16 queue_id) 1151 { 1152 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1153 u8 msg_data[2]; 1154 int ret; 1155 1156 memcpy(&msg_data[0], &queue_id, sizeof(queue_id)); 1157 1158 /* disable vf queue before send queue reset msg to PF */ 1159 ret = hclgevf_tqp_enable(hdev, queue_id, 0, false); 1160 if (ret) 1161 return ret; 1162 1163 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_QUEUE_RESET, 0, msg_data, 1164 2, true, NULL, 0); 1165 } 1166 1167 static int hclgevf_set_mtu(struct hnae3_handle *handle, int new_mtu) 1168 { 1169 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1170 1171 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MTU, 0, (u8 *)&new_mtu, 1172 sizeof(new_mtu), true, NULL, 0); 1173 } 1174 1175 static int hclgevf_notify_client(struct hclgevf_dev *hdev, 1176 enum hnae3_reset_notify_type type) 1177 { 1178 struct hnae3_client *client = hdev->nic_client; 1179 struct hnae3_handle *handle = &hdev->nic; 1180 int ret; 1181 1182 if (!client->ops->reset_notify) 1183 return -EOPNOTSUPP; 1184 1185 ret = client->ops->reset_notify(handle, type); 1186 if (ret) 1187 dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n", 1188 type, ret); 1189 1190 return ret; 1191 } 1192 1193 static void hclgevf_flr_done(struct hnae3_ae_dev *ae_dev) 1194 { 1195 struct hclgevf_dev *hdev = ae_dev->priv; 1196 1197 set_bit(HNAE3_FLR_DONE, &hdev->flr_state); 1198 } 1199 1200 static int hclgevf_flr_poll_timeout(struct hclgevf_dev *hdev, 1201 unsigned long delay_us, 1202 unsigned long wait_cnt) 1203 { 1204 unsigned long cnt = 0; 1205 1206 while (!test_bit(HNAE3_FLR_DONE, &hdev->flr_state) && 1207 cnt++ < wait_cnt) 1208 usleep_range(delay_us, delay_us * 2); 1209 1210 if (!test_bit(HNAE3_FLR_DONE, &hdev->flr_state)) { 1211 dev_err(&hdev->pdev->dev, 1212 "flr wait timeout\n"); 1213 return -ETIMEDOUT; 1214 } 1215 1216 return 0; 1217 } 1218 1219 static int hclgevf_reset_wait(struct hclgevf_dev *hdev) 1220 { 1221 #define HCLGEVF_RESET_WAIT_US 20000 1222 #define HCLGEVF_RESET_WAIT_CNT 2000 1223 #define HCLGEVF_RESET_WAIT_TIMEOUT_US \ 1224 (HCLGEVF_RESET_WAIT_US * HCLGEVF_RESET_WAIT_CNT) 1225 1226 u32 val; 1227 int ret; 1228 1229 /* wait to check the hardware reset completion status */ 1230 val = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 1231 dev_info(&hdev->pdev->dev, "checking vf resetting status: %x\n", val); 1232 1233 if (hdev->reset_type == HNAE3_FLR_RESET) 1234 return hclgevf_flr_poll_timeout(hdev, 1235 HCLGEVF_RESET_WAIT_US, 1236 HCLGEVF_RESET_WAIT_CNT); 1237 1238 ret = readl_poll_timeout(hdev->hw.io_base + HCLGEVF_RST_ING, val, 1239 !(val & HCLGEVF_RST_ING_BITS), 1240 HCLGEVF_RESET_WAIT_US, 1241 HCLGEVF_RESET_WAIT_TIMEOUT_US); 1242 1243 /* hardware completion status should be available by this time */ 1244 if (ret) { 1245 dev_err(&hdev->pdev->dev, 1246 "could'nt get reset done status from h/w, timeout!\n"); 1247 return ret; 1248 } 1249 1250 /* we will wait a bit more to let reset of the stack to complete. This 1251 * might happen in case reset assertion was made by PF. Yes, this also 1252 * means we might end up waiting bit more even for VF reset. 1253 */ 1254 msleep(5000); 1255 1256 return 0; 1257 } 1258 1259 static int hclgevf_reset_stack(struct hclgevf_dev *hdev) 1260 { 1261 int ret; 1262 1263 /* uninitialize the nic client */ 1264 ret = hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT); 1265 if (ret) 1266 return ret; 1267 1268 /* re-initialize the hclge device */ 1269 ret = hclgevf_reset_hdev(hdev); 1270 if (ret) { 1271 dev_err(&hdev->pdev->dev, 1272 "hclge device re-init failed, VF is disabled!\n"); 1273 return ret; 1274 } 1275 1276 /* bring up the nic client again */ 1277 ret = hclgevf_notify_client(hdev, HNAE3_INIT_CLIENT); 1278 if (ret) 1279 return ret; 1280 1281 return hclgevf_notify_client(hdev, HNAE3_RESTORE_CLIENT); 1282 } 1283 1284 static int hclgevf_reset_prepare_wait(struct hclgevf_dev *hdev) 1285 { 1286 int ret = 0; 1287 1288 switch (hdev->reset_type) { 1289 case HNAE3_VF_FUNC_RESET: 1290 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_RESET, 0, NULL, 1291 0, true, NULL, sizeof(u8)); 1292 break; 1293 case HNAE3_FLR_RESET: 1294 set_bit(HNAE3_FLR_DOWN, &hdev->flr_state); 1295 break; 1296 default: 1297 break; 1298 } 1299 1300 set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 1301 1302 dev_info(&hdev->pdev->dev, "prepare reset(%d) wait done, ret:%d\n", 1303 hdev->reset_type, ret); 1304 1305 return ret; 1306 } 1307 1308 static int hclgevf_reset(struct hclgevf_dev *hdev) 1309 { 1310 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1311 int ret; 1312 1313 /* Initialize ae_dev reset status as well, in case enet layer wants to 1314 * know if device is undergoing reset 1315 */ 1316 ae_dev->reset_type = hdev->reset_type; 1317 hdev->reset_count++; 1318 rtnl_lock(); 1319 1320 /* bring down the nic to stop any ongoing TX/RX */ 1321 ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 1322 if (ret) 1323 goto err_reset_lock; 1324 1325 rtnl_unlock(); 1326 1327 ret = hclgevf_reset_prepare_wait(hdev); 1328 if (ret) 1329 goto err_reset; 1330 1331 /* check if VF could successfully fetch the hardware reset completion 1332 * status from the hardware 1333 */ 1334 ret = hclgevf_reset_wait(hdev); 1335 if (ret) { 1336 /* can't do much in this situation, will disable VF */ 1337 dev_err(&hdev->pdev->dev, 1338 "VF failed(=%d) to fetch H/W reset completion status\n", 1339 ret); 1340 goto err_reset; 1341 } 1342 1343 rtnl_lock(); 1344 1345 /* now, re-initialize the nic client and ae device*/ 1346 ret = hclgevf_reset_stack(hdev); 1347 if (ret) { 1348 dev_err(&hdev->pdev->dev, "failed to reset VF stack\n"); 1349 goto err_reset_lock; 1350 } 1351 1352 /* bring up the nic to enable TX/RX again */ 1353 ret = hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 1354 if (ret) 1355 goto err_reset_lock; 1356 1357 rtnl_unlock(); 1358 1359 hdev->last_reset_time = jiffies; 1360 ae_dev->reset_type = HNAE3_NONE_RESET; 1361 1362 return ret; 1363 err_reset_lock: 1364 rtnl_unlock(); 1365 err_reset: 1366 /* When VF reset failed, only the higher level reset asserted by PF 1367 * can restore it, so re-initialize the command queue to receive 1368 * this higher reset event. 1369 */ 1370 hclgevf_cmd_init(hdev); 1371 dev_err(&hdev->pdev->dev, "failed to reset VF\n"); 1372 1373 return ret; 1374 } 1375 1376 static enum hnae3_reset_type hclgevf_get_reset_level(struct hclgevf_dev *hdev, 1377 unsigned long *addr) 1378 { 1379 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; 1380 1381 /* return the highest priority reset level amongst all */ 1382 if (test_bit(HNAE3_VF_RESET, addr)) { 1383 rst_level = HNAE3_VF_RESET; 1384 clear_bit(HNAE3_VF_RESET, addr); 1385 clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1386 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1387 } else if (test_bit(HNAE3_VF_FULL_RESET, addr)) { 1388 rst_level = HNAE3_VF_FULL_RESET; 1389 clear_bit(HNAE3_VF_FULL_RESET, addr); 1390 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1391 } else if (test_bit(HNAE3_VF_PF_FUNC_RESET, addr)) { 1392 rst_level = HNAE3_VF_PF_FUNC_RESET; 1393 clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1394 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1395 } else if (test_bit(HNAE3_VF_FUNC_RESET, addr)) { 1396 rst_level = HNAE3_VF_FUNC_RESET; 1397 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1398 } else if (test_bit(HNAE3_FLR_RESET, addr)) { 1399 rst_level = HNAE3_FLR_RESET; 1400 clear_bit(HNAE3_FLR_RESET, addr); 1401 } 1402 1403 return rst_level; 1404 } 1405 1406 static void hclgevf_reset_event(struct pci_dev *pdev, 1407 struct hnae3_handle *handle) 1408 { 1409 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 1410 struct hclgevf_dev *hdev = ae_dev->priv; 1411 1412 dev_info(&hdev->pdev->dev, "received reset request from VF enet\n"); 1413 1414 if (hdev->default_reset_request) 1415 hdev->reset_level = 1416 hclgevf_get_reset_level(hdev, 1417 &hdev->default_reset_request); 1418 else 1419 hdev->reset_level = HNAE3_VF_FUNC_RESET; 1420 1421 /* reset of this VF requested */ 1422 set_bit(HCLGEVF_RESET_REQUESTED, &hdev->reset_state); 1423 hclgevf_reset_task_schedule(hdev); 1424 1425 hdev->last_reset_time = jiffies; 1426 } 1427 1428 static void hclgevf_set_def_reset_request(struct hnae3_ae_dev *ae_dev, 1429 enum hnae3_reset_type rst_type) 1430 { 1431 struct hclgevf_dev *hdev = ae_dev->priv; 1432 1433 set_bit(rst_type, &hdev->default_reset_request); 1434 } 1435 1436 static void hclgevf_flr_prepare(struct hnae3_ae_dev *ae_dev) 1437 { 1438 #define HCLGEVF_FLR_WAIT_MS 100 1439 #define HCLGEVF_FLR_WAIT_CNT 50 1440 struct hclgevf_dev *hdev = ae_dev->priv; 1441 int cnt = 0; 1442 1443 clear_bit(HNAE3_FLR_DOWN, &hdev->flr_state); 1444 clear_bit(HNAE3_FLR_DONE, &hdev->flr_state); 1445 set_bit(HNAE3_FLR_RESET, &hdev->default_reset_request); 1446 hclgevf_reset_event(hdev->pdev, NULL); 1447 1448 while (!test_bit(HNAE3_FLR_DOWN, &hdev->flr_state) && 1449 cnt++ < HCLGEVF_FLR_WAIT_CNT) 1450 msleep(HCLGEVF_FLR_WAIT_MS); 1451 1452 if (!test_bit(HNAE3_FLR_DOWN, &hdev->flr_state)) 1453 dev_err(&hdev->pdev->dev, 1454 "flr wait down timeout: %d\n", cnt); 1455 } 1456 1457 static u32 hclgevf_get_fw_version(struct hnae3_handle *handle) 1458 { 1459 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1460 1461 return hdev->fw_version; 1462 } 1463 1464 static void hclgevf_get_misc_vector(struct hclgevf_dev *hdev) 1465 { 1466 struct hclgevf_misc_vector *vector = &hdev->misc_vector; 1467 1468 vector->vector_irq = pci_irq_vector(hdev->pdev, 1469 HCLGEVF_MISC_VECTOR_NUM); 1470 vector->addr = hdev->hw.io_base + HCLGEVF_MISC_VECTOR_REG_BASE; 1471 /* vector status always valid for Vector 0 */ 1472 hdev->vector_status[HCLGEVF_MISC_VECTOR_NUM] = 0; 1473 hdev->vector_irq[HCLGEVF_MISC_VECTOR_NUM] = vector->vector_irq; 1474 1475 hdev->num_msi_left -= 1; 1476 hdev->num_msi_used += 1; 1477 } 1478 1479 void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev) 1480 { 1481 if (!test_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state) && 1482 !test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) { 1483 set_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state); 1484 schedule_work(&hdev->rst_service_task); 1485 } 1486 } 1487 1488 void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev) 1489 { 1490 if (!test_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state) && 1491 !test_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) { 1492 set_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 1493 schedule_work(&hdev->mbx_service_task); 1494 } 1495 } 1496 1497 static void hclgevf_task_schedule(struct hclgevf_dev *hdev) 1498 { 1499 if (!test_bit(HCLGEVF_STATE_DOWN, &hdev->state) && 1500 !test_and_set_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state)) 1501 schedule_work(&hdev->service_task); 1502 } 1503 1504 static void hclgevf_deferred_task_schedule(struct hclgevf_dev *hdev) 1505 { 1506 /* if we have any pending mailbox event then schedule the mbx task */ 1507 if (hdev->mbx_event_pending) 1508 hclgevf_mbx_task_schedule(hdev); 1509 1510 if (test_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state)) 1511 hclgevf_reset_task_schedule(hdev); 1512 } 1513 1514 static void hclgevf_service_timer(struct timer_list *t) 1515 { 1516 struct hclgevf_dev *hdev = from_timer(hdev, t, service_timer); 1517 1518 mod_timer(&hdev->service_timer, jiffies + 5 * HZ); 1519 1520 hclgevf_task_schedule(hdev); 1521 } 1522 1523 static void hclgevf_reset_service_task(struct work_struct *work) 1524 { 1525 struct hclgevf_dev *hdev = 1526 container_of(work, struct hclgevf_dev, rst_service_task); 1527 int ret; 1528 1529 if (test_and_set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 1530 return; 1531 1532 clear_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state); 1533 1534 if (test_and_clear_bit(HCLGEVF_RESET_PENDING, 1535 &hdev->reset_state)) { 1536 /* PF has initmated that it is about to reset the hardware. 1537 * We now have to poll & check if harware has actually completed 1538 * the reset sequence. On hardware reset completion, VF needs to 1539 * reset the client and ae device. 1540 */ 1541 hdev->reset_attempts = 0; 1542 1543 hdev->last_reset_time = jiffies; 1544 while ((hdev->reset_type = 1545 hclgevf_get_reset_level(hdev, &hdev->reset_pending)) 1546 != HNAE3_NONE_RESET) { 1547 ret = hclgevf_reset(hdev); 1548 if (ret) 1549 dev_err(&hdev->pdev->dev, 1550 "VF stack reset failed %d.\n", ret); 1551 } 1552 } else if (test_and_clear_bit(HCLGEVF_RESET_REQUESTED, 1553 &hdev->reset_state)) { 1554 /* we could be here when either of below happens: 1555 * 1. reset was initiated due to watchdog timeout due to 1556 * a. IMP was earlier reset and our TX got choked down and 1557 * which resulted in watchdog reacting and inducing VF 1558 * reset. This also means our cmdq would be unreliable. 1559 * b. problem in TX due to other lower layer(example link 1560 * layer not functioning properly etc.) 1561 * 2. VF reset might have been initiated due to some config 1562 * change. 1563 * 1564 * NOTE: Theres no clear way to detect above cases than to react 1565 * to the response of PF for this reset request. PF will ack the 1566 * 1b and 2. cases but we will not get any intimation about 1a 1567 * from PF as cmdq would be in unreliable state i.e. mailbox 1568 * communication between PF and VF would be broken. 1569 */ 1570 1571 /* if we are never geting into pending state it means either: 1572 * 1. PF is not receiving our request which could be due to IMP 1573 * reset 1574 * 2. PF is screwed 1575 * We cannot do much for 2. but to check first we can try reset 1576 * our PCIe + stack and see if it alleviates the problem. 1577 */ 1578 if (hdev->reset_attempts > 3) { 1579 /* prepare for full reset of stack + pcie interface */ 1580 set_bit(HNAE3_VF_FULL_RESET, &hdev->reset_pending); 1581 1582 /* "defer" schedule the reset task again */ 1583 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1584 } else { 1585 hdev->reset_attempts++; 1586 1587 set_bit(hdev->reset_level, &hdev->reset_pending); 1588 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1589 } 1590 hclgevf_reset_task_schedule(hdev); 1591 } 1592 1593 clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 1594 } 1595 1596 static void hclgevf_mailbox_service_task(struct work_struct *work) 1597 { 1598 struct hclgevf_dev *hdev; 1599 1600 hdev = container_of(work, struct hclgevf_dev, mbx_service_task); 1601 1602 if (test_and_set_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) 1603 return; 1604 1605 clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 1606 1607 hclgevf_mbx_async_handler(hdev); 1608 1609 clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 1610 } 1611 1612 static void hclgevf_keep_alive_timer(struct timer_list *t) 1613 { 1614 struct hclgevf_dev *hdev = from_timer(hdev, t, keep_alive_timer); 1615 1616 schedule_work(&hdev->keep_alive_task); 1617 mod_timer(&hdev->keep_alive_timer, jiffies + 2 * HZ); 1618 } 1619 1620 static void hclgevf_keep_alive_task(struct work_struct *work) 1621 { 1622 struct hclgevf_dev *hdev; 1623 u8 respmsg; 1624 int ret; 1625 1626 hdev = container_of(work, struct hclgevf_dev, keep_alive_task); 1627 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_KEEP_ALIVE, 0, NULL, 1628 0, false, &respmsg, sizeof(u8)); 1629 if (ret) 1630 dev_err(&hdev->pdev->dev, 1631 "VF sends keep alive cmd failed(=%d)\n", ret); 1632 } 1633 1634 static void hclgevf_service_task(struct work_struct *work) 1635 { 1636 struct hclgevf_dev *hdev; 1637 1638 hdev = container_of(work, struct hclgevf_dev, service_task); 1639 1640 /* request the link status from the PF. PF would be able to tell VF 1641 * about such updates in future so we might remove this later 1642 */ 1643 hclgevf_request_link_info(hdev); 1644 1645 hclgevf_deferred_task_schedule(hdev); 1646 1647 clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 1648 } 1649 1650 static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regclr) 1651 { 1652 hclgevf_write_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_SRC_REG, regclr); 1653 } 1654 1655 static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev, 1656 u32 *clearval) 1657 { 1658 u32 cmdq_src_reg, rst_ing_reg; 1659 1660 /* fetch the events from their corresponding regs */ 1661 cmdq_src_reg = hclgevf_read_dev(&hdev->hw, 1662 HCLGEVF_VECTOR0_CMDQ_SRC_REG); 1663 1664 if (BIT(HCLGEVF_VECTOR0_RST_INT_B) & cmdq_src_reg) { 1665 rst_ing_reg = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 1666 dev_info(&hdev->pdev->dev, 1667 "receive reset interrupt 0x%x!\n", rst_ing_reg); 1668 set_bit(HNAE3_VF_RESET, &hdev->reset_pending); 1669 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1670 set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 1671 cmdq_src_reg &= ~BIT(HCLGEVF_VECTOR0_RST_INT_B); 1672 *clearval = cmdq_src_reg; 1673 return HCLGEVF_VECTOR0_EVENT_RST; 1674 } 1675 1676 /* check for vector0 mailbox(=CMDQ RX) event source */ 1677 if (BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) { 1678 cmdq_src_reg &= ~BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 1679 *clearval = cmdq_src_reg; 1680 return HCLGEVF_VECTOR0_EVENT_MBX; 1681 } 1682 1683 dev_dbg(&hdev->pdev->dev, "vector 0 interrupt from unknown source\n"); 1684 1685 return HCLGEVF_VECTOR0_EVENT_OTHER; 1686 } 1687 1688 static void hclgevf_enable_vector(struct hclgevf_misc_vector *vector, bool en) 1689 { 1690 writel(en ? 1 : 0, vector->addr); 1691 } 1692 1693 static irqreturn_t hclgevf_misc_irq_handle(int irq, void *data) 1694 { 1695 enum hclgevf_evt_cause event_cause; 1696 struct hclgevf_dev *hdev = data; 1697 u32 clearval; 1698 1699 hclgevf_enable_vector(&hdev->misc_vector, false); 1700 event_cause = hclgevf_check_evt_cause(hdev, &clearval); 1701 1702 switch (event_cause) { 1703 case HCLGEVF_VECTOR0_EVENT_RST: 1704 hclgevf_reset_task_schedule(hdev); 1705 break; 1706 case HCLGEVF_VECTOR0_EVENT_MBX: 1707 hclgevf_mbx_handler(hdev); 1708 break; 1709 default: 1710 break; 1711 } 1712 1713 if (event_cause != HCLGEVF_VECTOR0_EVENT_OTHER) { 1714 hclgevf_clear_event_cause(hdev, clearval); 1715 hclgevf_enable_vector(&hdev->misc_vector, true); 1716 } 1717 1718 return IRQ_HANDLED; 1719 } 1720 1721 static int hclgevf_configure(struct hclgevf_dev *hdev) 1722 { 1723 int ret; 1724 1725 hdev->hw.mac.media_type = HNAE3_MEDIA_TYPE_NONE; 1726 1727 /* get queue configuration from PF */ 1728 ret = hclgevf_get_queue_info(hdev); 1729 if (ret) 1730 return ret; 1731 /* get tc configuration from PF */ 1732 return hclgevf_get_tc_info(hdev); 1733 } 1734 1735 static int hclgevf_alloc_hdev(struct hnae3_ae_dev *ae_dev) 1736 { 1737 struct pci_dev *pdev = ae_dev->pdev; 1738 struct hclgevf_dev *hdev; 1739 1740 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 1741 if (!hdev) 1742 return -ENOMEM; 1743 1744 hdev->pdev = pdev; 1745 hdev->ae_dev = ae_dev; 1746 ae_dev->priv = hdev; 1747 1748 return 0; 1749 } 1750 1751 static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev) 1752 { 1753 struct hnae3_handle *roce = &hdev->roce; 1754 struct hnae3_handle *nic = &hdev->nic; 1755 1756 roce->rinfo.num_vectors = hdev->num_roce_msix; 1757 1758 if (hdev->num_msi_left < roce->rinfo.num_vectors || 1759 hdev->num_msi_left == 0) 1760 return -EINVAL; 1761 1762 roce->rinfo.base_vector = hdev->roce_base_vector; 1763 1764 roce->rinfo.netdev = nic->kinfo.netdev; 1765 roce->rinfo.roce_io_base = hdev->hw.io_base; 1766 1767 roce->pdev = nic->pdev; 1768 roce->ae_algo = nic->ae_algo; 1769 roce->numa_node_mask = nic->numa_node_mask; 1770 1771 return 0; 1772 } 1773 1774 static int hclgevf_config_gro(struct hclgevf_dev *hdev, bool en) 1775 { 1776 struct hclgevf_cfg_gro_status_cmd *req; 1777 struct hclgevf_desc desc; 1778 int ret; 1779 1780 if (!hnae3_dev_gro_supported(hdev)) 1781 return 0; 1782 1783 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_GRO_GENERIC_CONFIG, 1784 false); 1785 req = (struct hclgevf_cfg_gro_status_cmd *)desc.data; 1786 1787 req->gro_en = cpu_to_le16(en ? 1 : 0); 1788 1789 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1790 if (ret) 1791 dev_err(&hdev->pdev->dev, 1792 "VF GRO hardware config cmd failed, ret = %d.\n", ret); 1793 1794 return ret; 1795 } 1796 1797 static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev) 1798 { 1799 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 1800 int i, ret; 1801 1802 rss_cfg->rss_size = hdev->rss_size_max; 1803 1804 if (hdev->pdev->revision >= 0x21) { 1805 rss_cfg->hash_algo = HCLGEVF_RSS_HASH_ALGO_SIMPLE; 1806 memcpy(rss_cfg->rss_hash_key, hclgevf_hash_key, 1807 HCLGEVF_RSS_KEY_SIZE); 1808 1809 ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 1810 rss_cfg->rss_hash_key); 1811 if (ret) 1812 return ret; 1813 1814 rss_cfg->rss_tuple_sets.ipv4_tcp_en = 1815 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1816 rss_cfg->rss_tuple_sets.ipv4_udp_en = 1817 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1818 rss_cfg->rss_tuple_sets.ipv4_sctp_en = 1819 HCLGEVF_RSS_INPUT_TUPLE_SCTP; 1820 rss_cfg->rss_tuple_sets.ipv4_fragment_en = 1821 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1822 rss_cfg->rss_tuple_sets.ipv6_tcp_en = 1823 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1824 rss_cfg->rss_tuple_sets.ipv6_udp_en = 1825 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1826 rss_cfg->rss_tuple_sets.ipv6_sctp_en = 1827 HCLGEVF_RSS_INPUT_TUPLE_SCTP; 1828 rss_cfg->rss_tuple_sets.ipv6_fragment_en = 1829 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1830 1831 ret = hclgevf_set_rss_input_tuple(hdev, rss_cfg); 1832 if (ret) 1833 return ret; 1834 1835 } 1836 1837 /* Initialize RSS indirect table for each vport */ 1838 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 1839 rss_cfg->rss_indirection_tbl[i] = i % hdev->rss_size_max; 1840 1841 ret = hclgevf_set_rss_indir_table(hdev); 1842 if (ret) 1843 return ret; 1844 1845 return hclgevf_set_rss_tc_mode(hdev, hdev->rss_size_max); 1846 } 1847 1848 static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev) 1849 { 1850 /* other vlan config(like, VLAN TX/RX offload) would also be added 1851 * here later 1852 */ 1853 return hclgevf_set_vlan_filter(&hdev->nic, htons(ETH_P_8021Q), 0, 1854 false); 1855 } 1856 1857 static void hclgevf_set_timer_task(struct hnae3_handle *handle, bool enable) 1858 { 1859 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1860 1861 if (enable) { 1862 mod_timer(&hdev->service_timer, jiffies + HZ); 1863 } else { 1864 del_timer_sync(&hdev->service_timer); 1865 cancel_work_sync(&hdev->service_task); 1866 clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 1867 } 1868 } 1869 1870 static int hclgevf_ae_start(struct hnae3_handle *handle) 1871 { 1872 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1873 1874 /* reset tqp stats */ 1875 hclgevf_reset_tqp_stats(handle); 1876 1877 hclgevf_request_link_info(hdev); 1878 1879 clear_bit(HCLGEVF_STATE_DOWN, &hdev->state); 1880 1881 return 0; 1882 } 1883 1884 static void hclgevf_ae_stop(struct hnae3_handle *handle) 1885 { 1886 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1887 int i; 1888 1889 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 1890 1891 for (i = 0; i < handle->kinfo.num_tqps; i++) 1892 hclgevf_reset_tqp(handle, i); 1893 1894 /* reset tqp stats */ 1895 hclgevf_reset_tqp_stats(handle); 1896 hclgevf_update_link_status(hdev, 0); 1897 } 1898 1899 static int hclgevf_set_alive(struct hnae3_handle *handle, bool alive) 1900 { 1901 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1902 u8 msg_data; 1903 1904 msg_data = alive ? 1 : 0; 1905 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_ALIVE, 1906 0, &msg_data, 1, false, NULL, 0); 1907 } 1908 1909 static int hclgevf_client_start(struct hnae3_handle *handle) 1910 { 1911 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1912 1913 mod_timer(&hdev->keep_alive_timer, jiffies + 2 * HZ); 1914 return hclgevf_set_alive(handle, true); 1915 } 1916 1917 static void hclgevf_client_stop(struct hnae3_handle *handle) 1918 { 1919 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1920 int ret; 1921 1922 ret = hclgevf_set_alive(handle, false); 1923 if (ret) 1924 dev_warn(&hdev->pdev->dev, 1925 "%s failed %d\n", __func__, ret); 1926 1927 del_timer_sync(&hdev->keep_alive_timer); 1928 cancel_work_sync(&hdev->keep_alive_task); 1929 } 1930 1931 static void hclgevf_state_init(struct hclgevf_dev *hdev) 1932 { 1933 /* setup tasks for the MBX */ 1934 INIT_WORK(&hdev->mbx_service_task, hclgevf_mailbox_service_task); 1935 clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 1936 clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 1937 1938 /* setup tasks for service timer */ 1939 timer_setup(&hdev->service_timer, hclgevf_service_timer, 0); 1940 1941 INIT_WORK(&hdev->service_task, hclgevf_service_task); 1942 clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 1943 1944 INIT_WORK(&hdev->rst_service_task, hclgevf_reset_service_task); 1945 1946 mutex_init(&hdev->mbx_resp.mbx_mutex); 1947 1948 /* bring the device down */ 1949 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 1950 } 1951 1952 static void hclgevf_state_uninit(struct hclgevf_dev *hdev) 1953 { 1954 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 1955 1956 if (hdev->service_timer.function) 1957 del_timer_sync(&hdev->service_timer); 1958 if (hdev->service_task.func) 1959 cancel_work_sync(&hdev->service_task); 1960 if (hdev->mbx_service_task.func) 1961 cancel_work_sync(&hdev->mbx_service_task); 1962 if (hdev->rst_service_task.func) 1963 cancel_work_sync(&hdev->rst_service_task); 1964 1965 mutex_destroy(&hdev->mbx_resp.mbx_mutex); 1966 } 1967 1968 static int hclgevf_init_msi(struct hclgevf_dev *hdev) 1969 { 1970 struct pci_dev *pdev = hdev->pdev; 1971 int vectors; 1972 int i; 1973 1974 if (hnae3_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B)) 1975 vectors = pci_alloc_irq_vectors(pdev, 1976 hdev->roce_base_msix_offset + 1, 1977 hdev->num_msi, 1978 PCI_IRQ_MSIX); 1979 else 1980 vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi, 1981 PCI_IRQ_MSI | PCI_IRQ_MSIX); 1982 1983 if (vectors < 0) { 1984 dev_err(&pdev->dev, 1985 "failed(%d) to allocate MSI/MSI-X vectors\n", 1986 vectors); 1987 return vectors; 1988 } 1989 if (vectors < hdev->num_msi) 1990 dev_warn(&hdev->pdev->dev, 1991 "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n", 1992 hdev->num_msi, vectors); 1993 1994 hdev->num_msi = vectors; 1995 hdev->num_msi_left = vectors; 1996 hdev->base_msi_vector = pdev->irq; 1997 hdev->roce_base_vector = pdev->irq + hdev->roce_base_msix_offset; 1998 1999 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 2000 sizeof(u16), GFP_KERNEL); 2001 if (!hdev->vector_status) { 2002 pci_free_irq_vectors(pdev); 2003 return -ENOMEM; 2004 } 2005 2006 for (i = 0; i < hdev->num_msi; i++) 2007 hdev->vector_status[i] = HCLGEVF_INVALID_VPORT; 2008 2009 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 2010 sizeof(int), GFP_KERNEL); 2011 if (!hdev->vector_irq) { 2012 devm_kfree(&pdev->dev, hdev->vector_status); 2013 pci_free_irq_vectors(pdev); 2014 return -ENOMEM; 2015 } 2016 2017 return 0; 2018 } 2019 2020 static void hclgevf_uninit_msi(struct hclgevf_dev *hdev) 2021 { 2022 struct pci_dev *pdev = hdev->pdev; 2023 2024 devm_kfree(&pdev->dev, hdev->vector_status); 2025 devm_kfree(&pdev->dev, hdev->vector_irq); 2026 pci_free_irq_vectors(pdev); 2027 } 2028 2029 static int hclgevf_misc_irq_init(struct hclgevf_dev *hdev) 2030 { 2031 int ret = 0; 2032 2033 hclgevf_get_misc_vector(hdev); 2034 2035 ret = request_irq(hdev->misc_vector.vector_irq, hclgevf_misc_irq_handle, 2036 0, "hclgevf_cmd", hdev); 2037 if (ret) { 2038 dev_err(&hdev->pdev->dev, "VF failed to request misc irq(%d)\n", 2039 hdev->misc_vector.vector_irq); 2040 return ret; 2041 } 2042 2043 hclgevf_clear_event_cause(hdev, 0); 2044 2045 /* enable misc. vector(vector 0) */ 2046 hclgevf_enable_vector(&hdev->misc_vector, true); 2047 2048 return ret; 2049 } 2050 2051 static void hclgevf_misc_irq_uninit(struct hclgevf_dev *hdev) 2052 { 2053 /* disable misc vector(vector 0) */ 2054 hclgevf_enable_vector(&hdev->misc_vector, false); 2055 synchronize_irq(hdev->misc_vector.vector_irq); 2056 free_irq(hdev->misc_vector.vector_irq, hdev); 2057 hclgevf_free_vector(hdev, 0); 2058 } 2059 2060 static int hclgevf_init_client_instance(struct hnae3_client *client, 2061 struct hnae3_ae_dev *ae_dev) 2062 { 2063 struct hclgevf_dev *hdev = ae_dev->priv; 2064 int ret; 2065 2066 switch (client->type) { 2067 case HNAE3_CLIENT_KNIC: 2068 hdev->nic_client = client; 2069 hdev->nic.client = client; 2070 2071 ret = client->ops->init_instance(&hdev->nic); 2072 if (ret) 2073 goto clear_nic; 2074 2075 hnae3_set_client_init_flag(client, ae_dev, 1); 2076 2077 if (hdev->roce_client && hnae3_dev_roce_supported(hdev)) { 2078 struct hnae3_client *rc = hdev->roce_client; 2079 2080 ret = hclgevf_init_roce_base_info(hdev); 2081 if (ret) 2082 goto clear_roce; 2083 ret = rc->ops->init_instance(&hdev->roce); 2084 if (ret) 2085 goto clear_roce; 2086 2087 hnae3_set_client_init_flag(hdev->roce_client, ae_dev, 2088 1); 2089 } 2090 break; 2091 case HNAE3_CLIENT_UNIC: 2092 hdev->nic_client = client; 2093 hdev->nic.client = client; 2094 2095 ret = client->ops->init_instance(&hdev->nic); 2096 if (ret) 2097 goto clear_nic; 2098 2099 hnae3_set_client_init_flag(client, ae_dev, 1); 2100 break; 2101 case HNAE3_CLIENT_ROCE: 2102 if (hnae3_dev_roce_supported(hdev)) { 2103 hdev->roce_client = client; 2104 hdev->roce.client = client; 2105 } 2106 2107 if (hdev->roce_client && hdev->nic_client) { 2108 ret = hclgevf_init_roce_base_info(hdev); 2109 if (ret) 2110 goto clear_roce; 2111 2112 ret = client->ops->init_instance(&hdev->roce); 2113 if (ret) 2114 goto clear_roce; 2115 } 2116 2117 hnae3_set_client_init_flag(client, ae_dev, 1); 2118 break; 2119 default: 2120 return -EINVAL; 2121 } 2122 2123 return 0; 2124 2125 clear_nic: 2126 hdev->nic_client = NULL; 2127 hdev->nic.client = NULL; 2128 return ret; 2129 clear_roce: 2130 hdev->roce_client = NULL; 2131 hdev->roce.client = NULL; 2132 return ret; 2133 } 2134 2135 static void hclgevf_uninit_client_instance(struct hnae3_client *client, 2136 struct hnae3_ae_dev *ae_dev) 2137 { 2138 struct hclgevf_dev *hdev = ae_dev->priv; 2139 2140 /* un-init roce, if it exists */ 2141 if (hdev->roce_client) { 2142 hdev->roce_client->ops->uninit_instance(&hdev->roce, 0); 2143 hdev->roce_client = NULL; 2144 hdev->roce.client = NULL; 2145 } 2146 2147 /* un-init nic/unic, if this was not called by roce client */ 2148 if (client->ops->uninit_instance && hdev->nic_client && 2149 client->type != HNAE3_CLIENT_ROCE) { 2150 client->ops->uninit_instance(&hdev->nic, 0); 2151 hdev->nic_client = NULL; 2152 hdev->nic.client = NULL; 2153 } 2154 } 2155 2156 static int hclgevf_pci_init(struct hclgevf_dev *hdev) 2157 { 2158 struct pci_dev *pdev = hdev->pdev; 2159 struct hclgevf_hw *hw; 2160 int ret; 2161 2162 ret = pci_enable_device(pdev); 2163 if (ret) { 2164 dev_err(&pdev->dev, "failed to enable PCI device\n"); 2165 return ret; 2166 } 2167 2168 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 2169 if (ret) { 2170 dev_err(&pdev->dev, "can't set consistent PCI DMA, exiting"); 2171 goto err_disable_device; 2172 } 2173 2174 ret = pci_request_regions(pdev, HCLGEVF_DRIVER_NAME); 2175 if (ret) { 2176 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 2177 goto err_disable_device; 2178 } 2179 2180 pci_set_master(pdev); 2181 hw = &hdev->hw; 2182 hw->hdev = hdev; 2183 hw->io_base = pci_iomap(pdev, 2, 0); 2184 if (!hw->io_base) { 2185 dev_err(&pdev->dev, "can't map configuration register space\n"); 2186 ret = -ENOMEM; 2187 goto err_clr_master; 2188 } 2189 2190 return 0; 2191 2192 err_clr_master: 2193 pci_clear_master(pdev); 2194 pci_release_regions(pdev); 2195 err_disable_device: 2196 pci_disable_device(pdev); 2197 2198 return ret; 2199 } 2200 2201 static void hclgevf_pci_uninit(struct hclgevf_dev *hdev) 2202 { 2203 struct pci_dev *pdev = hdev->pdev; 2204 2205 pci_iounmap(pdev, hdev->hw.io_base); 2206 pci_clear_master(pdev); 2207 pci_release_regions(pdev); 2208 pci_disable_device(pdev); 2209 } 2210 2211 static int hclgevf_query_vf_resource(struct hclgevf_dev *hdev) 2212 { 2213 struct hclgevf_query_res_cmd *req; 2214 struct hclgevf_desc desc; 2215 int ret; 2216 2217 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_VF_RSRC, true); 2218 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 2219 if (ret) { 2220 dev_err(&hdev->pdev->dev, 2221 "query vf resource failed, ret = %d.\n", ret); 2222 return ret; 2223 } 2224 2225 req = (struct hclgevf_query_res_cmd *)desc.data; 2226 2227 if (hnae3_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B)) { 2228 hdev->roce_base_msix_offset = 2229 hnae3_get_field(__le16_to_cpu(req->msixcap_localid_ba_rocee), 2230 HCLGEVF_MSIX_OFT_ROCEE_M, 2231 HCLGEVF_MSIX_OFT_ROCEE_S); 2232 hdev->num_roce_msix = 2233 hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number), 2234 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 2235 2236 /* VF should have NIC vectors and Roce vectors, NIC vectors 2237 * are queued before Roce vectors. The offset is fixed to 64. 2238 */ 2239 hdev->num_msi = hdev->num_roce_msix + 2240 hdev->roce_base_msix_offset; 2241 } else { 2242 hdev->num_msi = 2243 hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number), 2244 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 2245 } 2246 2247 return 0; 2248 } 2249 2250 static int hclgevf_pci_reset(struct hclgevf_dev *hdev) 2251 { 2252 struct pci_dev *pdev = hdev->pdev; 2253 int ret = 0; 2254 2255 if (hdev->reset_type == HNAE3_VF_FULL_RESET && 2256 test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2257 hclgevf_misc_irq_uninit(hdev); 2258 hclgevf_uninit_msi(hdev); 2259 clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2260 } 2261 2262 if (!test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2263 pci_set_master(pdev); 2264 ret = hclgevf_init_msi(hdev); 2265 if (ret) { 2266 dev_err(&pdev->dev, 2267 "failed(%d) to init MSI/MSI-X\n", ret); 2268 return ret; 2269 } 2270 2271 ret = hclgevf_misc_irq_init(hdev); 2272 if (ret) { 2273 hclgevf_uninit_msi(hdev); 2274 dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 2275 ret); 2276 return ret; 2277 } 2278 2279 set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2280 } 2281 2282 return ret; 2283 } 2284 2285 static int hclgevf_reset_hdev(struct hclgevf_dev *hdev) 2286 { 2287 struct pci_dev *pdev = hdev->pdev; 2288 int ret; 2289 2290 ret = hclgevf_pci_reset(hdev); 2291 if (ret) { 2292 dev_err(&pdev->dev, "pci reset failed %d\n", ret); 2293 return ret; 2294 } 2295 2296 ret = hclgevf_cmd_init(hdev); 2297 if (ret) { 2298 dev_err(&pdev->dev, "cmd failed %d\n", ret); 2299 return ret; 2300 } 2301 2302 ret = hclgevf_rss_init_hw(hdev); 2303 if (ret) { 2304 dev_err(&hdev->pdev->dev, 2305 "failed(%d) to initialize RSS\n", ret); 2306 return ret; 2307 } 2308 2309 ret = hclgevf_config_gro(hdev, true); 2310 if (ret) 2311 return ret; 2312 2313 ret = hclgevf_init_vlan_config(hdev); 2314 if (ret) { 2315 dev_err(&hdev->pdev->dev, 2316 "failed(%d) to initialize VLAN config\n", ret); 2317 return ret; 2318 } 2319 2320 dev_info(&hdev->pdev->dev, "Reset done\n"); 2321 2322 return 0; 2323 } 2324 2325 static int hclgevf_init_hdev(struct hclgevf_dev *hdev) 2326 { 2327 struct pci_dev *pdev = hdev->pdev; 2328 int ret; 2329 2330 ret = hclgevf_pci_init(hdev); 2331 if (ret) { 2332 dev_err(&pdev->dev, "PCI initialization failed\n"); 2333 return ret; 2334 } 2335 2336 ret = hclgevf_cmd_queue_init(hdev); 2337 if (ret) { 2338 dev_err(&pdev->dev, "Cmd queue init failed: %d\n", ret); 2339 goto err_cmd_queue_init; 2340 } 2341 2342 ret = hclgevf_cmd_init(hdev); 2343 if (ret) 2344 goto err_cmd_init; 2345 2346 /* Get vf resource */ 2347 ret = hclgevf_query_vf_resource(hdev); 2348 if (ret) { 2349 dev_err(&hdev->pdev->dev, 2350 "Query vf status error, ret = %d.\n", ret); 2351 goto err_cmd_init; 2352 } 2353 2354 ret = hclgevf_init_msi(hdev); 2355 if (ret) { 2356 dev_err(&pdev->dev, "failed(%d) to init MSI/MSI-X\n", ret); 2357 goto err_cmd_init; 2358 } 2359 2360 hclgevf_state_init(hdev); 2361 hdev->reset_level = HNAE3_VF_FUNC_RESET; 2362 2363 ret = hclgevf_misc_irq_init(hdev); 2364 if (ret) { 2365 dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 2366 ret); 2367 goto err_misc_irq_init; 2368 } 2369 2370 set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2371 2372 ret = hclgevf_configure(hdev); 2373 if (ret) { 2374 dev_err(&pdev->dev, "failed(%d) to fetch configuration\n", ret); 2375 goto err_config; 2376 } 2377 2378 ret = hclgevf_alloc_tqps(hdev); 2379 if (ret) { 2380 dev_err(&pdev->dev, "failed(%d) to allocate TQPs\n", ret); 2381 goto err_config; 2382 } 2383 2384 ret = hclgevf_set_handle_info(hdev); 2385 if (ret) { 2386 dev_err(&pdev->dev, "failed(%d) to set handle info\n", ret); 2387 goto err_config; 2388 } 2389 2390 ret = hclgevf_config_gro(hdev, true); 2391 if (ret) 2392 goto err_config; 2393 2394 /* vf is not allowed to enable unicast/multicast promisc mode. 2395 * For revision 0x20, default to disable broadcast promisc mode, 2396 * firmware makes sure broadcast packets can be accepted. 2397 * For revision 0x21, default to enable broadcast promisc mode. 2398 */ 2399 ret = hclgevf_set_promisc_mode(hdev, true); 2400 if (ret) 2401 goto err_config; 2402 2403 /* Initialize RSS for this VF */ 2404 ret = hclgevf_rss_init_hw(hdev); 2405 if (ret) { 2406 dev_err(&hdev->pdev->dev, 2407 "failed(%d) to initialize RSS\n", ret); 2408 goto err_config; 2409 } 2410 2411 ret = hclgevf_init_vlan_config(hdev); 2412 if (ret) { 2413 dev_err(&hdev->pdev->dev, 2414 "failed(%d) to initialize VLAN config\n", ret); 2415 goto err_config; 2416 } 2417 2418 hdev->last_reset_time = jiffies; 2419 pr_info("finished initializing %s driver\n", HCLGEVF_DRIVER_NAME); 2420 2421 return 0; 2422 2423 err_config: 2424 hclgevf_misc_irq_uninit(hdev); 2425 err_misc_irq_init: 2426 hclgevf_state_uninit(hdev); 2427 hclgevf_uninit_msi(hdev); 2428 err_cmd_init: 2429 hclgevf_cmd_uninit(hdev); 2430 err_cmd_queue_init: 2431 hclgevf_pci_uninit(hdev); 2432 clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2433 return ret; 2434 } 2435 2436 static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev) 2437 { 2438 hclgevf_state_uninit(hdev); 2439 2440 if (test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2441 hclgevf_misc_irq_uninit(hdev); 2442 hclgevf_uninit_msi(hdev); 2443 } 2444 2445 hclgevf_pci_uninit(hdev); 2446 hclgevf_cmd_uninit(hdev); 2447 } 2448 2449 static int hclgevf_init_ae_dev(struct hnae3_ae_dev *ae_dev) 2450 { 2451 struct pci_dev *pdev = ae_dev->pdev; 2452 struct hclgevf_dev *hdev; 2453 int ret; 2454 2455 ret = hclgevf_alloc_hdev(ae_dev); 2456 if (ret) { 2457 dev_err(&pdev->dev, "hclge device allocation failed\n"); 2458 return ret; 2459 } 2460 2461 ret = hclgevf_init_hdev(ae_dev->priv); 2462 if (ret) { 2463 dev_err(&pdev->dev, "hclge device initialization failed\n"); 2464 return ret; 2465 } 2466 2467 hdev = ae_dev->priv; 2468 timer_setup(&hdev->keep_alive_timer, hclgevf_keep_alive_timer, 0); 2469 INIT_WORK(&hdev->keep_alive_task, hclgevf_keep_alive_task); 2470 2471 return 0; 2472 } 2473 2474 static void hclgevf_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 2475 { 2476 struct hclgevf_dev *hdev = ae_dev->priv; 2477 2478 hclgevf_uninit_hdev(hdev); 2479 ae_dev->priv = NULL; 2480 } 2481 2482 static u32 hclgevf_get_max_channels(struct hclgevf_dev *hdev) 2483 { 2484 struct hnae3_handle *nic = &hdev->nic; 2485 struct hnae3_knic_private_info *kinfo = &nic->kinfo; 2486 2487 return min_t(u32, hdev->rss_size_max, 2488 hdev->num_tqps / kinfo->num_tc); 2489 } 2490 2491 /** 2492 * hclgevf_get_channels - Get the current channels enabled and max supported. 2493 * @handle: hardware information for network interface 2494 * @ch: ethtool channels structure 2495 * 2496 * We don't support separate tx and rx queues as channels. The other count 2497 * represents how many queues are being used for control. max_combined counts 2498 * how many queue pairs we can support. They may not be mapped 1 to 1 with 2499 * q_vectors since we support a lot more queue pairs than q_vectors. 2500 **/ 2501 static void hclgevf_get_channels(struct hnae3_handle *handle, 2502 struct ethtool_channels *ch) 2503 { 2504 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2505 2506 ch->max_combined = hclgevf_get_max_channels(hdev); 2507 ch->other_count = 0; 2508 ch->max_other = 0; 2509 ch->combined_count = handle->kinfo.rss_size; 2510 } 2511 2512 static void hclgevf_get_tqps_and_rss_info(struct hnae3_handle *handle, 2513 u16 *alloc_tqps, u16 *max_rss_size) 2514 { 2515 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2516 2517 *alloc_tqps = hdev->num_tqps; 2518 *max_rss_size = hdev->rss_size_max; 2519 } 2520 2521 static int hclgevf_get_status(struct hnae3_handle *handle) 2522 { 2523 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2524 2525 return hdev->hw.mac.link; 2526 } 2527 2528 static void hclgevf_get_ksettings_an_result(struct hnae3_handle *handle, 2529 u8 *auto_neg, u32 *speed, 2530 u8 *duplex) 2531 { 2532 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2533 2534 if (speed) 2535 *speed = hdev->hw.mac.speed; 2536 if (duplex) 2537 *duplex = hdev->hw.mac.duplex; 2538 if (auto_neg) 2539 *auto_neg = AUTONEG_DISABLE; 2540 } 2541 2542 void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed, 2543 u8 duplex) 2544 { 2545 hdev->hw.mac.speed = speed; 2546 hdev->hw.mac.duplex = duplex; 2547 } 2548 2549 static int hclgevf_gro_en(struct hnae3_handle *handle, int enable) 2550 { 2551 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2552 2553 return hclgevf_config_gro(hdev, enable); 2554 } 2555 2556 static void hclgevf_get_media_type(struct hnae3_handle *handle, 2557 u8 *media_type) 2558 { 2559 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2560 if (media_type) 2561 *media_type = hdev->hw.mac.media_type; 2562 } 2563 2564 static bool hclgevf_get_hw_reset_stat(struct hnae3_handle *handle) 2565 { 2566 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2567 2568 return !!hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 2569 } 2570 2571 static bool hclgevf_ae_dev_resetting(struct hnae3_handle *handle) 2572 { 2573 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2574 2575 return test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 2576 } 2577 2578 static unsigned long hclgevf_ae_dev_reset_cnt(struct hnae3_handle *handle) 2579 { 2580 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2581 2582 return hdev->reset_count; 2583 } 2584 2585 #define MAX_SEPARATE_NUM 4 2586 #define SEPARATOR_VALUE 0xFFFFFFFF 2587 #define REG_NUM_PER_LINE 4 2588 #define REG_LEN_PER_LINE (REG_NUM_PER_LINE * sizeof(u32)) 2589 2590 static int hclgevf_get_regs_len(struct hnae3_handle *handle) 2591 { 2592 int cmdq_lines, common_lines, ring_lines, tqp_intr_lines; 2593 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2594 2595 cmdq_lines = sizeof(cmdq_reg_addr_list) / REG_LEN_PER_LINE + 1; 2596 common_lines = sizeof(common_reg_addr_list) / REG_LEN_PER_LINE + 1; 2597 ring_lines = sizeof(ring_reg_addr_list) / REG_LEN_PER_LINE + 1; 2598 tqp_intr_lines = sizeof(tqp_intr_reg_addr_list) / REG_LEN_PER_LINE + 1; 2599 2600 return (cmdq_lines + common_lines + ring_lines * hdev->num_tqps + 2601 tqp_intr_lines * (hdev->num_msi_used - 1)) * REG_LEN_PER_LINE; 2602 } 2603 2604 static void hclgevf_get_regs(struct hnae3_handle *handle, u32 *version, 2605 void *data) 2606 { 2607 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2608 int i, j, reg_um, separator_num; 2609 u32 *reg = data; 2610 2611 *version = hdev->fw_version; 2612 2613 /* fetching per-VF registers values from VF PCIe register space */ 2614 reg_um = sizeof(cmdq_reg_addr_list) / sizeof(u32); 2615 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 2616 for (i = 0; i < reg_um; i++) 2617 *reg++ = hclgevf_read_dev(&hdev->hw, cmdq_reg_addr_list[i]); 2618 for (i = 0; i < separator_num; i++) 2619 *reg++ = SEPARATOR_VALUE; 2620 2621 reg_um = sizeof(common_reg_addr_list) / sizeof(u32); 2622 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 2623 for (i = 0; i < reg_um; i++) 2624 *reg++ = hclgevf_read_dev(&hdev->hw, common_reg_addr_list[i]); 2625 for (i = 0; i < separator_num; i++) 2626 *reg++ = SEPARATOR_VALUE; 2627 2628 reg_um = sizeof(ring_reg_addr_list) / sizeof(u32); 2629 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 2630 for (j = 0; j < hdev->num_tqps; j++) { 2631 for (i = 0; i < reg_um; i++) 2632 *reg++ = hclgevf_read_dev(&hdev->hw, 2633 ring_reg_addr_list[i] + 2634 0x200 * j); 2635 for (i = 0; i < separator_num; i++) 2636 *reg++ = SEPARATOR_VALUE; 2637 } 2638 2639 reg_um = sizeof(tqp_intr_reg_addr_list) / sizeof(u32); 2640 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 2641 for (j = 0; j < hdev->num_msi_used - 1; j++) { 2642 for (i = 0; i < reg_um; i++) 2643 *reg++ = hclgevf_read_dev(&hdev->hw, 2644 tqp_intr_reg_addr_list[i] + 2645 4 * j); 2646 for (i = 0; i < separator_num; i++) 2647 *reg++ = SEPARATOR_VALUE; 2648 } 2649 } 2650 2651 static const struct hnae3_ae_ops hclgevf_ops = { 2652 .init_ae_dev = hclgevf_init_ae_dev, 2653 .uninit_ae_dev = hclgevf_uninit_ae_dev, 2654 .flr_prepare = hclgevf_flr_prepare, 2655 .flr_done = hclgevf_flr_done, 2656 .init_client_instance = hclgevf_init_client_instance, 2657 .uninit_client_instance = hclgevf_uninit_client_instance, 2658 .start = hclgevf_ae_start, 2659 .stop = hclgevf_ae_stop, 2660 .client_start = hclgevf_client_start, 2661 .client_stop = hclgevf_client_stop, 2662 .map_ring_to_vector = hclgevf_map_ring_to_vector, 2663 .unmap_ring_from_vector = hclgevf_unmap_ring_from_vector, 2664 .get_vector = hclgevf_get_vector, 2665 .put_vector = hclgevf_put_vector, 2666 .reset_queue = hclgevf_reset_tqp, 2667 .get_mac_addr = hclgevf_get_mac_addr, 2668 .set_mac_addr = hclgevf_set_mac_addr, 2669 .add_uc_addr = hclgevf_add_uc_addr, 2670 .rm_uc_addr = hclgevf_rm_uc_addr, 2671 .add_mc_addr = hclgevf_add_mc_addr, 2672 .rm_mc_addr = hclgevf_rm_mc_addr, 2673 .get_stats = hclgevf_get_stats, 2674 .update_stats = hclgevf_update_stats, 2675 .get_strings = hclgevf_get_strings, 2676 .get_sset_count = hclgevf_get_sset_count, 2677 .get_rss_key_size = hclgevf_get_rss_key_size, 2678 .get_rss_indir_size = hclgevf_get_rss_indir_size, 2679 .get_rss = hclgevf_get_rss, 2680 .set_rss = hclgevf_set_rss, 2681 .get_rss_tuple = hclgevf_get_rss_tuple, 2682 .set_rss_tuple = hclgevf_set_rss_tuple, 2683 .get_tc_size = hclgevf_get_tc_size, 2684 .get_fw_version = hclgevf_get_fw_version, 2685 .set_vlan_filter = hclgevf_set_vlan_filter, 2686 .enable_hw_strip_rxvtag = hclgevf_en_hw_strip_rxvtag, 2687 .reset_event = hclgevf_reset_event, 2688 .set_default_reset_request = hclgevf_set_def_reset_request, 2689 .get_channels = hclgevf_get_channels, 2690 .get_tqps_and_rss_info = hclgevf_get_tqps_and_rss_info, 2691 .get_regs_len = hclgevf_get_regs_len, 2692 .get_regs = hclgevf_get_regs, 2693 .get_status = hclgevf_get_status, 2694 .get_ksettings_an_result = hclgevf_get_ksettings_an_result, 2695 .get_media_type = hclgevf_get_media_type, 2696 .get_hw_reset_stat = hclgevf_get_hw_reset_stat, 2697 .ae_dev_resetting = hclgevf_ae_dev_resetting, 2698 .ae_dev_reset_cnt = hclgevf_ae_dev_reset_cnt, 2699 .set_gro_en = hclgevf_gro_en, 2700 .set_mtu = hclgevf_set_mtu, 2701 .get_global_queue_id = hclgevf_get_qid_global, 2702 .set_timer_task = hclgevf_set_timer_task, 2703 }; 2704 2705 static struct hnae3_ae_algo ae_algovf = { 2706 .ops = &hclgevf_ops, 2707 .pdev_id_table = ae_algovf_pci_tbl, 2708 }; 2709 2710 static int hclgevf_init(void) 2711 { 2712 pr_info("%s is initializing\n", HCLGEVF_NAME); 2713 2714 hnae3_register_ae_algo(&ae_algovf); 2715 2716 return 0; 2717 } 2718 2719 static void hclgevf_exit(void) 2720 { 2721 hnae3_unregister_ae_algo(&ae_algovf); 2722 } 2723 module_init(hclgevf_init); 2724 module_exit(hclgevf_exit); 2725 2726 MODULE_LICENSE("GPL"); 2727 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 2728 MODULE_DESCRIPTION("HCLGEVF Driver"); 2729 MODULE_VERSION(HCLGEVF_MOD_VERSION); 2730