1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/etherdevice.h> 5 #include <linux/iopoll.h> 6 #include <net/rtnetlink.h> 7 #include "hclgevf_cmd.h" 8 #include "hclgevf_main.h" 9 #include "hclge_mbx.h" 10 #include "hnae3.h" 11 12 #define HCLGEVF_NAME "hclgevf" 13 14 #define HCLGEVF_RESET_MAX_FAIL_CNT 5 15 16 static int hclgevf_reset_hdev(struct hclgevf_dev *hdev); 17 static void hclgevf_task_schedule(struct hclgevf_dev *hdev, 18 unsigned long delay); 19 20 static struct hnae3_ae_algo ae_algovf; 21 22 static struct workqueue_struct *hclgevf_wq; 23 24 static const struct pci_device_id ae_algovf_pci_tbl[] = { 25 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_VF), 0}, 26 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF), 27 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 28 /* required last entry */ 29 {0, } 30 }; 31 32 static const u8 hclgevf_hash_key[] = { 33 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2, 34 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0, 35 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4, 36 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C, 37 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA 38 }; 39 40 MODULE_DEVICE_TABLE(pci, ae_algovf_pci_tbl); 41 42 static const u32 cmdq_reg_addr_list[] = {HCLGEVF_CMDQ_TX_ADDR_L_REG, 43 HCLGEVF_CMDQ_TX_ADDR_H_REG, 44 HCLGEVF_CMDQ_TX_DEPTH_REG, 45 HCLGEVF_CMDQ_TX_TAIL_REG, 46 HCLGEVF_CMDQ_TX_HEAD_REG, 47 HCLGEVF_CMDQ_RX_ADDR_L_REG, 48 HCLGEVF_CMDQ_RX_ADDR_H_REG, 49 HCLGEVF_CMDQ_RX_DEPTH_REG, 50 HCLGEVF_CMDQ_RX_TAIL_REG, 51 HCLGEVF_CMDQ_RX_HEAD_REG, 52 HCLGEVF_VECTOR0_CMDQ_SRC_REG, 53 HCLGEVF_VECTOR0_CMDQ_STATE_REG, 54 HCLGEVF_CMDQ_INTR_EN_REG, 55 HCLGEVF_CMDQ_INTR_GEN_REG}; 56 57 static const u32 common_reg_addr_list[] = {HCLGEVF_MISC_VECTOR_REG_BASE, 58 HCLGEVF_RST_ING, 59 HCLGEVF_GRO_EN_REG}; 60 61 static const u32 ring_reg_addr_list[] = {HCLGEVF_RING_RX_ADDR_L_REG, 62 HCLGEVF_RING_RX_ADDR_H_REG, 63 HCLGEVF_RING_RX_BD_NUM_REG, 64 HCLGEVF_RING_RX_BD_LENGTH_REG, 65 HCLGEVF_RING_RX_MERGE_EN_REG, 66 HCLGEVF_RING_RX_TAIL_REG, 67 HCLGEVF_RING_RX_HEAD_REG, 68 HCLGEVF_RING_RX_FBD_NUM_REG, 69 HCLGEVF_RING_RX_OFFSET_REG, 70 HCLGEVF_RING_RX_FBD_OFFSET_REG, 71 HCLGEVF_RING_RX_STASH_REG, 72 HCLGEVF_RING_RX_BD_ERR_REG, 73 HCLGEVF_RING_TX_ADDR_L_REG, 74 HCLGEVF_RING_TX_ADDR_H_REG, 75 HCLGEVF_RING_TX_BD_NUM_REG, 76 HCLGEVF_RING_TX_PRIORITY_REG, 77 HCLGEVF_RING_TX_TC_REG, 78 HCLGEVF_RING_TX_MERGE_EN_REG, 79 HCLGEVF_RING_TX_TAIL_REG, 80 HCLGEVF_RING_TX_HEAD_REG, 81 HCLGEVF_RING_TX_FBD_NUM_REG, 82 HCLGEVF_RING_TX_OFFSET_REG, 83 HCLGEVF_RING_TX_EBD_NUM_REG, 84 HCLGEVF_RING_TX_EBD_OFFSET_REG, 85 HCLGEVF_RING_TX_BD_ERR_REG, 86 HCLGEVF_RING_EN_REG}; 87 88 static const u32 tqp_intr_reg_addr_list[] = {HCLGEVF_TQP_INTR_CTRL_REG, 89 HCLGEVF_TQP_INTR_GL0_REG, 90 HCLGEVF_TQP_INTR_GL1_REG, 91 HCLGEVF_TQP_INTR_GL2_REG, 92 HCLGEVF_TQP_INTR_RL_REG}; 93 94 static struct hclgevf_dev *hclgevf_ae_get_hdev(struct hnae3_handle *handle) 95 { 96 if (!handle->client) 97 return container_of(handle, struct hclgevf_dev, nic); 98 else if (handle->client->type == HNAE3_CLIENT_ROCE) 99 return container_of(handle, struct hclgevf_dev, roce); 100 else 101 return container_of(handle, struct hclgevf_dev, nic); 102 } 103 104 static int hclgevf_tqps_update_stats(struct hnae3_handle *handle) 105 { 106 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 107 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 108 struct hclgevf_desc desc; 109 struct hclgevf_tqp *tqp; 110 int status; 111 int i; 112 113 for (i = 0; i < kinfo->num_tqps; i++) { 114 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 115 hclgevf_cmd_setup_basic_desc(&desc, 116 HCLGEVF_OPC_QUERY_RX_STATUS, 117 true); 118 119 desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 120 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 121 if (status) { 122 dev_err(&hdev->pdev->dev, 123 "Query tqp stat fail, status = %d,queue = %d\n", 124 status, i); 125 return status; 126 } 127 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd += 128 le32_to_cpu(desc.data[1]); 129 130 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_TX_STATUS, 131 true); 132 133 desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 134 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 135 if (status) { 136 dev_err(&hdev->pdev->dev, 137 "Query tqp stat fail, status = %d,queue = %d\n", 138 status, i); 139 return status; 140 } 141 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd += 142 le32_to_cpu(desc.data[1]); 143 } 144 145 return 0; 146 } 147 148 static u64 *hclgevf_tqps_get_stats(struct hnae3_handle *handle, u64 *data) 149 { 150 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 151 struct hclgevf_tqp *tqp; 152 u64 *buff = data; 153 int i; 154 155 for (i = 0; i < kinfo->num_tqps; i++) { 156 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 157 *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd; 158 } 159 for (i = 0; i < kinfo->num_tqps; i++) { 160 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 161 *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd; 162 } 163 164 return buff; 165 } 166 167 static int hclgevf_tqps_get_sset_count(struct hnae3_handle *handle, int strset) 168 { 169 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 170 171 return kinfo->num_tqps * 2; 172 } 173 174 static u8 *hclgevf_tqps_get_strings(struct hnae3_handle *handle, u8 *data) 175 { 176 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 177 u8 *buff = data; 178 int i; 179 180 for (i = 0; i < kinfo->num_tqps; i++) { 181 struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 182 struct hclgevf_tqp, q); 183 snprintf(buff, ETH_GSTRING_LEN, "txq%u_pktnum_rcd", 184 tqp->index); 185 buff += ETH_GSTRING_LEN; 186 } 187 188 for (i = 0; i < kinfo->num_tqps; i++) { 189 struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 190 struct hclgevf_tqp, q); 191 snprintf(buff, ETH_GSTRING_LEN, "rxq%u_pktnum_rcd", 192 tqp->index); 193 buff += ETH_GSTRING_LEN; 194 } 195 196 return buff; 197 } 198 199 static void hclgevf_update_stats(struct hnae3_handle *handle, 200 struct net_device_stats *net_stats) 201 { 202 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 203 int status; 204 205 status = hclgevf_tqps_update_stats(handle); 206 if (status) 207 dev_err(&hdev->pdev->dev, 208 "VF update of TQPS stats fail, status = %d.\n", 209 status); 210 } 211 212 static int hclgevf_get_sset_count(struct hnae3_handle *handle, int strset) 213 { 214 if (strset == ETH_SS_TEST) 215 return -EOPNOTSUPP; 216 else if (strset == ETH_SS_STATS) 217 return hclgevf_tqps_get_sset_count(handle, strset); 218 219 return 0; 220 } 221 222 static void hclgevf_get_strings(struct hnae3_handle *handle, u32 strset, 223 u8 *data) 224 { 225 u8 *p = (char *)data; 226 227 if (strset == ETH_SS_STATS) 228 p = hclgevf_tqps_get_strings(handle, p); 229 } 230 231 static void hclgevf_get_stats(struct hnae3_handle *handle, u64 *data) 232 { 233 hclgevf_tqps_get_stats(handle, data); 234 } 235 236 static void hclgevf_build_send_msg(struct hclge_vf_to_pf_msg *msg, u8 code, 237 u8 subcode) 238 { 239 if (msg) { 240 memset(msg, 0, sizeof(struct hclge_vf_to_pf_msg)); 241 msg->code = code; 242 msg->subcode = subcode; 243 } 244 } 245 246 static int hclgevf_get_tc_info(struct hclgevf_dev *hdev) 247 { 248 struct hclge_vf_to_pf_msg send_msg; 249 u8 resp_msg; 250 int status; 251 252 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_TCINFO, 0); 253 status = hclgevf_send_mbx_msg(hdev, &send_msg, true, &resp_msg, 254 sizeof(resp_msg)); 255 if (status) { 256 dev_err(&hdev->pdev->dev, 257 "VF request to get TC info from PF failed %d", 258 status); 259 return status; 260 } 261 262 hdev->hw_tc_map = resp_msg; 263 264 return 0; 265 } 266 267 static int hclgevf_get_port_base_vlan_filter_state(struct hclgevf_dev *hdev) 268 { 269 struct hnae3_handle *nic = &hdev->nic; 270 struct hclge_vf_to_pf_msg send_msg; 271 u8 resp_msg; 272 int ret; 273 274 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 275 HCLGE_MBX_GET_PORT_BASE_VLAN_STATE); 276 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, &resp_msg, 277 sizeof(u8)); 278 if (ret) { 279 dev_err(&hdev->pdev->dev, 280 "VF request to get port based vlan state failed %d", 281 ret); 282 return ret; 283 } 284 285 nic->port_base_vlan_state = resp_msg; 286 287 return 0; 288 } 289 290 static int hclgevf_get_queue_info(struct hclgevf_dev *hdev) 291 { 292 #define HCLGEVF_TQPS_RSS_INFO_LEN 6 293 #define HCLGEVF_TQPS_ALLOC_OFFSET 0 294 #define HCLGEVF_TQPS_RSS_SIZE_OFFSET 2 295 #define HCLGEVF_TQPS_RX_BUFFER_LEN_OFFSET 4 296 297 u8 resp_msg[HCLGEVF_TQPS_RSS_INFO_LEN]; 298 struct hclge_vf_to_pf_msg send_msg; 299 int status; 300 301 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QINFO, 0); 302 status = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 303 HCLGEVF_TQPS_RSS_INFO_LEN); 304 if (status) { 305 dev_err(&hdev->pdev->dev, 306 "VF request to get tqp info from PF failed %d", 307 status); 308 return status; 309 } 310 311 memcpy(&hdev->num_tqps, &resp_msg[HCLGEVF_TQPS_ALLOC_OFFSET], 312 sizeof(u16)); 313 memcpy(&hdev->rss_size_max, &resp_msg[HCLGEVF_TQPS_RSS_SIZE_OFFSET], 314 sizeof(u16)); 315 memcpy(&hdev->rx_buf_len, &resp_msg[HCLGEVF_TQPS_RX_BUFFER_LEN_OFFSET], 316 sizeof(u16)); 317 318 return 0; 319 } 320 321 static int hclgevf_get_queue_depth(struct hclgevf_dev *hdev) 322 { 323 #define HCLGEVF_TQPS_DEPTH_INFO_LEN 4 324 #define HCLGEVF_TQPS_NUM_TX_DESC_OFFSET 0 325 #define HCLGEVF_TQPS_NUM_RX_DESC_OFFSET 2 326 327 u8 resp_msg[HCLGEVF_TQPS_DEPTH_INFO_LEN]; 328 struct hclge_vf_to_pf_msg send_msg; 329 int ret; 330 331 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QDEPTH, 0); 332 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 333 HCLGEVF_TQPS_DEPTH_INFO_LEN); 334 if (ret) { 335 dev_err(&hdev->pdev->dev, 336 "VF request to get tqp depth info from PF failed %d", 337 ret); 338 return ret; 339 } 340 341 memcpy(&hdev->num_tx_desc, &resp_msg[HCLGEVF_TQPS_NUM_TX_DESC_OFFSET], 342 sizeof(u16)); 343 memcpy(&hdev->num_rx_desc, &resp_msg[HCLGEVF_TQPS_NUM_RX_DESC_OFFSET], 344 sizeof(u16)); 345 346 return 0; 347 } 348 349 static u16 hclgevf_get_qid_global(struct hnae3_handle *handle, u16 queue_id) 350 { 351 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 352 struct hclge_vf_to_pf_msg send_msg; 353 u16 qid_in_pf = 0; 354 u8 resp_data[2]; 355 int ret; 356 357 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QID_IN_PF, 0); 358 memcpy(send_msg.data, &queue_id, sizeof(queue_id)); 359 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_data, 360 sizeof(resp_data)); 361 if (!ret) 362 qid_in_pf = *(u16 *)resp_data; 363 364 return qid_in_pf; 365 } 366 367 static int hclgevf_get_pf_media_type(struct hclgevf_dev *hdev) 368 { 369 struct hclge_vf_to_pf_msg send_msg; 370 u8 resp_msg[2]; 371 int ret; 372 373 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_MEDIA_TYPE, 0); 374 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 375 sizeof(resp_msg)); 376 if (ret) { 377 dev_err(&hdev->pdev->dev, 378 "VF request to get the pf port media type failed %d", 379 ret); 380 return ret; 381 } 382 383 hdev->hw.mac.media_type = resp_msg[0]; 384 hdev->hw.mac.module_type = resp_msg[1]; 385 386 return 0; 387 } 388 389 static int hclgevf_alloc_tqps(struct hclgevf_dev *hdev) 390 { 391 struct hclgevf_tqp *tqp; 392 int i; 393 394 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 395 sizeof(struct hclgevf_tqp), GFP_KERNEL); 396 if (!hdev->htqp) 397 return -ENOMEM; 398 399 tqp = hdev->htqp; 400 401 for (i = 0; i < hdev->num_tqps; i++) { 402 tqp->dev = &hdev->pdev->dev; 403 tqp->index = i; 404 405 tqp->q.ae_algo = &ae_algovf; 406 tqp->q.buf_size = hdev->rx_buf_len; 407 tqp->q.tx_desc_num = hdev->num_tx_desc; 408 tqp->q.rx_desc_num = hdev->num_rx_desc; 409 410 /* need an extended offset to configure queues >= 411 * HCLGEVF_TQP_MAX_SIZE_DEV_V2. 412 */ 413 if (i < HCLGEVF_TQP_MAX_SIZE_DEV_V2) 414 tqp->q.io_base = hdev->hw.io_base + 415 HCLGEVF_TQP_REG_OFFSET + 416 i * HCLGEVF_TQP_REG_SIZE; 417 else 418 tqp->q.io_base = hdev->hw.io_base + 419 HCLGEVF_TQP_REG_OFFSET + 420 HCLGEVF_TQP_EXT_REG_OFFSET + 421 (i - HCLGEVF_TQP_MAX_SIZE_DEV_V2) * 422 HCLGEVF_TQP_REG_SIZE; 423 424 tqp++; 425 } 426 427 return 0; 428 } 429 430 static int hclgevf_knic_setup(struct hclgevf_dev *hdev) 431 { 432 struct hnae3_handle *nic = &hdev->nic; 433 struct hnae3_knic_private_info *kinfo; 434 u16 new_tqps = hdev->num_tqps; 435 unsigned int i; 436 u8 num_tc = 0; 437 438 kinfo = &nic->kinfo; 439 kinfo->num_tx_desc = hdev->num_tx_desc; 440 kinfo->num_rx_desc = hdev->num_rx_desc; 441 kinfo->rx_buf_len = hdev->rx_buf_len; 442 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) 443 if (hdev->hw_tc_map & BIT(i)) 444 num_tc++; 445 446 num_tc = num_tc ? num_tc : 1; 447 kinfo->tc_info.num_tc = num_tc; 448 kinfo->rss_size = min_t(u16, hdev->rss_size_max, new_tqps / num_tc); 449 new_tqps = kinfo->rss_size * num_tc; 450 kinfo->num_tqps = min(new_tqps, hdev->num_tqps); 451 452 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps, 453 sizeof(struct hnae3_queue *), GFP_KERNEL); 454 if (!kinfo->tqp) 455 return -ENOMEM; 456 457 for (i = 0; i < kinfo->num_tqps; i++) { 458 hdev->htqp[i].q.handle = &hdev->nic; 459 hdev->htqp[i].q.tqp_index = i; 460 kinfo->tqp[i] = &hdev->htqp[i].q; 461 } 462 463 /* after init the max rss_size and tqps, adjust the default tqp numbers 464 * and rss size with the actual vector numbers 465 */ 466 kinfo->num_tqps = min_t(u16, hdev->num_nic_msix - 1, kinfo->num_tqps); 467 kinfo->rss_size = min_t(u16, kinfo->num_tqps / num_tc, 468 kinfo->rss_size); 469 470 return 0; 471 } 472 473 static void hclgevf_request_link_info(struct hclgevf_dev *hdev) 474 { 475 struct hclge_vf_to_pf_msg send_msg; 476 int status; 477 478 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_LINK_STATUS, 0); 479 status = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 480 if (status) 481 dev_err(&hdev->pdev->dev, 482 "VF failed to fetch link status(%d) from PF", status); 483 } 484 485 void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state) 486 { 487 struct hnae3_handle *rhandle = &hdev->roce; 488 struct hnae3_handle *handle = &hdev->nic; 489 struct hnae3_client *rclient; 490 struct hnae3_client *client; 491 492 if (test_and_set_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state)) 493 return; 494 495 client = handle->client; 496 rclient = hdev->roce_client; 497 498 link_state = 499 test_bit(HCLGEVF_STATE_DOWN, &hdev->state) ? 0 : link_state; 500 501 if (link_state != hdev->hw.mac.link) { 502 client->ops->link_status_change(handle, !!link_state); 503 if (rclient && rclient->ops->link_status_change) 504 rclient->ops->link_status_change(rhandle, !!link_state); 505 hdev->hw.mac.link = link_state; 506 } 507 508 clear_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state); 509 } 510 511 static void hclgevf_update_link_mode(struct hclgevf_dev *hdev) 512 { 513 #define HCLGEVF_ADVERTISING 0 514 #define HCLGEVF_SUPPORTED 1 515 516 struct hclge_vf_to_pf_msg send_msg; 517 518 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_LINK_MODE, 0); 519 send_msg.data[0] = HCLGEVF_ADVERTISING; 520 hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 521 send_msg.data[0] = HCLGEVF_SUPPORTED; 522 hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 523 } 524 525 static int hclgevf_set_handle_info(struct hclgevf_dev *hdev) 526 { 527 struct hnae3_handle *nic = &hdev->nic; 528 int ret; 529 530 nic->ae_algo = &ae_algovf; 531 nic->pdev = hdev->pdev; 532 nic->numa_node_mask = hdev->numa_node_mask; 533 nic->flags |= HNAE3_SUPPORT_VF; 534 535 ret = hclgevf_knic_setup(hdev); 536 if (ret) 537 dev_err(&hdev->pdev->dev, "VF knic setup failed %d\n", 538 ret); 539 return ret; 540 } 541 542 static void hclgevf_free_vector(struct hclgevf_dev *hdev, int vector_id) 543 { 544 if (hdev->vector_status[vector_id] == HCLGEVF_INVALID_VPORT) { 545 dev_warn(&hdev->pdev->dev, 546 "vector(vector_id %d) has been freed.\n", vector_id); 547 return; 548 } 549 550 hdev->vector_status[vector_id] = HCLGEVF_INVALID_VPORT; 551 hdev->num_msi_left += 1; 552 hdev->num_msi_used -= 1; 553 } 554 555 static int hclgevf_get_vector(struct hnae3_handle *handle, u16 vector_num, 556 struct hnae3_vector_info *vector_info) 557 { 558 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 559 struct hnae3_vector_info *vector = vector_info; 560 int alloc = 0; 561 int i, j; 562 563 vector_num = min_t(u16, hdev->num_nic_msix - 1, vector_num); 564 vector_num = min(hdev->num_msi_left, vector_num); 565 566 for (j = 0; j < vector_num; j++) { 567 for (i = HCLGEVF_MISC_VECTOR_NUM + 1; i < hdev->num_msi; i++) { 568 if (hdev->vector_status[i] == HCLGEVF_INVALID_VPORT) { 569 vector->vector = pci_irq_vector(hdev->pdev, i); 570 vector->io_addr = hdev->hw.io_base + 571 HCLGEVF_VECTOR_REG_BASE + 572 (i - 1) * HCLGEVF_VECTOR_REG_OFFSET; 573 hdev->vector_status[i] = 0; 574 hdev->vector_irq[i] = vector->vector; 575 576 vector++; 577 alloc++; 578 579 break; 580 } 581 } 582 } 583 hdev->num_msi_left -= alloc; 584 hdev->num_msi_used += alloc; 585 586 return alloc; 587 } 588 589 static int hclgevf_get_vector_index(struct hclgevf_dev *hdev, int vector) 590 { 591 int i; 592 593 for (i = 0; i < hdev->num_msi; i++) 594 if (vector == hdev->vector_irq[i]) 595 return i; 596 597 return -EINVAL; 598 } 599 600 static int hclgevf_set_rss_algo_key(struct hclgevf_dev *hdev, 601 const u8 hfunc, const u8 *key) 602 { 603 struct hclgevf_rss_config_cmd *req; 604 unsigned int key_offset = 0; 605 struct hclgevf_desc desc; 606 int key_counts; 607 int key_size; 608 int ret; 609 610 key_counts = HCLGEVF_RSS_KEY_SIZE; 611 req = (struct hclgevf_rss_config_cmd *)desc.data; 612 613 while (key_counts) { 614 hclgevf_cmd_setup_basic_desc(&desc, 615 HCLGEVF_OPC_RSS_GENERIC_CONFIG, 616 false); 617 618 req->hash_config |= (hfunc & HCLGEVF_RSS_HASH_ALGO_MASK); 619 req->hash_config |= 620 (key_offset << HCLGEVF_RSS_HASH_KEY_OFFSET_B); 621 622 key_size = min(HCLGEVF_RSS_HASH_KEY_NUM, key_counts); 623 memcpy(req->hash_key, 624 key + key_offset * HCLGEVF_RSS_HASH_KEY_NUM, key_size); 625 626 key_counts -= key_size; 627 key_offset++; 628 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 629 if (ret) { 630 dev_err(&hdev->pdev->dev, 631 "Configure RSS config fail, status = %d\n", 632 ret); 633 return ret; 634 } 635 } 636 637 return 0; 638 } 639 640 static u32 hclgevf_get_rss_key_size(struct hnae3_handle *handle) 641 { 642 return HCLGEVF_RSS_KEY_SIZE; 643 } 644 645 static int hclgevf_set_rss_indir_table(struct hclgevf_dev *hdev) 646 { 647 const u8 *indir = hdev->rss_cfg.rss_indirection_tbl; 648 struct hclgevf_rss_indirection_table_cmd *req; 649 struct hclgevf_desc desc; 650 int rss_cfg_tbl_num; 651 int status; 652 int i, j; 653 654 req = (struct hclgevf_rss_indirection_table_cmd *)desc.data; 655 rss_cfg_tbl_num = hdev->ae_dev->dev_specs.rss_ind_tbl_size / 656 HCLGEVF_RSS_CFG_TBL_SIZE; 657 658 for (i = 0; i < rss_cfg_tbl_num; i++) { 659 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INDIR_TABLE, 660 false); 661 req->start_table_index = 662 cpu_to_le16(i * HCLGEVF_RSS_CFG_TBL_SIZE); 663 req->rss_set_bitmap = cpu_to_le16(HCLGEVF_RSS_SET_BITMAP_MSK); 664 for (j = 0; j < HCLGEVF_RSS_CFG_TBL_SIZE; j++) 665 req->rss_result[j] = 666 indir[i * HCLGEVF_RSS_CFG_TBL_SIZE + j]; 667 668 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 669 if (status) { 670 dev_err(&hdev->pdev->dev, 671 "VF failed(=%d) to set RSS indirection table\n", 672 status); 673 return status; 674 } 675 } 676 677 return 0; 678 } 679 680 static int hclgevf_set_rss_tc_mode(struct hclgevf_dev *hdev, u16 rss_size) 681 { 682 struct hclgevf_rss_tc_mode_cmd *req; 683 u16 tc_offset[HCLGEVF_MAX_TC_NUM]; 684 u16 tc_valid[HCLGEVF_MAX_TC_NUM]; 685 u16 tc_size[HCLGEVF_MAX_TC_NUM]; 686 struct hclgevf_desc desc; 687 u16 roundup_size; 688 unsigned int i; 689 int status; 690 691 req = (struct hclgevf_rss_tc_mode_cmd *)desc.data; 692 693 roundup_size = roundup_pow_of_two(rss_size); 694 roundup_size = ilog2(roundup_size); 695 696 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 697 tc_valid[i] = !!(hdev->hw_tc_map & BIT(i)); 698 tc_size[i] = roundup_size; 699 tc_offset[i] = rss_size * i; 700 } 701 702 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_TC_MODE, false); 703 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 704 u16 mode = 0; 705 706 hnae3_set_bit(mode, HCLGEVF_RSS_TC_VALID_B, 707 (tc_valid[i] & 0x1)); 708 hnae3_set_field(mode, HCLGEVF_RSS_TC_SIZE_M, 709 HCLGEVF_RSS_TC_SIZE_S, tc_size[i]); 710 hnae3_set_field(mode, HCLGEVF_RSS_TC_OFFSET_M, 711 HCLGEVF_RSS_TC_OFFSET_S, tc_offset[i]); 712 713 req->rss_tc_mode[i] = cpu_to_le16(mode); 714 } 715 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 716 if (status) 717 dev_err(&hdev->pdev->dev, 718 "VF failed(=%d) to set rss tc mode\n", status); 719 720 return status; 721 } 722 723 /* for revision 0x20, vf shared the same rss config with pf */ 724 static int hclgevf_get_rss_hash_key(struct hclgevf_dev *hdev) 725 { 726 #define HCLGEVF_RSS_MBX_RESP_LEN 8 727 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 728 u8 resp_msg[HCLGEVF_RSS_MBX_RESP_LEN]; 729 struct hclge_vf_to_pf_msg send_msg; 730 u16 msg_num, hash_key_index; 731 u8 index; 732 int ret; 733 734 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_RSS_KEY, 0); 735 msg_num = (HCLGEVF_RSS_KEY_SIZE + HCLGEVF_RSS_MBX_RESP_LEN - 1) / 736 HCLGEVF_RSS_MBX_RESP_LEN; 737 for (index = 0; index < msg_num; index++) { 738 send_msg.data[0] = index; 739 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 740 HCLGEVF_RSS_MBX_RESP_LEN); 741 if (ret) { 742 dev_err(&hdev->pdev->dev, 743 "VF get rss hash key from PF failed, ret=%d", 744 ret); 745 return ret; 746 } 747 748 hash_key_index = HCLGEVF_RSS_MBX_RESP_LEN * index; 749 if (index == msg_num - 1) 750 memcpy(&rss_cfg->rss_hash_key[hash_key_index], 751 &resp_msg[0], 752 HCLGEVF_RSS_KEY_SIZE - hash_key_index); 753 else 754 memcpy(&rss_cfg->rss_hash_key[hash_key_index], 755 &resp_msg[0], HCLGEVF_RSS_MBX_RESP_LEN); 756 } 757 758 return 0; 759 } 760 761 static int hclgevf_get_rss(struct hnae3_handle *handle, u32 *indir, u8 *key, 762 u8 *hfunc) 763 { 764 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 765 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 766 int i, ret; 767 768 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 769 /* Get hash algorithm */ 770 if (hfunc) { 771 switch (rss_cfg->hash_algo) { 772 case HCLGEVF_RSS_HASH_ALGO_TOEPLITZ: 773 *hfunc = ETH_RSS_HASH_TOP; 774 break; 775 case HCLGEVF_RSS_HASH_ALGO_SIMPLE: 776 *hfunc = ETH_RSS_HASH_XOR; 777 break; 778 default: 779 *hfunc = ETH_RSS_HASH_UNKNOWN; 780 break; 781 } 782 } 783 784 /* Get the RSS Key required by the user */ 785 if (key) 786 memcpy(key, rss_cfg->rss_hash_key, 787 HCLGEVF_RSS_KEY_SIZE); 788 } else { 789 if (hfunc) 790 *hfunc = ETH_RSS_HASH_TOP; 791 if (key) { 792 ret = hclgevf_get_rss_hash_key(hdev); 793 if (ret) 794 return ret; 795 memcpy(key, rss_cfg->rss_hash_key, 796 HCLGEVF_RSS_KEY_SIZE); 797 } 798 } 799 800 if (indir) 801 for (i = 0; i < hdev->ae_dev->dev_specs.rss_ind_tbl_size; i++) 802 indir[i] = rss_cfg->rss_indirection_tbl[i]; 803 804 return 0; 805 } 806 807 static int hclgevf_set_rss(struct hnae3_handle *handle, const u32 *indir, 808 const u8 *key, const u8 hfunc) 809 { 810 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 811 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 812 int ret, i; 813 814 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 815 /* Set the RSS Hash Key if specififed by the user */ 816 if (key) { 817 switch (hfunc) { 818 case ETH_RSS_HASH_TOP: 819 rss_cfg->hash_algo = 820 HCLGEVF_RSS_HASH_ALGO_TOEPLITZ; 821 break; 822 case ETH_RSS_HASH_XOR: 823 rss_cfg->hash_algo = 824 HCLGEVF_RSS_HASH_ALGO_SIMPLE; 825 break; 826 case ETH_RSS_HASH_NO_CHANGE: 827 break; 828 default: 829 return -EINVAL; 830 } 831 832 ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 833 key); 834 if (ret) 835 return ret; 836 837 /* Update the shadow RSS key with user specified qids */ 838 memcpy(rss_cfg->rss_hash_key, key, 839 HCLGEVF_RSS_KEY_SIZE); 840 } 841 } 842 843 /* update the shadow RSS table with user specified qids */ 844 for (i = 0; i < hdev->ae_dev->dev_specs.rss_ind_tbl_size; i++) 845 rss_cfg->rss_indirection_tbl[i] = indir[i]; 846 847 /* update the hardware */ 848 return hclgevf_set_rss_indir_table(hdev); 849 } 850 851 static u8 hclgevf_get_rss_hash_bits(struct ethtool_rxnfc *nfc) 852 { 853 u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGEVF_S_PORT_BIT : 0; 854 855 if (nfc->data & RXH_L4_B_2_3) 856 hash_sets |= HCLGEVF_D_PORT_BIT; 857 else 858 hash_sets &= ~HCLGEVF_D_PORT_BIT; 859 860 if (nfc->data & RXH_IP_SRC) 861 hash_sets |= HCLGEVF_S_IP_BIT; 862 else 863 hash_sets &= ~HCLGEVF_S_IP_BIT; 864 865 if (nfc->data & RXH_IP_DST) 866 hash_sets |= HCLGEVF_D_IP_BIT; 867 else 868 hash_sets &= ~HCLGEVF_D_IP_BIT; 869 870 if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW) 871 hash_sets |= HCLGEVF_V_TAG_BIT; 872 873 return hash_sets; 874 } 875 876 static int hclgevf_init_rss_tuple_cmd(struct hnae3_handle *handle, 877 struct ethtool_rxnfc *nfc, 878 struct hclgevf_rss_input_tuple_cmd *req) 879 { 880 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 881 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 882 u8 tuple_sets; 883 884 req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 885 req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 886 req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 887 req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 888 req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 889 req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 890 req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 891 req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 892 893 tuple_sets = hclgevf_get_rss_hash_bits(nfc); 894 switch (nfc->flow_type) { 895 case TCP_V4_FLOW: 896 req->ipv4_tcp_en = tuple_sets; 897 break; 898 case TCP_V6_FLOW: 899 req->ipv6_tcp_en = tuple_sets; 900 break; 901 case UDP_V4_FLOW: 902 req->ipv4_udp_en = tuple_sets; 903 break; 904 case UDP_V6_FLOW: 905 req->ipv6_udp_en = tuple_sets; 906 break; 907 case SCTP_V4_FLOW: 908 req->ipv4_sctp_en = tuple_sets; 909 break; 910 case SCTP_V6_FLOW: 911 if (hdev->ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2 && 912 (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3))) 913 return -EINVAL; 914 915 req->ipv6_sctp_en = tuple_sets; 916 break; 917 case IPV4_FLOW: 918 req->ipv4_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 919 break; 920 case IPV6_FLOW: 921 req->ipv6_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 922 break; 923 default: 924 return -EINVAL; 925 } 926 927 return 0; 928 } 929 930 static int hclgevf_set_rss_tuple(struct hnae3_handle *handle, 931 struct ethtool_rxnfc *nfc) 932 { 933 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 934 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 935 struct hclgevf_rss_input_tuple_cmd *req; 936 struct hclgevf_desc desc; 937 int ret; 938 939 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 940 return -EOPNOTSUPP; 941 942 if (nfc->data & 943 ~(RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3)) 944 return -EINVAL; 945 946 req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 947 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 948 949 ret = hclgevf_init_rss_tuple_cmd(handle, nfc, req); 950 if (ret) { 951 dev_err(&hdev->pdev->dev, 952 "failed to init rss tuple cmd, ret = %d\n", ret); 953 return ret; 954 } 955 956 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 957 if (ret) { 958 dev_err(&hdev->pdev->dev, 959 "Set rss tuple fail, status = %d\n", ret); 960 return ret; 961 } 962 963 rss_cfg->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en; 964 rss_cfg->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en; 965 rss_cfg->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en; 966 rss_cfg->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en; 967 rss_cfg->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en; 968 rss_cfg->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en; 969 rss_cfg->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en; 970 rss_cfg->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en; 971 return 0; 972 } 973 974 static int hclgevf_get_rss_tuple_by_flow_type(struct hclgevf_dev *hdev, 975 int flow_type, u8 *tuple_sets) 976 { 977 switch (flow_type) { 978 case TCP_V4_FLOW: 979 *tuple_sets = hdev->rss_cfg.rss_tuple_sets.ipv4_tcp_en; 980 break; 981 case UDP_V4_FLOW: 982 *tuple_sets = hdev->rss_cfg.rss_tuple_sets.ipv4_udp_en; 983 break; 984 case TCP_V6_FLOW: 985 *tuple_sets = hdev->rss_cfg.rss_tuple_sets.ipv6_tcp_en; 986 break; 987 case UDP_V6_FLOW: 988 *tuple_sets = hdev->rss_cfg.rss_tuple_sets.ipv6_udp_en; 989 break; 990 case SCTP_V4_FLOW: 991 *tuple_sets = hdev->rss_cfg.rss_tuple_sets.ipv4_sctp_en; 992 break; 993 case SCTP_V6_FLOW: 994 *tuple_sets = hdev->rss_cfg.rss_tuple_sets.ipv6_sctp_en; 995 break; 996 case IPV4_FLOW: 997 case IPV6_FLOW: 998 *tuple_sets = HCLGEVF_S_IP_BIT | HCLGEVF_D_IP_BIT; 999 break; 1000 default: 1001 return -EINVAL; 1002 } 1003 1004 return 0; 1005 } 1006 1007 static u64 hclgevf_convert_rss_tuple(u8 tuple_sets) 1008 { 1009 u64 tuple_data = 0; 1010 1011 if (tuple_sets & HCLGEVF_D_PORT_BIT) 1012 tuple_data |= RXH_L4_B_2_3; 1013 if (tuple_sets & HCLGEVF_S_PORT_BIT) 1014 tuple_data |= RXH_L4_B_0_1; 1015 if (tuple_sets & HCLGEVF_D_IP_BIT) 1016 tuple_data |= RXH_IP_DST; 1017 if (tuple_sets & HCLGEVF_S_IP_BIT) 1018 tuple_data |= RXH_IP_SRC; 1019 1020 return tuple_data; 1021 } 1022 1023 static int hclgevf_get_rss_tuple(struct hnae3_handle *handle, 1024 struct ethtool_rxnfc *nfc) 1025 { 1026 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1027 u8 tuple_sets; 1028 int ret; 1029 1030 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 1031 return -EOPNOTSUPP; 1032 1033 nfc->data = 0; 1034 1035 ret = hclgevf_get_rss_tuple_by_flow_type(hdev, nfc->flow_type, 1036 &tuple_sets); 1037 if (ret || !tuple_sets) 1038 return ret; 1039 1040 nfc->data = hclgevf_convert_rss_tuple(tuple_sets); 1041 1042 return 0; 1043 } 1044 1045 static int hclgevf_set_rss_input_tuple(struct hclgevf_dev *hdev, 1046 struct hclgevf_rss_cfg *rss_cfg) 1047 { 1048 struct hclgevf_rss_input_tuple_cmd *req; 1049 struct hclgevf_desc desc; 1050 int ret; 1051 1052 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 1053 1054 req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 1055 1056 req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 1057 req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 1058 req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 1059 req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 1060 req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 1061 req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 1062 req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 1063 req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 1064 1065 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1066 if (ret) 1067 dev_err(&hdev->pdev->dev, 1068 "Configure rss input fail, status = %d\n", ret); 1069 return ret; 1070 } 1071 1072 static int hclgevf_get_tc_size(struct hnae3_handle *handle) 1073 { 1074 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1075 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 1076 1077 return rss_cfg->rss_size; 1078 } 1079 1080 static int hclgevf_bind_ring_to_vector(struct hnae3_handle *handle, bool en, 1081 int vector_id, 1082 struct hnae3_ring_chain_node *ring_chain) 1083 { 1084 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1085 struct hclge_vf_to_pf_msg send_msg; 1086 struct hnae3_ring_chain_node *node; 1087 int status; 1088 int i = 0; 1089 1090 memset(&send_msg, 0, sizeof(send_msg)); 1091 send_msg.code = en ? HCLGE_MBX_MAP_RING_TO_VECTOR : 1092 HCLGE_MBX_UNMAP_RING_TO_VECTOR; 1093 send_msg.vector_id = vector_id; 1094 1095 for (node = ring_chain; node; node = node->next) { 1096 send_msg.param[i].ring_type = 1097 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B); 1098 1099 send_msg.param[i].tqp_index = node->tqp_index; 1100 send_msg.param[i].int_gl_index = 1101 hnae3_get_field(node->int_gl_idx, 1102 HNAE3_RING_GL_IDX_M, 1103 HNAE3_RING_GL_IDX_S); 1104 1105 i++; 1106 if (i == HCLGE_MBX_MAX_RING_CHAIN_PARAM_NUM || !node->next) { 1107 send_msg.ring_num = i; 1108 1109 status = hclgevf_send_mbx_msg(hdev, &send_msg, false, 1110 NULL, 0); 1111 if (status) { 1112 dev_err(&hdev->pdev->dev, 1113 "Map TQP fail, status is %d.\n", 1114 status); 1115 return status; 1116 } 1117 i = 0; 1118 } 1119 } 1120 1121 return 0; 1122 } 1123 1124 static int hclgevf_map_ring_to_vector(struct hnae3_handle *handle, int vector, 1125 struct hnae3_ring_chain_node *ring_chain) 1126 { 1127 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1128 int vector_id; 1129 1130 vector_id = hclgevf_get_vector_index(hdev, vector); 1131 if (vector_id < 0) { 1132 dev_err(&handle->pdev->dev, 1133 "Get vector index fail. ret =%d\n", vector_id); 1134 return vector_id; 1135 } 1136 1137 return hclgevf_bind_ring_to_vector(handle, true, vector_id, ring_chain); 1138 } 1139 1140 static int hclgevf_unmap_ring_from_vector( 1141 struct hnae3_handle *handle, 1142 int vector, 1143 struct hnae3_ring_chain_node *ring_chain) 1144 { 1145 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1146 int ret, vector_id; 1147 1148 if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 1149 return 0; 1150 1151 vector_id = hclgevf_get_vector_index(hdev, vector); 1152 if (vector_id < 0) { 1153 dev_err(&handle->pdev->dev, 1154 "Get vector index fail. ret =%d\n", vector_id); 1155 return vector_id; 1156 } 1157 1158 ret = hclgevf_bind_ring_to_vector(handle, false, vector_id, ring_chain); 1159 if (ret) 1160 dev_err(&handle->pdev->dev, 1161 "Unmap ring from vector fail. vector=%d, ret =%d\n", 1162 vector_id, 1163 ret); 1164 1165 return ret; 1166 } 1167 1168 static int hclgevf_put_vector(struct hnae3_handle *handle, int vector) 1169 { 1170 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1171 int vector_id; 1172 1173 vector_id = hclgevf_get_vector_index(hdev, vector); 1174 if (vector_id < 0) { 1175 dev_err(&handle->pdev->dev, 1176 "hclgevf_put_vector get vector index fail. ret =%d\n", 1177 vector_id); 1178 return vector_id; 1179 } 1180 1181 hclgevf_free_vector(hdev, vector_id); 1182 1183 return 0; 1184 } 1185 1186 static int hclgevf_cmd_set_promisc_mode(struct hclgevf_dev *hdev, 1187 bool en_uc_pmc, bool en_mc_pmc, 1188 bool en_bc_pmc) 1189 { 1190 struct hnae3_handle *handle = &hdev->nic; 1191 struct hclge_vf_to_pf_msg send_msg; 1192 int ret; 1193 1194 memset(&send_msg, 0, sizeof(send_msg)); 1195 send_msg.code = HCLGE_MBX_SET_PROMISC_MODE; 1196 send_msg.en_bc = en_bc_pmc ? 1 : 0; 1197 send_msg.en_uc = en_uc_pmc ? 1 : 0; 1198 send_msg.en_mc = en_mc_pmc ? 1 : 0; 1199 send_msg.en_limit_promisc = test_bit(HNAE3_PFLAG_LIMIT_PROMISC, 1200 &handle->priv_flags) ? 1 : 0; 1201 1202 ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 1203 if (ret) 1204 dev_err(&hdev->pdev->dev, 1205 "Set promisc mode fail, status is %d.\n", ret); 1206 1207 return ret; 1208 } 1209 1210 static int hclgevf_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc, 1211 bool en_mc_pmc) 1212 { 1213 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1214 bool en_bc_pmc; 1215 1216 en_bc_pmc = hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2; 1217 1218 return hclgevf_cmd_set_promisc_mode(hdev, en_uc_pmc, en_mc_pmc, 1219 en_bc_pmc); 1220 } 1221 1222 static void hclgevf_request_update_promisc_mode(struct hnae3_handle *handle) 1223 { 1224 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1225 1226 set_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state); 1227 hclgevf_task_schedule(hdev, 0); 1228 } 1229 1230 static void hclgevf_sync_promisc_mode(struct hclgevf_dev *hdev) 1231 { 1232 struct hnae3_handle *handle = &hdev->nic; 1233 bool en_uc_pmc = handle->netdev_flags & HNAE3_UPE; 1234 bool en_mc_pmc = handle->netdev_flags & HNAE3_MPE; 1235 int ret; 1236 1237 if (test_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state)) { 1238 ret = hclgevf_set_promisc_mode(handle, en_uc_pmc, en_mc_pmc); 1239 if (!ret) 1240 clear_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state); 1241 } 1242 } 1243 1244 static int hclgevf_tqp_enable(struct hclgevf_dev *hdev, unsigned int tqp_id, 1245 int stream_id, bool enable) 1246 { 1247 struct hclgevf_cfg_com_tqp_queue_cmd *req; 1248 struct hclgevf_desc desc; 1249 int status; 1250 1251 req = (struct hclgevf_cfg_com_tqp_queue_cmd *)desc.data; 1252 1253 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_CFG_COM_TQP_QUEUE, 1254 false); 1255 req->tqp_id = cpu_to_le16(tqp_id & HCLGEVF_RING_ID_MASK); 1256 req->stream_id = cpu_to_le16(stream_id); 1257 if (enable) 1258 req->enable |= 1U << HCLGEVF_TQP_ENABLE_B; 1259 1260 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1261 if (status) 1262 dev_err(&hdev->pdev->dev, 1263 "TQP enable fail, status =%d.\n", status); 1264 1265 return status; 1266 } 1267 1268 static void hclgevf_reset_tqp_stats(struct hnae3_handle *handle) 1269 { 1270 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 1271 struct hclgevf_tqp *tqp; 1272 int i; 1273 1274 for (i = 0; i < kinfo->num_tqps; i++) { 1275 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 1276 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats)); 1277 } 1278 } 1279 1280 static int hclgevf_get_host_mac_addr(struct hclgevf_dev *hdev, u8 *p) 1281 { 1282 struct hclge_vf_to_pf_msg send_msg; 1283 u8 host_mac[ETH_ALEN]; 1284 int status; 1285 1286 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_MAC_ADDR, 0); 1287 status = hclgevf_send_mbx_msg(hdev, &send_msg, true, host_mac, 1288 ETH_ALEN); 1289 if (status) { 1290 dev_err(&hdev->pdev->dev, 1291 "fail to get VF MAC from host %d", status); 1292 return status; 1293 } 1294 1295 ether_addr_copy(p, host_mac); 1296 1297 return 0; 1298 } 1299 1300 static void hclgevf_get_mac_addr(struct hnae3_handle *handle, u8 *p) 1301 { 1302 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1303 u8 host_mac_addr[ETH_ALEN]; 1304 1305 if (hclgevf_get_host_mac_addr(hdev, host_mac_addr)) 1306 return; 1307 1308 hdev->has_pf_mac = !is_zero_ether_addr(host_mac_addr); 1309 if (hdev->has_pf_mac) 1310 ether_addr_copy(p, host_mac_addr); 1311 else 1312 ether_addr_copy(p, hdev->hw.mac.mac_addr); 1313 } 1314 1315 static int hclgevf_set_mac_addr(struct hnae3_handle *handle, void *p, 1316 bool is_first) 1317 { 1318 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1319 u8 *old_mac_addr = (u8 *)hdev->hw.mac.mac_addr; 1320 struct hclge_vf_to_pf_msg send_msg; 1321 u8 *new_mac_addr = (u8 *)p; 1322 int status; 1323 1324 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_UNICAST, 0); 1325 send_msg.subcode = HCLGE_MBX_MAC_VLAN_UC_MODIFY; 1326 ether_addr_copy(send_msg.data, new_mac_addr); 1327 if (is_first && !hdev->has_pf_mac) 1328 eth_zero_addr(&send_msg.data[ETH_ALEN]); 1329 else 1330 ether_addr_copy(&send_msg.data[ETH_ALEN], old_mac_addr); 1331 status = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1332 if (!status) 1333 ether_addr_copy(hdev->hw.mac.mac_addr, new_mac_addr); 1334 1335 return status; 1336 } 1337 1338 static struct hclgevf_mac_addr_node * 1339 hclgevf_find_mac_node(struct list_head *list, const u8 *mac_addr) 1340 { 1341 struct hclgevf_mac_addr_node *mac_node, *tmp; 1342 1343 list_for_each_entry_safe(mac_node, tmp, list, node) 1344 if (ether_addr_equal(mac_addr, mac_node->mac_addr)) 1345 return mac_node; 1346 1347 return NULL; 1348 } 1349 1350 static void hclgevf_update_mac_node(struct hclgevf_mac_addr_node *mac_node, 1351 enum HCLGEVF_MAC_NODE_STATE state) 1352 { 1353 switch (state) { 1354 /* from set_rx_mode or tmp_add_list */ 1355 case HCLGEVF_MAC_TO_ADD: 1356 if (mac_node->state == HCLGEVF_MAC_TO_DEL) 1357 mac_node->state = HCLGEVF_MAC_ACTIVE; 1358 break; 1359 /* only from set_rx_mode */ 1360 case HCLGEVF_MAC_TO_DEL: 1361 if (mac_node->state == HCLGEVF_MAC_TO_ADD) { 1362 list_del(&mac_node->node); 1363 kfree(mac_node); 1364 } else { 1365 mac_node->state = HCLGEVF_MAC_TO_DEL; 1366 } 1367 break; 1368 /* only from tmp_add_list, the mac_node->state won't be 1369 * HCLGEVF_MAC_ACTIVE 1370 */ 1371 case HCLGEVF_MAC_ACTIVE: 1372 if (mac_node->state == HCLGEVF_MAC_TO_ADD) 1373 mac_node->state = HCLGEVF_MAC_ACTIVE; 1374 break; 1375 } 1376 } 1377 1378 static int hclgevf_update_mac_list(struct hnae3_handle *handle, 1379 enum HCLGEVF_MAC_NODE_STATE state, 1380 enum HCLGEVF_MAC_ADDR_TYPE mac_type, 1381 const unsigned char *addr) 1382 { 1383 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1384 struct hclgevf_mac_addr_node *mac_node; 1385 struct list_head *list; 1386 1387 list = (mac_type == HCLGEVF_MAC_ADDR_UC) ? 1388 &hdev->mac_table.uc_mac_list : &hdev->mac_table.mc_mac_list; 1389 1390 spin_lock_bh(&hdev->mac_table.mac_list_lock); 1391 1392 /* if the mac addr is already in the mac list, no need to add a new 1393 * one into it, just check the mac addr state, convert it to a new 1394 * new state, or just remove it, or do nothing. 1395 */ 1396 mac_node = hclgevf_find_mac_node(list, addr); 1397 if (mac_node) { 1398 hclgevf_update_mac_node(mac_node, state); 1399 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1400 return 0; 1401 } 1402 /* if this address is never added, unnecessary to delete */ 1403 if (state == HCLGEVF_MAC_TO_DEL) { 1404 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1405 return -ENOENT; 1406 } 1407 1408 mac_node = kzalloc(sizeof(*mac_node), GFP_ATOMIC); 1409 if (!mac_node) { 1410 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1411 return -ENOMEM; 1412 } 1413 1414 mac_node->state = state; 1415 ether_addr_copy(mac_node->mac_addr, addr); 1416 list_add_tail(&mac_node->node, list); 1417 1418 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1419 return 0; 1420 } 1421 1422 static int hclgevf_add_uc_addr(struct hnae3_handle *handle, 1423 const unsigned char *addr) 1424 { 1425 return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_ADD, 1426 HCLGEVF_MAC_ADDR_UC, addr); 1427 } 1428 1429 static int hclgevf_rm_uc_addr(struct hnae3_handle *handle, 1430 const unsigned char *addr) 1431 { 1432 return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_DEL, 1433 HCLGEVF_MAC_ADDR_UC, addr); 1434 } 1435 1436 static int hclgevf_add_mc_addr(struct hnae3_handle *handle, 1437 const unsigned char *addr) 1438 { 1439 return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_ADD, 1440 HCLGEVF_MAC_ADDR_MC, addr); 1441 } 1442 1443 static int hclgevf_rm_mc_addr(struct hnae3_handle *handle, 1444 const unsigned char *addr) 1445 { 1446 return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_DEL, 1447 HCLGEVF_MAC_ADDR_MC, addr); 1448 } 1449 1450 static int hclgevf_add_del_mac_addr(struct hclgevf_dev *hdev, 1451 struct hclgevf_mac_addr_node *mac_node, 1452 enum HCLGEVF_MAC_ADDR_TYPE mac_type) 1453 { 1454 struct hclge_vf_to_pf_msg send_msg; 1455 u8 code, subcode; 1456 1457 if (mac_type == HCLGEVF_MAC_ADDR_UC) { 1458 code = HCLGE_MBX_SET_UNICAST; 1459 if (mac_node->state == HCLGEVF_MAC_TO_ADD) 1460 subcode = HCLGE_MBX_MAC_VLAN_UC_ADD; 1461 else 1462 subcode = HCLGE_MBX_MAC_VLAN_UC_REMOVE; 1463 } else { 1464 code = HCLGE_MBX_SET_MULTICAST; 1465 if (mac_node->state == HCLGEVF_MAC_TO_ADD) 1466 subcode = HCLGE_MBX_MAC_VLAN_MC_ADD; 1467 else 1468 subcode = HCLGE_MBX_MAC_VLAN_MC_REMOVE; 1469 } 1470 1471 hclgevf_build_send_msg(&send_msg, code, subcode); 1472 ether_addr_copy(send_msg.data, mac_node->mac_addr); 1473 return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 1474 } 1475 1476 static void hclgevf_config_mac_list(struct hclgevf_dev *hdev, 1477 struct list_head *list, 1478 enum HCLGEVF_MAC_ADDR_TYPE mac_type) 1479 { 1480 struct hclgevf_mac_addr_node *mac_node, *tmp; 1481 int ret; 1482 1483 list_for_each_entry_safe(mac_node, tmp, list, node) { 1484 ret = hclgevf_add_del_mac_addr(hdev, mac_node, mac_type); 1485 if (ret) { 1486 dev_err(&hdev->pdev->dev, 1487 "failed to configure mac %pM, state = %d, ret = %d\n", 1488 mac_node->mac_addr, mac_node->state, ret); 1489 return; 1490 } 1491 if (mac_node->state == HCLGEVF_MAC_TO_ADD) { 1492 mac_node->state = HCLGEVF_MAC_ACTIVE; 1493 } else { 1494 list_del(&mac_node->node); 1495 kfree(mac_node); 1496 } 1497 } 1498 } 1499 1500 static void hclgevf_sync_from_add_list(struct list_head *add_list, 1501 struct list_head *mac_list) 1502 { 1503 struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node; 1504 1505 list_for_each_entry_safe(mac_node, tmp, add_list, node) { 1506 /* if the mac address from tmp_add_list is not in the 1507 * uc/mc_mac_list, it means have received a TO_DEL request 1508 * during the time window of sending mac config request to PF 1509 * If mac_node state is ACTIVE, then change its state to TO_DEL, 1510 * then it will be removed at next time. If is TO_ADD, it means 1511 * send TO_ADD request failed, so just remove the mac node. 1512 */ 1513 new_node = hclgevf_find_mac_node(mac_list, mac_node->mac_addr); 1514 if (new_node) { 1515 hclgevf_update_mac_node(new_node, mac_node->state); 1516 list_del(&mac_node->node); 1517 kfree(mac_node); 1518 } else if (mac_node->state == HCLGEVF_MAC_ACTIVE) { 1519 mac_node->state = HCLGEVF_MAC_TO_DEL; 1520 list_del(&mac_node->node); 1521 list_add_tail(&mac_node->node, mac_list); 1522 } else { 1523 list_del(&mac_node->node); 1524 kfree(mac_node); 1525 } 1526 } 1527 } 1528 1529 static void hclgevf_sync_from_del_list(struct list_head *del_list, 1530 struct list_head *mac_list) 1531 { 1532 struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node; 1533 1534 list_for_each_entry_safe(mac_node, tmp, del_list, node) { 1535 new_node = hclgevf_find_mac_node(mac_list, mac_node->mac_addr); 1536 if (new_node) { 1537 /* If the mac addr is exist in the mac list, it means 1538 * received a new request TO_ADD during the time window 1539 * of sending mac addr configurrequest to PF, so just 1540 * change the mac state to ACTIVE. 1541 */ 1542 new_node->state = HCLGEVF_MAC_ACTIVE; 1543 list_del(&mac_node->node); 1544 kfree(mac_node); 1545 } else { 1546 list_del(&mac_node->node); 1547 list_add_tail(&mac_node->node, mac_list); 1548 } 1549 } 1550 } 1551 1552 static void hclgevf_clear_list(struct list_head *list) 1553 { 1554 struct hclgevf_mac_addr_node *mac_node, *tmp; 1555 1556 list_for_each_entry_safe(mac_node, tmp, list, node) { 1557 list_del(&mac_node->node); 1558 kfree(mac_node); 1559 } 1560 } 1561 1562 static void hclgevf_sync_mac_list(struct hclgevf_dev *hdev, 1563 enum HCLGEVF_MAC_ADDR_TYPE mac_type) 1564 { 1565 struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node; 1566 struct list_head tmp_add_list, tmp_del_list; 1567 struct list_head *list; 1568 1569 INIT_LIST_HEAD(&tmp_add_list); 1570 INIT_LIST_HEAD(&tmp_del_list); 1571 1572 /* move the mac addr to the tmp_add_list and tmp_del_list, then 1573 * we can add/delete these mac addr outside the spin lock 1574 */ 1575 list = (mac_type == HCLGEVF_MAC_ADDR_UC) ? 1576 &hdev->mac_table.uc_mac_list : &hdev->mac_table.mc_mac_list; 1577 1578 spin_lock_bh(&hdev->mac_table.mac_list_lock); 1579 1580 list_for_each_entry_safe(mac_node, tmp, list, node) { 1581 switch (mac_node->state) { 1582 case HCLGEVF_MAC_TO_DEL: 1583 list_del(&mac_node->node); 1584 list_add_tail(&mac_node->node, &tmp_del_list); 1585 break; 1586 case HCLGEVF_MAC_TO_ADD: 1587 new_node = kzalloc(sizeof(*new_node), GFP_ATOMIC); 1588 if (!new_node) 1589 goto stop_traverse; 1590 1591 ether_addr_copy(new_node->mac_addr, mac_node->mac_addr); 1592 new_node->state = mac_node->state; 1593 list_add_tail(&new_node->node, &tmp_add_list); 1594 break; 1595 default: 1596 break; 1597 } 1598 } 1599 1600 stop_traverse: 1601 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1602 1603 /* delete first, in order to get max mac table space for adding */ 1604 hclgevf_config_mac_list(hdev, &tmp_del_list, mac_type); 1605 hclgevf_config_mac_list(hdev, &tmp_add_list, mac_type); 1606 1607 /* if some mac addresses were added/deleted fail, move back to the 1608 * mac_list, and retry at next time. 1609 */ 1610 spin_lock_bh(&hdev->mac_table.mac_list_lock); 1611 1612 hclgevf_sync_from_del_list(&tmp_del_list, list); 1613 hclgevf_sync_from_add_list(&tmp_add_list, list); 1614 1615 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1616 } 1617 1618 static void hclgevf_sync_mac_table(struct hclgevf_dev *hdev) 1619 { 1620 hclgevf_sync_mac_list(hdev, HCLGEVF_MAC_ADDR_UC); 1621 hclgevf_sync_mac_list(hdev, HCLGEVF_MAC_ADDR_MC); 1622 } 1623 1624 static void hclgevf_uninit_mac_list(struct hclgevf_dev *hdev) 1625 { 1626 spin_lock_bh(&hdev->mac_table.mac_list_lock); 1627 1628 hclgevf_clear_list(&hdev->mac_table.uc_mac_list); 1629 hclgevf_clear_list(&hdev->mac_table.mc_mac_list); 1630 1631 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1632 } 1633 1634 static int hclgevf_set_vlan_filter(struct hnae3_handle *handle, 1635 __be16 proto, u16 vlan_id, 1636 bool is_kill) 1637 { 1638 #define HCLGEVF_VLAN_MBX_IS_KILL_OFFSET 0 1639 #define HCLGEVF_VLAN_MBX_VLAN_ID_OFFSET 1 1640 #define HCLGEVF_VLAN_MBX_PROTO_OFFSET 3 1641 1642 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1643 struct hclge_vf_to_pf_msg send_msg; 1644 int ret; 1645 1646 if (vlan_id > HCLGEVF_MAX_VLAN_ID) 1647 return -EINVAL; 1648 1649 if (proto != htons(ETH_P_8021Q)) 1650 return -EPROTONOSUPPORT; 1651 1652 /* When device is resetting or reset failed, firmware is unable to 1653 * handle mailbox. Just record the vlan id, and remove it after 1654 * reset finished. 1655 */ 1656 if ((test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) || 1657 test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) && is_kill) { 1658 set_bit(vlan_id, hdev->vlan_del_fail_bmap); 1659 return -EBUSY; 1660 } 1661 1662 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 1663 HCLGE_MBX_VLAN_FILTER); 1664 send_msg.data[HCLGEVF_VLAN_MBX_IS_KILL_OFFSET] = is_kill; 1665 memcpy(&send_msg.data[HCLGEVF_VLAN_MBX_VLAN_ID_OFFSET], &vlan_id, 1666 sizeof(vlan_id)); 1667 memcpy(&send_msg.data[HCLGEVF_VLAN_MBX_PROTO_OFFSET], &proto, 1668 sizeof(proto)); 1669 /* when remove hw vlan filter failed, record the vlan id, 1670 * and try to remove it from hw later, to be consistence 1671 * with stack. 1672 */ 1673 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1674 if (is_kill && ret) 1675 set_bit(vlan_id, hdev->vlan_del_fail_bmap); 1676 1677 return ret; 1678 } 1679 1680 static void hclgevf_sync_vlan_filter(struct hclgevf_dev *hdev) 1681 { 1682 #define HCLGEVF_MAX_SYNC_COUNT 60 1683 struct hnae3_handle *handle = &hdev->nic; 1684 int ret, sync_cnt = 0; 1685 u16 vlan_id; 1686 1687 vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID); 1688 while (vlan_id != VLAN_N_VID) { 1689 ret = hclgevf_set_vlan_filter(handle, htons(ETH_P_8021Q), 1690 vlan_id, true); 1691 if (ret) 1692 return; 1693 1694 clear_bit(vlan_id, hdev->vlan_del_fail_bmap); 1695 sync_cnt++; 1696 if (sync_cnt >= HCLGEVF_MAX_SYNC_COUNT) 1697 return; 1698 1699 vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID); 1700 } 1701 } 1702 1703 static int hclgevf_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) 1704 { 1705 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1706 struct hclge_vf_to_pf_msg send_msg; 1707 1708 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 1709 HCLGE_MBX_VLAN_RX_OFF_CFG); 1710 send_msg.data[0] = enable ? 1 : 0; 1711 return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 1712 } 1713 1714 static int hclgevf_reset_tqp(struct hnae3_handle *handle, u16 queue_id) 1715 { 1716 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1717 struct hclge_vf_to_pf_msg send_msg; 1718 int ret; 1719 1720 /* disable vf queue before send queue reset msg to PF */ 1721 ret = hclgevf_tqp_enable(hdev, queue_id, 0, false); 1722 if (ret) 1723 return ret; 1724 1725 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_QUEUE_RESET, 0); 1726 memcpy(send_msg.data, &queue_id, sizeof(queue_id)); 1727 return hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1728 } 1729 1730 static int hclgevf_set_mtu(struct hnae3_handle *handle, int new_mtu) 1731 { 1732 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1733 struct hclge_vf_to_pf_msg send_msg; 1734 1735 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_MTU, 0); 1736 memcpy(send_msg.data, &new_mtu, sizeof(new_mtu)); 1737 return hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1738 } 1739 1740 static int hclgevf_notify_client(struct hclgevf_dev *hdev, 1741 enum hnae3_reset_notify_type type) 1742 { 1743 struct hnae3_client *client = hdev->nic_client; 1744 struct hnae3_handle *handle = &hdev->nic; 1745 int ret; 1746 1747 if (!test_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state) || 1748 !client) 1749 return 0; 1750 1751 if (!client->ops->reset_notify) 1752 return -EOPNOTSUPP; 1753 1754 ret = client->ops->reset_notify(handle, type); 1755 if (ret) 1756 dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n", 1757 type, ret); 1758 1759 return ret; 1760 } 1761 1762 static int hclgevf_notify_roce_client(struct hclgevf_dev *hdev, 1763 enum hnae3_reset_notify_type type) 1764 { 1765 struct hnae3_client *client = hdev->roce_client; 1766 struct hnae3_handle *handle = &hdev->roce; 1767 int ret; 1768 1769 if (!test_bit(HCLGEVF_STATE_ROCE_REGISTERED, &hdev->state) || !client) 1770 return 0; 1771 1772 if (!client->ops->reset_notify) 1773 return -EOPNOTSUPP; 1774 1775 ret = client->ops->reset_notify(handle, type); 1776 if (ret) 1777 dev_err(&hdev->pdev->dev, "notify roce client failed %d(%d)", 1778 type, ret); 1779 return ret; 1780 } 1781 1782 static int hclgevf_reset_wait(struct hclgevf_dev *hdev) 1783 { 1784 #define HCLGEVF_RESET_WAIT_US 20000 1785 #define HCLGEVF_RESET_WAIT_CNT 2000 1786 #define HCLGEVF_RESET_WAIT_TIMEOUT_US \ 1787 (HCLGEVF_RESET_WAIT_US * HCLGEVF_RESET_WAIT_CNT) 1788 1789 u32 val; 1790 int ret; 1791 1792 if (hdev->reset_type == HNAE3_VF_RESET) 1793 ret = readl_poll_timeout(hdev->hw.io_base + 1794 HCLGEVF_VF_RST_ING, val, 1795 !(val & HCLGEVF_VF_RST_ING_BIT), 1796 HCLGEVF_RESET_WAIT_US, 1797 HCLGEVF_RESET_WAIT_TIMEOUT_US); 1798 else 1799 ret = readl_poll_timeout(hdev->hw.io_base + 1800 HCLGEVF_RST_ING, val, 1801 !(val & HCLGEVF_RST_ING_BITS), 1802 HCLGEVF_RESET_WAIT_US, 1803 HCLGEVF_RESET_WAIT_TIMEOUT_US); 1804 1805 /* hardware completion status should be available by this time */ 1806 if (ret) { 1807 dev_err(&hdev->pdev->dev, 1808 "couldn't get reset done status from h/w, timeout!\n"); 1809 return ret; 1810 } 1811 1812 /* we will wait a bit more to let reset of the stack to complete. This 1813 * might happen in case reset assertion was made by PF. Yes, this also 1814 * means we might end up waiting bit more even for VF reset. 1815 */ 1816 msleep(5000); 1817 1818 return 0; 1819 } 1820 1821 static void hclgevf_reset_handshake(struct hclgevf_dev *hdev, bool enable) 1822 { 1823 u32 reg_val; 1824 1825 reg_val = hclgevf_read_dev(&hdev->hw, HCLGEVF_NIC_CSQ_DEPTH_REG); 1826 if (enable) 1827 reg_val |= HCLGEVF_NIC_SW_RST_RDY; 1828 else 1829 reg_val &= ~HCLGEVF_NIC_SW_RST_RDY; 1830 1831 hclgevf_write_dev(&hdev->hw, HCLGEVF_NIC_CSQ_DEPTH_REG, 1832 reg_val); 1833 } 1834 1835 static int hclgevf_reset_stack(struct hclgevf_dev *hdev) 1836 { 1837 int ret; 1838 1839 /* uninitialize the nic client */ 1840 ret = hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT); 1841 if (ret) 1842 return ret; 1843 1844 /* re-initialize the hclge device */ 1845 ret = hclgevf_reset_hdev(hdev); 1846 if (ret) { 1847 dev_err(&hdev->pdev->dev, 1848 "hclge device re-init failed, VF is disabled!\n"); 1849 return ret; 1850 } 1851 1852 /* bring up the nic client again */ 1853 ret = hclgevf_notify_client(hdev, HNAE3_INIT_CLIENT); 1854 if (ret) 1855 return ret; 1856 1857 /* clear handshake status with IMP */ 1858 hclgevf_reset_handshake(hdev, false); 1859 1860 /* bring up the nic to enable TX/RX again */ 1861 return hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 1862 } 1863 1864 static int hclgevf_reset_prepare_wait(struct hclgevf_dev *hdev) 1865 { 1866 #define HCLGEVF_RESET_SYNC_TIME 100 1867 1868 if (hdev->reset_type == HNAE3_VF_FUNC_RESET) { 1869 struct hclge_vf_to_pf_msg send_msg; 1870 int ret; 1871 1872 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_RESET, 0); 1873 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1874 if (ret) { 1875 dev_err(&hdev->pdev->dev, 1876 "failed to assert VF reset, ret = %d\n", ret); 1877 return ret; 1878 } 1879 hdev->rst_stats.vf_func_rst_cnt++; 1880 } 1881 1882 set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 1883 /* inform hardware that preparatory work is done */ 1884 msleep(HCLGEVF_RESET_SYNC_TIME); 1885 hclgevf_reset_handshake(hdev, true); 1886 dev_info(&hdev->pdev->dev, "prepare reset(%d) wait done\n", 1887 hdev->reset_type); 1888 1889 return 0; 1890 } 1891 1892 static void hclgevf_dump_rst_info(struct hclgevf_dev *hdev) 1893 { 1894 dev_info(&hdev->pdev->dev, "VF function reset count: %u\n", 1895 hdev->rst_stats.vf_func_rst_cnt); 1896 dev_info(&hdev->pdev->dev, "FLR reset count: %u\n", 1897 hdev->rst_stats.flr_rst_cnt); 1898 dev_info(&hdev->pdev->dev, "VF reset count: %u\n", 1899 hdev->rst_stats.vf_rst_cnt); 1900 dev_info(&hdev->pdev->dev, "reset done count: %u\n", 1901 hdev->rst_stats.rst_done_cnt); 1902 dev_info(&hdev->pdev->dev, "HW reset done count: %u\n", 1903 hdev->rst_stats.hw_rst_done_cnt); 1904 dev_info(&hdev->pdev->dev, "reset count: %u\n", 1905 hdev->rst_stats.rst_cnt); 1906 dev_info(&hdev->pdev->dev, "reset fail count: %u\n", 1907 hdev->rst_stats.rst_fail_cnt); 1908 dev_info(&hdev->pdev->dev, "vector0 interrupt enable status: 0x%x\n", 1909 hclgevf_read_dev(&hdev->hw, HCLGEVF_MISC_VECTOR_REG_BASE)); 1910 dev_info(&hdev->pdev->dev, "vector0 interrupt status: 0x%x\n", 1911 hclgevf_read_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_STATE_REG)); 1912 dev_info(&hdev->pdev->dev, "handshake status: 0x%x\n", 1913 hclgevf_read_dev(&hdev->hw, HCLGEVF_CMDQ_TX_DEPTH_REG)); 1914 dev_info(&hdev->pdev->dev, "function reset status: 0x%x\n", 1915 hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING)); 1916 dev_info(&hdev->pdev->dev, "hdev state: 0x%lx\n", hdev->state); 1917 } 1918 1919 static void hclgevf_reset_err_handle(struct hclgevf_dev *hdev) 1920 { 1921 /* recover handshake status with IMP when reset fail */ 1922 hclgevf_reset_handshake(hdev, true); 1923 hdev->rst_stats.rst_fail_cnt++; 1924 dev_err(&hdev->pdev->dev, "failed to reset VF(%u)\n", 1925 hdev->rst_stats.rst_fail_cnt); 1926 1927 if (hdev->rst_stats.rst_fail_cnt < HCLGEVF_RESET_MAX_FAIL_CNT) 1928 set_bit(hdev->reset_type, &hdev->reset_pending); 1929 1930 if (hclgevf_is_reset_pending(hdev)) { 1931 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1932 hclgevf_reset_task_schedule(hdev); 1933 } else { 1934 set_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state); 1935 hclgevf_dump_rst_info(hdev); 1936 } 1937 } 1938 1939 static int hclgevf_reset_prepare(struct hclgevf_dev *hdev) 1940 { 1941 int ret; 1942 1943 hdev->rst_stats.rst_cnt++; 1944 1945 /* perform reset of the stack & ae device for a client */ 1946 ret = hclgevf_notify_roce_client(hdev, HNAE3_DOWN_CLIENT); 1947 if (ret) 1948 return ret; 1949 1950 rtnl_lock(); 1951 /* bring down the nic to stop any ongoing TX/RX */ 1952 ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 1953 rtnl_unlock(); 1954 if (ret) 1955 return ret; 1956 1957 return hclgevf_reset_prepare_wait(hdev); 1958 } 1959 1960 static int hclgevf_reset_rebuild(struct hclgevf_dev *hdev) 1961 { 1962 int ret; 1963 1964 hdev->rst_stats.hw_rst_done_cnt++; 1965 ret = hclgevf_notify_roce_client(hdev, HNAE3_UNINIT_CLIENT); 1966 if (ret) 1967 return ret; 1968 1969 rtnl_lock(); 1970 /* now, re-initialize the nic client and ae device */ 1971 ret = hclgevf_reset_stack(hdev); 1972 rtnl_unlock(); 1973 if (ret) { 1974 dev_err(&hdev->pdev->dev, "failed to reset VF stack\n"); 1975 return ret; 1976 } 1977 1978 ret = hclgevf_notify_roce_client(hdev, HNAE3_INIT_CLIENT); 1979 /* ignore RoCE notify error if it fails HCLGEVF_RESET_MAX_FAIL_CNT - 1 1980 * times 1981 */ 1982 if (ret && 1983 hdev->rst_stats.rst_fail_cnt < HCLGEVF_RESET_MAX_FAIL_CNT - 1) 1984 return ret; 1985 1986 ret = hclgevf_notify_roce_client(hdev, HNAE3_UP_CLIENT); 1987 if (ret) 1988 return ret; 1989 1990 hdev->last_reset_time = jiffies; 1991 hdev->rst_stats.rst_done_cnt++; 1992 hdev->rst_stats.rst_fail_cnt = 0; 1993 clear_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state); 1994 1995 return 0; 1996 } 1997 1998 static void hclgevf_reset(struct hclgevf_dev *hdev) 1999 { 2000 if (hclgevf_reset_prepare(hdev)) 2001 goto err_reset; 2002 2003 /* check if VF could successfully fetch the hardware reset completion 2004 * status from the hardware 2005 */ 2006 if (hclgevf_reset_wait(hdev)) { 2007 /* can't do much in this situation, will disable VF */ 2008 dev_err(&hdev->pdev->dev, 2009 "failed to fetch H/W reset completion status\n"); 2010 goto err_reset; 2011 } 2012 2013 if (hclgevf_reset_rebuild(hdev)) 2014 goto err_reset; 2015 2016 return; 2017 2018 err_reset: 2019 hclgevf_reset_err_handle(hdev); 2020 } 2021 2022 static enum hnae3_reset_type hclgevf_get_reset_level(struct hclgevf_dev *hdev, 2023 unsigned long *addr) 2024 { 2025 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; 2026 2027 /* return the highest priority reset level amongst all */ 2028 if (test_bit(HNAE3_VF_RESET, addr)) { 2029 rst_level = HNAE3_VF_RESET; 2030 clear_bit(HNAE3_VF_RESET, addr); 2031 clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 2032 clear_bit(HNAE3_VF_FUNC_RESET, addr); 2033 } else if (test_bit(HNAE3_VF_FULL_RESET, addr)) { 2034 rst_level = HNAE3_VF_FULL_RESET; 2035 clear_bit(HNAE3_VF_FULL_RESET, addr); 2036 clear_bit(HNAE3_VF_FUNC_RESET, addr); 2037 } else if (test_bit(HNAE3_VF_PF_FUNC_RESET, addr)) { 2038 rst_level = HNAE3_VF_PF_FUNC_RESET; 2039 clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 2040 clear_bit(HNAE3_VF_FUNC_RESET, addr); 2041 } else if (test_bit(HNAE3_VF_FUNC_RESET, addr)) { 2042 rst_level = HNAE3_VF_FUNC_RESET; 2043 clear_bit(HNAE3_VF_FUNC_RESET, addr); 2044 } else if (test_bit(HNAE3_FLR_RESET, addr)) { 2045 rst_level = HNAE3_FLR_RESET; 2046 clear_bit(HNAE3_FLR_RESET, addr); 2047 } 2048 2049 return rst_level; 2050 } 2051 2052 static void hclgevf_reset_event(struct pci_dev *pdev, 2053 struct hnae3_handle *handle) 2054 { 2055 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2056 struct hclgevf_dev *hdev = ae_dev->priv; 2057 2058 dev_info(&hdev->pdev->dev, "received reset request from VF enet\n"); 2059 2060 if (hdev->default_reset_request) 2061 hdev->reset_level = 2062 hclgevf_get_reset_level(hdev, 2063 &hdev->default_reset_request); 2064 else 2065 hdev->reset_level = HNAE3_VF_FUNC_RESET; 2066 2067 /* reset of this VF requested */ 2068 set_bit(HCLGEVF_RESET_REQUESTED, &hdev->reset_state); 2069 hclgevf_reset_task_schedule(hdev); 2070 2071 hdev->last_reset_time = jiffies; 2072 } 2073 2074 static void hclgevf_set_def_reset_request(struct hnae3_ae_dev *ae_dev, 2075 enum hnae3_reset_type rst_type) 2076 { 2077 struct hclgevf_dev *hdev = ae_dev->priv; 2078 2079 set_bit(rst_type, &hdev->default_reset_request); 2080 } 2081 2082 static void hclgevf_enable_vector(struct hclgevf_misc_vector *vector, bool en) 2083 { 2084 writel(en ? 1 : 0, vector->addr); 2085 } 2086 2087 static void hclgevf_flr_prepare(struct hnae3_ae_dev *ae_dev) 2088 { 2089 #define HCLGEVF_FLR_RETRY_WAIT_MS 500 2090 #define HCLGEVF_FLR_RETRY_CNT 5 2091 2092 struct hclgevf_dev *hdev = ae_dev->priv; 2093 int retry_cnt = 0; 2094 int ret; 2095 2096 retry: 2097 down(&hdev->reset_sem); 2098 set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 2099 hdev->reset_type = HNAE3_FLR_RESET; 2100 ret = hclgevf_reset_prepare(hdev); 2101 if (ret) { 2102 dev_err(&hdev->pdev->dev, "fail to prepare FLR, ret=%d\n", 2103 ret); 2104 if (hdev->reset_pending || 2105 retry_cnt++ < HCLGEVF_FLR_RETRY_CNT) { 2106 dev_err(&hdev->pdev->dev, 2107 "reset_pending:0x%lx, retry_cnt:%d\n", 2108 hdev->reset_pending, retry_cnt); 2109 clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 2110 up(&hdev->reset_sem); 2111 msleep(HCLGEVF_FLR_RETRY_WAIT_MS); 2112 goto retry; 2113 } 2114 } 2115 2116 /* disable misc vector before FLR done */ 2117 hclgevf_enable_vector(&hdev->misc_vector, false); 2118 hdev->rst_stats.flr_rst_cnt++; 2119 } 2120 2121 static void hclgevf_flr_done(struct hnae3_ae_dev *ae_dev) 2122 { 2123 struct hclgevf_dev *hdev = ae_dev->priv; 2124 int ret; 2125 2126 hclgevf_enable_vector(&hdev->misc_vector, true); 2127 2128 ret = hclgevf_reset_rebuild(hdev); 2129 if (ret) 2130 dev_warn(&hdev->pdev->dev, "fail to rebuild, ret=%d\n", 2131 ret); 2132 2133 hdev->reset_type = HNAE3_NONE_RESET; 2134 clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 2135 up(&hdev->reset_sem); 2136 } 2137 2138 static u32 hclgevf_get_fw_version(struct hnae3_handle *handle) 2139 { 2140 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2141 2142 return hdev->fw_version; 2143 } 2144 2145 static void hclgevf_get_misc_vector(struct hclgevf_dev *hdev) 2146 { 2147 struct hclgevf_misc_vector *vector = &hdev->misc_vector; 2148 2149 vector->vector_irq = pci_irq_vector(hdev->pdev, 2150 HCLGEVF_MISC_VECTOR_NUM); 2151 vector->addr = hdev->hw.io_base + HCLGEVF_MISC_VECTOR_REG_BASE; 2152 /* vector status always valid for Vector 0 */ 2153 hdev->vector_status[HCLGEVF_MISC_VECTOR_NUM] = 0; 2154 hdev->vector_irq[HCLGEVF_MISC_VECTOR_NUM] = vector->vector_irq; 2155 2156 hdev->num_msi_left -= 1; 2157 hdev->num_msi_used += 1; 2158 } 2159 2160 void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev) 2161 { 2162 if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) && 2163 !test_and_set_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, 2164 &hdev->state)) 2165 mod_delayed_work(hclgevf_wq, &hdev->service_task, 0); 2166 } 2167 2168 void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev) 2169 { 2170 if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) && 2171 !test_and_set_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, 2172 &hdev->state)) 2173 mod_delayed_work(hclgevf_wq, &hdev->service_task, 0); 2174 } 2175 2176 static void hclgevf_task_schedule(struct hclgevf_dev *hdev, 2177 unsigned long delay) 2178 { 2179 if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) && 2180 !test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) 2181 mod_delayed_work(hclgevf_wq, &hdev->service_task, delay); 2182 } 2183 2184 static void hclgevf_reset_service_task(struct hclgevf_dev *hdev) 2185 { 2186 #define HCLGEVF_MAX_RESET_ATTEMPTS_CNT 3 2187 2188 if (!test_and_clear_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state)) 2189 return; 2190 2191 down(&hdev->reset_sem); 2192 set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 2193 2194 if (test_and_clear_bit(HCLGEVF_RESET_PENDING, 2195 &hdev->reset_state)) { 2196 /* PF has initmated that it is about to reset the hardware. 2197 * We now have to poll & check if hardware has actually 2198 * completed the reset sequence. On hardware reset completion, 2199 * VF needs to reset the client and ae device. 2200 */ 2201 hdev->reset_attempts = 0; 2202 2203 hdev->last_reset_time = jiffies; 2204 while ((hdev->reset_type = 2205 hclgevf_get_reset_level(hdev, &hdev->reset_pending)) 2206 != HNAE3_NONE_RESET) 2207 hclgevf_reset(hdev); 2208 } else if (test_and_clear_bit(HCLGEVF_RESET_REQUESTED, 2209 &hdev->reset_state)) { 2210 /* we could be here when either of below happens: 2211 * 1. reset was initiated due to watchdog timeout caused by 2212 * a. IMP was earlier reset and our TX got choked down and 2213 * which resulted in watchdog reacting and inducing VF 2214 * reset. This also means our cmdq would be unreliable. 2215 * b. problem in TX due to other lower layer(example link 2216 * layer not functioning properly etc.) 2217 * 2. VF reset might have been initiated due to some config 2218 * change. 2219 * 2220 * NOTE: Theres no clear way to detect above cases than to react 2221 * to the response of PF for this reset request. PF will ack the 2222 * 1b and 2. cases but we will not get any intimation about 1a 2223 * from PF as cmdq would be in unreliable state i.e. mailbox 2224 * communication between PF and VF would be broken. 2225 * 2226 * if we are never geting into pending state it means either: 2227 * 1. PF is not receiving our request which could be due to IMP 2228 * reset 2229 * 2. PF is screwed 2230 * We cannot do much for 2. but to check first we can try reset 2231 * our PCIe + stack and see if it alleviates the problem. 2232 */ 2233 if (hdev->reset_attempts > HCLGEVF_MAX_RESET_ATTEMPTS_CNT) { 2234 /* prepare for full reset of stack + pcie interface */ 2235 set_bit(HNAE3_VF_FULL_RESET, &hdev->reset_pending); 2236 2237 /* "defer" schedule the reset task again */ 2238 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 2239 } else { 2240 hdev->reset_attempts++; 2241 2242 set_bit(hdev->reset_level, &hdev->reset_pending); 2243 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 2244 } 2245 hclgevf_reset_task_schedule(hdev); 2246 } 2247 2248 hdev->reset_type = HNAE3_NONE_RESET; 2249 clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 2250 up(&hdev->reset_sem); 2251 } 2252 2253 static void hclgevf_mailbox_service_task(struct hclgevf_dev *hdev) 2254 { 2255 if (!test_and_clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state)) 2256 return; 2257 2258 if (test_and_set_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) 2259 return; 2260 2261 hclgevf_mbx_async_handler(hdev); 2262 2263 clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 2264 } 2265 2266 static void hclgevf_keep_alive(struct hclgevf_dev *hdev) 2267 { 2268 struct hclge_vf_to_pf_msg send_msg; 2269 int ret; 2270 2271 if (test_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state)) 2272 return; 2273 2274 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_KEEP_ALIVE, 0); 2275 ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 2276 if (ret) 2277 dev_err(&hdev->pdev->dev, 2278 "VF sends keep alive cmd failed(=%d)\n", ret); 2279 } 2280 2281 static void hclgevf_periodic_service_task(struct hclgevf_dev *hdev) 2282 { 2283 unsigned long delta = round_jiffies_relative(HZ); 2284 struct hnae3_handle *handle = &hdev->nic; 2285 2286 if (test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) 2287 return; 2288 2289 if (time_is_after_jiffies(hdev->last_serv_processed + HZ)) { 2290 delta = jiffies - hdev->last_serv_processed; 2291 2292 if (delta < round_jiffies_relative(HZ)) { 2293 delta = round_jiffies_relative(HZ) - delta; 2294 goto out; 2295 } 2296 } 2297 2298 hdev->serv_processed_cnt++; 2299 if (!(hdev->serv_processed_cnt % HCLGEVF_KEEP_ALIVE_TASK_INTERVAL)) 2300 hclgevf_keep_alive(hdev); 2301 2302 if (test_bit(HCLGEVF_STATE_DOWN, &hdev->state)) { 2303 hdev->last_serv_processed = jiffies; 2304 goto out; 2305 } 2306 2307 if (!(hdev->serv_processed_cnt % HCLGEVF_STATS_TIMER_INTERVAL)) 2308 hclgevf_tqps_update_stats(handle); 2309 2310 /* request the link status from the PF. PF would be able to tell VF 2311 * about such updates in future so we might remove this later 2312 */ 2313 hclgevf_request_link_info(hdev); 2314 2315 hclgevf_update_link_mode(hdev); 2316 2317 hclgevf_sync_vlan_filter(hdev); 2318 2319 hclgevf_sync_mac_table(hdev); 2320 2321 hclgevf_sync_promisc_mode(hdev); 2322 2323 hdev->last_serv_processed = jiffies; 2324 2325 out: 2326 hclgevf_task_schedule(hdev, delta); 2327 } 2328 2329 static void hclgevf_service_task(struct work_struct *work) 2330 { 2331 struct hclgevf_dev *hdev = container_of(work, struct hclgevf_dev, 2332 service_task.work); 2333 2334 hclgevf_reset_service_task(hdev); 2335 hclgevf_mailbox_service_task(hdev); 2336 hclgevf_periodic_service_task(hdev); 2337 2338 /* Handle reset and mbx again in case periodical task delays the 2339 * handling by calling hclgevf_task_schedule() in 2340 * hclgevf_periodic_service_task() 2341 */ 2342 hclgevf_reset_service_task(hdev); 2343 hclgevf_mailbox_service_task(hdev); 2344 } 2345 2346 static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regclr) 2347 { 2348 hclgevf_write_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_SRC_REG, regclr); 2349 } 2350 2351 static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev, 2352 u32 *clearval) 2353 { 2354 u32 val, cmdq_stat_reg, rst_ing_reg; 2355 2356 /* fetch the events from their corresponding regs */ 2357 cmdq_stat_reg = hclgevf_read_dev(&hdev->hw, 2358 HCLGEVF_VECTOR0_CMDQ_STATE_REG); 2359 2360 if (BIT(HCLGEVF_VECTOR0_RST_INT_B) & cmdq_stat_reg) { 2361 rst_ing_reg = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 2362 dev_info(&hdev->pdev->dev, 2363 "receive reset interrupt 0x%x!\n", rst_ing_reg); 2364 set_bit(HNAE3_VF_RESET, &hdev->reset_pending); 2365 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 2366 set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 2367 *clearval = ~(1U << HCLGEVF_VECTOR0_RST_INT_B); 2368 hdev->rst_stats.vf_rst_cnt++; 2369 /* set up VF hardware reset status, its PF will clear 2370 * this status when PF has initialized done. 2371 */ 2372 val = hclgevf_read_dev(&hdev->hw, HCLGEVF_VF_RST_ING); 2373 hclgevf_write_dev(&hdev->hw, HCLGEVF_VF_RST_ING, 2374 val | HCLGEVF_VF_RST_ING_BIT); 2375 return HCLGEVF_VECTOR0_EVENT_RST; 2376 } 2377 2378 /* check for vector0 mailbox(=CMDQ RX) event source */ 2379 if (BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) { 2380 /* for revision 0x21, clearing interrupt is writing bit 0 2381 * to the clear register, writing bit 1 means to keep the 2382 * old value. 2383 * for revision 0x20, the clear register is a read & write 2384 * register, so we should just write 0 to the bit we are 2385 * handling, and keep other bits as cmdq_stat_reg. 2386 */ 2387 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) 2388 *clearval = ~(1U << HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 2389 else 2390 *clearval = cmdq_stat_reg & 2391 ~BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 2392 2393 return HCLGEVF_VECTOR0_EVENT_MBX; 2394 } 2395 2396 /* print other vector0 event source */ 2397 dev_info(&hdev->pdev->dev, 2398 "vector 0 interrupt from unknown source, cmdq_src = %#x\n", 2399 cmdq_stat_reg); 2400 2401 return HCLGEVF_VECTOR0_EVENT_OTHER; 2402 } 2403 2404 static irqreturn_t hclgevf_misc_irq_handle(int irq, void *data) 2405 { 2406 enum hclgevf_evt_cause event_cause; 2407 struct hclgevf_dev *hdev = data; 2408 u32 clearval; 2409 2410 hclgevf_enable_vector(&hdev->misc_vector, false); 2411 event_cause = hclgevf_check_evt_cause(hdev, &clearval); 2412 2413 switch (event_cause) { 2414 case HCLGEVF_VECTOR0_EVENT_RST: 2415 hclgevf_reset_task_schedule(hdev); 2416 break; 2417 case HCLGEVF_VECTOR0_EVENT_MBX: 2418 hclgevf_mbx_handler(hdev); 2419 break; 2420 default: 2421 break; 2422 } 2423 2424 if (event_cause != HCLGEVF_VECTOR0_EVENT_OTHER) { 2425 hclgevf_clear_event_cause(hdev, clearval); 2426 hclgevf_enable_vector(&hdev->misc_vector, true); 2427 } 2428 2429 return IRQ_HANDLED; 2430 } 2431 2432 static int hclgevf_configure(struct hclgevf_dev *hdev) 2433 { 2434 int ret; 2435 2436 /* get current port based vlan state from PF */ 2437 ret = hclgevf_get_port_base_vlan_filter_state(hdev); 2438 if (ret) 2439 return ret; 2440 2441 /* get queue configuration from PF */ 2442 ret = hclgevf_get_queue_info(hdev); 2443 if (ret) 2444 return ret; 2445 2446 /* get queue depth info from PF */ 2447 ret = hclgevf_get_queue_depth(hdev); 2448 if (ret) 2449 return ret; 2450 2451 ret = hclgevf_get_pf_media_type(hdev); 2452 if (ret) 2453 return ret; 2454 2455 /* get tc configuration from PF */ 2456 return hclgevf_get_tc_info(hdev); 2457 } 2458 2459 static int hclgevf_alloc_hdev(struct hnae3_ae_dev *ae_dev) 2460 { 2461 struct pci_dev *pdev = ae_dev->pdev; 2462 struct hclgevf_dev *hdev; 2463 2464 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 2465 if (!hdev) 2466 return -ENOMEM; 2467 2468 hdev->pdev = pdev; 2469 hdev->ae_dev = ae_dev; 2470 ae_dev->priv = hdev; 2471 2472 return 0; 2473 } 2474 2475 static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev) 2476 { 2477 struct hnae3_handle *roce = &hdev->roce; 2478 struct hnae3_handle *nic = &hdev->nic; 2479 2480 roce->rinfo.num_vectors = hdev->num_roce_msix; 2481 2482 if (hdev->num_msi_left < roce->rinfo.num_vectors || 2483 hdev->num_msi_left == 0) 2484 return -EINVAL; 2485 2486 roce->rinfo.base_vector = hdev->roce_base_vector; 2487 2488 roce->rinfo.netdev = nic->kinfo.netdev; 2489 roce->rinfo.roce_io_base = hdev->hw.io_base; 2490 roce->rinfo.roce_mem_base = hdev->hw.mem_base; 2491 2492 roce->pdev = nic->pdev; 2493 roce->ae_algo = nic->ae_algo; 2494 roce->numa_node_mask = nic->numa_node_mask; 2495 2496 return 0; 2497 } 2498 2499 static int hclgevf_config_gro(struct hclgevf_dev *hdev, bool en) 2500 { 2501 struct hclgevf_cfg_gro_status_cmd *req; 2502 struct hclgevf_desc desc; 2503 int ret; 2504 2505 if (!hnae3_dev_gro_supported(hdev)) 2506 return 0; 2507 2508 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_GRO_GENERIC_CONFIG, 2509 false); 2510 req = (struct hclgevf_cfg_gro_status_cmd *)desc.data; 2511 2512 req->gro_en = en ? 1 : 0; 2513 2514 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 2515 if (ret) 2516 dev_err(&hdev->pdev->dev, 2517 "VF GRO hardware config cmd failed, ret = %d.\n", ret); 2518 2519 return ret; 2520 } 2521 2522 static int hclgevf_rss_init_cfg(struct hclgevf_dev *hdev) 2523 { 2524 u16 rss_ind_tbl_size = hdev->ae_dev->dev_specs.rss_ind_tbl_size; 2525 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 2526 struct hclgevf_rss_tuple_cfg *tuple_sets; 2527 u32 i; 2528 2529 rss_cfg->hash_algo = HCLGEVF_RSS_HASH_ALGO_TOEPLITZ; 2530 rss_cfg->rss_size = hdev->nic.kinfo.rss_size; 2531 tuple_sets = &rss_cfg->rss_tuple_sets; 2532 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 2533 u8 *rss_ind_tbl; 2534 2535 rss_cfg->hash_algo = HCLGEVF_RSS_HASH_ALGO_SIMPLE; 2536 2537 rss_ind_tbl = devm_kcalloc(&hdev->pdev->dev, rss_ind_tbl_size, 2538 sizeof(*rss_ind_tbl), GFP_KERNEL); 2539 if (!rss_ind_tbl) 2540 return -ENOMEM; 2541 2542 rss_cfg->rss_indirection_tbl = rss_ind_tbl; 2543 memcpy(rss_cfg->rss_hash_key, hclgevf_hash_key, 2544 HCLGEVF_RSS_KEY_SIZE); 2545 2546 tuple_sets->ipv4_tcp_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2547 tuple_sets->ipv4_udp_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2548 tuple_sets->ipv4_sctp_en = HCLGEVF_RSS_INPUT_TUPLE_SCTP; 2549 tuple_sets->ipv4_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2550 tuple_sets->ipv6_tcp_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2551 tuple_sets->ipv6_udp_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2552 tuple_sets->ipv6_sctp_en = 2553 hdev->ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2 ? 2554 HCLGEVF_RSS_INPUT_TUPLE_SCTP_NO_PORT : 2555 HCLGEVF_RSS_INPUT_TUPLE_SCTP; 2556 tuple_sets->ipv6_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2557 } 2558 2559 /* Initialize RSS indirect table */ 2560 for (i = 0; i < rss_ind_tbl_size; i++) 2561 rss_cfg->rss_indirection_tbl[i] = i % rss_cfg->rss_size; 2562 2563 return 0; 2564 } 2565 2566 static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev) 2567 { 2568 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 2569 int ret; 2570 2571 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 2572 ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 2573 rss_cfg->rss_hash_key); 2574 if (ret) 2575 return ret; 2576 2577 ret = hclgevf_set_rss_input_tuple(hdev, rss_cfg); 2578 if (ret) 2579 return ret; 2580 } 2581 2582 ret = hclgevf_set_rss_indir_table(hdev); 2583 if (ret) 2584 return ret; 2585 2586 return hclgevf_set_rss_tc_mode(hdev, rss_cfg->rss_size); 2587 } 2588 2589 static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev) 2590 { 2591 return hclgevf_set_vlan_filter(&hdev->nic, htons(ETH_P_8021Q), 0, 2592 false); 2593 } 2594 2595 static void hclgevf_flush_link_update(struct hclgevf_dev *hdev) 2596 { 2597 #define HCLGEVF_FLUSH_LINK_TIMEOUT 100000 2598 2599 unsigned long last = hdev->serv_processed_cnt; 2600 int i = 0; 2601 2602 while (test_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state) && 2603 i++ < HCLGEVF_FLUSH_LINK_TIMEOUT && 2604 last == hdev->serv_processed_cnt) 2605 usleep_range(1, 1); 2606 } 2607 2608 static void hclgevf_set_timer_task(struct hnae3_handle *handle, bool enable) 2609 { 2610 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2611 2612 if (enable) { 2613 hclgevf_task_schedule(hdev, 0); 2614 } else { 2615 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2616 2617 /* flush memory to make sure DOWN is seen by service task */ 2618 smp_mb__before_atomic(); 2619 hclgevf_flush_link_update(hdev); 2620 } 2621 } 2622 2623 static int hclgevf_ae_start(struct hnae3_handle *handle) 2624 { 2625 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2626 2627 clear_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2628 2629 hclgevf_reset_tqp_stats(handle); 2630 2631 hclgevf_request_link_info(hdev); 2632 2633 hclgevf_update_link_mode(hdev); 2634 2635 return 0; 2636 } 2637 2638 static void hclgevf_ae_stop(struct hnae3_handle *handle) 2639 { 2640 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2641 int i; 2642 2643 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2644 2645 if (hdev->reset_type != HNAE3_VF_RESET) 2646 for (i = 0; i < handle->kinfo.num_tqps; i++) 2647 if (hclgevf_reset_tqp(handle, i)) 2648 break; 2649 2650 hclgevf_reset_tqp_stats(handle); 2651 hclgevf_update_link_status(hdev, 0); 2652 } 2653 2654 static int hclgevf_set_alive(struct hnae3_handle *handle, bool alive) 2655 { 2656 #define HCLGEVF_STATE_ALIVE 1 2657 #define HCLGEVF_STATE_NOT_ALIVE 0 2658 2659 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2660 struct hclge_vf_to_pf_msg send_msg; 2661 2662 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_ALIVE, 0); 2663 send_msg.data[0] = alive ? HCLGEVF_STATE_ALIVE : 2664 HCLGEVF_STATE_NOT_ALIVE; 2665 return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 2666 } 2667 2668 static int hclgevf_client_start(struct hnae3_handle *handle) 2669 { 2670 return hclgevf_set_alive(handle, true); 2671 } 2672 2673 static void hclgevf_client_stop(struct hnae3_handle *handle) 2674 { 2675 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2676 int ret; 2677 2678 ret = hclgevf_set_alive(handle, false); 2679 if (ret) 2680 dev_warn(&hdev->pdev->dev, 2681 "%s failed %d\n", __func__, ret); 2682 } 2683 2684 static void hclgevf_state_init(struct hclgevf_dev *hdev) 2685 { 2686 clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 2687 clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 2688 clear_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state); 2689 2690 INIT_DELAYED_WORK(&hdev->service_task, hclgevf_service_task); 2691 2692 mutex_init(&hdev->mbx_resp.mbx_mutex); 2693 sema_init(&hdev->reset_sem, 1); 2694 2695 spin_lock_init(&hdev->mac_table.mac_list_lock); 2696 INIT_LIST_HEAD(&hdev->mac_table.uc_mac_list); 2697 INIT_LIST_HEAD(&hdev->mac_table.mc_mac_list); 2698 2699 /* bring the device down */ 2700 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2701 } 2702 2703 static void hclgevf_state_uninit(struct hclgevf_dev *hdev) 2704 { 2705 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2706 set_bit(HCLGEVF_STATE_REMOVING, &hdev->state); 2707 2708 if (hdev->service_task.work.func) 2709 cancel_delayed_work_sync(&hdev->service_task); 2710 2711 mutex_destroy(&hdev->mbx_resp.mbx_mutex); 2712 } 2713 2714 static int hclgevf_init_msi(struct hclgevf_dev *hdev) 2715 { 2716 struct pci_dev *pdev = hdev->pdev; 2717 int vectors; 2718 int i; 2719 2720 if (hnae3_dev_roce_supported(hdev)) 2721 vectors = pci_alloc_irq_vectors(pdev, 2722 hdev->roce_base_msix_offset + 1, 2723 hdev->num_msi, 2724 PCI_IRQ_MSIX); 2725 else 2726 vectors = pci_alloc_irq_vectors(pdev, HNAE3_MIN_VECTOR_NUM, 2727 hdev->num_msi, 2728 PCI_IRQ_MSI | PCI_IRQ_MSIX); 2729 2730 if (vectors < 0) { 2731 dev_err(&pdev->dev, 2732 "failed(%d) to allocate MSI/MSI-X vectors\n", 2733 vectors); 2734 return vectors; 2735 } 2736 if (vectors < hdev->num_msi) 2737 dev_warn(&hdev->pdev->dev, 2738 "requested %u MSI/MSI-X, but allocated %d MSI/MSI-X\n", 2739 hdev->num_msi, vectors); 2740 2741 hdev->num_msi = vectors; 2742 hdev->num_msi_left = vectors; 2743 2744 hdev->base_msi_vector = pdev->irq; 2745 hdev->roce_base_vector = pdev->irq + hdev->roce_base_msix_offset; 2746 2747 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 2748 sizeof(u16), GFP_KERNEL); 2749 if (!hdev->vector_status) { 2750 pci_free_irq_vectors(pdev); 2751 return -ENOMEM; 2752 } 2753 2754 for (i = 0; i < hdev->num_msi; i++) 2755 hdev->vector_status[i] = HCLGEVF_INVALID_VPORT; 2756 2757 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 2758 sizeof(int), GFP_KERNEL); 2759 if (!hdev->vector_irq) { 2760 devm_kfree(&pdev->dev, hdev->vector_status); 2761 pci_free_irq_vectors(pdev); 2762 return -ENOMEM; 2763 } 2764 2765 return 0; 2766 } 2767 2768 static void hclgevf_uninit_msi(struct hclgevf_dev *hdev) 2769 { 2770 struct pci_dev *pdev = hdev->pdev; 2771 2772 devm_kfree(&pdev->dev, hdev->vector_status); 2773 devm_kfree(&pdev->dev, hdev->vector_irq); 2774 pci_free_irq_vectors(pdev); 2775 } 2776 2777 static int hclgevf_misc_irq_init(struct hclgevf_dev *hdev) 2778 { 2779 int ret; 2780 2781 hclgevf_get_misc_vector(hdev); 2782 2783 snprintf(hdev->misc_vector.name, HNAE3_INT_NAME_LEN, "%s-misc-%s", 2784 HCLGEVF_NAME, pci_name(hdev->pdev)); 2785 ret = request_irq(hdev->misc_vector.vector_irq, hclgevf_misc_irq_handle, 2786 0, hdev->misc_vector.name, hdev); 2787 if (ret) { 2788 dev_err(&hdev->pdev->dev, "VF failed to request misc irq(%d)\n", 2789 hdev->misc_vector.vector_irq); 2790 return ret; 2791 } 2792 2793 hclgevf_clear_event_cause(hdev, 0); 2794 2795 /* enable misc. vector(vector 0) */ 2796 hclgevf_enable_vector(&hdev->misc_vector, true); 2797 2798 return ret; 2799 } 2800 2801 static void hclgevf_misc_irq_uninit(struct hclgevf_dev *hdev) 2802 { 2803 /* disable misc vector(vector 0) */ 2804 hclgevf_enable_vector(&hdev->misc_vector, false); 2805 synchronize_irq(hdev->misc_vector.vector_irq); 2806 free_irq(hdev->misc_vector.vector_irq, hdev); 2807 hclgevf_free_vector(hdev, 0); 2808 } 2809 2810 static void hclgevf_info_show(struct hclgevf_dev *hdev) 2811 { 2812 struct device *dev = &hdev->pdev->dev; 2813 2814 dev_info(dev, "VF info begin:\n"); 2815 2816 dev_info(dev, "Task queue pairs numbers: %u\n", hdev->num_tqps); 2817 dev_info(dev, "Desc num per TX queue: %u\n", hdev->num_tx_desc); 2818 dev_info(dev, "Desc num per RX queue: %u\n", hdev->num_rx_desc); 2819 dev_info(dev, "Numbers of vports: %u\n", hdev->num_alloc_vport); 2820 dev_info(dev, "HW tc map: 0x%x\n", hdev->hw_tc_map); 2821 dev_info(dev, "PF media type of this VF: %u\n", 2822 hdev->hw.mac.media_type); 2823 2824 dev_info(dev, "VF info end.\n"); 2825 } 2826 2827 static int hclgevf_init_nic_client_instance(struct hnae3_ae_dev *ae_dev, 2828 struct hnae3_client *client) 2829 { 2830 struct hclgevf_dev *hdev = ae_dev->priv; 2831 int rst_cnt = hdev->rst_stats.rst_cnt; 2832 int ret; 2833 2834 ret = client->ops->init_instance(&hdev->nic); 2835 if (ret) 2836 return ret; 2837 2838 set_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 2839 if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) || 2840 rst_cnt != hdev->rst_stats.rst_cnt) { 2841 clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 2842 2843 client->ops->uninit_instance(&hdev->nic, 0); 2844 return -EBUSY; 2845 } 2846 2847 hnae3_set_client_init_flag(client, ae_dev, 1); 2848 2849 if (netif_msg_drv(&hdev->nic)) 2850 hclgevf_info_show(hdev); 2851 2852 return 0; 2853 } 2854 2855 static int hclgevf_init_roce_client_instance(struct hnae3_ae_dev *ae_dev, 2856 struct hnae3_client *client) 2857 { 2858 struct hclgevf_dev *hdev = ae_dev->priv; 2859 int ret; 2860 2861 if (!hnae3_dev_roce_supported(hdev) || !hdev->roce_client || 2862 !hdev->nic_client) 2863 return 0; 2864 2865 ret = hclgevf_init_roce_base_info(hdev); 2866 if (ret) 2867 return ret; 2868 2869 ret = client->ops->init_instance(&hdev->roce); 2870 if (ret) 2871 return ret; 2872 2873 set_bit(HCLGEVF_STATE_ROCE_REGISTERED, &hdev->state); 2874 hnae3_set_client_init_flag(client, ae_dev, 1); 2875 2876 return 0; 2877 } 2878 2879 static int hclgevf_init_client_instance(struct hnae3_client *client, 2880 struct hnae3_ae_dev *ae_dev) 2881 { 2882 struct hclgevf_dev *hdev = ae_dev->priv; 2883 int ret; 2884 2885 switch (client->type) { 2886 case HNAE3_CLIENT_KNIC: 2887 hdev->nic_client = client; 2888 hdev->nic.client = client; 2889 2890 ret = hclgevf_init_nic_client_instance(ae_dev, client); 2891 if (ret) 2892 goto clear_nic; 2893 2894 ret = hclgevf_init_roce_client_instance(ae_dev, 2895 hdev->roce_client); 2896 if (ret) 2897 goto clear_roce; 2898 2899 break; 2900 case HNAE3_CLIENT_ROCE: 2901 if (hnae3_dev_roce_supported(hdev)) { 2902 hdev->roce_client = client; 2903 hdev->roce.client = client; 2904 } 2905 2906 ret = hclgevf_init_roce_client_instance(ae_dev, client); 2907 if (ret) 2908 goto clear_roce; 2909 2910 break; 2911 default: 2912 return -EINVAL; 2913 } 2914 2915 return 0; 2916 2917 clear_nic: 2918 hdev->nic_client = NULL; 2919 hdev->nic.client = NULL; 2920 return ret; 2921 clear_roce: 2922 hdev->roce_client = NULL; 2923 hdev->roce.client = NULL; 2924 return ret; 2925 } 2926 2927 static void hclgevf_uninit_client_instance(struct hnae3_client *client, 2928 struct hnae3_ae_dev *ae_dev) 2929 { 2930 struct hclgevf_dev *hdev = ae_dev->priv; 2931 2932 /* un-init roce, if it exists */ 2933 if (hdev->roce_client) { 2934 clear_bit(HCLGEVF_STATE_ROCE_REGISTERED, &hdev->state); 2935 hdev->roce_client->ops->uninit_instance(&hdev->roce, 0); 2936 hdev->roce_client = NULL; 2937 hdev->roce.client = NULL; 2938 } 2939 2940 /* un-init nic/unic, if this was not called by roce client */ 2941 if (client->ops->uninit_instance && hdev->nic_client && 2942 client->type != HNAE3_CLIENT_ROCE) { 2943 clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 2944 2945 client->ops->uninit_instance(&hdev->nic, 0); 2946 hdev->nic_client = NULL; 2947 hdev->nic.client = NULL; 2948 } 2949 } 2950 2951 static int hclgevf_dev_mem_map(struct hclgevf_dev *hdev) 2952 { 2953 #define HCLGEVF_MEM_BAR 4 2954 2955 struct pci_dev *pdev = hdev->pdev; 2956 struct hclgevf_hw *hw = &hdev->hw; 2957 2958 /* for device does not have device memory, return directly */ 2959 if (!(pci_select_bars(pdev, IORESOURCE_MEM) & BIT(HCLGEVF_MEM_BAR))) 2960 return 0; 2961 2962 hw->mem_base = devm_ioremap_wc(&pdev->dev, 2963 pci_resource_start(pdev, 2964 HCLGEVF_MEM_BAR), 2965 pci_resource_len(pdev, HCLGEVF_MEM_BAR)); 2966 if (!hw->mem_base) { 2967 dev_err(&pdev->dev, "failed to map device memory\n"); 2968 return -EFAULT; 2969 } 2970 2971 return 0; 2972 } 2973 2974 static int hclgevf_pci_init(struct hclgevf_dev *hdev) 2975 { 2976 struct pci_dev *pdev = hdev->pdev; 2977 struct hclgevf_hw *hw; 2978 int ret; 2979 2980 ret = pci_enable_device(pdev); 2981 if (ret) { 2982 dev_err(&pdev->dev, "failed to enable PCI device\n"); 2983 return ret; 2984 } 2985 2986 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 2987 if (ret) { 2988 dev_err(&pdev->dev, "can't set consistent PCI DMA, exiting"); 2989 goto err_disable_device; 2990 } 2991 2992 ret = pci_request_regions(pdev, HCLGEVF_DRIVER_NAME); 2993 if (ret) { 2994 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 2995 goto err_disable_device; 2996 } 2997 2998 pci_set_master(pdev); 2999 hw = &hdev->hw; 3000 hw->hdev = hdev; 3001 hw->io_base = pci_iomap(pdev, 2, 0); 3002 if (!hw->io_base) { 3003 dev_err(&pdev->dev, "can't map configuration register space\n"); 3004 ret = -ENOMEM; 3005 goto err_clr_master; 3006 } 3007 3008 ret = hclgevf_dev_mem_map(hdev); 3009 if (ret) 3010 goto err_unmap_io_base; 3011 3012 return 0; 3013 3014 err_unmap_io_base: 3015 pci_iounmap(pdev, hdev->hw.io_base); 3016 err_clr_master: 3017 pci_clear_master(pdev); 3018 pci_release_regions(pdev); 3019 err_disable_device: 3020 pci_disable_device(pdev); 3021 3022 return ret; 3023 } 3024 3025 static void hclgevf_pci_uninit(struct hclgevf_dev *hdev) 3026 { 3027 struct pci_dev *pdev = hdev->pdev; 3028 3029 if (hdev->hw.mem_base) 3030 devm_iounmap(&pdev->dev, hdev->hw.mem_base); 3031 3032 pci_iounmap(pdev, hdev->hw.io_base); 3033 pci_clear_master(pdev); 3034 pci_release_regions(pdev); 3035 pci_disable_device(pdev); 3036 } 3037 3038 static int hclgevf_query_vf_resource(struct hclgevf_dev *hdev) 3039 { 3040 struct hclgevf_query_res_cmd *req; 3041 struct hclgevf_desc desc; 3042 int ret; 3043 3044 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_VF_RSRC, true); 3045 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 3046 if (ret) { 3047 dev_err(&hdev->pdev->dev, 3048 "query vf resource failed, ret = %d.\n", ret); 3049 return ret; 3050 } 3051 3052 req = (struct hclgevf_query_res_cmd *)desc.data; 3053 3054 if (hnae3_dev_roce_supported(hdev)) { 3055 hdev->roce_base_msix_offset = 3056 hnae3_get_field(le16_to_cpu(req->msixcap_localid_ba_rocee), 3057 HCLGEVF_MSIX_OFT_ROCEE_M, 3058 HCLGEVF_MSIX_OFT_ROCEE_S); 3059 hdev->num_roce_msix = 3060 hnae3_get_field(le16_to_cpu(req->vf_intr_vector_number), 3061 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 3062 3063 /* nic's msix numbers is always equals to the roce's. */ 3064 hdev->num_nic_msix = hdev->num_roce_msix; 3065 3066 /* VF should have NIC vectors and Roce vectors, NIC vectors 3067 * are queued before Roce vectors. The offset is fixed to 64. 3068 */ 3069 hdev->num_msi = hdev->num_roce_msix + 3070 hdev->roce_base_msix_offset; 3071 } else { 3072 hdev->num_msi = 3073 hnae3_get_field(le16_to_cpu(req->vf_intr_vector_number), 3074 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 3075 3076 hdev->num_nic_msix = hdev->num_msi; 3077 } 3078 3079 if (hdev->num_nic_msix < HNAE3_MIN_VECTOR_NUM) { 3080 dev_err(&hdev->pdev->dev, 3081 "Just %u msi resources, not enough for vf(min:2).\n", 3082 hdev->num_nic_msix); 3083 return -EINVAL; 3084 } 3085 3086 return 0; 3087 } 3088 3089 static void hclgevf_set_default_dev_specs(struct hclgevf_dev *hdev) 3090 { 3091 #define HCLGEVF_MAX_NON_TSO_BD_NUM 8U 3092 3093 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 3094 3095 ae_dev->dev_specs.max_non_tso_bd_num = 3096 HCLGEVF_MAX_NON_TSO_BD_NUM; 3097 ae_dev->dev_specs.rss_ind_tbl_size = HCLGEVF_RSS_IND_TBL_SIZE; 3098 ae_dev->dev_specs.rss_key_size = HCLGEVF_RSS_KEY_SIZE; 3099 ae_dev->dev_specs.max_int_gl = HCLGEVF_DEF_MAX_INT_GL; 3100 ae_dev->dev_specs.max_frm_size = HCLGEVF_MAC_MAX_FRAME; 3101 } 3102 3103 static void hclgevf_parse_dev_specs(struct hclgevf_dev *hdev, 3104 struct hclgevf_desc *desc) 3105 { 3106 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 3107 struct hclgevf_dev_specs_0_cmd *req0; 3108 struct hclgevf_dev_specs_1_cmd *req1; 3109 3110 req0 = (struct hclgevf_dev_specs_0_cmd *)desc[0].data; 3111 req1 = (struct hclgevf_dev_specs_1_cmd *)desc[1].data; 3112 3113 ae_dev->dev_specs.max_non_tso_bd_num = req0->max_non_tso_bd_num; 3114 ae_dev->dev_specs.rss_ind_tbl_size = 3115 le16_to_cpu(req0->rss_ind_tbl_size); 3116 ae_dev->dev_specs.int_ql_max = le16_to_cpu(req0->int_ql_max); 3117 ae_dev->dev_specs.rss_key_size = le16_to_cpu(req0->rss_key_size); 3118 ae_dev->dev_specs.max_int_gl = le16_to_cpu(req1->max_int_gl); 3119 ae_dev->dev_specs.max_frm_size = le16_to_cpu(req1->max_frm_size); 3120 } 3121 3122 static void hclgevf_check_dev_specs(struct hclgevf_dev *hdev) 3123 { 3124 struct hnae3_dev_specs *dev_specs = &hdev->ae_dev->dev_specs; 3125 3126 if (!dev_specs->max_non_tso_bd_num) 3127 dev_specs->max_non_tso_bd_num = HCLGEVF_MAX_NON_TSO_BD_NUM; 3128 if (!dev_specs->rss_ind_tbl_size) 3129 dev_specs->rss_ind_tbl_size = HCLGEVF_RSS_IND_TBL_SIZE; 3130 if (!dev_specs->rss_key_size) 3131 dev_specs->rss_key_size = HCLGEVF_RSS_KEY_SIZE; 3132 if (!dev_specs->max_int_gl) 3133 dev_specs->max_int_gl = HCLGEVF_DEF_MAX_INT_GL; 3134 if (!dev_specs->max_frm_size) 3135 dev_specs->max_frm_size = HCLGEVF_MAC_MAX_FRAME; 3136 } 3137 3138 static int hclgevf_query_dev_specs(struct hclgevf_dev *hdev) 3139 { 3140 struct hclgevf_desc desc[HCLGEVF_QUERY_DEV_SPECS_BD_NUM]; 3141 int ret; 3142 int i; 3143 3144 /* set default specifications as devices lower than version V3 do not 3145 * support querying specifications from firmware. 3146 */ 3147 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3) { 3148 hclgevf_set_default_dev_specs(hdev); 3149 return 0; 3150 } 3151 3152 for (i = 0; i < HCLGEVF_QUERY_DEV_SPECS_BD_NUM - 1; i++) { 3153 hclgevf_cmd_setup_basic_desc(&desc[i], 3154 HCLGEVF_OPC_QUERY_DEV_SPECS, true); 3155 desc[i].flag |= cpu_to_le16(HCLGEVF_CMD_FLAG_NEXT); 3156 } 3157 hclgevf_cmd_setup_basic_desc(&desc[i], HCLGEVF_OPC_QUERY_DEV_SPECS, 3158 true); 3159 3160 ret = hclgevf_cmd_send(&hdev->hw, desc, HCLGEVF_QUERY_DEV_SPECS_BD_NUM); 3161 if (ret) 3162 return ret; 3163 3164 hclgevf_parse_dev_specs(hdev, desc); 3165 hclgevf_check_dev_specs(hdev); 3166 3167 return 0; 3168 } 3169 3170 static int hclgevf_pci_reset(struct hclgevf_dev *hdev) 3171 { 3172 struct pci_dev *pdev = hdev->pdev; 3173 int ret = 0; 3174 3175 if (hdev->reset_type == HNAE3_VF_FULL_RESET && 3176 test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 3177 hclgevf_misc_irq_uninit(hdev); 3178 hclgevf_uninit_msi(hdev); 3179 clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 3180 } 3181 3182 if (!test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 3183 pci_set_master(pdev); 3184 ret = hclgevf_init_msi(hdev); 3185 if (ret) { 3186 dev_err(&pdev->dev, 3187 "failed(%d) to init MSI/MSI-X\n", ret); 3188 return ret; 3189 } 3190 3191 ret = hclgevf_misc_irq_init(hdev); 3192 if (ret) { 3193 hclgevf_uninit_msi(hdev); 3194 dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 3195 ret); 3196 return ret; 3197 } 3198 3199 set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 3200 } 3201 3202 return ret; 3203 } 3204 3205 static int hclgevf_clear_vport_list(struct hclgevf_dev *hdev) 3206 { 3207 struct hclge_vf_to_pf_msg send_msg; 3208 3209 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_HANDLE_VF_TBL, 3210 HCLGE_MBX_VPORT_LIST_CLEAR); 3211 return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 3212 } 3213 3214 static int hclgevf_reset_hdev(struct hclgevf_dev *hdev) 3215 { 3216 struct pci_dev *pdev = hdev->pdev; 3217 int ret; 3218 3219 ret = hclgevf_pci_reset(hdev); 3220 if (ret) { 3221 dev_err(&pdev->dev, "pci reset failed %d\n", ret); 3222 return ret; 3223 } 3224 3225 ret = hclgevf_cmd_init(hdev); 3226 if (ret) { 3227 dev_err(&pdev->dev, "cmd failed %d\n", ret); 3228 return ret; 3229 } 3230 3231 ret = hclgevf_rss_init_hw(hdev); 3232 if (ret) { 3233 dev_err(&hdev->pdev->dev, 3234 "failed(%d) to initialize RSS\n", ret); 3235 return ret; 3236 } 3237 3238 ret = hclgevf_config_gro(hdev, true); 3239 if (ret) 3240 return ret; 3241 3242 ret = hclgevf_init_vlan_config(hdev); 3243 if (ret) { 3244 dev_err(&hdev->pdev->dev, 3245 "failed(%d) to initialize VLAN config\n", ret); 3246 return ret; 3247 } 3248 3249 set_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state); 3250 3251 dev_info(&hdev->pdev->dev, "Reset done\n"); 3252 3253 return 0; 3254 } 3255 3256 static int hclgevf_init_hdev(struct hclgevf_dev *hdev) 3257 { 3258 struct pci_dev *pdev = hdev->pdev; 3259 int ret; 3260 3261 ret = hclgevf_pci_init(hdev); 3262 if (ret) 3263 return ret; 3264 3265 ret = hclgevf_cmd_queue_init(hdev); 3266 if (ret) 3267 goto err_cmd_queue_init; 3268 3269 ret = hclgevf_cmd_init(hdev); 3270 if (ret) 3271 goto err_cmd_init; 3272 3273 /* Get vf resource */ 3274 ret = hclgevf_query_vf_resource(hdev); 3275 if (ret) 3276 goto err_cmd_init; 3277 3278 ret = hclgevf_query_dev_specs(hdev); 3279 if (ret) { 3280 dev_err(&pdev->dev, 3281 "failed to query dev specifications, ret = %d\n", ret); 3282 goto err_cmd_init; 3283 } 3284 3285 ret = hclgevf_init_msi(hdev); 3286 if (ret) { 3287 dev_err(&pdev->dev, "failed(%d) to init MSI/MSI-X\n", ret); 3288 goto err_cmd_init; 3289 } 3290 3291 hclgevf_state_init(hdev); 3292 hdev->reset_level = HNAE3_VF_FUNC_RESET; 3293 hdev->reset_type = HNAE3_NONE_RESET; 3294 3295 ret = hclgevf_misc_irq_init(hdev); 3296 if (ret) 3297 goto err_misc_irq_init; 3298 3299 set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 3300 3301 ret = hclgevf_configure(hdev); 3302 if (ret) { 3303 dev_err(&pdev->dev, "failed(%d) to fetch configuration\n", ret); 3304 goto err_config; 3305 } 3306 3307 ret = hclgevf_alloc_tqps(hdev); 3308 if (ret) { 3309 dev_err(&pdev->dev, "failed(%d) to allocate TQPs\n", ret); 3310 goto err_config; 3311 } 3312 3313 ret = hclgevf_set_handle_info(hdev); 3314 if (ret) 3315 goto err_config; 3316 3317 ret = hclgevf_config_gro(hdev, true); 3318 if (ret) 3319 goto err_config; 3320 3321 /* Initialize RSS for this VF */ 3322 ret = hclgevf_rss_init_cfg(hdev); 3323 if (ret) { 3324 dev_err(&pdev->dev, "failed to init rss cfg, ret = %d\n", ret); 3325 goto err_config; 3326 } 3327 3328 ret = hclgevf_rss_init_hw(hdev); 3329 if (ret) { 3330 dev_err(&hdev->pdev->dev, 3331 "failed(%d) to initialize RSS\n", ret); 3332 goto err_config; 3333 } 3334 3335 /* ensure vf tbl list as empty before init*/ 3336 ret = hclgevf_clear_vport_list(hdev); 3337 if (ret) { 3338 dev_err(&pdev->dev, 3339 "failed to clear tbl list configuration, ret = %d.\n", 3340 ret); 3341 goto err_config; 3342 } 3343 3344 ret = hclgevf_init_vlan_config(hdev); 3345 if (ret) { 3346 dev_err(&hdev->pdev->dev, 3347 "failed(%d) to initialize VLAN config\n", ret); 3348 goto err_config; 3349 } 3350 3351 hdev->last_reset_time = jiffies; 3352 dev_info(&hdev->pdev->dev, "finished initializing %s driver\n", 3353 HCLGEVF_DRIVER_NAME); 3354 3355 hclgevf_task_schedule(hdev, round_jiffies_relative(HZ)); 3356 3357 return 0; 3358 3359 err_config: 3360 hclgevf_misc_irq_uninit(hdev); 3361 err_misc_irq_init: 3362 hclgevf_state_uninit(hdev); 3363 hclgevf_uninit_msi(hdev); 3364 err_cmd_init: 3365 hclgevf_cmd_uninit(hdev); 3366 err_cmd_queue_init: 3367 hclgevf_pci_uninit(hdev); 3368 clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 3369 return ret; 3370 } 3371 3372 static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev) 3373 { 3374 struct hclge_vf_to_pf_msg send_msg; 3375 3376 hclgevf_state_uninit(hdev); 3377 3378 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_VF_UNINIT, 0); 3379 hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 3380 3381 if (test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 3382 hclgevf_misc_irq_uninit(hdev); 3383 hclgevf_uninit_msi(hdev); 3384 } 3385 3386 hclgevf_cmd_uninit(hdev); 3387 hclgevf_pci_uninit(hdev); 3388 hclgevf_uninit_mac_list(hdev); 3389 } 3390 3391 static int hclgevf_init_ae_dev(struct hnae3_ae_dev *ae_dev) 3392 { 3393 struct pci_dev *pdev = ae_dev->pdev; 3394 int ret; 3395 3396 ret = hclgevf_alloc_hdev(ae_dev); 3397 if (ret) { 3398 dev_err(&pdev->dev, "hclge device allocation failed\n"); 3399 return ret; 3400 } 3401 3402 ret = hclgevf_init_hdev(ae_dev->priv); 3403 if (ret) { 3404 dev_err(&pdev->dev, "hclge device initialization failed\n"); 3405 return ret; 3406 } 3407 3408 return 0; 3409 } 3410 3411 static void hclgevf_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 3412 { 3413 struct hclgevf_dev *hdev = ae_dev->priv; 3414 3415 hclgevf_uninit_hdev(hdev); 3416 ae_dev->priv = NULL; 3417 } 3418 3419 static u32 hclgevf_get_max_channels(struct hclgevf_dev *hdev) 3420 { 3421 struct hnae3_handle *nic = &hdev->nic; 3422 struct hnae3_knic_private_info *kinfo = &nic->kinfo; 3423 3424 return min_t(u32, hdev->rss_size_max, 3425 hdev->num_tqps / kinfo->tc_info.num_tc); 3426 } 3427 3428 /** 3429 * hclgevf_get_channels - Get the current channels enabled and max supported. 3430 * @handle: hardware information for network interface 3431 * @ch: ethtool channels structure 3432 * 3433 * We don't support separate tx and rx queues as channels. The other count 3434 * represents how many queues are being used for control. max_combined counts 3435 * how many queue pairs we can support. They may not be mapped 1 to 1 with 3436 * q_vectors since we support a lot more queue pairs than q_vectors. 3437 **/ 3438 static void hclgevf_get_channels(struct hnae3_handle *handle, 3439 struct ethtool_channels *ch) 3440 { 3441 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3442 3443 ch->max_combined = hclgevf_get_max_channels(hdev); 3444 ch->other_count = 0; 3445 ch->max_other = 0; 3446 ch->combined_count = handle->kinfo.rss_size; 3447 } 3448 3449 static void hclgevf_get_tqps_and_rss_info(struct hnae3_handle *handle, 3450 u16 *alloc_tqps, u16 *max_rss_size) 3451 { 3452 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3453 3454 *alloc_tqps = hdev->num_tqps; 3455 *max_rss_size = hdev->rss_size_max; 3456 } 3457 3458 static void hclgevf_update_rss_size(struct hnae3_handle *handle, 3459 u32 new_tqps_num) 3460 { 3461 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 3462 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3463 u16 max_rss_size; 3464 3465 kinfo->req_rss_size = new_tqps_num; 3466 3467 max_rss_size = min_t(u16, hdev->rss_size_max, 3468 hdev->num_tqps / kinfo->tc_info.num_tc); 3469 3470 /* Use the user's configuration when it is not larger than 3471 * max_rss_size, otherwise, use the maximum specification value. 3472 */ 3473 if (kinfo->req_rss_size != kinfo->rss_size && kinfo->req_rss_size && 3474 kinfo->req_rss_size <= max_rss_size) 3475 kinfo->rss_size = kinfo->req_rss_size; 3476 else if (kinfo->rss_size > max_rss_size || 3477 (!kinfo->req_rss_size && kinfo->rss_size < max_rss_size)) 3478 kinfo->rss_size = max_rss_size; 3479 3480 kinfo->num_tqps = kinfo->tc_info.num_tc * kinfo->rss_size; 3481 } 3482 3483 static int hclgevf_set_channels(struct hnae3_handle *handle, u32 new_tqps_num, 3484 bool rxfh_configured) 3485 { 3486 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3487 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 3488 u16 cur_rss_size = kinfo->rss_size; 3489 u16 cur_tqps = kinfo->num_tqps; 3490 u32 *rss_indir; 3491 unsigned int i; 3492 int ret; 3493 3494 hclgevf_update_rss_size(handle, new_tqps_num); 3495 3496 ret = hclgevf_set_rss_tc_mode(hdev, kinfo->rss_size); 3497 if (ret) 3498 return ret; 3499 3500 /* RSS indirection table has been configuared by user */ 3501 if (rxfh_configured) 3502 goto out; 3503 3504 /* Reinitializes the rss indirect table according to the new RSS size */ 3505 rss_indir = kcalloc(hdev->ae_dev->dev_specs.rss_ind_tbl_size, 3506 sizeof(u32), GFP_KERNEL); 3507 if (!rss_indir) 3508 return -ENOMEM; 3509 3510 for (i = 0; i < hdev->ae_dev->dev_specs.rss_ind_tbl_size; i++) 3511 rss_indir[i] = i % kinfo->rss_size; 3512 3513 hdev->rss_cfg.rss_size = kinfo->rss_size; 3514 3515 ret = hclgevf_set_rss(handle, rss_indir, NULL, 0); 3516 if (ret) 3517 dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n", 3518 ret); 3519 3520 kfree(rss_indir); 3521 3522 out: 3523 if (!ret) 3524 dev_info(&hdev->pdev->dev, 3525 "Channels changed, rss_size from %u to %u, tqps from %u to %u", 3526 cur_rss_size, kinfo->rss_size, 3527 cur_tqps, kinfo->rss_size * kinfo->tc_info.num_tc); 3528 3529 return ret; 3530 } 3531 3532 static int hclgevf_get_status(struct hnae3_handle *handle) 3533 { 3534 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3535 3536 return hdev->hw.mac.link; 3537 } 3538 3539 static void hclgevf_get_ksettings_an_result(struct hnae3_handle *handle, 3540 u8 *auto_neg, u32 *speed, 3541 u8 *duplex) 3542 { 3543 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3544 3545 if (speed) 3546 *speed = hdev->hw.mac.speed; 3547 if (duplex) 3548 *duplex = hdev->hw.mac.duplex; 3549 if (auto_neg) 3550 *auto_neg = AUTONEG_DISABLE; 3551 } 3552 3553 void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed, 3554 u8 duplex) 3555 { 3556 hdev->hw.mac.speed = speed; 3557 hdev->hw.mac.duplex = duplex; 3558 } 3559 3560 static int hclgevf_gro_en(struct hnae3_handle *handle, bool enable) 3561 { 3562 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3563 3564 return hclgevf_config_gro(hdev, enable); 3565 } 3566 3567 static void hclgevf_get_media_type(struct hnae3_handle *handle, u8 *media_type, 3568 u8 *module_type) 3569 { 3570 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3571 3572 if (media_type) 3573 *media_type = hdev->hw.mac.media_type; 3574 3575 if (module_type) 3576 *module_type = hdev->hw.mac.module_type; 3577 } 3578 3579 static bool hclgevf_get_hw_reset_stat(struct hnae3_handle *handle) 3580 { 3581 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3582 3583 return !!hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 3584 } 3585 3586 static bool hclgevf_get_cmdq_stat(struct hnae3_handle *handle) 3587 { 3588 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3589 3590 return test_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 3591 } 3592 3593 static bool hclgevf_ae_dev_resetting(struct hnae3_handle *handle) 3594 { 3595 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3596 3597 return test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 3598 } 3599 3600 static unsigned long hclgevf_ae_dev_reset_cnt(struct hnae3_handle *handle) 3601 { 3602 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3603 3604 return hdev->rst_stats.hw_rst_done_cnt; 3605 } 3606 3607 static void hclgevf_get_link_mode(struct hnae3_handle *handle, 3608 unsigned long *supported, 3609 unsigned long *advertising) 3610 { 3611 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3612 3613 *supported = hdev->hw.mac.supported; 3614 *advertising = hdev->hw.mac.advertising; 3615 } 3616 3617 #define MAX_SEPARATE_NUM 4 3618 #define SEPARATOR_VALUE 0xFFFFFFFF 3619 #define REG_NUM_PER_LINE 4 3620 #define REG_LEN_PER_LINE (REG_NUM_PER_LINE * sizeof(u32)) 3621 3622 static int hclgevf_get_regs_len(struct hnae3_handle *handle) 3623 { 3624 int cmdq_lines, common_lines, ring_lines, tqp_intr_lines; 3625 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3626 3627 cmdq_lines = sizeof(cmdq_reg_addr_list) / REG_LEN_PER_LINE + 1; 3628 common_lines = sizeof(common_reg_addr_list) / REG_LEN_PER_LINE + 1; 3629 ring_lines = sizeof(ring_reg_addr_list) / REG_LEN_PER_LINE + 1; 3630 tqp_intr_lines = sizeof(tqp_intr_reg_addr_list) / REG_LEN_PER_LINE + 1; 3631 3632 return (cmdq_lines + common_lines + ring_lines * hdev->num_tqps + 3633 tqp_intr_lines * (hdev->num_msi_used - 1)) * REG_LEN_PER_LINE; 3634 } 3635 3636 static void hclgevf_get_regs(struct hnae3_handle *handle, u32 *version, 3637 void *data) 3638 { 3639 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3640 int i, j, reg_um, separator_num; 3641 u32 *reg = data; 3642 3643 *version = hdev->fw_version; 3644 3645 /* fetching per-VF registers values from VF PCIe register space */ 3646 reg_um = sizeof(cmdq_reg_addr_list) / sizeof(u32); 3647 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 3648 for (i = 0; i < reg_um; i++) 3649 *reg++ = hclgevf_read_dev(&hdev->hw, cmdq_reg_addr_list[i]); 3650 for (i = 0; i < separator_num; i++) 3651 *reg++ = SEPARATOR_VALUE; 3652 3653 reg_um = sizeof(common_reg_addr_list) / sizeof(u32); 3654 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 3655 for (i = 0; i < reg_um; i++) 3656 *reg++ = hclgevf_read_dev(&hdev->hw, common_reg_addr_list[i]); 3657 for (i = 0; i < separator_num; i++) 3658 *reg++ = SEPARATOR_VALUE; 3659 3660 reg_um = sizeof(ring_reg_addr_list) / sizeof(u32); 3661 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 3662 for (j = 0; j < hdev->num_tqps; j++) { 3663 for (i = 0; i < reg_um; i++) 3664 *reg++ = hclgevf_read_dev(&hdev->hw, 3665 ring_reg_addr_list[i] + 3666 0x200 * j); 3667 for (i = 0; i < separator_num; i++) 3668 *reg++ = SEPARATOR_VALUE; 3669 } 3670 3671 reg_um = sizeof(tqp_intr_reg_addr_list) / sizeof(u32); 3672 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 3673 for (j = 0; j < hdev->num_msi_used - 1; j++) { 3674 for (i = 0; i < reg_um; i++) 3675 *reg++ = hclgevf_read_dev(&hdev->hw, 3676 tqp_intr_reg_addr_list[i] + 3677 4 * j); 3678 for (i = 0; i < separator_num; i++) 3679 *reg++ = SEPARATOR_VALUE; 3680 } 3681 } 3682 3683 void hclgevf_update_port_base_vlan_info(struct hclgevf_dev *hdev, u16 state, 3684 u8 *port_base_vlan_info, u8 data_size) 3685 { 3686 struct hnae3_handle *nic = &hdev->nic; 3687 struct hclge_vf_to_pf_msg send_msg; 3688 int ret; 3689 3690 rtnl_lock(); 3691 3692 if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) || 3693 test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) { 3694 dev_warn(&hdev->pdev->dev, 3695 "is resetting when updating port based vlan info\n"); 3696 rtnl_unlock(); 3697 return; 3698 } 3699 3700 ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 3701 if (ret) { 3702 rtnl_unlock(); 3703 return; 3704 } 3705 3706 /* send msg to PF and wait update port based vlan info */ 3707 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 3708 HCLGE_MBX_PORT_BASE_VLAN_CFG); 3709 memcpy(send_msg.data, port_base_vlan_info, data_size); 3710 ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 3711 if (!ret) { 3712 if (state == HNAE3_PORT_BASE_VLAN_DISABLE) 3713 nic->port_base_vlan_state = state; 3714 else 3715 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_ENABLE; 3716 } 3717 3718 hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 3719 rtnl_unlock(); 3720 } 3721 3722 static const struct hnae3_ae_ops hclgevf_ops = { 3723 .init_ae_dev = hclgevf_init_ae_dev, 3724 .uninit_ae_dev = hclgevf_uninit_ae_dev, 3725 .flr_prepare = hclgevf_flr_prepare, 3726 .flr_done = hclgevf_flr_done, 3727 .init_client_instance = hclgevf_init_client_instance, 3728 .uninit_client_instance = hclgevf_uninit_client_instance, 3729 .start = hclgevf_ae_start, 3730 .stop = hclgevf_ae_stop, 3731 .client_start = hclgevf_client_start, 3732 .client_stop = hclgevf_client_stop, 3733 .map_ring_to_vector = hclgevf_map_ring_to_vector, 3734 .unmap_ring_from_vector = hclgevf_unmap_ring_from_vector, 3735 .get_vector = hclgevf_get_vector, 3736 .put_vector = hclgevf_put_vector, 3737 .reset_queue = hclgevf_reset_tqp, 3738 .get_mac_addr = hclgevf_get_mac_addr, 3739 .set_mac_addr = hclgevf_set_mac_addr, 3740 .add_uc_addr = hclgevf_add_uc_addr, 3741 .rm_uc_addr = hclgevf_rm_uc_addr, 3742 .add_mc_addr = hclgevf_add_mc_addr, 3743 .rm_mc_addr = hclgevf_rm_mc_addr, 3744 .get_stats = hclgevf_get_stats, 3745 .update_stats = hclgevf_update_stats, 3746 .get_strings = hclgevf_get_strings, 3747 .get_sset_count = hclgevf_get_sset_count, 3748 .get_rss_key_size = hclgevf_get_rss_key_size, 3749 .get_rss = hclgevf_get_rss, 3750 .set_rss = hclgevf_set_rss, 3751 .get_rss_tuple = hclgevf_get_rss_tuple, 3752 .set_rss_tuple = hclgevf_set_rss_tuple, 3753 .get_tc_size = hclgevf_get_tc_size, 3754 .get_fw_version = hclgevf_get_fw_version, 3755 .set_vlan_filter = hclgevf_set_vlan_filter, 3756 .enable_hw_strip_rxvtag = hclgevf_en_hw_strip_rxvtag, 3757 .reset_event = hclgevf_reset_event, 3758 .set_default_reset_request = hclgevf_set_def_reset_request, 3759 .set_channels = hclgevf_set_channels, 3760 .get_channels = hclgevf_get_channels, 3761 .get_tqps_and_rss_info = hclgevf_get_tqps_and_rss_info, 3762 .get_regs_len = hclgevf_get_regs_len, 3763 .get_regs = hclgevf_get_regs, 3764 .get_status = hclgevf_get_status, 3765 .get_ksettings_an_result = hclgevf_get_ksettings_an_result, 3766 .get_media_type = hclgevf_get_media_type, 3767 .get_hw_reset_stat = hclgevf_get_hw_reset_stat, 3768 .ae_dev_resetting = hclgevf_ae_dev_resetting, 3769 .ae_dev_reset_cnt = hclgevf_ae_dev_reset_cnt, 3770 .set_gro_en = hclgevf_gro_en, 3771 .set_mtu = hclgevf_set_mtu, 3772 .get_global_queue_id = hclgevf_get_qid_global, 3773 .set_timer_task = hclgevf_set_timer_task, 3774 .get_link_mode = hclgevf_get_link_mode, 3775 .set_promisc_mode = hclgevf_set_promisc_mode, 3776 .request_update_promisc_mode = hclgevf_request_update_promisc_mode, 3777 .get_cmdq_stat = hclgevf_get_cmdq_stat, 3778 }; 3779 3780 static struct hnae3_ae_algo ae_algovf = { 3781 .ops = &hclgevf_ops, 3782 .pdev_id_table = ae_algovf_pci_tbl, 3783 }; 3784 3785 static int hclgevf_init(void) 3786 { 3787 pr_info("%s is initializing\n", HCLGEVF_NAME); 3788 3789 hclgevf_wq = alloc_workqueue("%s", 0, 0, HCLGEVF_NAME); 3790 if (!hclgevf_wq) { 3791 pr_err("%s: failed to create workqueue\n", HCLGEVF_NAME); 3792 return -ENOMEM; 3793 } 3794 3795 hnae3_register_ae_algo(&ae_algovf); 3796 3797 return 0; 3798 } 3799 3800 static void hclgevf_exit(void) 3801 { 3802 hnae3_unregister_ae_algo(&ae_algovf); 3803 destroy_workqueue(hclgevf_wq); 3804 } 3805 module_init(hclgevf_init); 3806 module_exit(hclgevf_exit); 3807 3808 MODULE_LICENSE("GPL"); 3809 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 3810 MODULE_DESCRIPTION("HCLGEVF Driver"); 3811 MODULE_VERSION(HCLGEVF_MOD_VERSION); 3812