1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/etherdevice.h> 5 #include <linux/iopoll.h> 6 #include <net/rtnetlink.h> 7 #include "hclgevf_cmd.h" 8 #include "hclgevf_main.h" 9 #include "hclge_mbx.h" 10 #include "hnae3.h" 11 12 #define HCLGEVF_NAME "hclgevf" 13 14 static int hclgevf_reset_hdev(struct hclgevf_dev *hdev); 15 static struct hnae3_ae_algo ae_algovf; 16 17 static const struct pci_device_id ae_algovf_pci_tbl[] = { 18 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0}, 19 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF), 0}, 20 /* required last entry */ 21 {0, } 22 }; 23 24 static const u8 hclgevf_hash_key[] = { 25 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2, 26 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0, 27 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4, 28 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C, 29 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA 30 }; 31 32 MODULE_DEVICE_TABLE(pci, ae_algovf_pci_tbl); 33 34 static const u32 cmdq_reg_addr_list[] = {HCLGEVF_CMDQ_TX_ADDR_L_REG, 35 HCLGEVF_CMDQ_TX_ADDR_H_REG, 36 HCLGEVF_CMDQ_TX_DEPTH_REG, 37 HCLGEVF_CMDQ_TX_TAIL_REG, 38 HCLGEVF_CMDQ_TX_HEAD_REG, 39 HCLGEVF_CMDQ_RX_ADDR_L_REG, 40 HCLGEVF_CMDQ_RX_ADDR_H_REG, 41 HCLGEVF_CMDQ_RX_DEPTH_REG, 42 HCLGEVF_CMDQ_RX_TAIL_REG, 43 HCLGEVF_CMDQ_RX_HEAD_REG, 44 HCLGEVF_VECTOR0_CMDQ_SRC_REG, 45 HCLGEVF_CMDQ_INTR_STS_REG, 46 HCLGEVF_CMDQ_INTR_EN_REG, 47 HCLGEVF_CMDQ_INTR_GEN_REG}; 48 49 static const u32 common_reg_addr_list[] = {HCLGEVF_MISC_VECTOR_REG_BASE, 50 HCLGEVF_RST_ING, 51 HCLGEVF_GRO_EN_REG}; 52 53 static const u32 ring_reg_addr_list[] = {HCLGEVF_RING_RX_ADDR_L_REG, 54 HCLGEVF_RING_RX_ADDR_H_REG, 55 HCLGEVF_RING_RX_BD_NUM_REG, 56 HCLGEVF_RING_RX_BD_LENGTH_REG, 57 HCLGEVF_RING_RX_MERGE_EN_REG, 58 HCLGEVF_RING_RX_TAIL_REG, 59 HCLGEVF_RING_RX_HEAD_REG, 60 HCLGEVF_RING_RX_FBD_NUM_REG, 61 HCLGEVF_RING_RX_OFFSET_REG, 62 HCLGEVF_RING_RX_FBD_OFFSET_REG, 63 HCLGEVF_RING_RX_STASH_REG, 64 HCLGEVF_RING_RX_BD_ERR_REG, 65 HCLGEVF_RING_TX_ADDR_L_REG, 66 HCLGEVF_RING_TX_ADDR_H_REG, 67 HCLGEVF_RING_TX_BD_NUM_REG, 68 HCLGEVF_RING_TX_PRIORITY_REG, 69 HCLGEVF_RING_TX_TC_REG, 70 HCLGEVF_RING_TX_MERGE_EN_REG, 71 HCLGEVF_RING_TX_TAIL_REG, 72 HCLGEVF_RING_TX_HEAD_REG, 73 HCLGEVF_RING_TX_FBD_NUM_REG, 74 HCLGEVF_RING_TX_OFFSET_REG, 75 HCLGEVF_RING_TX_EBD_NUM_REG, 76 HCLGEVF_RING_TX_EBD_OFFSET_REG, 77 HCLGEVF_RING_TX_BD_ERR_REG, 78 HCLGEVF_RING_EN_REG}; 79 80 static const u32 tqp_intr_reg_addr_list[] = {HCLGEVF_TQP_INTR_CTRL_REG, 81 HCLGEVF_TQP_INTR_GL0_REG, 82 HCLGEVF_TQP_INTR_GL1_REG, 83 HCLGEVF_TQP_INTR_GL2_REG, 84 HCLGEVF_TQP_INTR_RL_REG}; 85 86 static struct hclgevf_dev *hclgevf_ae_get_hdev(struct hnae3_handle *handle) 87 { 88 if (!handle->client) 89 return container_of(handle, struct hclgevf_dev, nic); 90 else if (handle->client->type == HNAE3_CLIENT_ROCE) 91 return container_of(handle, struct hclgevf_dev, roce); 92 else 93 return container_of(handle, struct hclgevf_dev, nic); 94 } 95 96 static int hclgevf_tqps_update_stats(struct hnae3_handle *handle) 97 { 98 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 99 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 100 struct hclgevf_desc desc; 101 struct hclgevf_tqp *tqp; 102 int status; 103 int i; 104 105 for (i = 0; i < kinfo->num_tqps; i++) { 106 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 107 hclgevf_cmd_setup_basic_desc(&desc, 108 HCLGEVF_OPC_QUERY_RX_STATUS, 109 true); 110 111 desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 112 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 113 if (status) { 114 dev_err(&hdev->pdev->dev, 115 "Query tqp stat fail, status = %d,queue = %d\n", 116 status, i); 117 return status; 118 } 119 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd += 120 le32_to_cpu(desc.data[1]); 121 122 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_TX_STATUS, 123 true); 124 125 desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 126 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 127 if (status) { 128 dev_err(&hdev->pdev->dev, 129 "Query tqp stat fail, status = %d,queue = %d\n", 130 status, i); 131 return status; 132 } 133 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd += 134 le32_to_cpu(desc.data[1]); 135 } 136 137 return 0; 138 } 139 140 static u64 *hclgevf_tqps_get_stats(struct hnae3_handle *handle, u64 *data) 141 { 142 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 143 struct hclgevf_tqp *tqp; 144 u64 *buff = data; 145 int i; 146 147 for (i = 0; i < kinfo->num_tqps; i++) { 148 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 149 *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd; 150 } 151 for (i = 0; i < kinfo->num_tqps; i++) { 152 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 153 *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd; 154 } 155 156 return buff; 157 } 158 159 static int hclgevf_tqps_get_sset_count(struct hnae3_handle *handle, int strset) 160 { 161 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 162 163 return kinfo->num_tqps * 2; 164 } 165 166 static u8 *hclgevf_tqps_get_strings(struct hnae3_handle *handle, u8 *data) 167 { 168 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 169 u8 *buff = data; 170 int i = 0; 171 172 for (i = 0; i < kinfo->num_tqps; i++) { 173 struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 174 struct hclgevf_tqp, q); 175 snprintf(buff, ETH_GSTRING_LEN, "txq%d_pktnum_rcd", 176 tqp->index); 177 buff += ETH_GSTRING_LEN; 178 } 179 180 for (i = 0; i < kinfo->num_tqps; i++) { 181 struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 182 struct hclgevf_tqp, q); 183 snprintf(buff, ETH_GSTRING_LEN, "rxq%d_pktnum_rcd", 184 tqp->index); 185 buff += ETH_GSTRING_LEN; 186 } 187 188 return buff; 189 } 190 191 static void hclgevf_update_stats(struct hnae3_handle *handle, 192 struct net_device_stats *net_stats) 193 { 194 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 195 int status; 196 197 status = hclgevf_tqps_update_stats(handle); 198 if (status) 199 dev_err(&hdev->pdev->dev, 200 "VF update of TQPS stats fail, status = %d.\n", 201 status); 202 } 203 204 static int hclgevf_get_sset_count(struct hnae3_handle *handle, int strset) 205 { 206 if (strset == ETH_SS_TEST) 207 return -EOPNOTSUPP; 208 else if (strset == ETH_SS_STATS) 209 return hclgevf_tqps_get_sset_count(handle, strset); 210 211 return 0; 212 } 213 214 static void hclgevf_get_strings(struct hnae3_handle *handle, u32 strset, 215 u8 *data) 216 { 217 u8 *p = (char *)data; 218 219 if (strset == ETH_SS_STATS) 220 p = hclgevf_tqps_get_strings(handle, p); 221 } 222 223 static void hclgevf_get_stats(struct hnae3_handle *handle, u64 *data) 224 { 225 hclgevf_tqps_get_stats(handle, data); 226 } 227 228 static int hclgevf_get_tc_info(struct hclgevf_dev *hdev) 229 { 230 u8 resp_msg; 231 int status; 232 233 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_TCINFO, 0, NULL, 0, 234 true, &resp_msg, sizeof(resp_msg)); 235 if (status) { 236 dev_err(&hdev->pdev->dev, 237 "VF request to get TC info from PF failed %d", 238 status); 239 return status; 240 } 241 242 hdev->hw_tc_map = resp_msg; 243 244 return 0; 245 } 246 247 static int hclgevf_get_port_base_vlan_filter_state(struct hclgevf_dev *hdev) 248 { 249 struct hnae3_handle *nic = &hdev->nic; 250 u8 resp_msg; 251 int ret; 252 253 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 254 HCLGE_MBX_GET_PORT_BASE_VLAN_STATE, 255 NULL, 0, true, &resp_msg, sizeof(u8)); 256 if (ret) { 257 dev_err(&hdev->pdev->dev, 258 "VF request to get port based vlan state failed %d", 259 ret); 260 return ret; 261 } 262 263 nic->port_base_vlan_state = resp_msg; 264 265 return 0; 266 } 267 268 static int hclgevf_get_queue_info(struct hclgevf_dev *hdev) 269 { 270 #define HCLGEVF_TQPS_RSS_INFO_LEN 6 271 u8 resp_msg[HCLGEVF_TQPS_RSS_INFO_LEN]; 272 int status; 273 274 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QINFO, 0, NULL, 0, 275 true, resp_msg, 276 HCLGEVF_TQPS_RSS_INFO_LEN); 277 if (status) { 278 dev_err(&hdev->pdev->dev, 279 "VF request to get tqp info from PF failed %d", 280 status); 281 return status; 282 } 283 284 memcpy(&hdev->num_tqps, &resp_msg[0], sizeof(u16)); 285 memcpy(&hdev->rss_size_max, &resp_msg[2], sizeof(u16)); 286 memcpy(&hdev->rx_buf_len, &resp_msg[4], sizeof(u16)); 287 288 return 0; 289 } 290 291 static int hclgevf_get_queue_depth(struct hclgevf_dev *hdev) 292 { 293 #define HCLGEVF_TQPS_DEPTH_INFO_LEN 4 294 u8 resp_msg[HCLGEVF_TQPS_DEPTH_INFO_LEN]; 295 int ret; 296 297 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QDEPTH, 0, NULL, 0, 298 true, resp_msg, 299 HCLGEVF_TQPS_DEPTH_INFO_LEN); 300 if (ret) { 301 dev_err(&hdev->pdev->dev, 302 "VF request to get tqp depth info from PF failed %d", 303 ret); 304 return ret; 305 } 306 307 memcpy(&hdev->num_tx_desc, &resp_msg[0], sizeof(u16)); 308 memcpy(&hdev->num_rx_desc, &resp_msg[2], sizeof(u16)); 309 310 return 0; 311 } 312 313 static u16 hclgevf_get_qid_global(struct hnae3_handle *handle, u16 queue_id) 314 { 315 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 316 u8 msg_data[2], resp_data[2]; 317 u16 qid_in_pf = 0; 318 int ret; 319 320 memcpy(&msg_data[0], &queue_id, sizeof(queue_id)); 321 322 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QID_IN_PF, 0, msg_data, 323 sizeof(msg_data), true, resp_data, 324 sizeof(resp_data)); 325 if (!ret) 326 qid_in_pf = *(u16 *)resp_data; 327 328 return qid_in_pf; 329 } 330 331 static int hclgevf_get_pf_media_type(struct hclgevf_dev *hdev) 332 { 333 u8 resp_msg[2]; 334 int ret; 335 336 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_MEDIA_TYPE, 0, NULL, 0, 337 true, resp_msg, sizeof(resp_msg)); 338 if (ret) { 339 dev_err(&hdev->pdev->dev, 340 "VF request to get the pf port media type failed %d", 341 ret); 342 return ret; 343 } 344 345 hdev->hw.mac.media_type = resp_msg[0]; 346 hdev->hw.mac.module_type = resp_msg[1]; 347 348 return 0; 349 } 350 351 static int hclgevf_alloc_tqps(struct hclgevf_dev *hdev) 352 { 353 struct hclgevf_tqp *tqp; 354 int i; 355 356 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 357 sizeof(struct hclgevf_tqp), GFP_KERNEL); 358 if (!hdev->htqp) 359 return -ENOMEM; 360 361 tqp = hdev->htqp; 362 363 for (i = 0; i < hdev->num_tqps; i++) { 364 tqp->dev = &hdev->pdev->dev; 365 tqp->index = i; 366 367 tqp->q.ae_algo = &ae_algovf; 368 tqp->q.buf_size = hdev->rx_buf_len; 369 tqp->q.tx_desc_num = hdev->num_tx_desc; 370 tqp->q.rx_desc_num = hdev->num_rx_desc; 371 tqp->q.io_base = hdev->hw.io_base + HCLGEVF_TQP_REG_OFFSET + 372 i * HCLGEVF_TQP_REG_SIZE; 373 374 tqp++; 375 } 376 377 return 0; 378 } 379 380 static int hclgevf_knic_setup(struct hclgevf_dev *hdev) 381 { 382 struct hnae3_handle *nic = &hdev->nic; 383 struct hnae3_knic_private_info *kinfo; 384 u16 new_tqps = hdev->num_tqps; 385 unsigned int i; 386 387 kinfo = &nic->kinfo; 388 kinfo->num_tc = 0; 389 kinfo->num_tx_desc = hdev->num_tx_desc; 390 kinfo->num_rx_desc = hdev->num_rx_desc; 391 kinfo->rx_buf_len = hdev->rx_buf_len; 392 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) 393 if (hdev->hw_tc_map & BIT(i)) 394 kinfo->num_tc++; 395 396 kinfo->rss_size 397 = min_t(u16, hdev->rss_size_max, new_tqps / kinfo->num_tc); 398 new_tqps = kinfo->rss_size * kinfo->num_tc; 399 kinfo->num_tqps = min(new_tqps, hdev->num_tqps); 400 401 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps, 402 sizeof(struct hnae3_queue *), GFP_KERNEL); 403 if (!kinfo->tqp) 404 return -ENOMEM; 405 406 for (i = 0; i < kinfo->num_tqps; i++) { 407 hdev->htqp[i].q.handle = &hdev->nic; 408 hdev->htqp[i].q.tqp_index = i; 409 kinfo->tqp[i] = &hdev->htqp[i].q; 410 } 411 412 return 0; 413 } 414 415 static void hclgevf_request_link_info(struct hclgevf_dev *hdev) 416 { 417 int status; 418 u8 resp_msg; 419 420 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_STATUS, 0, NULL, 421 0, false, &resp_msg, sizeof(resp_msg)); 422 if (status) 423 dev_err(&hdev->pdev->dev, 424 "VF failed to fetch link status(%d) from PF", status); 425 } 426 427 void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state) 428 { 429 struct hnae3_handle *rhandle = &hdev->roce; 430 struct hnae3_handle *handle = &hdev->nic; 431 struct hnae3_client *rclient; 432 struct hnae3_client *client; 433 434 client = handle->client; 435 rclient = hdev->roce_client; 436 437 link_state = 438 test_bit(HCLGEVF_STATE_DOWN, &hdev->state) ? 0 : link_state; 439 440 if (link_state != hdev->hw.mac.link) { 441 client->ops->link_status_change(handle, !!link_state); 442 if (rclient && rclient->ops->link_status_change) 443 rclient->ops->link_status_change(rhandle, !!link_state); 444 hdev->hw.mac.link = link_state; 445 } 446 } 447 448 static void hclgevf_update_link_mode(struct hclgevf_dev *hdev) 449 { 450 #define HCLGEVF_ADVERTISING 0 451 #define HCLGEVF_SUPPORTED 1 452 u8 send_msg; 453 u8 resp_msg; 454 455 send_msg = HCLGEVF_ADVERTISING; 456 hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_MODE, 0, 457 &send_msg, sizeof(send_msg), false, 458 &resp_msg, sizeof(resp_msg)); 459 send_msg = HCLGEVF_SUPPORTED; 460 hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_MODE, 0, 461 &send_msg, sizeof(send_msg), false, 462 &resp_msg, sizeof(resp_msg)); 463 } 464 465 static int hclgevf_set_handle_info(struct hclgevf_dev *hdev) 466 { 467 struct hnae3_handle *nic = &hdev->nic; 468 int ret; 469 470 nic->ae_algo = &ae_algovf; 471 nic->pdev = hdev->pdev; 472 nic->numa_node_mask = hdev->numa_node_mask; 473 nic->flags |= HNAE3_SUPPORT_VF; 474 475 ret = hclgevf_knic_setup(hdev); 476 if (ret) 477 dev_err(&hdev->pdev->dev, "VF knic setup failed %d\n", 478 ret); 479 return ret; 480 } 481 482 static void hclgevf_free_vector(struct hclgevf_dev *hdev, int vector_id) 483 { 484 if (hdev->vector_status[vector_id] == HCLGEVF_INVALID_VPORT) { 485 dev_warn(&hdev->pdev->dev, 486 "vector(vector_id %d) has been freed.\n", vector_id); 487 return; 488 } 489 490 hdev->vector_status[vector_id] = HCLGEVF_INVALID_VPORT; 491 hdev->num_msi_left += 1; 492 hdev->num_msi_used -= 1; 493 } 494 495 static int hclgevf_get_vector(struct hnae3_handle *handle, u16 vector_num, 496 struct hnae3_vector_info *vector_info) 497 { 498 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 499 struct hnae3_vector_info *vector = vector_info; 500 int alloc = 0; 501 int i, j; 502 503 vector_num = min(hdev->num_msi_left, vector_num); 504 505 for (j = 0; j < vector_num; j++) { 506 for (i = HCLGEVF_MISC_VECTOR_NUM + 1; i < hdev->num_msi; i++) { 507 if (hdev->vector_status[i] == HCLGEVF_INVALID_VPORT) { 508 vector->vector = pci_irq_vector(hdev->pdev, i); 509 vector->io_addr = hdev->hw.io_base + 510 HCLGEVF_VECTOR_REG_BASE + 511 (i - 1) * HCLGEVF_VECTOR_REG_OFFSET; 512 hdev->vector_status[i] = 0; 513 hdev->vector_irq[i] = vector->vector; 514 515 vector++; 516 alloc++; 517 518 break; 519 } 520 } 521 } 522 hdev->num_msi_left -= alloc; 523 hdev->num_msi_used += alloc; 524 525 return alloc; 526 } 527 528 static int hclgevf_get_vector_index(struct hclgevf_dev *hdev, int vector) 529 { 530 int i; 531 532 for (i = 0; i < hdev->num_msi; i++) 533 if (vector == hdev->vector_irq[i]) 534 return i; 535 536 return -EINVAL; 537 } 538 539 static int hclgevf_set_rss_algo_key(struct hclgevf_dev *hdev, 540 const u8 hfunc, const u8 *key) 541 { 542 struct hclgevf_rss_config_cmd *req; 543 unsigned int key_offset = 0; 544 struct hclgevf_desc desc; 545 int key_counts; 546 int key_size; 547 int ret; 548 549 key_counts = HCLGEVF_RSS_KEY_SIZE; 550 req = (struct hclgevf_rss_config_cmd *)desc.data; 551 552 while (key_counts) { 553 hclgevf_cmd_setup_basic_desc(&desc, 554 HCLGEVF_OPC_RSS_GENERIC_CONFIG, 555 false); 556 557 req->hash_config |= (hfunc & HCLGEVF_RSS_HASH_ALGO_MASK); 558 req->hash_config |= 559 (key_offset << HCLGEVF_RSS_HASH_KEY_OFFSET_B); 560 561 key_size = min(HCLGEVF_RSS_HASH_KEY_NUM, key_counts); 562 memcpy(req->hash_key, 563 key + key_offset * HCLGEVF_RSS_HASH_KEY_NUM, key_size); 564 565 key_counts -= key_size; 566 key_offset++; 567 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 568 if (ret) { 569 dev_err(&hdev->pdev->dev, 570 "Configure RSS config fail, status = %d\n", 571 ret); 572 return ret; 573 } 574 } 575 576 return 0; 577 } 578 579 static u32 hclgevf_get_rss_key_size(struct hnae3_handle *handle) 580 { 581 return HCLGEVF_RSS_KEY_SIZE; 582 } 583 584 static u32 hclgevf_get_rss_indir_size(struct hnae3_handle *handle) 585 { 586 return HCLGEVF_RSS_IND_TBL_SIZE; 587 } 588 589 static int hclgevf_set_rss_indir_table(struct hclgevf_dev *hdev) 590 { 591 const u8 *indir = hdev->rss_cfg.rss_indirection_tbl; 592 struct hclgevf_rss_indirection_table_cmd *req; 593 struct hclgevf_desc desc; 594 int status; 595 int i, j; 596 597 req = (struct hclgevf_rss_indirection_table_cmd *)desc.data; 598 599 for (i = 0; i < HCLGEVF_RSS_CFG_TBL_NUM; i++) { 600 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INDIR_TABLE, 601 false); 602 req->start_table_index = i * HCLGEVF_RSS_CFG_TBL_SIZE; 603 req->rss_set_bitmap = HCLGEVF_RSS_SET_BITMAP_MSK; 604 for (j = 0; j < HCLGEVF_RSS_CFG_TBL_SIZE; j++) 605 req->rss_result[j] = 606 indir[i * HCLGEVF_RSS_CFG_TBL_SIZE + j]; 607 608 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 609 if (status) { 610 dev_err(&hdev->pdev->dev, 611 "VF failed(=%d) to set RSS indirection table\n", 612 status); 613 return status; 614 } 615 } 616 617 return 0; 618 } 619 620 static int hclgevf_set_rss_tc_mode(struct hclgevf_dev *hdev, u16 rss_size) 621 { 622 struct hclgevf_rss_tc_mode_cmd *req; 623 u16 tc_offset[HCLGEVF_MAX_TC_NUM]; 624 u16 tc_valid[HCLGEVF_MAX_TC_NUM]; 625 u16 tc_size[HCLGEVF_MAX_TC_NUM]; 626 struct hclgevf_desc desc; 627 u16 roundup_size; 628 int status; 629 unsigned int i; 630 631 req = (struct hclgevf_rss_tc_mode_cmd *)desc.data; 632 633 roundup_size = roundup_pow_of_two(rss_size); 634 roundup_size = ilog2(roundup_size); 635 636 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 637 tc_valid[i] = !!(hdev->hw_tc_map & BIT(i)); 638 tc_size[i] = roundup_size; 639 tc_offset[i] = rss_size * i; 640 } 641 642 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_TC_MODE, false); 643 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 644 hnae3_set_bit(req->rss_tc_mode[i], HCLGEVF_RSS_TC_VALID_B, 645 (tc_valid[i] & 0x1)); 646 hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_SIZE_M, 647 HCLGEVF_RSS_TC_SIZE_S, tc_size[i]); 648 hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_OFFSET_M, 649 HCLGEVF_RSS_TC_OFFSET_S, tc_offset[i]); 650 } 651 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 652 if (status) 653 dev_err(&hdev->pdev->dev, 654 "VF failed(=%d) to set rss tc mode\n", status); 655 656 return status; 657 } 658 659 /* for revision 0x20, vf shared the same rss config with pf */ 660 static int hclgevf_get_rss_hash_key(struct hclgevf_dev *hdev) 661 { 662 #define HCLGEVF_RSS_MBX_RESP_LEN 8 663 664 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 665 u8 resp_msg[HCLGEVF_RSS_MBX_RESP_LEN]; 666 u16 msg_num, hash_key_index; 667 u8 index; 668 int ret; 669 670 msg_num = (HCLGEVF_RSS_KEY_SIZE + HCLGEVF_RSS_MBX_RESP_LEN - 1) / 671 HCLGEVF_RSS_MBX_RESP_LEN; 672 for (index = 0; index < msg_num; index++) { 673 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_RSS_KEY, 0, 674 &index, sizeof(index), 675 true, resp_msg, 676 HCLGEVF_RSS_MBX_RESP_LEN); 677 if (ret) { 678 dev_err(&hdev->pdev->dev, 679 "VF get rss hash key from PF failed, ret=%d", 680 ret); 681 return ret; 682 } 683 684 hash_key_index = HCLGEVF_RSS_MBX_RESP_LEN * index; 685 if (index == msg_num - 1) 686 memcpy(&rss_cfg->rss_hash_key[hash_key_index], 687 &resp_msg[0], 688 HCLGEVF_RSS_KEY_SIZE - hash_key_index); 689 else 690 memcpy(&rss_cfg->rss_hash_key[hash_key_index], 691 &resp_msg[0], HCLGEVF_RSS_MBX_RESP_LEN); 692 } 693 694 return 0; 695 } 696 697 static int hclgevf_get_rss(struct hnae3_handle *handle, u32 *indir, u8 *key, 698 u8 *hfunc) 699 { 700 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 701 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 702 int i, ret; 703 704 if (handle->pdev->revision >= 0x21) { 705 /* Get hash algorithm */ 706 if (hfunc) { 707 switch (rss_cfg->hash_algo) { 708 case HCLGEVF_RSS_HASH_ALGO_TOEPLITZ: 709 *hfunc = ETH_RSS_HASH_TOP; 710 break; 711 case HCLGEVF_RSS_HASH_ALGO_SIMPLE: 712 *hfunc = ETH_RSS_HASH_XOR; 713 break; 714 default: 715 *hfunc = ETH_RSS_HASH_UNKNOWN; 716 break; 717 } 718 } 719 720 /* Get the RSS Key required by the user */ 721 if (key) 722 memcpy(key, rss_cfg->rss_hash_key, 723 HCLGEVF_RSS_KEY_SIZE); 724 } else { 725 if (hfunc) 726 *hfunc = ETH_RSS_HASH_TOP; 727 if (key) { 728 ret = hclgevf_get_rss_hash_key(hdev); 729 if (ret) 730 return ret; 731 memcpy(key, rss_cfg->rss_hash_key, 732 HCLGEVF_RSS_KEY_SIZE); 733 } 734 } 735 736 if (indir) 737 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 738 indir[i] = rss_cfg->rss_indirection_tbl[i]; 739 740 return 0; 741 } 742 743 static int hclgevf_set_rss(struct hnae3_handle *handle, const u32 *indir, 744 const u8 *key, const u8 hfunc) 745 { 746 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 747 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 748 int ret, i; 749 750 if (handle->pdev->revision >= 0x21) { 751 /* Set the RSS Hash Key if specififed by the user */ 752 if (key) { 753 switch (hfunc) { 754 case ETH_RSS_HASH_TOP: 755 rss_cfg->hash_algo = 756 HCLGEVF_RSS_HASH_ALGO_TOEPLITZ; 757 break; 758 case ETH_RSS_HASH_XOR: 759 rss_cfg->hash_algo = 760 HCLGEVF_RSS_HASH_ALGO_SIMPLE; 761 break; 762 case ETH_RSS_HASH_NO_CHANGE: 763 break; 764 default: 765 return -EINVAL; 766 } 767 768 ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 769 key); 770 if (ret) 771 return ret; 772 773 /* Update the shadow RSS key with user specified qids */ 774 memcpy(rss_cfg->rss_hash_key, key, 775 HCLGEVF_RSS_KEY_SIZE); 776 } 777 } 778 779 /* update the shadow RSS table with user specified qids */ 780 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 781 rss_cfg->rss_indirection_tbl[i] = indir[i]; 782 783 /* update the hardware */ 784 return hclgevf_set_rss_indir_table(hdev); 785 } 786 787 static u8 hclgevf_get_rss_hash_bits(struct ethtool_rxnfc *nfc) 788 { 789 u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGEVF_S_PORT_BIT : 0; 790 791 if (nfc->data & RXH_L4_B_2_3) 792 hash_sets |= HCLGEVF_D_PORT_BIT; 793 else 794 hash_sets &= ~HCLGEVF_D_PORT_BIT; 795 796 if (nfc->data & RXH_IP_SRC) 797 hash_sets |= HCLGEVF_S_IP_BIT; 798 else 799 hash_sets &= ~HCLGEVF_S_IP_BIT; 800 801 if (nfc->data & RXH_IP_DST) 802 hash_sets |= HCLGEVF_D_IP_BIT; 803 else 804 hash_sets &= ~HCLGEVF_D_IP_BIT; 805 806 if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW) 807 hash_sets |= HCLGEVF_V_TAG_BIT; 808 809 return hash_sets; 810 } 811 812 static int hclgevf_set_rss_tuple(struct hnae3_handle *handle, 813 struct ethtool_rxnfc *nfc) 814 { 815 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 816 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 817 struct hclgevf_rss_input_tuple_cmd *req; 818 struct hclgevf_desc desc; 819 u8 tuple_sets; 820 int ret; 821 822 if (handle->pdev->revision == 0x20) 823 return -EOPNOTSUPP; 824 825 if (nfc->data & 826 ~(RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3)) 827 return -EINVAL; 828 829 req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 830 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 831 832 req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 833 req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 834 req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 835 req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 836 req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 837 req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 838 req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 839 req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 840 841 tuple_sets = hclgevf_get_rss_hash_bits(nfc); 842 switch (nfc->flow_type) { 843 case TCP_V4_FLOW: 844 req->ipv4_tcp_en = tuple_sets; 845 break; 846 case TCP_V6_FLOW: 847 req->ipv6_tcp_en = tuple_sets; 848 break; 849 case UDP_V4_FLOW: 850 req->ipv4_udp_en = tuple_sets; 851 break; 852 case UDP_V6_FLOW: 853 req->ipv6_udp_en = tuple_sets; 854 break; 855 case SCTP_V4_FLOW: 856 req->ipv4_sctp_en = tuple_sets; 857 break; 858 case SCTP_V6_FLOW: 859 if ((nfc->data & RXH_L4_B_0_1) || 860 (nfc->data & RXH_L4_B_2_3)) 861 return -EINVAL; 862 863 req->ipv6_sctp_en = tuple_sets; 864 break; 865 case IPV4_FLOW: 866 req->ipv4_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 867 break; 868 case IPV6_FLOW: 869 req->ipv6_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 870 break; 871 default: 872 return -EINVAL; 873 } 874 875 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 876 if (ret) { 877 dev_err(&hdev->pdev->dev, 878 "Set rss tuple fail, status = %d\n", ret); 879 return ret; 880 } 881 882 rss_cfg->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en; 883 rss_cfg->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en; 884 rss_cfg->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en; 885 rss_cfg->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en; 886 rss_cfg->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en; 887 rss_cfg->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en; 888 rss_cfg->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en; 889 rss_cfg->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en; 890 return 0; 891 } 892 893 static int hclgevf_get_rss_tuple(struct hnae3_handle *handle, 894 struct ethtool_rxnfc *nfc) 895 { 896 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 897 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 898 u8 tuple_sets; 899 900 if (handle->pdev->revision == 0x20) 901 return -EOPNOTSUPP; 902 903 nfc->data = 0; 904 905 switch (nfc->flow_type) { 906 case TCP_V4_FLOW: 907 tuple_sets = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 908 break; 909 case UDP_V4_FLOW: 910 tuple_sets = rss_cfg->rss_tuple_sets.ipv4_udp_en; 911 break; 912 case TCP_V6_FLOW: 913 tuple_sets = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 914 break; 915 case UDP_V6_FLOW: 916 tuple_sets = rss_cfg->rss_tuple_sets.ipv6_udp_en; 917 break; 918 case SCTP_V4_FLOW: 919 tuple_sets = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 920 break; 921 case SCTP_V6_FLOW: 922 tuple_sets = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 923 break; 924 case IPV4_FLOW: 925 case IPV6_FLOW: 926 tuple_sets = HCLGEVF_S_IP_BIT | HCLGEVF_D_IP_BIT; 927 break; 928 default: 929 return -EINVAL; 930 } 931 932 if (!tuple_sets) 933 return 0; 934 935 if (tuple_sets & HCLGEVF_D_PORT_BIT) 936 nfc->data |= RXH_L4_B_2_3; 937 if (tuple_sets & HCLGEVF_S_PORT_BIT) 938 nfc->data |= RXH_L4_B_0_1; 939 if (tuple_sets & HCLGEVF_D_IP_BIT) 940 nfc->data |= RXH_IP_DST; 941 if (tuple_sets & HCLGEVF_S_IP_BIT) 942 nfc->data |= RXH_IP_SRC; 943 944 return 0; 945 } 946 947 static int hclgevf_set_rss_input_tuple(struct hclgevf_dev *hdev, 948 struct hclgevf_rss_cfg *rss_cfg) 949 { 950 struct hclgevf_rss_input_tuple_cmd *req; 951 struct hclgevf_desc desc; 952 int ret; 953 954 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 955 956 req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 957 958 req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 959 req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 960 req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 961 req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 962 req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 963 req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 964 req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 965 req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 966 967 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 968 if (ret) 969 dev_err(&hdev->pdev->dev, 970 "Configure rss input fail, status = %d\n", ret); 971 return ret; 972 } 973 974 static int hclgevf_get_tc_size(struct hnae3_handle *handle) 975 { 976 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 977 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 978 979 return rss_cfg->rss_size; 980 } 981 982 static int hclgevf_bind_ring_to_vector(struct hnae3_handle *handle, bool en, 983 int vector_id, 984 struct hnae3_ring_chain_node *ring_chain) 985 { 986 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 987 struct hnae3_ring_chain_node *node; 988 struct hclge_mbx_vf_to_pf_cmd *req; 989 struct hclgevf_desc desc; 990 int i = 0; 991 int status; 992 u8 type; 993 994 req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data; 995 996 for (node = ring_chain; node; node = node->next) { 997 int idx_offset = HCLGE_MBX_RING_MAP_BASIC_MSG_NUM + 998 HCLGE_MBX_RING_NODE_VARIABLE_NUM * i; 999 1000 if (i == 0) { 1001 hclgevf_cmd_setup_basic_desc(&desc, 1002 HCLGEVF_OPC_MBX_VF_TO_PF, 1003 false); 1004 type = en ? 1005 HCLGE_MBX_MAP_RING_TO_VECTOR : 1006 HCLGE_MBX_UNMAP_RING_TO_VECTOR; 1007 req->msg[0] = type; 1008 req->msg[1] = vector_id; 1009 } 1010 1011 req->msg[idx_offset] = 1012 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B); 1013 req->msg[idx_offset + 1] = node->tqp_index; 1014 req->msg[idx_offset + 2] = hnae3_get_field(node->int_gl_idx, 1015 HNAE3_RING_GL_IDX_M, 1016 HNAE3_RING_GL_IDX_S); 1017 1018 i++; 1019 if ((i == (HCLGE_MBX_VF_MSG_DATA_NUM - 1020 HCLGE_MBX_RING_MAP_BASIC_MSG_NUM) / 1021 HCLGE_MBX_RING_NODE_VARIABLE_NUM) || 1022 !node->next) { 1023 req->msg[2] = i; 1024 1025 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1026 if (status) { 1027 dev_err(&hdev->pdev->dev, 1028 "Map TQP fail, status is %d.\n", 1029 status); 1030 return status; 1031 } 1032 i = 0; 1033 hclgevf_cmd_setup_basic_desc(&desc, 1034 HCLGEVF_OPC_MBX_VF_TO_PF, 1035 false); 1036 req->msg[0] = type; 1037 req->msg[1] = vector_id; 1038 } 1039 } 1040 1041 return 0; 1042 } 1043 1044 static int hclgevf_map_ring_to_vector(struct hnae3_handle *handle, int vector, 1045 struct hnae3_ring_chain_node *ring_chain) 1046 { 1047 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1048 int vector_id; 1049 1050 vector_id = hclgevf_get_vector_index(hdev, vector); 1051 if (vector_id < 0) { 1052 dev_err(&handle->pdev->dev, 1053 "Get vector index fail. ret =%d\n", vector_id); 1054 return vector_id; 1055 } 1056 1057 return hclgevf_bind_ring_to_vector(handle, true, vector_id, ring_chain); 1058 } 1059 1060 static int hclgevf_unmap_ring_from_vector( 1061 struct hnae3_handle *handle, 1062 int vector, 1063 struct hnae3_ring_chain_node *ring_chain) 1064 { 1065 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1066 int ret, vector_id; 1067 1068 if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 1069 return 0; 1070 1071 vector_id = hclgevf_get_vector_index(hdev, vector); 1072 if (vector_id < 0) { 1073 dev_err(&handle->pdev->dev, 1074 "Get vector index fail. ret =%d\n", vector_id); 1075 return vector_id; 1076 } 1077 1078 ret = hclgevf_bind_ring_to_vector(handle, false, vector_id, ring_chain); 1079 if (ret) 1080 dev_err(&handle->pdev->dev, 1081 "Unmap ring from vector fail. vector=%d, ret =%d\n", 1082 vector_id, 1083 ret); 1084 1085 return ret; 1086 } 1087 1088 static int hclgevf_put_vector(struct hnae3_handle *handle, int vector) 1089 { 1090 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1091 int vector_id; 1092 1093 vector_id = hclgevf_get_vector_index(hdev, vector); 1094 if (vector_id < 0) { 1095 dev_err(&handle->pdev->dev, 1096 "hclgevf_put_vector get vector index fail. ret =%d\n", 1097 vector_id); 1098 return vector_id; 1099 } 1100 1101 hclgevf_free_vector(hdev, vector_id); 1102 1103 return 0; 1104 } 1105 1106 static int hclgevf_cmd_set_promisc_mode(struct hclgevf_dev *hdev, 1107 bool en_bc_pmc) 1108 { 1109 struct hclge_mbx_vf_to_pf_cmd *req; 1110 struct hclgevf_desc desc; 1111 int ret; 1112 1113 req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data; 1114 1115 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_MBX_VF_TO_PF, false); 1116 req->msg[0] = HCLGE_MBX_SET_PROMISC_MODE; 1117 req->msg[1] = en_bc_pmc ? 1 : 0; 1118 1119 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1120 if (ret) 1121 dev_err(&hdev->pdev->dev, 1122 "Set promisc mode fail, status is %d.\n", ret); 1123 1124 return ret; 1125 } 1126 1127 static int hclgevf_set_promisc_mode(struct hclgevf_dev *hdev, bool en_bc_pmc) 1128 { 1129 return hclgevf_cmd_set_promisc_mode(hdev, en_bc_pmc); 1130 } 1131 1132 static int hclgevf_tqp_enable(struct hclgevf_dev *hdev, unsigned int tqp_id, 1133 int stream_id, bool enable) 1134 { 1135 struct hclgevf_cfg_com_tqp_queue_cmd *req; 1136 struct hclgevf_desc desc; 1137 int status; 1138 1139 req = (struct hclgevf_cfg_com_tqp_queue_cmd *)desc.data; 1140 1141 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_CFG_COM_TQP_QUEUE, 1142 false); 1143 req->tqp_id = cpu_to_le16(tqp_id & HCLGEVF_RING_ID_MASK); 1144 req->stream_id = cpu_to_le16(stream_id); 1145 if (enable) 1146 req->enable |= 1U << HCLGEVF_TQP_ENABLE_B; 1147 1148 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1149 if (status) 1150 dev_err(&hdev->pdev->dev, 1151 "TQP enable fail, status =%d.\n", status); 1152 1153 return status; 1154 } 1155 1156 static void hclgevf_reset_tqp_stats(struct hnae3_handle *handle) 1157 { 1158 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 1159 struct hclgevf_tqp *tqp; 1160 int i; 1161 1162 for (i = 0; i < kinfo->num_tqps; i++) { 1163 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 1164 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats)); 1165 } 1166 } 1167 1168 static void hclgevf_get_mac_addr(struct hnae3_handle *handle, u8 *p) 1169 { 1170 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1171 1172 ether_addr_copy(p, hdev->hw.mac.mac_addr); 1173 } 1174 1175 static int hclgevf_set_mac_addr(struct hnae3_handle *handle, void *p, 1176 bool is_first) 1177 { 1178 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1179 u8 *old_mac_addr = (u8 *)hdev->hw.mac.mac_addr; 1180 u8 *new_mac_addr = (u8 *)p; 1181 u8 msg_data[ETH_ALEN * 2]; 1182 u16 subcode; 1183 int status; 1184 1185 ether_addr_copy(msg_data, new_mac_addr); 1186 ether_addr_copy(&msg_data[ETH_ALEN], old_mac_addr); 1187 1188 subcode = is_first ? HCLGE_MBX_MAC_VLAN_UC_ADD : 1189 HCLGE_MBX_MAC_VLAN_UC_MODIFY; 1190 1191 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 1192 subcode, msg_data, sizeof(msg_data), 1193 true, NULL, 0); 1194 if (!status) 1195 ether_addr_copy(hdev->hw.mac.mac_addr, new_mac_addr); 1196 1197 return status; 1198 } 1199 1200 static int hclgevf_add_uc_addr(struct hnae3_handle *handle, 1201 const unsigned char *addr) 1202 { 1203 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1204 1205 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 1206 HCLGE_MBX_MAC_VLAN_UC_ADD, 1207 addr, ETH_ALEN, false, NULL, 0); 1208 } 1209 1210 static int hclgevf_rm_uc_addr(struct hnae3_handle *handle, 1211 const unsigned char *addr) 1212 { 1213 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1214 1215 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 1216 HCLGE_MBX_MAC_VLAN_UC_REMOVE, 1217 addr, ETH_ALEN, false, NULL, 0); 1218 } 1219 1220 static int hclgevf_add_mc_addr(struct hnae3_handle *handle, 1221 const unsigned char *addr) 1222 { 1223 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1224 1225 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 1226 HCLGE_MBX_MAC_VLAN_MC_ADD, 1227 addr, ETH_ALEN, false, NULL, 0); 1228 } 1229 1230 static int hclgevf_rm_mc_addr(struct hnae3_handle *handle, 1231 const unsigned char *addr) 1232 { 1233 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1234 1235 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 1236 HCLGE_MBX_MAC_VLAN_MC_REMOVE, 1237 addr, ETH_ALEN, false, NULL, 0); 1238 } 1239 1240 static int hclgevf_set_vlan_filter(struct hnae3_handle *handle, 1241 __be16 proto, u16 vlan_id, 1242 bool is_kill) 1243 { 1244 #define HCLGEVF_VLAN_MBX_MSG_LEN 5 1245 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1246 u8 msg_data[HCLGEVF_VLAN_MBX_MSG_LEN]; 1247 1248 if (vlan_id > HCLGEVF_MAX_VLAN_ID) 1249 return -EINVAL; 1250 1251 if (proto != htons(ETH_P_8021Q)) 1252 return -EPROTONOSUPPORT; 1253 1254 msg_data[0] = is_kill; 1255 memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id)); 1256 memcpy(&msg_data[3], &proto, sizeof(proto)); 1257 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 1258 HCLGE_MBX_VLAN_FILTER, msg_data, 1259 HCLGEVF_VLAN_MBX_MSG_LEN, false, NULL, 0); 1260 } 1261 1262 static int hclgevf_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) 1263 { 1264 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1265 u8 msg_data; 1266 1267 msg_data = enable ? 1 : 0; 1268 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 1269 HCLGE_MBX_VLAN_RX_OFF_CFG, &msg_data, 1270 1, false, NULL, 0); 1271 } 1272 1273 static int hclgevf_reset_tqp(struct hnae3_handle *handle, u16 queue_id) 1274 { 1275 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1276 u8 msg_data[2]; 1277 int ret; 1278 1279 memcpy(msg_data, &queue_id, sizeof(queue_id)); 1280 1281 /* disable vf queue before send queue reset msg to PF */ 1282 ret = hclgevf_tqp_enable(hdev, queue_id, 0, false); 1283 if (ret) 1284 return ret; 1285 1286 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_QUEUE_RESET, 0, msg_data, 1287 sizeof(msg_data), true, NULL, 0); 1288 } 1289 1290 static int hclgevf_set_mtu(struct hnae3_handle *handle, int new_mtu) 1291 { 1292 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1293 1294 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MTU, 0, (u8 *)&new_mtu, 1295 sizeof(new_mtu), true, NULL, 0); 1296 } 1297 1298 static int hclgevf_notify_client(struct hclgevf_dev *hdev, 1299 enum hnae3_reset_notify_type type) 1300 { 1301 struct hnae3_client *client = hdev->nic_client; 1302 struct hnae3_handle *handle = &hdev->nic; 1303 int ret; 1304 1305 if (!test_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state) || 1306 !client) 1307 return 0; 1308 1309 if (!client->ops->reset_notify) 1310 return -EOPNOTSUPP; 1311 1312 ret = client->ops->reset_notify(handle, type); 1313 if (ret) 1314 dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n", 1315 type, ret); 1316 1317 return ret; 1318 } 1319 1320 static void hclgevf_flr_done(struct hnae3_ae_dev *ae_dev) 1321 { 1322 struct hclgevf_dev *hdev = ae_dev->priv; 1323 1324 set_bit(HNAE3_FLR_DONE, &hdev->flr_state); 1325 } 1326 1327 static int hclgevf_flr_poll_timeout(struct hclgevf_dev *hdev, 1328 unsigned long delay_us, 1329 unsigned long wait_cnt) 1330 { 1331 unsigned long cnt = 0; 1332 1333 while (!test_bit(HNAE3_FLR_DONE, &hdev->flr_state) && 1334 cnt++ < wait_cnt) 1335 usleep_range(delay_us, delay_us * 2); 1336 1337 if (!test_bit(HNAE3_FLR_DONE, &hdev->flr_state)) { 1338 dev_err(&hdev->pdev->dev, 1339 "flr wait timeout\n"); 1340 return -ETIMEDOUT; 1341 } 1342 1343 return 0; 1344 } 1345 1346 static int hclgevf_reset_wait(struct hclgevf_dev *hdev) 1347 { 1348 #define HCLGEVF_RESET_WAIT_US 20000 1349 #define HCLGEVF_RESET_WAIT_CNT 2000 1350 #define HCLGEVF_RESET_WAIT_TIMEOUT_US \ 1351 (HCLGEVF_RESET_WAIT_US * HCLGEVF_RESET_WAIT_CNT) 1352 1353 u32 val; 1354 int ret; 1355 1356 /* wait to check the hardware reset completion status */ 1357 val = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 1358 dev_info(&hdev->pdev->dev, "checking vf resetting status: %x\n", val); 1359 1360 if (hdev->reset_type == HNAE3_FLR_RESET) 1361 return hclgevf_flr_poll_timeout(hdev, 1362 HCLGEVF_RESET_WAIT_US, 1363 HCLGEVF_RESET_WAIT_CNT); 1364 1365 ret = readl_poll_timeout(hdev->hw.io_base + HCLGEVF_RST_ING, val, 1366 !(val & HCLGEVF_RST_ING_BITS), 1367 HCLGEVF_RESET_WAIT_US, 1368 HCLGEVF_RESET_WAIT_TIMEOUT_US); 1369 1370 /* hardware completion status should be available by this time */ 1371 if (ret) { 1372 dev_err(&hdev->pdev->dev, 1373 "could'nt get reset done status from h/w, timeout!\n"); 1374 return ret; 1375 } 1376 1377 /* we will wait a bit more to let reset of the stack to complete. This 1378 * might happen in case reset assertion was made by PF. Yes, this also 1379 * means we might end up waiting bit more even for VF reset. 1380 */ 1381 msleep(5000); 1382 1383 return 0; 1384 } 1385 1386 static int hclgevf_reset_stack(struct hclgevf_dev *hdev) 1387 { 1388 int ret; 1389 1390 /* uninitialize the nic client */ 1391 ret = hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT); 1392 if (ret) 1393 return ret; 1394 1395 /* re-initialize the hclge device */ 1396 ret = hclgevf_reset_hdev(hdev); 1397 if (ret) { 1398 dev_err(&hdev->pdev->dev, 1399 "hclge device re-init failed, VF is disabled!\n"); 1400 return ret; 1401 } 1402 1403 /* bring up the nic client again */ 1404 ret = hclgevf_notify_client(hdev, HNAE3_INIT_CLIENT); 1405 if (ret) 1406 return ret; 1407 1408 return hclgevf_notify_client(hdev, HNAE3_RESTORE_CLIENT); 1409 } 1410 1411 static int hclgevf_reset_prepare_wait(struct hclgevf_dev *hdev) 1412 { 1413 #define HCLGEVF_RESET_SYNC_TIME 100 1414 1415 int ret = 0; 1416 1417 switch (hdev->reset_type) { 1418 case HNAE3_VF_FUNC_RESET: 1419 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_RESET, 0, NULL, 1420 0, true, NULL, sizeof(u8)); 1421 hdev->rst_stats.vf_func_rst_cnt++; 1422 break; 1423 case HNAE3_FLR_RESET: 1424 set_bit(HNAE3_FLR_DOWN, &hdev->flr_state); 1425 hdev->rst_stats.flr_rst_cnt++; 1426 break; 1427 default: 1428 break; 1429 } 1430 1431 set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 1432 /* inform hardware that preparatory work is done */ 1433 msleep(HCLGEVF_RESET_SYNC_TIME); 1434 hclgevf_write_dev(&hdev->hw, HCLGEVF_NIC_CSQ_DEPTH_REG, 1435 HCLGEVF_NIC_CMQ_ENABLE); 1436 dev_info(&hdev->pdev->dev, "prepare reset(%d) wait done, ret:%d\n", 1437 hdev->reset_type, ret); 1438 1439 return ret; 1440 } 1441 1442 static int hclgevf_reset(struct hclgevf_dev *hdev) 1443 { 1444 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1445 int ret; 1446 1447 /* Initialize ae_dev reset status as well, in case enet layer wants to 1448 * know if device is undergoing reset 1449 */ 1450 ae_dev->reset_type = hdev->reset_type; 1451 hdev->rst_stats.rst_cnt++; 1452 rtnl_lock(); 1453 1454 /* bring down the nic to stop any ongoing TX/RX */ 1455 ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 1456 if (ret) 1457 goto err_reset_lock; 1458 1459 rtnl_unlock(); 1460 1461 ret = hclgevf_reset_prepare_wait(hdev); 1462 if (ret) 1463 goto err_reset; 1464 1465 /* check if VF could successfully fetch the hardware reset completion 1466 * status from the hardware 1467 */ 1468 ret = hclgevf_reset_wait(hdev); 1469 if (ret) { 1470 /* can't do much in this situation, will disable VF */ 1471 dev_err(&hdev->pdev->dev, 1472 "VF failed(=%d) to fetch H/W reset completion status\n", 1473 ret); 1474 goto err_reset; 1475 } 1476 1477 hdev->rst_stats.hw_rst_done_cnt++; 1478 1479 rtnl_lock(); 1480 1481 /* now, re-initialize the nic client and ae device*/ 1482 ret = hclgevf_reset_stack(hdev); 1483 if (ret) { 1484 dev_err(&hdev->pdev->dev, "failed to reset VF stack\n"); 1485 goto err_reset_lock; 1486 } 1487 1488 /* bring up the nic to enable TX/RX again */ 1489 ret = hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 1490 if (ret) 1491 goto err_reset_lock; 1492 1493 rtnl_unlock(); 1494 1495 hdev->last_reset_time = jiffies; 1496 ae_dev->reset_type = HNAE3_NONE_RESET; 1497 hdev->rst_stats.rst_done_cnt++; 1498 1499 return ret; 1500 err_reset_lock: 1501 rtnl_unlock(); 1502 err_reset: 1503 /* When VF reset failed, only the higher level reset asserted by PF 1504 * can restore it, so re-initialize the command queue to receive 1505 * this higher reset event. 1506 */ 1507 hclgevf_cmd_init(hdev); 1508 dev_err(&hdev->pdev->dev, "failed to reset VF\n"); 1509 if (hclgevf_is_reset_pending(hdev)) 1510 hclgevf_reset_task_schedule(hdev); 1511 1512 return ret; 1513 } 1514 1515 static enum hnae3_reset_type hclgevf_get_reset_level(struct hclgevf_dev *hdev, 1516 unsigned long *addr) 1517 { 1518 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; 1519 1520 /* return the highest priority reset level amongst all */ 1521 if (test_bit(HNAE3_VF_RESET, addr)) { 1522 rst_level = HNAE3_VF_RESET; 1523 clear_bit(HNAE3_VF_RESET, addr); 1524 clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1525 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1526 } else if (test_bit(HNAE3_VF_FULL_RESET, addr)) { 1527 rst_level = HNAE3_VF_FULL_RESET; 1528 clear_bit(HNAE3_VF_FULL_RESET, addr); 1529 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1530 } else if (test_bit(HNAE3_VF_PF_FUNC_RESET, addr)) { 1531 rst_level = HNAE3_VF_PF_FUNC_RESET; 1532 clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1533 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1534 } else if (test_bit(HNAE3_VF_FUNC_RESET, addr)) { 1535 rst_level = HNAE3_VF_FUNC_RESET; 1536 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1537 } else if (test_bit(HNAE3_FLR_RESET, addr)) { 1538 rst_level = HNAE3_FLR_RESET; 1539 clear_bit(HNAE3_FLR_RESET, addr); 1540 } 1541 1542 return rst_level; 1543 } 1544 1545 static void hclgevf_reset_event(struct pci_dev *pdev, 1546 struct hnae3_handle *handle) 1547 { 1548 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 1549 struct hclgevf_dev *hdev = ae_dev->priv; 1550 1551 dev_info(&hdev->pdev->dev, "received reset request from VF enet\n"); 1552 1553 if (hdev->default_reset_request) 1554 hdev->reset_level = 1555 hclgevf_get_reset_level(hdev, 1556 &hdev->default_reset_request); 1557 else 1558 hdev->reset_level = HNAE3_VF_FUNC_RESET; 1559 1560 /* reset of this VF requested */ 1561 set_bit(HCLGEVF_RESET_REQUESTED, &hdev->reset_state); 1562 hclgevf_reset_task_schedule(hdev); 1563 1564 hdev->last_reset_time = jiffies; 1565 } 1566 1567 static void hclgevf_set_def_reset_request(struct hnae3_ae_dev *ae_dev, 1568 enum hnae3_reset_type rst_type) 1569 { 1570 struct hclgevf_dev *hdev = ae_dev->priv; 1571 1572 set_bit(rst_type, &hdev->default_reset_request); 1573 } 1574 1575 static void hclgevf_flr_prepare(struct hnae3_ae_dev *ae_dev) 1576 { 1577 #define HCLGEVF_FLR_WAIT_MS 100 1578 #define HCLGEVF_FLR_WAIT_CNT 50 1579 struct hclgevf_dev *hdev = ae_dev->priv; 1580 int cnt = 0; 1581 1582 clear_bit(HNAE3_FLR_DOWN, &hdev->flr_state); 1583 clear_bit(HNAE3_FLR_DONE, &hdev->flr_state); 1584 set_bit(HNAE3_FLR_RESET, &hdev->default_reset_request); 1585 hclgevf_reset_event(hdev->pdev, NULL); 1586 1587 while (!test_bit(HNAE3_FLR_DOWN, &hdev->flr_state) && 1588 cnt++ < HCLGEVF_FLR_WAIT_CNT) 1589 msleep(HCLGEVF_FLR_WAIT_MS); 1590 1591 if (!test_bit(HNAE3_FLR_DOWN, &hdev->flr_state)) 1592 dev_err(&hdev->pdev->dev, 1593 "flr wait down timeout: %d\n", cnt); 1594 } 1595 1596 static u32 hclgevf_get_fw_version(struct hnae3_handle *handle) 1597 { 1598 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1599 1600 return hdev->fw_version; 1601 } 1602 1603 static void hclgevf_get_misc_vector(struct hclgevf_dev *hdev) 1604 { 1605 struct hclgevf_misc_vector *vector = &hdev->misc_vector; 1606 1607 vector->vector_irq = pci_irq_vector(hdev->pdev, 1608 HCLGEVF_MISC_VECTOR_NUM); 1609 vector->addr = hdev->hw.io_base + HCLGEVF_MISC_VECTOR_REG_BASE; 1610 /* vector status always valid for Vector 0 */ 1611 hdev->vector_status[HCLGEVF_MISC_VECTOR_NUM] = 0; 1612 hdev->vector_irq[HCLGEVF_MISC_VECTOR_NUM] = vector->vector_irq; 1613 1614 hdev->num_msi_left -= 1; 1615 hdev->num_msi_used += 1; 1616 } 1617 1618 void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev) 1619 { 1620 if (!test_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state) && 1621 !test_bit(HCLGEVF_STATE_REMOVING, &hdev->state)) { 1622 set_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state); 1623 schedule_work(&hdev->rst_service_task); 1624 } 1625 } 1626 1627 void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev) 1628 { 1629 if (!test_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state) && 1630 !test_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) { 1631 set_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 1632 schedule_work(&hdev->mbx_service_task); 1633 } 1634 } 1635 1636 static void hclgevf_task_schedule(struct hclgevf_dev *hdev) 1637 { 1638 if (!test_bit(HCLGEVF_STATE_DOWN, &hdev->state) && 1639 !test_and_set_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state)) 1640 schedule_work(&hdev->service_task); 1641 } 1642 1643 static void hclgevf_deferred_task_schedule(struct hclgevf_dev *hdev) 1644 { 1645 /* if we have any pending mailbox event then schedule the mbx task */ 1646 if (hdev->mbx_event_pending) 1647 hclgevf_mbx_task_schedule(hdev); 1648 1649 if (test_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state)) 1650 hclgevf_reset_task_schedule(hdev); 1651 } 1652 1653 static void hclgevf_service_timer(struct timer_list *t) 1654 { 1655 struct hclgevf_dev *hdev = from_timer(hdev, t, service_timer); 1656 1657 mod_timer(&hdev->service_timer, jiffies + 1658 HCLGEVF_GENERAL_TASK_INTERVAL * HZ); 1659 1660 hdev->stats_timer++; 1661 hclgevf_task_schedule(hdev); 1662 } 1663 1664 static void hclgevf_reset_service_task(struct work_struct *work) 1665 { 1666 struct hclgevf_dev *hdev = 1667 container_of(work, struct hclgevf_dev, rst_service_task); 1668 int ret; 1669 1670 if (test_and_set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 1671 return; 1672 1673 clear_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state); 1674 1675 if (test_and_clear_bit(HCLGEVF_RESET_PENDING, 1676 &hdev->reset_state)) { 1677 /* PF has initmated that it is about to reset the hardware. 1678 * We now have to poll & check if hardware has actually 1679 * completed the reset sequence. On hardware reset completion, 1680 * VF needs to reset the client and ae device. 1681 */ 1682 hdev->reset_attempts = 0; 1683 1684 hdev->last_reset_time = jiffies; 1685 while ((hdev->reset_type = 1686 hclgevf_get_reset_level(hdev, &hdev->reset_pending)) 1687 != HNAE3_NONE_RESET) { 1688 ret = hclgevf_reset(hdev); 1689 if (ret) 1690 dev_err(&hdev->pdev->dev, 1691 "VF stack reset failed %d.\n", ret); 1692 } 1693 } else if (test_and_clear_bit(HCLGEVF_RESET_REQUESTED, 1694 &hdev->reset_state)) { 1695 /* we could be here when either of below happens: 1696 * 1. reset was initiated due to watchdog timeout caused by 1697 * a. IMP was earlier reset and our TX got choked down and 1698 * which resulted in watchdog reacting and inducing VF 1699 * reset. This also means our cmdq would be unreliable. 1700 * b. problem in TX due to other lower layer(example link 1701 * layer not functioning properly etc.) 1702 * 2. VF reset might have been initiated due to some config 1703 * change. 1704 * 1705 * NOTE: Theres no clear way to detect above cases than to react 1706 * to the response of PF for this reset request. PF will ack the 1707 * 1b and 2. cases but we will not get any intimation about 1a 1708 * from PF as cmdq would be in unreliable state i.e. mailbox 1709 * communication between PF and VF would be broken. 1710 */ 1711 1712 /* if we are never geting into pending state it means either: 1713 * 1. PF is not receiving our request which could be due to IMP 1714 * reset 1715 * 2. PF is screwed 1716 * We cannot do much for 2. but to check first we can try reset 1717 * our PCIe + stack and see if it alleviates the problem. 1718 */ 1719 if (hdev->reset_attempts > 3) { 1720 /* prepare for full reset of stack + pcie interface */ 1721 set_bit(HNAE3_VF_FULL_RESET, &hdev->reset_pending); 1722 1723 /* "defer" schedule the reset task again */ 1724 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1725 } else { 1726 hdev->reset_attempts++; 1727 1728 set_bit(hdev->reset_level, &hdev->reset_pending); 1729 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1730 } 1731 hclgevf_reset_task_schedule(hdev); 1732 } 1733 1734 clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 1735 } 1736 1737 static void hclgevf_mailbox_service_task(struct work_struct *work) 1738 { 1739 struct hclgevf_dev *hdev; 1740 1741 hdev = container_of(work, struct hclgevf_dev, mbx_service_task); 1742 1743 if (test_and_set_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) 1744 return; 1745 1746 clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 1747 1748 hclgevf_mbx_async_handler(hdev); 1749 1750 clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 1751 } 1752 1753 static void hclgevf_keep_alive_timer(struct timer_list *t) 1754 { 1755 struct hclgevf_dev *hdev = from_timer(hdev, t, keep_alive_timer); 1756 1757 schedule_work(&hdev->keep_alive_task); 1758 mod_timer(&hdev->keep_alive_timer, jiffies + 1759 HCLGEVF_KEEP_ALIVE_TASK_INTERVAL * HZ); 1760 } 1761 1762 static void hclgevf_keep_alive_task(struct work_struct *work) 1763 { 1764 struct hclgevf_dev *hdev; 1765 u8 respmsg; 1766 int ret; 1767 1768 hdev = container_of(work, struct hclgevf_dev, keep_alive_task); 1769 1770 if (test_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state)) 1771 return; 1772 1773 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_KEEP_ALIVE, 0, NULL, 1774 0, false, &respmsg, sizeof(respmsg)); 1775 if (ret) 1776 dev_err(&hdev->pdev->dev, 1777 "VF sends keep alive cmd failed(=%d)\n", ret); 1778 } 1779 1780 static void hclgevf_service_task(struct work_struct *work) 1781 { 1782 struct hnae3_handle *handle; 1783 struct hclgevf_dev *hdev; 1784 1785 hdev = container_of(work, struct hclgevf_dev, service_task); 1786 handle = &hdev->nic; 1787 1788 if (hdev->stats_timer >= HCLGEVF_STATS_TIMER_INTERVAL) { 1789 hclgevf_tqps_update_stats(handle); 1790 hdev->stats_timer = 0; 1791 } 1792 1793 /* request the link status from the PF. PF would be able to tell VF 1794 * about such updates in future so we might remove this later 1795 */ 1796 hclgevf_request_link_info(hdev); 1797 1798 hclgevf_update_link_mode(hdev); 1799 1800 hclgevf_deferred_task_schedule(hdev); 1801 1802 clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 1803 } 1804 1805 static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regclr) 1806 { 1807 hclgevf_write_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_SRC_REG, regclr); 1808 } 1809 1810 static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev, 1811 u32 *clearval) 1812 { 1813 u32 cmdq_src_reg, rst_ing_reg; 1814 1815 /* fetch the events from their corresponding regs */ 1816 cmdq_src_reg = hclgevf_read_dev(&hdev->hw, 1817 HCLGEVF_VECTOR0_CMDQ_SRC_REG); 1818 1819 if (BIT(HCLGEVF_VECTOR0_RST_INT_B) & cmdq_src_reg) { 1820 rst_ing_reg = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 1821 dev_info(&hdev->pdev->dev, 1822 "receive reset interrupt 0x%x!\n", rst_ing_reg); 1823 set_bit(HNAE3_VF_RESET, &hdev->reset_pending); 1824 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1825 set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 1826 cmdq_src_reg &= ~BIT(HCLGEVF_VECTOR0_RST_INT_B); 1827 *clearval = cmdq_src_reg; 1828 hdev->rst_stats.vf_rst_cnt++; 1829 return HCLGEVF_VECTOR0_EVENT_RST; 1830 } 1831 1832 /* check for vector0 mailbox(=CMDQ RX) event source */ 1833 if (BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) { 1834 cmdq_src_reg &= ~BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 1835 *clearval = cmdq_src_reg; 1836 return HCLGEVF_VECTOR0_EVENT_MBX; 1837 } 1838 1839 dev_dbg(&hdev->pdev->dev, "vector 0 interrupt from unknown source\n"); 1840 1841 return HCLGEVF_VECTOR0_EVENT_OTHER; 1842 } 1843 1844 static void hclgevf_enable_vector(struct hclgevf_misc_vector *vector, bool en) 1845 { 1846 writel(en ? 1 : 0, vector->addr); 1847 } 1848 1849 static irqreturn_t hclgevf_misc_irq_handle(int irq, void *data) 1850 { 1851 enum hclgevf_evt_cause event_cause; 1852 struct hclgevf_dev *hdev = data; 1853 u32 clearval; 1854 1855 hclgevf_enable_vector(&hdev->misc_vector, false); 1856 event_cause = hclgevf_check_evt_cause(hdev, &clearval); 1857 1858 switch (event_cause) { 1859 case HCLGEVF_VECTOR0_EVENT_RST: 1860 hclgevf_reset_task_schedule(hdev); 1861 break; 1862 case HCLGEVF_VECTOR0_EVENT_MBX: 1863 hclgevf_mbx_handler(hdev); 1864 break; 1865 default: 1866 break; 1867 } 1868 1869 if (event_cause != HCLGEVF_VECTOR0_EVENT_OTHER) { 1870 hclgevf_clear_event_cause(hdev, clearval); 1871 hclgevf_enable_vector(&hdev->misc_vector, true); 1872 } 1873 1874 return IRQ_HANDLED; 1875 } 1876 1877 static int hclgevf_configure(struct hclgevf_dev *hdev) 1878 { 1879 int ret; 1880 1881 /* get current port based vlan state from PF */ 1882 ret = hclgevf_get_port_base_vlan_filter_state(hdev); 1883 if (ret) 1884 return ret; 1885 1886 /* get queue configuration from PF */ 1887 ret = hclgevf_get_queue_info(hdev); 1888 if (ret) 1889 return ret; 1890 1891 /* get queue depth info from PF */ 1892 ret = hclgevf_get_queue_depth(hdev); 1893 if (ret) 1894 return ret; 1895 1896 ret = hclgevf_get_pf_media_type(hdev); 1897 if (ret) 1898 return ret; 1899 1900 /* get tc configuration from PF */ 1901 return hclgevf_get_tc_info(hdev); 1902 } 1903 1904 static int hclgevf_alloc_hdev(struct hnae3_ae_dev *ae_dev) 1905 { 1906 struct pci_dev *pdev = ae_dev->pdev; 1907 struct hclgevf_dev *hdev; 1908 1909 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 1910 if (!hdev) 1911 return -ENOMEM; 1912 1913 hdev->pdev = pdev; 1914 hdev->ae_dev = ae_dev; 1915 ae_dev->priv = hdev; 1916 1917 return 0; 1918 } 1919 1920 static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev) 1921 { 1922 struct hnae3_handle *roce = &hdev->roce; 1923 struct hnae3_handle *nic = &hdev->nic; 1924 1925 roce->rinfo.num_vectors = hdev->num_roce_msix; 1926 1927 if (hdev->num_msi_left < roce->rinfo.num_vectors || 1928 hdev->num_msi_left == 0) 1929 return -EINVAL; 1930 1931 roce->rinfo.base_vector = hdev->roce_base_vector; 1932 1933 roce->rinfo.netdev = nic->kinfo.netdev; 1934 roce->rinfo.roce_io_base = hdev->hw.io_base; 1935 1936 roce->pdev = nic->pdev; 1937 roce->ae_algo = nic->ae_algo; 1938 roce->numa_node_mask = nic->numa_node_mask; 1939 1940 return 0; 1941 } 1942 1943 static int hclgevf_config_gro(struct hclgevf_dev *hdev, bool en) 1944 { 1945 struct hclgevf_cfg_gro_status_cmd *req; 1946 struct hclgevf_desc desc; 1947 int ret; 1948 1949 if (!hnae3_dev_gro_supported(hdev)) 1950 return 0; 1951 1952 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_GRO_GENERIC_CONFIG, 1953 false); 1954 req = (struct hclgevf_cfg_gro_status_cmd *)desc.data; 1955 1956 req->gro_en = cpu_to_le16(en ? 1 : 0); 1957 1958 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1959 if (ret) 1960 dev_err(&hdev->pdev->dev, 1961 "VF GRO hardware config cmd failed, ret = %d.\n", ret); 1962 1963 return ret; 1964 } 1965 1966 static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev) 1967 { 1968 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 1969 int i, ret; 1970 1971 rss_cfg->rss_size = hdev->rss_size_max; 1972 1973 if (hdev->pdev->revision >= 0x21) { 1974 rss_cfg->hash_algo = HCLGEVF_RSS_HASH_ALGO_SIMPLE; 1975 memcpy(rss_cfg->rss_hash_key, hclgevf_hash_key, 1976 HCLGEVF_RSS_KEY_SIZE); 1977 1978 ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 1979 rss_cfg->rss_hash_key); 1980 if (ret) 1981 return ret; 1982 1983 rss_cfg->rss_tuple_sets.ipv4_tcp_en = 1984 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1985 rss_cfg->rss_tuple_sets.ipv4_udp_en = 1986 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1987 rss_cfg->rss_tuple_sets.ipv4_sctp_en = 1988 HCLGEVF_RSS_INPUT_TUPLE_SCTP; 1989 rss_cfg->rss_tuple_sets.ipv4_fragment_en = 1990 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1991 rss_cfg->rss_tuple_sets.ipv6_tcp_en = 1992 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1993 rss_cfg->rss_tuple_sets.ipv6_udp_en = 1994 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1995 rss_cfg->rss_tuple_sets.ipv6_sctp_en = 1996 HCLGEVF_RSS_INPUT_TUPLE_SCTP; 1997 rss_cfg->rss_tuple_sets.ipv6_fragment_en = 1998 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1999 2000 ret = hclgevf_set_rss_input_tuple(hdev, rss_cfg); 2001 if (ret) 2002 return ret; 2003 2004 } 2005 2006 /* Initialize RSS indirect table */ 2007 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 2008 rss_cfg->rss_indirection_tbl[i] = i % hdev->rss_size_max; 2009 2010 ret = hclgevf_set_rss_indir_table(hdev); 2011 if (ret) 2012 return ret; 2013 2014 return hclgevf_set_rss_tc_mode(hdev, hdev->rss_size_max); 2015 } 2016 2017 static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev) 2018 { 2019 return hclgevf_set_vlan_filter(&hdev->nic, htons(ETH_P_8021Q), 0, 2020 false); 2021 } 2022 2023 static void hclgevf_set_timer_task(struct hnae3_handle *handle, bool enable) 2024 { 2025 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2026 2027 if (enable) { 2028 mod_timer(&hdev->service_timer, jiffies + HZ); 2029 } else { 2030 del_timer_sync(&hdev->service_timer); 2031 cancel_work_sync(&hdev->service_task); 2032 clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 2033 } 2034 } 2035 2036 static int hclgevf_ae_start(struct hnae3_handle *handle) 2037 { 2038 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2039 2040 hclgevf_reset_tqp_stats(handle); 2041 2042 hclgevf_request_link_info(hdev); 2043 2044 hclgevf_update_link_mode(hdev); 2045 2046 clear_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2047 2048 return 0; 2049 } 2050 2051 static void hclgevf_ae_stop(struct hnae3_handle *handle) 2052 { 2053 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2054 int i; 2055 2056 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2057 2058 if (hdev->reset_type != HNAE3_VF_RESET) 2059 for (i = 0; i < handle->kinfo.num_tqps; i++) 2060 if (hclgevf_reset_tqp(handle, i)) 2061 break; 2062 2063 hclgevf_reset_tqp_stats(handle); 2064 hclgevf_update_link_status(hdev, 0); 2065 } 2066 2067 static int hclgevf_set_alive(struct hnae3_handle *handle, bool alive) 2068 { 2069 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2070 u8 msg_data; 2071 2072 msg_data = alive ? 1 : 0; 2073 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_ALIVE, 2074 0, &msg_data, 1, false, NULL, 0); 2075 } 2076 2077 static int hclgevf_client_start(struct hnae3_handle *handle) 2078 { 2079 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2080 int ret; 2081 2082 ret = hclgevf_set_alive(handle, true); 2083 if (ret) 2084 return ret; 2085 2086 mod_timer(&hdev->keep_alive_timer, jiffies + 2087 HCLGEVF_KEEP_ALIVE_TASK_INTERVAL * HZ); 2088 2089 return 0; 2090 } 2091 2092 static void hclgevf_client_stop(struct hnae3_handle *handle) 2093 { 2094 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2095 int ret; 2096 2097 ret = hclgevf_set_alive(handle, false); 2098 if (ret) 2099 dev_warn(&hdev->pdev->dev, 2100 "%s failed %d\n", __func__, ret); 2101 2102 del_timer_sync(&hdev->keep_alive_timer); 2103 cancel_work_sync(&hdev->keep_alive_task); 2104 } 2105 2106 static void hclgevf_state_init(struct hclgevf_dev *hdev) 2107 { 2108 /* setup tasks for the MBX */ 2109 INIT_WORK(&hdev->mbx_service_task, hclgevf_mailbox_service_task); 2110 clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 2111 clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 2112 2113 /* setup tasks for service timer */ 2114 timer_setup(&hdev->service_timer, hclgevf_service_timer, 0); 2115 2116 INIT_WORK(&hdev->service_task, hclgevf_service_task); 2117 clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 2118 2119 INIT_WORK(&hdev->rst_service_task, hclgevf_reset_service_task); 2120 2121 mutex_init(&hdev->mbx_resp.mbx_mutex); 2122 2123 /* bring the device down */ 2124 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2125 } 2126 2127 static void hclgevf_state_uninit(struct hclgevf_dev *hdev) 2128 { 2129 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2130 set_bit(HCLGEVF_STATE_REMOVING, &hdev->state); 2131 2132 if (hdev->keep_alive_timer.function) 2133 del_timer_sync(&hdev->keep_alive_timer); 2134 if (hdev->keep_alive_task.func) 2135 cancel_work_sync(&hdev->keep_alive_task); 2136 if (hdev->service_timer.function) 2137 del_timer_sync(&hdev->service_timer); 2138 if (hdev->service_task.func) 2139 cancel_work_sync(&hdev->service_task); 2140 if (hdev->mbx_service_task.func) 2141 cancel_work_sync(&hdev->mbx_service_task); 2142 if (hdev->rst_service_task.func) 2143 cancel_work_sync(&hdev->rst_service_task); 2144 2145 mutex_destroy(&hdev->mbx_resp.mbx_mutex); 2146 } 2147 2148 static int hclgevf_init_msi(struct hclgevf_dev *hdev) 2149 { 2150 struct pci_dev *pdev = hdev->pdev; 2151 int vectors; 2152 int i; 2153 2154 if (hnae3_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B)) 2155 vectors = pci_alloc_irq_vectors(pdev, 2156 hdev->roce_base_msix_offset + 1, 2157 hdev->num_msi, 2158 PCI_IRQ_MSIX); 2159 else 2160 vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi, 2161 PCI_IRQ_MSI | PCI_IRQ_MSIX); 2162 2163 if (vectors < 0) { 2164 dev_err(&pdev->dev, 2165 "failed(%d) to allocate MSI/MSI-X vectors\n", 2166 vectors); 2167 return vectors; 2168 } 2169 if (vectors < hdev->num_msi) 2170 dev_warn(&hdev->pdev->dev, 2171 "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n", 2172 hdev->num_msi, vectors); 2173 2174 hdev->num_msi = vectors; 2175 hdev->num_msi_left = vectors; 2176 hdev->base_msi_vector = pdev->irq; 2177 hdev->roce_base_vector = pdev->irq + hdev->roce_base_msix_offset; 2178 2179 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 2180 sizeof(u16), GFP_KERNEL); 2181 if (!hdev->vector_status) { 2182 pci_free_irq_vectors(pdev); 2183 return -ENOMEM; 2184 } 2185 2186 for (i = 0; i < hdev->num_msi; i++) 2187 hdev->vector_status[i] = HCLGEVF_INVALID_VPORT; 2188 2189 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 2190 sizeof(int), GFP_KERNEL); 2191 if (!hdev->vector_irq) { 2192 devm_kfree(&pdev->dev, hdev->vector_status); 2193 pci_free_irq_vectors(pdev); 2194 return -ENOMEM; 2195 } 2196 2197 return 0; 2198 } 2199 2200 static void hclgevf_uninit_msi(struct hclgevf_dev *hdev) 2201 { 2202 struct pci_dev *pdev = hdev->pdev; 2203 2204 devm_kfree(&pdev->dev, hdev->vector_status); 2205 devm_kfree(&pdev->dev, hdev->vector_irq); 2206 pci_free_irq_vectors(pdev); 2207 } 2208 2209 static int hclgevf_misc_irq_init(struct hclgevf_dev *hdev) 2210 { 2211 int ret = 0; 2212 2213 hclgevf_get_misc_vector(hdev); 2214 2215 ret = request_irq(hdev->misc_vector.vector_irq, hclgevf_misc_irq_handle, 2216 0, "hclgevf_cmd", hdev); 2217 if (ret) { 2218 dev_err(&hdev->pdev->dev, "VF failed to request misc irq(%d)\n", 2219 hdev->misc_vector.vector_irq); 2220 return ret; 2221 } 2222 2223 hclgevf_clear_event_cause(hdev, 0); 2224 2225 /* enable misc. vector(vector 0) */ 2226 hclgevf_enable_vector(&hdev->misc_vector, true); 2227 2228 return ret; 2229 } 2230 2231 static void hclgevf_misc_irq_uninit(struct hclgevf_dev *hdev) 2232 { 2233 /* disable misc vector(vector 0) */ 2234 hclgevf_enable_vector(&hdev->misc_vector, false); 2235 synchronize_irq(hdev->misc_vector.vector_irq); 2236 free_irq(hdev->misc_vector.vector_irq, hdev); 2237 hclgevf_free_vector(hdev, 0); 2238 } 2239 2240 static void hclgevf_info_show(struct hclgevf_dev *hdev) 2241 { 2242 struct device *dev = &hdev->pdev->dev; 2243 2244 dev_info(dev, "VF info begin:\n"); 2245 2246 dev_info(dev, "Task queue pairs numbers: %d\n", hdev->num_tqps); 2247 dev_info(dev, "Desc num per TX queue: %d\n", hdev->num_tx_desc); 2248 dev_info(dev, "Desc num per RX queue: %d\n", hdev->num_rx_desc); 2249 dev_info(dev, "Numbers of vports: %d\n", hdev->num_alloc_vport); 2250 dev_info(dev, "HW tc map: %d\n", hdev->hw_tc_map); 2251 dev_info(dev, "PF media type of this VF: %d\n", 2252 hdev->hw.mac.media_type); 2253 2254 dev_info(dev, "VF info end.\n"); 2255 } 2256 2257 static int hclgevf_init_nic_client_instance(struct hnae3_ae_dev *ae_dev, 2258 struct hnae3_client *client) 2259 { 2260 struct hclgevf_dev *hdev = ae_dev->priv; 2261 int ret; 2262 2263 ret = client->ops->init_instance(&hdev->nic); 2264 if (ret) 2265 return ret; 2266 2267 set_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 2268 hnae3_set_client_init_flag(client, ae_dev, 1); 2269 2270 if (netif_msg_drv(&hdev->nic)) 2271 hclgevf_info_show(hdev); 2272 2273 return 0; 2274 } 2275 2276 static int hclgevf_init_roce_client_instance(struct hnae3_ae_dev *ae_dev, 2277 struct hnae3_client *client) 2278 { 2279 struct hclgevf_dev *hdev = ae_dev->priv; 2280 int ret; 2281 2282 if (!hnae3_dev_roce_supported(hdev) || !hdev->roce_client || 2283 !hdev->nic_client) 2284 return 0; 2285 2286 ret = hclgevf_init_roce_base_info(hdev); 2287 if (ret) 2288 return ret; 2289 2290 ret = client->ops->init_instance(&hdev->roce); 2291 if (ret) 2292 return ret; 2293 2294 hnae3_set_client_init_flag(client, ae_dev, 1); 2295 2296 return 0; 2297 } 2298 2299 static int hclgevf_init_client_instance(struct hnae3_client *client, 2300 struct hnae3_ae_dev *ae_dev) 2301 { 2302 struct hclgevf_dev *hdev = ae_dev->priv; 2303 int ret; 2304 2305 switch (client->type) { 2306 case HNAE3_CLIENT_KNIC: 2307 hdev->nic_client = client; 2308 hdev->nic.client = client; 2309 2310 ret = hclgevf_init_nic_client_instance(ae_dev, client); 2311 if (ret) 2312 goto clear_nic; 2313 2314 ret = hclgevf_init_roce_client_instance(ae_dev, 2315 hdev->roce_client); 2316 if (ret) 2317 goto clear_roce; 2318 2319 break; 2320 case HNAE3_CLIENT_ROCE: 2321 if (hnae3_dev_roce_supported(hdev)) { 2322 hdev->roce_client = client; 2323 hdev->roce.client = client; 2324 } 2325 2326 ret = hclgevf_init_roce_client_instance(ae_dev, client); 2327 if (ret) 2328 goto clear_roce; 2329 2330 break; 2331 default: 2332 return -EINVAL; 2333 } 2334 2335 return 0; 2336 2337 clear_nic: 2338 hdev->nic_client = NULL; 2339 hdev->nic.client = NULL; 2340 return ret; 2341 clear_roce: 2342 hdev->roce_client = NULL; 2343 hdev->roce.client = NULL; 2344 return ret; 2345 } 2346 2347 static void hclgevf_uninit_client_instance(struct hnae3_client *client, 2348 struct hnae3_ae_dev *ae_dev) 2349 { 2350 struct hclgevf_dev *hdev = ae_dev->priv; 2351 2352 /* un-init roce, if it exists */ 2353 if (hdev->roce_client) { 2354 hdev->roce_client->ops->uninit_instance(&hdev->roce, 0); 2355 hdev->roce_client = NULL; 2356 hdev->roce.client = NULL; 2357 } 2358 2359 /* un-init nic/unic, if this was not called by roce client */ 2360 if (client->ops->uninit_instance && hdev->nic_client && 2361 client->type != HNAE3_CLIENT_ROCE) { 2362 clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 2363 2364 client->ops->uninit_instance(&hdev->nic, 0); 2365 hdev->nic_client = NULL; 2366 hdev->nic.client = NULL; 2367 } 2368 } 2369 2370 static int hclgevf_pci_init(struct hclgevf_dev *hdev) 2371 { 2372 struct pci_dev *pdev = hdev->pdev; 2373 struct hclgevf_hw *hw; 2374 int ret; 2375 2376 ret = pci_enable_device(pdev); 2377 if (ret) { 2378 dev_err(&pdev->dev, "failed to enable PCI device\n"); 2379 return ret; 2380 } 2381 2382 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 2383 if (ret) { 2384 dev_err(&pdev->dev, "can't set consistent PCI DMA, exiting"); 2385 goto err_disable_device; 2386 } 2387 2388 ret = pci_request_regions(pdev, HCLGEVF_DRIVER_NAME); 2389 if (ret) { 2390 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 2391 goto err_disable_device; 2392 } 2393 2394 pci_set_master(pdev); 2395 hw = &hdev->hw; 2396 hw->hdev = hdev; 2397 hw->io_base = pci_iomap(pdev, 2, 0); 2398 if (!hw->io_base) { 2399 dev_err(&pdev->dev, "can't map configuration register space\n"); 2400 ret = -ENOMEM; 2401 goto err_clr_master; 2402 } 2403 2404 return 0; 2405 2406 err_clr_master: 2407 pci_clear_master(pdev); 2408 pci_release_regions(pdev); 2409 err_disable_device: 2410 pci_disable_device(pdev); 2411 2412 return ret; 2413 } 2414 2415 static void hclgevf_pci_uninit(struct hclgevf_dev *hdev) 2416 { 2417 struct pci_dev *pdev = hdev->pdev; 2418 2419 pci_iounmap(pdev, hdev->hw.io_base); 2420 pci_clear_master(pdev); 2421 pci_release_regions(pdev); 2422 pci_disable_device(pdev); 2423 } 2424 2425 static int hclgevf_query_vf_resource(struct hclgevf_dev *hdev) 2426 { 2427 struct hclgevf_query_res_cmd *req; 2428 struct hclgevf_desc desc; 2429 int ret; 2430 2431 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_VF_RSRC, true); 2432 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 2433 if (ret) { 2434 dev_err(&hdev->pdev->dev, 2435 "query vf resource failed, ret = %d.\n", ret); 2436 return ret; 2437 } 2438 2439 req = (struct hclgevf_query_res_cmd *)desc.data; 2440 2441 if (hnae3_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B)) { 2442 hdev->roce_base_msix_offset = 2443 hnae3_get_field(__le16_to_cpu(req->msixcap_localid_ba_rocee), 2444 HCLGEVF_MSIX_OFT_ROCEE_M, 2445 HCLGEVF_MSIX_OFT_ROCEE_S); 2446 hdev->num_roce_msix = 2447 hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number), 2448 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 2449 2450 /* VF should have NIC vectors and Roce vectors, NIC vectors 2451 * are queued before Roce vectors. The offset is fixed to 64. 2452 */ 2453 hdev->num_msi = hdev->num_roce_msix + 2454 hdev->roce_base_msix_offset; 2455 } else { 2456 hdev->num_msi = 2457 hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number), 2458 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 2459 } 2460 2461 return 0; 2462 } 2463 2464 static int hclgevf_pci_reset(struct hclgevf_dev *hdev) 2465 { 2466 struct pci_dev *pdev = hdev->pdev; 2467 int ret = 0; 2468 2469 if (hdev->reset_type == HNAE3_VF_FULL_RESET && 2470 test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2471 hclgevf_misc_irq_uninit(hdev); 2472 hclgevf_uninit_msi(hdev); 2473 clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2474 } 2475 2476 if (!test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2477 pci_set_master(pdev); 2478 ret = hclgevf_init_msi(hdev); 2479 if (ret) { 2480 dev_err(&pdev->dev, 2481 "failed(%d) to init MSI/MSI-X\n", ret); 2482 return ret; 2483 } 2484 2485 ret = hclgevf_misc_irq_init(hdev); 2486 if (ret) { 2487 hclgevf_uninit_msi(hdev); 2488 dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 2489 ret); 2490 return ret; 2491 } 2492 2493 set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2494 } 2495 2496 return ret; 2497 } 2498 2499 static int hclgevf_reset_hdev(struct hclgevf_dev *hdev) 2500 { 2501 struct pci_dev *pdev = hdev->pdev; 2502 int ret; 2503 2504 ret = hclgevf_pci_reset(hdev); 2505 if (ret) { 2506 dev_err(&pdev->dev, "pci reset failed %d\n", ret); 2507 return ret; 2508 } 2509 2510 ret = hclgevf_cmd_init(hdev); 2511 if (ret) { 2512 dev_err(&pdev->dev, "cmd failed %d\n", ret); 2513 return ret; 2514 } 2515 2516 ret = hclgevf_rss_init_hw(hdev); 2517 if (ret) { 2518 dev_err(&hdev->pdev->dev, 2519 "failed(%d) to initialize RSS\n", ret); 2520 return ret; 2521 } 2522 2523 ret = hclgevf_config_gro(hdev, true); 2524 if (ret) 2525 return ret; 2526 2527 ret = hclgevf_init_vlan_config(hdev); 2528 if (ret) { 2529 dev_err(&hdev->pdev->dev, 2530 "failed(%d) to initialize VLAN config\n", ret); 2531 return ret; 2532 } 2533 2534 dev_info(&hdev->pdev->dev, "Reset done\n"); 2535 2536 return 0; 2537 } 2538 2539 static int hclgevf_init_hdev(struct hclgevf_dev *hdev) 2540 { 2541 struct pci_dev *pdev = hdev->pdev; 2542 int ret; 2543 2544 ret = hclgevf_pci_init(hdev); 2545 if (ret) { 2546 dev_err(&pdev->dev, "PCI initialization failed\n"); 2547 return ret; 2548 } 2549 2550 ret = hclgevf_cmd_queue_init(hdev); 2551 if (ret) { 2552 dev_err(&pdev->dev, "Cmd queue init failed: %d\n", ret); 2553 goto err_cmd_queue_init; 2554 } 2555 2556 ret = hclgevf_cmd_init(hdev); 2557 if (ret) 2558 goto err_cmd_init; 2559 2560 /* Get vf resource */ 2561 ret = hclgevf_query_vf_resource(hdev); 2562 if (ret) { 2563 dev_err(&hdev->pdev->dev, 2564 "Query vf status error, ret = %d.\n", ret); 2565 goto err_cmd_init; 2566 } 2567 2568 ret = hclgevf_init_msi(hdev); 2569 if (ret) { 2570 dev_err(&pdev->dev, "failed(%d) to init MSI/MSI-X\n", ret); 2571 goto err_cmd_init; 2572 } 2573 2574 hclgevf_state_init(hdev); 2575 hdev->reset_level = HNAE3_VF_FUNC_RESET; 2576 2577 ret = hclgevf_misc_irq_init(hdev); 2578 if (ret) { 2579 dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 2580 ret); 2581 goto err_misc_irq_init; 2582 } 2583 2584 set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2585 2586 ret = hclgevf_configure(hdev); 2587 if (ret) { 2588 dev_err(&pdev->dev, "failed(%d) to fetch configuration\n", ret); 2589 goto err_config; 2590 } 2591 2592 ret = hclgevf_alloc_tqps(hdev); 2593 if (ret) { 2594 dev_err(&pdev->dev, "failed(%d) to allocate TQPs\n", ret); 2595 goto err_config; 2596 } 2597 2598 ret = hclgevf_set_handle_info(hdev); 2599 if (ret) { 2600 dev_err(&pdev->dev, "failed(%d) to set handle info\n", ret); 2601 goto err_config; 2602 } 2603 2604 ret = hclgevf_config_gro(hdev, true); 2605 if (ret) 2606 goto err_config; 2607 2608 /* vf is not allowed to enable unicast/multicast promisc mode. 2609 * For revision 0x20, default to disable broadcast promisc mode, 2610 * firmware makes sure broadcast packets can be accepted. 2611 * For revision 0x21, default to enable broadcast promisc mode. 2612 */ 2613 ret = hclgevf_set_promisc_mode(hdev, true); 2614 if (ret) 2615 goto err_config; 2616 2617 /* Initialize RSS for this VF */ 2618 ret = hclgevf_rss_init_hw(hdev); 2619 if (ret) { 2620 dev_err(&hdev->pdev->dev, 2621 "failed(%d) to initialize RSS\n", ret); 2622 goto err_config; 2623 } 2624 2625 ret = hclgevf_init_vlan_config(hdev); 2626 if (ret) { 2627 dev_err(&hdev->pdev->dev, 2628 "failed(%d) to initialize VLAN config\n", ret); 2629 goto err_config; 2630 } 2631 2632 hdev->last_reset_time = jiffies; 2633 pr_info("finished initializing %s driver\n", HCLGEVF_DRIVER_NAME); 2634 2635 return 0; 2636 2637 err_config: 2638 hclgevf_misc_irq_uninit(hdev); 2639 err_misc_irq_init: 2640 hclgevf_state_uninit(hdev); 2641 hclgevf_uninit_msi(hdev); 2642 err_cmd_init: 2643 hclgevf_cmd_uninit(hdev); 2644 err_cmd_queue_init: 2645 hclgevf_pci_uninit(hdev); 2646 clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2647 return ret; 2648 } 2649 2650 static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev) 2651 { 2652 hclgevf_state_uninit(hdev); 2653 2654 if (test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2655 hclgevf_misc_irq_uninit(hdev); 2656 hclgevf_uninit_msi(hdev); 2657 } 2658 2659 hclgevf_pci_uninit(hdev); 2660 hclgevf_cmd_uninit(hdev); 2661 } 2662 2663 static int hclgevf_init_ae_dev(struct hnae3_ae_dev *ae_dev) 2664 { 2665 struct pci_dev *pdev = ae_dev->pdev; 2666 struct hclgevf_dev *hdev; 2667 int ret; 2668 2669 ret = hclgevf_alloc_hdev(ae_dev); 2670 if (ret) { 2671 dev_err(&pdev->dev, "hclge device allocation failed\n"); 2672 return ret; 2673 } 2674 2675 ret = hclgevf_init_hdev(ae_dev->priv); 2676 if (ret) { 2677 dev_err(&pdev->dev, "hclge device initialization failed\n"); 2678 return ret; 2679 } 2680 2681 hdev = ae_dev->priv; 2682 timer_setup(&hdev->keep_alive_timer, hclgevf_keep_alive_timer, 0); 2683 INIT_WORK(&hdev->keep_alive_task, hclgevf_keep_alive_task); 2684 2685 return 0; 2686 } 2687 2688 static void hclgevf_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 2689 { 2690 struct hclgevf_dev *hdev = ae_dev->priv; 2691 2692 hclgevf_uninit_hdev(hdev); 2693 ae_dev->priv = NULL; 2694 } 2695 2696 static u32 hclgevf_get_max_channels(struct hclgevf_dev *hdev) 2697 { 2698 struct hnae3_handle *nic = &hdev->nic; 2699 struct hnae3_knic_private_info *kinfo = &nic->kinfo; 2700 2701 return min_t(u32, hdev->rss_size_max, 2702 hdev->num_tqps / kinfo->num_tc); 2703 } 2704 2705 /** 2706 * hclgevf_get_channels - Get the current channels enabled and max supported. 2707 * @handle: hardware information for network interface 2708 * @ch: ethtool channels structure 2709 * 2710 * We don't support separate tx and rx queues as channels. The other count 2711 * represents how many queues are being used for control. max_combined counts 2712 * how many queue pairs we can support. They may not be mapped 1 to 1 with 2713 * q_vectors since we support a lot more queue pairs than q_vectors. 2714 **/ 2715 static void hclgevf_get_channels(struct hnae3_handle *handle, 2716 struct ethtool_channels *ch) 2717 { 2718 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2719 2720 ch->max_combined = hclgevf_get_max_channels(hdev); 2721 ch->other_count = 0; 2722 ch->max_other = 0; 2723 ch->combined_count = handle->kinfo.rss_size; 2724 } 2725 2726 static void hclgevf_get_tqps_and_rss_info(struct hnae3_handle *handle, 2727 u16 *alloc_tqps, u16 *max_rss_size) 2728 { 2729 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2730 2731 *alloc_tqps = hdev->num_tqps; 2732 *max_rss_size = hdev->rss_size_max; 2733 } 2734 2735 static int hclgevf_get_status(struct hnae3_handle *handle) 2736 { 2737 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2738 2739 return hdev->hw.mac.link; 2740 } 2741 2742 static void hclgevf_get_ksettings_an_result(struct hnae3_handle *handle, 2743 u8 *auto_neg, u32 *speed, 2744 u8 *duplex) 2745 { 2746 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2747 2748 if (speed) 2749 *speed = hdev->hw.mac.speed; 2750 if (duplex) 2751 *duplex = hdev->hw.mac.duplex; 2752 if (auto_neg) 2753 *auto_neg = AUTONEG_DISABLE; 2754 } 2755 2756 void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed, 2757 u8 duplex) 2758 { 2759 hdev->hw.mac.speed = speed; 2760 hdev->hw.mac.duplex = duplex; 2761 } 2762 2763 static int hclgevf_gro_en(struct hnae3_handle *handle, bool enable) 2764 { 2765 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2766 2767 return hclgevf_config_gro(hdev, enable); 2768 } 2769 2770 static void hclgevf_get_media_type(struct hnae3_handle *handle, u8 *media_type, 2771 u8 *module_type) 2772 { 2773 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2774 2775 if (media_type) 2776 *media_type = hdev->hw.mac.media_type; 2777 2778 if (module_type) 2779 *module_type = hdev->hw.mac.module_type; 2780 } 2781 2782 static bool hclgevf_get_hw_reset_stat(struct hnae3_handle *handle) 2783 { 2784 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2785 2786 return !!hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 2787 } 2788 2789 static bool hclgevf_ae_dev_resetting(struct hnae3_handle *handle) 2790 { 2791 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2792 2793 return test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 2794 } 2795 2796 static unsigned long hclgevf_ae_dev_reset_cnt(struct hnae3_handle *handle) 2797 { 2798 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2799 2800 return hdev->rst_stats.hw_rst_done_cnt; 2801 } 2802 2803 static void hclgevf_get_link_mode(struct hnae3_handle *handle, 2804 unsigned long *supported, 2805 unsigned long *advertising) 2806 { 2807 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2808 2809 *supported = hdev->hw.mac.supported; 2810 *advertising = hdev->hw.mac.advertising; 2811 } 2812 2813 #define MAX_SEPARATE_NUM 4 2814 #define SEPARATOR_VALUE 0xFFFFFFFF 2815 #define REG_NUM_PER_LINE 4 2816 #define REG_LEN_PER_LINE (REG_NUM_PER_LINE * sizeof(u32)) 2817 2818 static int hclgevf_get_regs_len(struct hnae3_handle *handle) 2819 { 2820 int cmdq_lines, common_lines, ring_lines, tqp_intr_lines; 2821 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2822 2823 cmdq_lines = sizeof(cmdq_reg_addr_list) / REG_LEN_PER_LINE + 1; 2824 common_lines = sizeof(common_reg_addr_list) / REG_LEN_PER_LINE + 1; 2825 ring_lines = sizeof(ring_reg_addr_list) / REG_LEN_PER_LINE + 1; 2826 tqp_intr_lines = sizeof(tqp_intr_reg_addr_list) / REG_LEN_PER_LINE + 1; 2827 2828 return (cmdq_lines + common_lines + ring_lines * hdev->num_tqps + 2829 tqp_intr_lines * (hdev->num_msi_used - 1)) * REG_LEN_PER_LINE; 2830 } 2831 2832 static void hclgevf_get_regs(struct hnae3_handle *handle, u32 *version, 2833 void *data) 2834 { 2835 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2836 int i, j, reg_um, separator_num; 2837 u32 *reg = data; 2838 2839 *version = hdev->fw_version; 2840 2841 /* fetching per-VF registers values from VF PCIe register space */ 2842 reg_um = sizeof(cmdq_reg_addr_list) / sizeof(u32); 2843 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 2844 for (i = 0; i < reg_um; i++) 2845 *reg++ = hclgevf_read_dev(&hdev->hw, cmdq_reg_addr_list[i]); 2846 for (i = 0; i < separator_num; i++) 2847 *reg++ = SEPARATOR_VALUE; 2848 2849 reg_um = sizeof(common_reg_addr_list) / sizeof(u32); 2850 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 2851 for (i = 0; i < reg_um; i++) 2852 *reg++ = hclgevf_read_dev(&hdev->hw, common_reg_addr_list[i]); 2853 for (i = 0; i < separator_num; i++) 2854 *reg++ = SEPARATOR_VALUE; 2855 2856 reg_um = sizeof(ring_reg_addr_list) / sizeof(u32); 2857 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 2858 for (j = 0; j < hdev->num_tqps; j++) { 2859 for (i = 0; i < reg_um; i++) 2860 *reg++ = hclgevf_read_dev(&hdev->hw, 2861 ring_reg_addr_list[i] + 2862 0x200 * j); 2863 for (i = 0; i < separator_num; i++) 2864 *reg++ = SEPARATOR_VALUE; 2865 } 2866 2867 reg_um = sizeof(tqp_intr_reg_addr_list) / sizeof(u32); 2868 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 2869 for (j = 0; j < hdev->num_msi_used - 1; j++) { 2870 for (i = 0; i < reg_um; i++) 2871 *reg++ = hclgevf_read_dev(&hdev->hw, 2872 tqp_intr_reg_addr_list[i] + 2873 4 * j); 2874 for (i = 0; i < separator_num; i++) 2875 *reg++ = SEPARATOR_VALUE; 2876 } 2877 } 2878 2879 void hclgevf_update_port_base_vlan_info(struct hclgevf_dev *hdev, u16 state, 2880 u8 *port_base_vlan_info, u8 data_size) 2881 { 2882 struct hnae3_handle *nic = &hdev->nic; 2883 2884 rtnl_lock(); 2885 hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 2886 rtnl_unlock(); 2887 2888 /* send msg to PF and wait update port based vlan info */ 2889 hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 2890 HCLGE_MBX_PORT_BASE_VLAN_CFG, 2891 port_base_vlan_info, data_size, 2892 false, NULL, 0); 2893 2894 if (state == HNAE3_PORT_BASE_VLAN_DISABLE) 2895 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_DISABLE; 2896 else 2897 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_ENABLE; 2898 2899 rtnl_lock(); 2900 hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 2901 rtnl_unlock(); 2902 } 2903 2904 static const struct hnae3_ae_ops hclgevf_ops = { 2905 .init_ae_dev = hclgevf_init_ae_dev, 2906 .uninit_ae_dev = hclgevf_uninit_ae_dev, 2907 .flr_prepare = hclgevf_flr_prepare, 2908 .flr_done = hclgevf_flr_done, 2909 .init_client_instance = hclgevf_init_client_instance, 2910 .uninit_client_instance = hclgevf_uninit_client_instance, 2911 .start = hclgevf_ae_start, 2912 .stop = hclgevf_ae_stop, 2913 .client_start = hclgevf_client_start, 2914 .client_stop = hclgevf_client_stop, 2915 .map_ring_to_vector = hclgevf_map_ring_to_vector, 2916 .unmap_ring_from_vector = hclgevf_unmap_ring_from_vector, 2917 .get_vector = hclgevf_get_vector, 2918 .put_vector = hclgevf_put_vector, 2919 .reset_queue = hclgevf_reset_tqp, 2920 .get_mac_addr = hclgevf_get_mac_addr, 2921 .set_mac_addr = hclgevf_set_mac_addr, 2922 .add_uc_addr = hclgevf_add_uc_addr, 2923 .rm_uc_addr = hclgevf_rm_uc_addr, 2924 .add_mc_addr = hclgevf_add_mc_addr, 2925 .rm_mc_addr = hclgevf_rm_mc_addr, 2926 .get_stats = hclgevf_get_stats, 2927 .update_stats = hclgevf_update_stats, 2928 .get_strings = hclgevf_get_strings, 2929 .get_sset_count = hclgevf_get_sset_count, 2930 .get_rss_key_size = hclgevf_get_rss_key_size, 2931 .get_rss_indir_size = hclgevf_get_rss_indir_size, 2932 .get_rss = hclgevf_get_rss, 2933 .set_rss = hclgevf_set_rss, 2934 .get_rss_tuple = hclgevf_get_rss_tuple, 2935 .set_rss_tuple = hclgevf_set_rss_tuple, 2936 .get_tc_size = hclgevf_get_tc_size, 2937 .get_fw_version = hclgevf_get_fw_version, 2938 .set_vlan_filter = hclgevf_set_vlan_filter, 2939 .enable_hw_strip_rxvtag = hclgevf_en_hw_strip_rxvtag, 2940 .reset_event = hclgevf_reset_event, 2941 .set_default_reset_request = hclgevf_set_def_reset_request, 2942 .get_channels = hclgevf_get_channels, 2943 .get_tqps_and_rss_info = hclgevf_get_tqps_and_rss_info, 2944 .get_regs_len = hclgevf_get_regs_len, 2945 .get_regs = hclgevf_get_regs, 2946 .get_status = hclgevf_get_status, 2947 .get_ksettings_an_result = hclgevf_get_ksettings_an_result, 2948 .get_media_type = hclgevf_get_media_type, 2949 .get_hw_reset_stat = hclgevf_get_hw_reset_stat, 2950 .ae_dev_resetting = hclgevf_ae_dev_resetting, 2951 .ae_dev_reset_cnt = hclgevf_ae_dev_reset_cnt, 2952 .set_gro_en = hclgevf_gro_en, 2953 .set_mtu = hclgevf_set_mtu, 2954 .get_global_queue_id = hclgevf_get_qid_global, 2955 .set_timer_task = hclgevf_set_timer_task, 2956 .get_link_mode = hclgevf_get_link_mode, 2957 }; 2958 2959 static struct hnae3_ae_algo ae_algovf = { 2960 .ops = &hclgevf_ops, 2961 .pdev_id_table = ae_algovf_pci_tbl, 2962 }; 2963 2964 static int hclgevf_init(void) 2965 { 2966 pr_info("%s is initializing\n", HCLGEVF_NAME); 2967 2968 hnae3_register_ae_algo(&ae_algovf); 2969 2970 return 0; 2971 } 2972 2973 static void hclgevf_exit(void) 2974 { 2975 hnae3_unregister_ae_algo(&ae_algovf); 2976 } 2977 module_init(hclgevf_init); 2978 module_exit(hclgevf_exit); 2979 2980 MODULE_LICENSE("GPL"); 2981 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 2982 MODULE_DESCRIPTION("HCLGEVF Driver"); 2983 MODULE_VERSION(HCLGEVF_MOD_VERSION); 2984