1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/etherdevice.h> 5 #include "hclgevf_cmd.h" 6 #include "hclgevf_main.h" 7 #include "hclge_mbx.h" 8 #include "hnae3.h" 9 10 #define HCLGEVF_NAME "hclgevf" 11 12 static struct hnae3_ae_algo ae_algovf; 13 14 static const struct pci_device_id ae_algovf_pci_tbl[] = { 15 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0}, 16 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF), 0}, 17 /* required last entry */ 18 {0, } 19 }; 20 21 static inline struct hclgevf_dev *hclgevf_ae_get_hdev( 22 struct hnae3_handle *handle) 23 { 24 return container_of(handle, struct hclgevf_dev, nic); 25 } 26 27 static int hclgevf_tqps_update_stats(struct hnae3_handle *handle) 28 { 29 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 30 struct hnae3_queue *queue; 31 struct hclgevf_desc desc; 32 struct hclgevf_tqp *tqp; 33 int status; 34 int i; 35 36 for (i = 0; i < hdev->num_tqps; i++) { 37 queue = handle->kinfo.tqp[i]; 38 tqp = container_of(queue, struct hclgevf_tqp, q); 39 hclgevf_cmd_setup_basic_desc(&desc, 40 HCLGEVF_OPC_QUERY_RX_STATUS, 41 true); 42 43 desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 44 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 45 if (status) { 46 dev_err(&hdev->pdev->dev, 47 "Query tqp stat fail, status = %d,queue = %d\n", 48 status, i); 49 return status; 50 } 51 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd += 52 le32_to_cpu(desc.data[4]); 53 54 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_TX_STATUS, 55 true); 56 57 desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 58 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 59 if (status) { 60 dev_err(&hdev->pdev->dev, 61 "Query tqp stat fail, status = %d,queue = %d\n", 62 status, i); 63 return status; 64 } 65 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd += 66 le32_to_cpu(desc.data[4]); 67 } 68 69 return 0; 70 } 71 72 static u64 *hclgevf_tqps_get_stats(struct hnae3_handle *handle, u64 *data) 73 { 74 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 75 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 76 struct hclgevf_tqp *tqp; 77 u64 *buff = data; 78 int i; 79 80 for (i = 0; i < hdev->num_tqps; i++) { 81 tqp = container_of(handle->kinfo.tqp[i], struct hclgevf_tqp, q); 82 *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd; 83 } 84 for (i = 0; i < kinfo->num_tqps; i++) { 85 tqp = container_of(handle->kinfo.tqp[i], struct hclgevf_tqp, q); 86 *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd; 87 } 88 89 return buff; 90 } 91 92 static int hclgevf_tqps_get_sset_count(struct hnae3_handle *handle, int strset) 93 { 94 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 95 96 return hdev->num_tqps * 2; 97 } 98 99 static u8 *hclgevf_tqps_get_strings(struct hnae3_handle *handle, u8 *data) 100 { 101 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 102 u8 *buff = data; 103 int i = 0; 104 105 for (i = 0; i < hdev->num_tqps; i++) { 106 struct hclgevf_tqp *tqp = container_of(handle->kinfo.tqp[i], 107 struct hclgevf_tqp, q); 108 snprintf(buff, ETH_GSTRING_LEN, "rcb_q%d_tx_pktnum_rcd", 109 tqp->index); 110 buff += ETH_GSTRING_LEN; 111 } 112 113 for (i = 0; i < hdev->num_tqps; i++) { 114 struct hclgevf_tqp *tqp = container_of(handle->kinfo.tqp[i], 115 struct hclgevf_tqp, q); 116 snprintf(buff, ETH_GSTRING_LEN, "rcb_q%d_rx_pktnum_rcd", 117 tqp->index); 118 buff += ETH_GSTRING_LEN; 119 } 120 121 return buff; 122 } 123 124 static void hclgevf_update_stats(struct hnae3_handle *handle, 125 struct net_device_stats *net_stats) 126 { 127 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 128 int status; 129 130 status = hclgevf_tqps_update_stats(handle); 131 if (status) 132 dev_err(&hdev->pdev->dev, 133 "VF update of TQPS stats fail, status = %d.\n", 134 status); 135 } 136 137 static int hclgevf_get_sset_count(struct hnae3_handle *handle, int strset) 138 { 139 if (strset == ETH_SS_TEST) 140 return -EOPNOTSUPP; 141 else if (strset == ETH_SS_STATS) 142 return hclgevf_tqps_get_sset_count(handle, strset); 143 144 return 0; 145 } 146 147 static void hclgevf_get_strings(struct hnae3_handle *handle, u32 strset, 148 u8 *data) 149 { 150 u8 *p = (char *)data; 151 152 if (strset == ETH_SS_STATS) 153 p = hclgevf_tqps_get_strings(handle, p); 154 } 155 156 static void hclgevf_get_stats(struct hnae3_handle *handle, u64 *data) 157 { 158 hclgevf_tqps_get_stats(handle, data); 159 } 160 161 static int hclgevf_get_tc_info(struct hclgevf_dev *hdev) 162 { 163 u8 resp_msg; 164 int status; 165 166 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_TCINFO, 0, NULL, 0, 167 true, &resp_msg, sizeof(u8)); 168 if (status) { 169 dev_err(&hdev->pdev->dev, 170 "VF request to get TC info from PF failed %d", 171 status); 172 return status; 173 } 174 175 hdev->hw_tc_map = resp_msg; 176 177 return 0; 178 } 179 180 static int hclge_get_queue_info(struct hclgevf_dev *hdev) 181 { 182 #define HCLGEVF_TQPS_RSS_INFO_LEN 8 183 u8 resp_msg[HCLGEVF_TQPS_RSS_INFO_LEN]; 184 int status; 185 186 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QINFO, 0, NULL, 0, 187 true, resp_msg, 188 HCLGEVF_TQPS_RSS_INFO_LEN); 189 if (status) { 190 dev_err(&hdev->pdev->dev, 191 "VF request to get tqp info from PF failed %d", 192 status); 193 return status; 194 } 195 196 memcpy(&hdev->num_tqps, &resp_msg[0], sizeof(u16)); 197 memcpy(&hdev->rss_size_max, &resp_msg[2], sizeof(u16)); 198 memcpy(&hdev->num_desc, &resp_msg[4], sizeof(u16)); 199 memcpy(&hdev->rx_buf_len, &resp_msg[6], sizeof(u16)); 200 201 return 0; 202 } 203 204 static int hclgevf_enable_tso(struct hclgevf_dev *hdev, int enable) 205 { 206 struct hclgevf_cfg_tso_status_cmd *req; 207 struct hclgevf_desc desc; 208 209 req = (struct hclgevf_cfg_tso_status_cmd *)desc.data; 210 211 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_TSO_GENERIC_CONFIG, 212 false); 213 hnae_set_bit(req->tso_enable, HCLGEVF_TSO_ENABLE_B, enable); 214 215 return hclgevf_cmd_send(&hdev->hw, &desc, 1); 216 } 217 218 static int hclgevf_alloc_tqps(struct hclgevf_dev *hdev) 219 { 220 struct hclgevf_tqp *tqp; 221 int i; 222 223 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 224 sizeof(struct hclgevf_tqp), GFP_KERNEL); 225 if (!hdev->htqp) 226 return -ENOMEM; 227 228 tqp = hdev->htqp; 229 230 for (i = 0; i < hdev->num_tqps; i++) { 231 tqp->dev = &hdev->pdev->dev; 232 tqp->index = i; 233 234 tqp->q.ae_algo = &ae_algovf; 235 tqp->q.buf_size = hdev->rx_buf_len; 236 tqp->q.desc_num = hdev->num_desc; 237 tqp->q.io_base = hdev->hw.io_base + HCLGEVF_TQP_REG_OFFSET + 238 i * HCLGEVF_TQP_REG_SIZE; 239 240 tqp++; 241 } 242 243 return 0; 244 } 245 246 static int hclgevf_knic_setup(struct hclgevf_dev *hdev) 247 { 248 struct hnae3_handle *nic = &hdev->nic; 249 struct hnae3_knic_private_info *kinfo; 250 u16 new_tqps = hdev->num_tqps; 251 int i; 252 253 kinfo = &nic->kinfo; 254 kinfo->num_tc = 0; 255 kinfo->num_desc = hdev->num_desc; 256 kinfo->rx_buf_len = hdev->rx_buf_len; 257 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) 258 if (hdev->hw_tc_map & BIT(i)) 259 kinfo->num_tc++; 260 261 kinfo->rss_size 262 = min_t(u16, hdev->rss_size_max, new_tqps / kinfo->num_tc); 263 new_tqps = kinfo->rss_size * kinfo->num_tc; 264 kinfo->num_tqps = min(new_tqps, hdev->num_tqps); 265 266 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps, 267 sizeof(struct hnae3_queue *), GFP_KERNEL); 268 if (!kinfo->tqp) 269 return -ENOMEM; 270 271 for (i = 0; i < kinfo->num_tqps; i++) { 272 hdev->htqp[i].q.handle = &hdev->nic; 273 hdev->htqp[i].q.tqp_index = i; 274 kinfo->tqp[i] = &hdev->htqp[i].q; 275 } 276 277 return 0; 278 } 279 280 static void hclgevf_request_link_info(struct hclgevf_dev *hdev) 281 { 282 int status; 283 u8 resp_msg; 284 285 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_STATUS, 0, NULL, 286 0, false, &resp_msg, sizeof(u8)); 287 if (status) 288 dev_err(&hdev->pdev->dev, 289 "VF failed to fetch link status(%d) from PF", status); 290 } 291 292 void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state) 293 { 294 struct hnae3_handle *handle = &hdev->nic; 295 struct hnae3_client *client; 296 297 client = handle->client; 298 299 if (link_state != hdev->hw.mac.link) { 300 client->ops->link_status_change(handle, !!link_state); 301 hdev->hw.mac.link = link_state; 302 } 303 } 304 305 static int hclgevf_set_handle_info(struct hclgevf_dev *hdev) 306 { 307 struct hnae3_handle *nic = &hdev->nic; 308 int ret; 309 310 nic->ae_algo = &ae_algovf; 311 nic->pdev = hdev->pdev; 312 nic->numa_node_mask = hdev->numa_node_mask; 313 314 if (hdev->ae_dev->dev_type != HNAE3_DEV_KNIC) { 315 dev_err(&hdev->pdev->dev, "unsupported device type %d\n", 316 hdev->ae_dev->dev_type); 317 return -EINVAL; 318 } 319 320 ret = hclgevf_knic_setup(hdev); 321 if (ret) 322 dev_err(&hdev->pdev->dev, "VF knic setup failed %d\n", 323 ret); 324 return ret; 325 } 326 327 static void hclgevf_free_vector(struct hclgevf_dev *hdev, int vector_id) 328 { 329 hdev->vector_status[vector_id] = HCLGEVF_INVALID_VPORT; 330 hdev->num_msi_left += 1; 331 hdev->num_msi_used -= 1; 332 } 333 334 static int hclgevf_get_vector(struct hnae3_handle *handle, u16 vector_num, 335 struct hnae3_vector_info *vector_info) 336 { 337 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 338 struct hnae3_vector_info *vector = vector_info; 339 int alloc = 0; 340 int i, j; 341 342 vector_num = min(hdev->num_msi_left, vector_num); 343 344 for (j = 0; j < vector_num; j++) { 345 for (i = HCLGEVF_MISC_VECTOR_NUM + 1; i < hdev->num_msi; i++) { 346 if (hdev->vector_status[i] == HCLGEVF_INVALID_VPORT) { 347 vector->vector = pci_irq_vector(hdev->pdev, i); 348 vector->io_addr = hdev->hw.io_base + 349 HCLGEVF_VECTOR_REG_BASE + 350 (i - 1) * HCLGEVF_VECTOR_REG_OFFSET; 351 hdev->vector_status[i] = 0; 352 hdev->vector_irq[i] = vector->vector; 353 354 vector++; 355 alloc++; 356 357 break; 358 } 359 } 360 } 361 hdev->num_msi_left -= alloc; 362 hdev->num_msi_used += alloc; 363 364 return alloc; 365 } 366 367 static int hclgevf_get_vector_index(struct hclgevf_dev *hdev, int vector) 368 { 369 int i; 370 371 for (i = 0; i < hdev->num_msi; i++) 372 if (vector == hdev->vector_irq[i]) 373 return i; 374 375 return -EINVAL; 376 } 377 378 static u32 hclgevf_get_rss_key_size(struct hnae3_handle *handle) 379 { 380 return HCLGEVF_RSS_KEY_SIZE; 381 } 382 383 static u32 hclgevf_get_rss_indir_size(struct hnae3_handle *handle) 384 { 385 return HCLGEVF_RSS_IND_TBL_SIZE; 386 } 387 388 static int hclgevf_set_rss_indir_table(struct hclgevf_dev *hdev) 389 { 390 const u8 *indir = hdev->rss_cfg.rss_indirection_tbl; 391 struct hclgevf_rss_indirection_table_cmd *req; 392 struct hclgevf_desc desc; 393 int status; 394 int i, j; 395 396 req = (struct hclgevf_rss_indirection_table_cmd *)desc.data; 397 398 for (i = 0; i < HCLGEVF_RSS_CFG_TBL_NUM; i++) { 399 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INDIR_TABLE, 400 false); 401 req->start_table_index = i * HCLGEVF_RSS_CFG_TBL_SIZE; 402 req->rss_set_bitmap = HCLGEVF_RSS_SET_BITMAP_MSK; 403 for (j = 0; j < HCLGEVF_RSS_CFG_TBL_SIZE; j++) 404 req->rss_result[j] = 405 indir[i * HCLGEVF_RSS_CFG_TBL_SIZE + j]; 406 407 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 408 if (status) { 409 dev_err(&hdev->pdev->dev, 410 "VF failed(=%d) to set RSS indirection table\n", 411 status); 412 return status; 413 } 414 } 415 416 return 0; 417 } 418 419 static int hclgevf_set_rss_tc_mode(struct hclgevf_dev *hdev, u16 rss_size) 420 { 421 struct hclgevf_rss_tc_mode_cmd *req; 422 u16 tc_offset[HCLGEVF_MAX_TC_NUM]; 423 u16 tc_valid[HCLGEVF_MAX_TC_NUM]; 424 u16 tc_size[HCLGEVF_MAX_TC_NUM]; 425 struct hclgevf_desc desc; 426 u16 roundup_size; 427 int status; 428 int i; 429 430 req = (struct hclgevf_rss_tc_mode_cmd *)desc.data; 431 432 roundup_size = roundup_pow_of_two(rss_size); 433 roundup_size = ilog2(roundup_size); 434 435 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 436 tc_valid[i] = !!(hdev->hw_tc_map & BIT(i)); 437 tc_size[i] = roundup_size; 438 tc_offset[i] = rss_size * i; 439 } 440 441 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_TC_MODE, false); 442 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 443 hnae_set_bit(req->rss_tc_mode[i], HCLGEVF_RSS_TC_VALID_B, 444 (tc_valid[i] & 0x1)); 445 hnae_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_SIZE_M, 446 HCLGEVF_RSS_TC_SIZE_S, tc_size[i]); 447 hnae_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_OFFSET_M, 448 HCLGEVF_RSS_TC_OFFSET_S, tc_offset[i]); 449 } 450 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 451 if (status) 452 dev_err(&hdev->pdev->dev, 453 "VF failed(=%d) to set rss tc mode\n", status); 454 455 return status; 456 } 457 458 static int hclgevf_get_rss_hw_cfg(struct hnae3_handle *handle, u8 *hash, 459 u8 *key) 460 { 461 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 462 struct hclgevf_rss_config_cmd *req; 463 int lkup_times = key ? 3 : 1; 464 struct hclgevf_desc desc; 465 int key_offset; 466 int key_size; 467 int status; 468 469 req = (struct hclgevf_rss_config_cmd *)desc.data; 470 lkup_times = (lkup_times == 3) ? 3 : ((hash) ? 1 : 0); 471 472 for (key_offset = 0; key_offset < lkup_times; key_offset++) { 473 hclgevf_cmd_setup_basic_desc(&desc, 474 HCLGEVF_OPC_RSS_GENERIC_CONFIG, 475 true); 476 req->hash_config |= (key_offset << HCLGEVF_RSS_HASH_KEY_OFFSET); 477 478 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 479 if (status) { 480 dev_err(&hdev->pdev->dev, 481 "failed to get hardware RSS cfg, status = %d\n", 482 status); 483 return status; 484 } 485 486 if (key_offset == 2) 487 key_size = 488 HCLGEVF_RSS_KEY_SIZE - HCLGEVF_RSS_HASH_KEY_NUM * 2; 489 else 490 key_size = HCLGEVF_RSS_HASH_KEY_NUM; 491 492 if (key) 493 memcpy(key + key_offset * HCLGEVF_RSS_HASH_KEY_NUM, 494 req->hash_key, 495 key_size); 496 } 497 498 if (hash) { 499 if ((req->hash_config & 0xf) == HCLGEVF_RSS_HASH_ALGO_TOEPLITZ) 500 *hash = ETH_RSS_HASH_TOP; 501 else 502 *hash = ETH_RSS_HASH_UNKNOWN; 503 } 504 505 return 0; 506 } 507 508 static int hclgevf_get_rss(struct hnae3_handle *handle, u32 *indir, u8 *key, 509 u8 *hfunc) 510 { 511 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 512 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 513 int i; 514 515 if (indir) 516 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 517 indir[i] = rss_cfg->rss_indirection_tbl[i]; 518 519 return hclgevf_get_rss_hw_cfg(handle, hfunc, key); 520 } 521 522 static int hclgevf_set_rss(struct hnae3_handle *handle, const u32 *indir, 523 const u8 *key, const u8 hfunc) 524 { 525 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 526 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 527 int i; 528 529 /* update the shadow RSS table with user specified qids */ 530 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 531 rss_cfg->rss_indirection_tbl[i] = indir[i]; 532 533 /* update the hardware */ 534 return hclgevf_set_rss_indir_table(hdev); 535 } 536 537 static int hclgevf_get_tc_size(struct hnae3_handle *handle) 538 { 539 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 540 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 541 542 return rss_cfg->rss_size; 543 } 544 545 static int hclgevf_bind_ring_to_vector(struct hnae3_handle *handle, bool en, 546 int vector, 547 struct hnae3_ring_chain_node *ring_chain) 548 { 549 #define HCLGEVF_RING_NODE_VARIABLE_NUM 3 550 #define HCLGEVF_RING_MAP_MBX_BASIC_MSG_NUM 3 551 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 552 struct hnae3_ring_chain_node *node; 553 struct hclge_mbx_vf_to_pf_cmd *req; 554 struct hclgevf_desc desc; 555 int i, vector_id; 556 int status; 557 u8 type; 558 559 req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data; 560 vector_id = hclgevf_get_vector_index(hdev, vector); 561 if (vector_id < 0) { 562 dev_err(&handle->pdev->dev, 563 "Get vector index fail. ret =%d\n", vector_id); 564 return vector_id; 565 } 566 567 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_MBX_VF_TO_PF, false); 568 type = en ? 569 HCLGE_MBX_MAP_RING_TO_VECTOR : HCLGE_MBX_UNMAP_RING_TO_VECTOR; 570 req->msg[0] = type; 571 req->msg[1] = vector_id; /* vector_id should be id in VF */ 572 573 i = 0; 574 for (node = ring_chain; node; node = node->next) { 575 i++; 576 /* msg[2] is cause num */ 577 req->msg[HCLGEVF_RING_NODE_VARIABLE_NUM * i] = 578 hnae_get_bit(node->flag, HNAE3_RING_TYPE_B); 579 req->msg[HCLGEVF_RING_NODE_VARIABLE_NUM * i + 1] = 580 node->tqp_index; 581 if (i == (HCLGE_MBX_VF_MSG_DATA_NUM - 582 HCLGEVF_RING_MAP_MBX_BASIC_MSG_NUM) / 583 HCLGEVF_RING_NODE_VARIABLE_NUM) { 584 req->msg[2] = i; 585 586 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 587 if (status) { 588 dev_err(&hdev->pdev->dev, 589 "Map TQP fail, status is %d.\n", 590 status); 591 return status; 592 } 593 i = 0; 594 hclgevf_cmd_setup_basic_desc(&desc, 595 HCLGEVF_OPC_MBX_VF_TO_PF, 596 false); 597 req->msg[0] = type; 598 req->msg[1] = vector_id; 599 } 600 } 601 602 if (i > 0) { 603 req->msg[2] = i; 604 605 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 606 if (status) { 607 dev_err(&hdev->pdev->dev, 608 "Map TQP fail, status is %d.\n", status); 609 return status; 610 } 611 } 612 613 return 0; 614 } 615 616 static int hclgevf_map_ring_to_vector(struct hnae3_handle *handle, int vector, 617 struct hnae3_ring_chain_node *ring_chain) 618 { 619 return hclgevf_bind_ring_to_vector(handle, true, vector, ring_chain); 620 } 621 622 static int hclgevf_unmap_ring_from_vector( 623 struct hnae3_handle *handle, 624 int vector, 625 struct hnae3_ring_chain_node *ring_chain) 626 { 627 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 628 int ret, vector_id; 629 630 vector_id = hclgevf_get_vector_index(hdev, vector); 631 if (vector_id < 0) { 632 dev_err(&handle->pdev->dev, 633 "Get vector index fail. ret =%d\n", vector_id); 634 return vector_id; 635 } 636 637 ret = hclgevf_bind_ring_to_vector(handle, false, vector, ring_chain); 638 if (ret) { 639 dev_err(&handle->pdev->dev, 640 "Unmap ring from vector fail. vector=%d, ret =%d\n", 641 vector_id, 642 ret); 643 return ret; 644 } 645 646 hclgevf_free_vector(hdev, vector); 647 648 return 0; 649 } 650 651 static int hclgevf_cmd_set_promisc_mode(struct hclgevf_dev *hdev, u32 en) 652 { 653 struct hclge_mbx_vf_to_pf_cmd *req; 654 struct hclgevf_desc desc; 655 int status; 656 657 req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data; 658 659 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_MBX_VF_TO_PF, false); 660 req->msg[0] = HCLGE_MBX_SET_PROMISC_MODE; 661 req->msg[1] = en; 662 663 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 664 if (status) 665 dev_err(&hdev->pdev->dev, 666 "Set promisc mode fail, status is %d.\n", status); 667 668 return status; 669 } 670 671 static void hclgevf_set_promisc_mode(struct hnae3_handle *handle, u32 en) 672 { 673 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 674 675 hclgevf_cmd_set_promisc_mode(hdev, en); 676 } 677 678 static int hclgevf_tqp_enable(struct hclgevf_dev *hdev, int tqp_id, 679 int stream_id, bool enable) 680 { 681 struct hclgevf_cfg_com_tqp_queue_cmd *req; 682 struct hclgevf_desc desc; 683 int status; 684 685 req = (struct hclgevf_cfg_com_tqp_queue_cmd *)desc.data; 686 687 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_CFG_COM_TQP_QUEUE, 688 false); 689 req->tqp_id = cpu_to_le16(tqp_id & HCLGEVF_RING_ID_MASK); 690 req->stream_id = cpu_to_le16(stream_id); 691 req->enable |= enable << HCLGEVF_TQP_ENABLE_B; 692 693 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 694 if (status) 695 dev_err(&hdev->pdev->dev, 696 "TQP enable fail, status =%d.\n", status); 697 698 return status; 699 } 700 701 static int hclgevf_get_queue_id(struct hnae3_queue *queue) 702 { 703 struct hclgevf_tqp *tqp = container_of(queue, struct hclgevf_tqp, q); 704 705 return tqp->index; 706 } 707 708 static void hclgevf_reset_tqp_stats(struct hnae3_handle *handle) 709 { 710 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 711 struct hnae3_queue *queue; 712 struct hclgevf_tqp *tqp; 713 int i; 714 715 for (i = 0; i < hdev->num_tqps; i++) { 716 queue = handle->kinfo.tqp[i]; 717 tqp = container_of(queue, struct hclgevf_tqp, q); 718 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats)); 719 } 720 } 721 722 static int hclgevf_cfg_func_mta_filter(struct hnae3_handle *handle, bool en) 723 { 724 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 725 u8 msg[2] = {0}; 726 727 msg[0] = en; 728 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 729 HCLGE_MBX_MAC_VLAN_MC_FUNC_MTA_ENABLE, 730 msg, 1, false, NULL, 0); 731 } 732 733 static void hclgevf_get_mac_addr(struct hnae3_handle *handle, u8 *p) 734 { 735 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 736 737 ether_addr_copy(p, hdev->hw.mac.mac_addr); 738 } 739 740 static int hclgevf_set_mac_addr(struct hnae3_handle *handle, void *p) 741 { 742 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 743 u8 *old_mac_addr = (u8 *)hdev->hw.mac.mac_addr; 744 u8 *new_mac_addr = (u8 *)p; 745 u8 msg_data[ETH_ALEN * 2]; 746 int status; 747 748 ether_addr_copy(msg_data, new_mac_addr); 749 ether_addr_copy(&msg_data[ETH_ALEN], old_mac_addr); 750 751 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 752 HCLGE_MBX_MAC_VLAN_UC_MODIFY, 753 msg_data, ETH_ALEN * 2, 754 false, NULL, 0); 755 if (!status) 756 ether_addr_copy(hdev->hw.mac.mac_addr, new_mac_addr); 757 758 return status; 759 } 760 761 static int hclgevf_add_uc_addr(struct hnae3_handle *handle, 762 const unsigned char *addr) 763 { 764 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 765 766 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 767 HCLGE_MBX_MAC_VLAN_UC_ADD, 768 addr, ETH_ALEN, false, NULL, 0); 769 } 770 771 static int hclgevf_rm_uc_addr(struct hnae3_handle *handle, 772 const unsigned char *addr) 773 { 774 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 775 776 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 777 HCLGE_MBX_MAC_VLAN_UC_REMOVE, 778 addr, ETH_ALEN, false, NULL, 0); 779 } 780 781 static int hclgevf_add_mc_addr(struct hnae3_handle *handle, 782 const unsigned char *addr) 783 { 784 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 785 786 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 787 HCLGE_MBX_MAC_VLAN_MC_ADD, 788 addr, ETH_ALEN, false, NULL, 0); 789 } 790 791 static int hclgevf_rm_mc_addr(struct hnae3_handle *handle, 792 const unsigned char *addr) 793 { 794 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 795 796 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 797 HCLGE_MBX_MAC_VLAN_MC_REMOVE, 798 addr, ETH_ALEN, false, NULL, 0); 799 } 800 801 static int hclgevf_set_vlan_filter(struct hnae3_handle *handle, 802 __be16 proto, u16 vlan_id, 803 bool is_kill) 804 { 805 #define HCLGEVF_VLAN_MBX_MSG_LEN 5 806 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 807 u8 msg_data[HCLGEVF_VLAN_MBX_MSG_LEN]; 808 809 if (vlan_id > 4095) 810 return -EINVAL; 811 812 if (proto != htons(ETH_P_8021Q)) 813 return -EPROTONOSUPPORT; 814 815 msg_data[0] = is_kill; 816 memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id)); 817 memcpy(&msg_data[3], &proto, sizeof(proto)); 818 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 819 HCLGE_MBX_VLAN_FILTER, msg_data, 820 HCLGEVF_VLAN_MBX_MSG_LEN, false, NULL, 0); 821 } 822 823 static void hclgevf_reset_tqp(struct hnae3_handle *handle, u16 queue_id) 824 { 825 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 826 u8 msg_data[2]; 827 828 memcpy(&msg_data[0], &queue_id, sizeof(queue_id)); 829 830 hclgevf_send_mbx_msg(hdev, HCLGE_MBX_QUEUE_RESET, 0, msg_data, 2, false, 831 NULL, 0); 832 } 833 834 static u32 hclgevf_get_fw_version(struct hnae3_handle *handle) 835 { 836 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 837 838 return hdev->fw_version; 839 } 840 841 static void hclgevf_get_misc_vector(struct hclgevf_dev *hdev) 842 { 843 struct hclgevf_misc_vector *vector = &hdev->misc_vector; 844 845 vector->vector_irq = pci_irq_vector(hdev->pdev, 846 HCLGEVF_MISC_VECTOR_NUM); 847 vector->addr = hdev->hw.io_base + HCLGEVF_MISC_VECTOR_REG_BASE; 848 /* vector status always valid for Vector 0 */ 849 hdev->vector_status[HCLGEVF_MISC_VECTOR_NUM] = 0; 850 hdev->vector_irq[HCLGEVF_MISC_VECTOR_NUM] = vector->vector_irq; 851 852 hdev->num_msi_left -= 1; 853 hdev->num_msi_used += 1; 854 } 855 856 static void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev) 857 { 858 if (!test_and_set_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state)) 859 schedule_work(&hdev->mbx_service_task); 860 } 861 862 static void hclgevf_task_schedule(struct hclgevf_dev *hdev) 863 { 864 if (!test_bit(HCLGEVF_STATE_DOWN, &hdev->state) && 865 !test_and_set_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state)) 866 schedule_work(&hdev->service_task); 867 } 868 869 static void hclgevf_service_timer(struct timer_list *t) 870 { 871 struct hclgevf_dev *hdev = from_timer(hdev, t, service_timer); 872 873 mod_timer(&hdev->service_timer, jiffies + 5 * HZ); 874 875 hclgevf_task_schedule(hdev); 876 } 877 878 static void hclgevf_mailbox_service_task(struct work_struct *work) 879 { 880 struct hclgevf_dev *hdev; 881 882 hdev = container_of(work, struct hclgevf_dev, mbx_service_task); 883 884 if (test_and_set_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) 885 return; 886 887 clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 888 889 hclgevf_mbx_handler(hdev); 890 891 clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 892 } 893 894 static void hclgevf_service_task(struct work_struct *work) 895 { 896 struct hclgevf_dev *hdev; 897 898 hdev = container_of(work, struct hclgevf_dev, service_task); 899 900 /* request the link status from the PF. PF would be able to tell VF 901 * about such updates in future so we might remove this later 902 */ 903 hclgevf_request_link_info(hdev); 904 905 clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 906 } 907 908 static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regclr) 909 { 910 hclgevf_write_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_SRC_REG, regclr); 911 } 912 913 static bool hclgevf_check_event_cause(struct hclgevf_dev *hdev, u32 *clearval) 914 { 915 u32 cmdq_src_reg; 916 917 /* fetch the events from their corresponding regs */ 918 cmdq_src_reg = hclgevf_read_dev(&hdev->hw, 919 HCLGEVF_VECTOR0_CMDQ_SRC_REG); 920 921 /* check for vector0 mailbox(=CMDQ RX) event source */ 922 if (BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) { 923 cmdq_src_reg &= ~BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 924 *clearval = cmdq_src_reg; 925 return true; 926 } 927 928 dev_dbg(&hdev->pdev->dev, "vector 0 interrupt from unknown source\n"); 929 930 return false; 931 } 932 933 static void hclgevf_enable_vector(struct hclgevf_misc_vector *vector, bool en) 934 { 935 writel(en ? 1 : 0, vector->addr); 936 } 937 938 static irqreturn_t hclgevf_misc_irq_handle(int irq, void *data) 939 { 940 struct hclgevf_dev *hdev = data; 941 u32 clearval; 942 943 hclgevf_enable_vector(&hdev->misc_vector, false); 944 if (!hclgevf_check_event_cause(hdev, &clearval)) 945 goto skip_sched; 946 947 /* schedule the VF mailbox service task, if not already scheduled */ 948 hclgevf_mbx_task_schedule(hdev); 949 950 hclgevf_clear_event_cause(hdev, clearval); 951 952 skip_sched: 953 hclgevf_enable_vector(&hdev->misc_vector, true); 954 955 return IRQ_HANDLED; 956 } 957 958 static int hclgevf_configure(struct hclgevf_dev *hdev) 959 { 960 int ret; 961 962 /* get queue configuration from PF */ 963 ret = hclge_get_queue_info(hdev); 964 if (ret) 965 return ret; 966 /* get tc configuration from PF */ 967 return hclgevf_get_tc_info(hdev); 968 } 969 970 static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev) 971 { 972 struct hnae3_handle *roce = &hdev->roce; 973 struct hnae3_handle *nic = &hdev->nic; 974 975 roce->rinfo.num_vectors = HCLGEVF_ROCEE_VECTOR_NUM; 976 977 if (hdev->num_msi_left < roce->rinfo.num_vectors || 978 hdev->num_msi_left == 0) 979 return -EINVAL; 980 981 roce->rinfo.base_vector = 982 hdev->vector_status[hdev->num_msi_used]; 983 984 roce->rinfo.netdev = nic->kinfo.netdev; 985 roce->rinfo.roce_io_base = hdev->hw.io_base; 986 987 roce->pdev = nic->pdev; 988 roce->ae_algo = nic->ae_algo; 989 roce->numa_node_mask = nic->numa_node_mask; 990 991 return 0; 992 } 993 994 static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev) 995 { 996 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 997 int i, ret; 998 999 rss_cfg->rss_size = hdev->rss_size_max; 1000 1001 /* Initialize RSS indirect table for each vport */ 1002 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 1003 rss_cfg->rss_indirection_tbl[i] = i % hdev->rss_size_max; 1004 1005 ret = hclgevf_set_rss_indir_table(hdev); 1006 if (ret) 1007 return ret; 1008 1009 return hclgevf_set_rss_tc_mode(hdev, hdev->rss_size_max); 1010 } 1011 1012 static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev) 1013 { 1014 /* other vlan config(like, VLAN TX/RX offload) would also be added 1015 * here later 1016 */ 1017 return hclgevf_set_vlan_filter(&hdev->nic, htons(ETH_P_8021Q), 0, 1018 false); 1019 } 1020 1021 static int hclgevf_ae_start(struct hnae3_handle *handle) 1022 { 1023 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1024 int i, queue_id; 1025 1026 for (i = 0; i < handle->kinfo.num_tqps; i++) { 1027 /* ring enable */ 1028 queue_id = hclgevf_get_queue_id(handle->kinfo.tqp[i]); 1029 if (queue_id < 0) { 1030 dev_warn(&hdev->pdev->dev, 1031 "Get invalid queue id, ignore it\n"); 1032 continue; 1033 } 1034 1035 hclgevf_tqp_enable(hdev, queue_id, 0, true); 1036 } 1037 1038 /* reset tqp stats */ 1039 hclgevf_reset_tqp_stats(handle); 1040 1041 hclgevf_request_link_info(hdev); 1042 1043 clear_bit(HCLGEVF_STATE_DOWN, &hdev->state); 1044 mod_timer(&hdev->service_timer, jiffies + HZ); 1045 1046 return 0; 1047 } 1048 1049 static void hclgevf_ae_stop(struct hnae3_handle *handle) 1050 { 1051 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1052 int i, queue_id; 1053 1054 for (i = 0; i < hdev->num_tqps; i++) { 1055 /* Ring disable */ 1056 queue_id = hclgevf_get_queue_id(handle->kinfo.tqp[i]); 1057 if (queue_id < 0) { 1058 dev_warn(&hdev->pdev->dev, 1059 "Get invalid queue id, ignore it\n"); 1060 continue; 1061 } 1062 1063 hclgevf_tqp_enable(hdev, queue_id, 0, false); 1064 } 1065 1066 /* reset tqp stats */ 1067 hclgevf_reset_tqp_stats(handle); 1068 } 1069 1070 static void hclgevf_state_init(struct hclgevf_dev *hdev) 1071 { 1072 /* setup tasks for the MBX */ 1073 INIT_WORK(&hdev->mbx_service_task, hclgevf_mailbox_service_task); 1074 clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 1075 clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 1076 1077 /* setup tasks for service timer */ 1078 timer_setup(&hdev->service_timer, hclgevf_service_timer, 0); 1079 1080 INIT_WORK(&hdev->service_task, hclgevf_service_task); 1081 clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 1082 1083 mutex_init(&hdev->mbx_resp.mbx_mutex); 1084 1085 /* bring the device down */ 1086 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 1087 } 1088 1089 static void hclgevf_state_uninit(struct hclgevf_dev *hdev) 1090 { 1091 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 1092 1093 if (hdev->service_timer.function) 1094 del_timer_sync(&hdev->service_timer); 1095 if (hdev->service_task.func) 1096 cancel_work_sync(&hdev->service_task); 1097 if (hdev->mbx_service_task.func) 1098 cancel_work_sync(&hdev->mbx_service_task); 1099 1100 mutex_destroy(&hdev->mbx_resp.mbx_mutex); 1101 } 1102 1103 static int hclgevf_init_msi(struct hclgevf_dev *hdev) 1104 { 1105 struct pci_dev *pdev = hdev->pdev; 1106 int vectors; 1107 int i; 1108 1109 hdev->num_msi = HCLGEVF_MAX_VF_VECTOR_NUM; 1110 1111 vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi, 1112 PCI_IRQ_MSI | PCI_IRQ_MSIX); 1113 if (vectors < 0) { 1114 dev_err(&pdev->dev, 1115 "failed(%d) to allocate MSI/MSI-X vectors\n", 1116 vectors); 1117 return vectors; 1118 } 1119 if (vectors < hdev->num_msi) 1120 dev_warn(&hdev->pdev->dev, 1121 "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n", 1122 hdev->num_msi, vectors); 1123 1124 hdev->num_msi = vectors; 1125 hdev->num_msi_left = vectors; 1126 hdev->base_msi_vector = pdev->irq; 1127 1128 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 1129 sizeof(u16), GFP_KERNEL); 1130 if (!hdev->vector_status) { 1131 pci_free_irq_vectors(pdev); 1132 return -ENOMEM; 1133 } 1134 1135 for (i = 0; i < hdev->num_msi; i++) 1136 hdev->vector_status[i] = HCLGEVF_INVALID_VPORT; 1137 1138 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 1139 sizeof(int), GFP_KERNEL); 1140 if (!hdev->vector_irq) { 1141 pci_free_irq_vectors(pdev); 1142 return -ENOMEM; 1143 } 1144 1145 return 0; 1146 } 1147 1148 static void hclgevf_uninit_msi(struct hclgevf_dev *hdev) 1149 { 1150 struct pci_dev *pdev = hdev->pdev; 1151 1152 pci_free_irq_vectors(pdev); 1153 } 1154 1155 static int hclgevf_misc_irq_init(struct hclgevf_dev *hdev) 1156 { 1157 int ret = 0; 1158 1159 hclgevf_get_misc_vector(hdev); 1160 1161 ret = request_irq(hdev->misc_vector.vector_irq, hclgevf_misc_irq_handle, 1162 0, "hclgevf_cmd", hdev); 1163 if (ret) { 1164 dev_err(&hdev->pdev->dev, "VF failed to request misc irq(%d)\n", 1165 hdev->misc_vector.vector_irq); 1166 return ret; 1167 } 1168 1169 /* enable misc. vector(vector 0) */ 1170 hclgevf_enable_vector(&hdev->misc_vector, true); 1171 1172 return ret; 1173 } 1174 1175 static void hclgevf_misc_irq_uninit(struct hclgevf_dev *hdev) 1176 { 1177 /* disable misc vector(vector 0) */ 1178 hclgevf_enable_vector(&hdev->misc_vector, false); 1179 free_irq(hdev->misc_vector.vector_irq, hdev); 1180 hclgevf_free_vector(hdev, 0); 1181 } 1182 1183 static int hclgevf_init_instance(struct hclgevf_dev *hdev, 1184 struct hnae3_client *client) 1185 { 1186 int ret; 1187 1188 switch (client->type) { 1189 case HNAE3_CLIENT_KNIC: 1190 hdev->nic_client = client; 1191 hdev->nic.client = client; 1192 1193 ret = client->ops->init_instance(&hdev->nic); 1194 if (ret) 1195 return ret; 1196 1197 if (hdev->roce_client && hnae3_dev_roce_supported(hdev)) { 1198 struct hnae3_client *rc = hdev->roce_client; 1199 1200 ret = hclgevf_init_roce_base_info(hdev); 1201 if (ret) 1202 return ret; 1203 ret = rc->ops->init_instance(&hdev->roce); 1204 if (ret) 1205 return ret; 1206 } 1207 break; 1208 case HNAE3_CLIENT_UNIC: 1209 hdev->nic_client = client; 1210 hdev->nic.client = client; 1211 1212 ret = client->ops->init_instance(&hdev->nic); 1213 if (ret) 1214 return ret; 1215 break; 1216 case HNAE3_CLIENT_ROCE: 1217 hdev->roce_client = client; 1218 hdev->roce.client = client; 1219 1220 if (hdev->roce_client && hnae3_dev_roce_supported(hdev)) { 1221 ret = hclgevf_init_roce_base_info(hdev); 1222 if (ret) 1223 return ret; 1224 1225 ret = client->ops->init_instance(&hdev->roce); 1226 if (ret) 1227 return ret; 1228 } 1229 } 1230 1231 return 0; 1232 } 1233 1234 static void hclgevf_uninit_instance(struct hclgevf_dev *hdev, 1235 struct hnae3_client *client) 1236 { 1237 /* un-init roce, if it exists */ 1238 if (hdev->roce_client) 1239 hdev->roce_client->ops->uninit_instance(&hdev->roce, 0); 1240 1241 /* un-init nic/unic, if this was not called by roce client */ 1242 if ((client->ops->uninit_instance) && 1243 (client->type != HNAE3_CLIENT_ROCE)) 1244 client->ops->uninit_instance(&hdev->nic, 0); 1245 } 1246 1247 static int hclgevf_register_client(struct hnae3_client *client, 1248 struct hnae3_ae_dev *ae_dev) 1249 { 1250 struct hclgevf_dev *hdev = ae_dev->priv; 1251 1252 return hclgevf_init_instance(hdev, client); 1253 } 1254 1255 static void hclgevf_unregister_client(struct hnae3_client *client, 1256 struct hnae3_ae_dev *ae_dev) 1257 { 1258 struct hclgevf_dev *hdev = ae_dev->priv; 1259 1260 hclgevf_uninit_instance(hdev, client); 1261 } 1262 1263 static int hclgevf_pci_init(struct hclgevf_dev *hdev) 1264 { 1265 struct pci_dev *pdev = hdev->pdev; 1266 struct hclgevf_hw *hw; 1267 int ret; 1268 1269 ret = pci_enable_device(pdev); 1270 if (ret) { 1271 dev_err(&pdev->dev, "failed to enable PCI device\n"); 1272 goto err_no_drvdata; 1273 } 1274 1275 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 1276 if (ret) { 1277 dev_err(&pdev->dev, "can't set consistent PCI DMA, exiting"); 1278 goto err_disable_device; 1279 } 1280 1281 ret = pci_request_regions(pdev, HCLGEVF_DRIVER_NAME); 1282 if (ret) { 1283 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 1284 goto err_disable_device; 1285 } 1286 1287 pci_set_master(pdev); 1288 hw = &hdev->hw; 1289 hw->hdev = hdev; 1290 hw->io_base = pci_iomap(pdev, 2, 0);; 1291 if (!hw->io_base) { 1292 dev_err(&pdev->dev, "can't map configuration register space\n"); 1293 ret = -ENOMEM; 1294 goto err_clr_master; 1295 } 1296 1297 return 0; 1298 1299 err_clr_master: 1300 pci_clear_master(pdev); 1301 pci_release_regions(pdev); 1302 err_disable_device: 1303 pci_disable_device(pdev); 1304 err_no_drvdata: 1305 pci_set_drvdata(pdev, NULL); 1306 return ret; 1307 } 1308 1309 static void hclgevf_pci_uninit(struct hclgevf_dev *hdev) 1310 { 1311 struct pci_dev *pdev = hdev->pdev; 1312 1313 pci_iounmap(pdev, hdev->hw.io_base); 1314 pci_clear_master(pdev); 1315 pci_release_regions(pdev); 1316 pci_disable_device(pdev); 1317 pci_set_drvdata(pdev, NULL); 1318 } 1319 1320 static int hclgevf_init_ae_dev(struct hnae3_ae_dev *ae_dev) 1321 { 1322 struct pci_dev *pdev = ae_dev->pdev; 1323 struct hclgevf_dev *hdev; 1324 int ret; 1325 1326 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 1327 if (!hdev) 1328 return -ENOMEM; 1329 1330 hdev->pdev = pdev; 1331 hdev->ae_dev = ae_dev; 1332 ae_dev->priv = hdev; 1333 1334 ret = hclgevf_pci_init(hdev); 1335 if (ret) { 1336 dev_err(&pdev->dev, "PCI initialization failed\n"); 1337 return ret; 1338 } 1339 1340 ret = hclgevf_init_msi(hdev); 1341 if (ret) { 1342 dev_err(&pdev->dev, "failed(%d) to init MSI/MSI-X\n", ret); 1343 goto err_irq_init; 1344 } 1345 1346 hclgevf_state_init(hdev); 1347 1348 ret = hclgevf_misc_irq_init(hdev); 1349 if (ret) { 1350 dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 1351 ret); 1352 goto err_misc_irq_init; 1353 } 1354 1355 ret = hclgevf_cmd_init(hdev); 1356 if (ret) 1357 goto err_cmd_init; 1358 1359 ret = hclgevf_configure(hdev); 1360 if (ret) { 1361 dev_err(&pdev->dev, "failed(%d) to fetch configuration\n", ret); 1362 goto err_config; 1363 } 1364 1365 ret = hclgevf_alloc_tqps(hdev); 1366 if (ret) { 1367 dev_err(&pdev->dev, "failed(%d) to allocate TQPs\n", ret); 1368 goto err_config; 1369 } 1370 1371 ret = hclgevf_set_handle_info(hdev); 1372 if (ret) { 1373 dev_err(&pdev->dev, "failed(%d) to set handle info\n", ret); 1374 goto err_config; 1375 } 1376 1377 ret = hclgevf_enable_tso(hdev, true); 1378 if (ret) { 1379 dev_err(&pdev->dev, "failed(%d) to enable tso\n", ret); 1380 goto err_config; 1381 } 1382 1383 /* Initialize VF's MTA */ 1384 hdev->accept_mta_mc = true; 1385 ret = hclgevf_cfg_func_mta_filter(&hdev->nic, hdev->accept_mta_mc); 1386 if (ret) { 1387 dev_err(&hdev->pdev->dev, 1388 "failed(%d) to set mta filter mode\n", ret); 1389 goto err_config; 1390 } 1391 1392 /* Initialize RSS for this VF */ 1393 ret = hclgevf_rss_init_hw(hdev); 1394 if (ret) { 1395 dev_err(&hdev->pdev->dev, 1396 "failed(%d) to initialize RSS\n", ret); 1397 goto err_config; 1398 } 1399 1400 ret = hclgevf_init_vlan_config(hdev); 1401 if (ret) { 1402 dev_err(&hdev->pdev->dev, 1403 "failed(%d) to initialize VLAN config\n", ret); 1404 goto err_config; 1405 } 1406 1407 pr_info("finished initializing %s driver\n", HCLGEVF_DRIVER_NAME); 1408 1409 return 0; 1410 1411 err_config: 1412 hclgevf_cmd_uninit(hdev); 1413 err_cmd_init: 1414 hclgevf_misc_irq_uninit(hdev); 1415 err_misc_irq_init: 1416 hclgevf_state_uninit(hdev); 1417 hclgevf_uninit_msi(hdev); 1418 err_irq_init: 1419 hclgevf_pci_uninit(hdev); 1420 return ret; 1421 } 1422 1423 static void hclgevf_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 1424 { 1425 struct hclgevf_dev *hdev = ae_dev->priv; 1426 1427 hclgevf_cmd_uninit(hdev); 1428 hclgevf_misc_irq_uninit(hdev); 1429 hclgevf_state_uninit(hdev); 1430 hclgevf_uninit_msi(hdev); 1431 hclgevf_pci_uninit(hdev); 1432 ae_dev->priv = NULL; 1433 } 1434 1435 static const struct hnae3_ae_ops hclgevf_ops = { 1436 .init_ae_dev = hclgevf_init_ae_dev, 1437 .uninit_ae_dev = hclgevf_uninit_ae_dev, 1438 .init_client_instance = hclgevf_register_client, 1439 .uninit_client_instance = hclgevf_unregister_client, 1440 .start = hclgevf_ae_start, 1441 .stop = hclgevf_ae_stop, 1442 .map_ring_to_vector = hclgevf_map_ring_to_vector, 1443 .unmap_ring_from_vector = hclgevf_unmap_ring_from_vector, 1444 .get_vector = hclgevf_get_vector, 1445 .reset_queue = hclgevf_reset_tqp, 1446 .set_promisc_mode = hclgevf_set_promisc_mode, 1447 .get_mac_addr = hclgevf_get_mac_addr, 1448 .set_mac_addr = hclgevf_set_mac_addr, 1449 .add_uc_addr = hclgevf_add_uc_addr, 1450 .rm_uc_addr = hclgevf_rm_uc_addr, 1451 .add_mc_addr = hclgevf_add_mc_addr, 1452 .rm_mc_addr = hclgevf_rm_mc_addr, 1453 .get_stats = hclgevf_get_stats, 1454 .update_stats = hclgevf_update_stats, 1455 .get_strings = hclgevf_get_strings, 1456 .get_sset_count = hclgevf_get_sset_count, 1457 .get_rss_key_size = hclgevf_get_rss_key_size, 1458 .get_rss_indir_size = hclgevf_get_rss_indir_size, 1459 .get_rss = hclgevf_get_rss, 1460 .set_rss = hclgevf_set_rss, 1461 .get_tc_size = hclgevf_get_tc_size, 1462 .get_fw_version = hclgevf_get_fw_version, 1463 .set_vlan_filter = hclgevf_set_vlan_filter, 1464 }; 1465 1466 static struct hnae3_ae_algo ae_algovf = { 1467 .ops = &hclgevf_ops, 1468 .name = HCLGEVF_NAME, 1469 .pdev_id_table = ae_algovf_pci_tbl, 1470 }; 1471 1472 static int hclgevf_init(void) 1473 { 1474 pr_info("%s is initializing\n", HCLGEVF_NAME); 1475 1476 return hnae3_register_ae_algo(&ae_algovf); 1477 } 1478 1479 static void hclgevf_exit(void) 1480 { 1481 hnae3_unregister_ae_algo(&ae_algovf); 1482 } 1483 module_init(hclgevf_init); 1484 module_exit(hclgevf_exit); 1485 1486 MODULE_LICENSE("GPL"); 1487 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 1488 MODULE_DESCRIPTION("HCLGEVF Driver"); 1489 MODULE_VERSION(HCLGEVF_MOD_VERSION); 1490