1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/etherdevice.h> 5 #include <linux/iopoll.h> 6 #include <net/rtnetlink.h> 7 #include "hclgevf_cmd.h" 8 #include "hclgevf_main.h" 9 #include "hclge_mbx.h" 10 #include "hnae3.h" 11 12 #define HCLGEVF_NAME "hclgevf" 13 14 #define HCLGEVF_RESET_MAX_FAIL_CNT 5 15 16 static int hclgevf_reset_hdev(struct hclgevf_dev *hdev); 17 static struct hnae3_ae_algo ae_algovf; 18 19 static const struct pci_device_id ae_algovf_pci_tbl[] = { 20 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0}, 21 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF), 0}, 22 /* required last entry */ 23 {0, } 24 }; 25 26 static const u8 hclgevf_hash_key[] = { 27 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2, 28 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0, 29 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4, 30 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C, 31 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA 32 }; 33 34 MODULE_DEVICE_TABLE(pci, ae_algovf_pci_tbl); 35 36 static const u32 cmdq_reg_addr_list[] = {HCLGEVF_CMDQ_TX_ADDR_L_REG, 37 HCLGEVF_CMDQ_TX_ADDR_H_REG, 38 HCLGEVF_CMDQ_TX_DEPTH_REG, 39 HCLGEVF_CMDQ_TX_TAIL_REG, 40 HCLGEVF_CMDQ_TX_HEAD_REG, 41 HCLGEVF_CMDQ_RX_ADDR_L_REG, 42 HCLGEVF_CMDQ_RX_ADDR_H_REG, 43 HCLGEVF_CMDQ_RX_DEPTH_REG, 44 HCLGEVF_CMDQ_RX_TAIL_REG, 45 HCLGEVF_CMDQ_RX_HEAD_REG, 46 HCLGEVF_VECTOR0_CMDQ_SRC_REG, 47 HCLGEVF_CMDQ_INTR_STS_REG, 48 HCLGEVF_CMDQ_INTR_EN_REG, 49 HCLGEVF_CMDQ_INTR_GEN_REG}; 50 51 static const u32 common_reg_addr_list[] = {HCLGEVF_MISC_VECTOR_REG_BASE, 52 HCLGEVF_RST_ING, 53 HCLGEVF_GRO_EN_REG}; 54 55 static const u32 ring_reg_addr_list[] = {HCLGEVF_RING_RX_ADDR_L_REG, 56 HCLGEVF_RING_RX_ADDR_H_REG, 57 HCLGEVF_RING_RX_BD_NUM_REG, 58 HCLGEVF_RING_RX_BD_LENGTH_REG, 59 HCLGEVF_RING_RX_MERGE_EN_REG, 60 HCLGEVF_RING_RX_TAIL_REG, 61 HCLGEVF_RING_RX_HEAD_REG, 62 HCLGEVF_RING_RX_FBD_NUM_REG, 63 HCLGEVF_RING_RX_OFFSET_REG, 64 HCLGEVF_RING_RX_FBD_OFFSET_REG, 65 HCLGEVF_RING_RX_STASH_REG, 66 HCLGEVF_RING_RX_BD_ERR_REG, 67 HCLGEVF_RING_TX_ADDR_L_REG, 68 HCLGEVF_RING_TX_ADDR_H_REG, 69 HCLGEVF_RING_TX_BD_NUM_REG, 70 HCLGEVF_RING_TX_PRIORITY_REG, 71 HCLGEVF_RING_TX_TC_REG, 72 HCLGEVF_RING_TX_MERGE_EN_REG, 73 HCLGEVF_RING_TX_TAIL_REG, 74 HCLGEVF_RING_TX_HEAD_REG, 75 HCLGEVF_RING_TX_FBD_NUM_REG, 76 HCLGEVF_RING_TX_OFFSET_REG, 77 HCLGEVF_RING_TX_EBD_NUM_REG, 78 HCLGEVF_RING_TX_EBD_OFFSET_REG, 79 HCLGEVF_RING_TX_BD_ERR_REG, 80 HCLGEVF_RING_EN_REG}; 81 82 static const u32 tqp_intr_reg_addr_list[] = {HCLGEVF_TQP_INTR_CTRL_REG, 83 HCLGEVF_TQP_INTR_GL0_REG, 84 HCLGEVF_TQP_INTR_GL1_REG, 85 HCLGEVF_TQP_INTR_GL2_REG, 86 HCLGEVF_TQP_INTR_RL_REG}; 87 88 static struct hclgevf_dev *hclgevf_ae_get_hdev(struct hnae3_handle *handle) 89 { 90 if (!handle->client) 91 return container_of(handle, struct hclgevf_dev, nic); 92 else if (handle->client->type == HNAE3_CLIENT_ROCE) 93 return container_of(handle, struct hclgevf_dev, roce); 94 else 95 return container_of(handle, struct hclgevf_dev, nic); 96 } 97 98 static int hclgevf_tqps_update_stats(struct hnae3_handle *handle) 99 { 100 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 101 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 102 struct hclgevf_desc desc; 103 struct hclgevf_tqp *tqp; 104 int status; 105 int i; 106 107 for (i = 0; i < kinfo->num_tqps; i++) { 108 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 109 hclgevf_cmd_setup_basic_desc(&desc, 110 HCLGEVF_OPC_QUERY_RX_STATUS, 111 true); 112 113 desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 114 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 115 if (status) { 116 dev_err(&hdev->pdev->dev, 117 "Query tqp stat fail, status = %d,queue = %d\n", 118 status, i); 119 return status; 120 } 121 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd += 122 le32_to_cpu(desc.data[1]); 123 124 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_TX_STATUS, 125 true); 126 127 desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 128 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 129 if (status) { 130 dev_err(&hdev->pdev->dev, 131 "Query tqp stat fail, status = %d,queue = %d\n", 132 status, i); 133 return status; 134 } 135 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd += 136 le32_to_cpu(desc.data[1]); 137 } 138 139 return 0; 140 } 141 142 static u64 *hclgevf_tqps_get_stats(struct hnae3_handle *handle, u64 *data) 143 { 144 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 145 struct hclgevf_tqp *tqp; 146 u64 *buff = data; 147 int i; 148 149 for (i = 0; i < kinfo->num_tqps; i++) { 150 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 151 *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd; 152 } 153 for (i = 0; i < kinfo->num_tqps; i++) { 154 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 155 *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd; 156 } 157 158 return buff; 159 } 160 161 static int hclgevf_tqps_get_sset_count(struct hnae3_handle *handle, int strset) 162 { 163 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 164 165 return kinfo->num_tqps * 2; 166 } 167 168 static u8 *hclgevf_tqps_get_strings(struct hnae3_handle *handle, u8 *data) 169 { 170 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 171 u8 *buff = data; 172 int i = 0; 173 174 for (i = 0; i < kinfo->num_tqps; i++) { 175 struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 176 struct hclgevf_tqp, q); 177 snprintf(buff, ETH_GSTRING_LEN, "txq%d_pktnum_rcd", 178 tqp->index); 179 buff += ETH_GSTRING_LEN; 180 } 181 182 for (i = 0; i < kinfo->num_tqps; i++) { 183 struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 184 struct hclgevf_tqp, q); 185 snprintf(buff, ETH_GSTRING_LEN, "rxq%d_pktnum_rcd", 186 tqp->index); 187 buff += ETH_GSTRING_LEN; 188 } 189 190 return buff; 191 } 192 193 static void hclgevf_update_stats(struct hnae3_handle *handle, 194 struct net_device_stats *net_stats) 195 { 196 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 197 int status; 198 199 status = hclgevf_tqps_update_stats(handle); 200 if (status) 201 dev_err(&hdev->pdev->dev, 202 "VF update of TQPS stats fail, status = %d.\n", 203 status); 204 } 205 206 static int hclgevf_get_sset_count(struct hnae3_handle *handle, int strset) 207 { 208 if (strset == ETH_SS_TEST) 209 return -EOPNOTSUPP; 210 else if (strset == ETH_SS_STATS) 211 return hclgevf_tqps_get_sset_count(handle, strset); 212 213 return 0; 214 } 215 216 static void hclgevf_get_strings(struct hnae3_handle *handle, u32 strset, 217 u8 *data) 218 { 219 u8 *p = (char *)data; 220 221 if (strset == ETH_SS_STATS) 222 p = hclgevf_tqps_get_strings(handle, p); 223 } 224 225 static void hclgevf_get_stats(struct hnae3_handle *handle, u64 *data) 226 { 227 hclgevf_tqps_get_stats(handle, data); 228 } 229 230 static int hclgevf_get_tc_info(struct hclgevf_dev *hdev) 231 { 232 u8 resp_msg; 233 int status; 234 235 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_TCINFO, 0, NULL, 0, 236 true, &resp_msg, sizeof(resp_msg)); 237 if (status) { 238 dev_err(&hdev->pdev->dev, 239 "VF request to get TC info from PF failed %d", 240 status); 241 return status; 242 } 243 244 hdev->hw_tc_map = resp_msg; 245 246 return 0; 247 } 248 249 static int hclgevf_get_port_base_vlan_filter_state(struct hclgevf_dev *hdev) 250 { 251 struct hnae3_handle *nic = &hdev->nic; 252 u8 resp_msg; 253 int ret; 254 255 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 256 HCLGE_MBX_GET_PORT_BASE_VLAN_STATE, 257 NULL, 0, true, &resp_msg, sizeof(u8)); 258 if (ret) { 259 dev_err(&hdev->pdev->dev, 260 "VF request to get port based vlan state failed %d", 261 ret); 262 return ret; 263 } 264 265 nic->port_base_vlan_state = resp_msg; 266 267 return 0; 268 } 269 270 static int hclgevf_get_queue_info(struct hclgevf_dev *hdev) 271 { 272 #define HCLGEVF_TQPS_RSS_INFO_LEN 6 273 u8 resp_msg[HCLGEVF_TQPS_RSS_INFO_LEN]; 274 int status; 275 276 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QINFO, 0, NULL, 0, 277 true, resp_msg, 278 HCLGEVF_TQPS_RSS_INFO_LEN); 279 if (status) { 280 dev_err(&hdev->pdev->dev, 281 "VF request to get tqp info from PF failed %d", 282 status); 283 return status; 284 } 285 286 memcpy(&hdev->num_tqps, &resp_msg[0], sizeof(u16)); 287 memcpy(&hdev->rss_size_max, &resp_msg[2], sizeof(u16)); 288 memcpy(&hdev->rx_buf_len, &resp_msg[4], sizeof(u16)); 289 290 return 0; 291 } 292 293 static int hclgevf_get_queue_depth(struct hclgevf_dev *hdev) 294 { 295 #define HCLGEVF_TQPS_DEPTH_INFO_LEN 4 296 u8 resp_msg[HCLGEVF_TQPS_DEPTH_INFO_LEN]; 297 int ret; 298 299 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QDEPTH, 0, NULL, 0, 300 true, resp_msg, 301 HCLGEVF_TQPS_DEPTH_INFO_LEN); 302 if (ret) { 303 dev_err(&hdev->pdev->dev, 304 "VF request to get tqp depth info from PF failed %d", 305 ret); 306 return ret; 307 } 308 309 memcpy(&hdev->num_tx_desc, &resp_msg[0], sizeof(u16)); 310 memcpy(&hdev->num_rx_desc, &resp_msg[2], sizeof(u16)); 311 312 return 0; 313 } 314 315 static u16 hclgevf_get_qid_global(struct hnae3_handle *handle, u16 queue_id) 316 { 317 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 318 u8 msg_data[2], resp_data[2]; 319 u16 qid_in_pf = 0; 320 int ret; 321 322 memcpy(&msg_data[0], &queue_id, sizeof(queue_id)); 323 324 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QID_IN_PF, 0, msg_data, 325 sizeof(msg_data), true, resp_data, 326 sizeof(resp_data)); 327 if (!ret) 328 qid_in_pf = *(u16 *)resp_data; 329 330 return qid_in_pf; 331 } 332 333 static int hclgevf_get_pf_media_type(struct hclgevf_dev *hdev) 334 { 335 u8 resp_msg[2]; 336 int ret; 337 338 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_MEDIA_TYPE, 0, NULL, 0, 339 true, resp_msg, sizeof(resp_msg)); 340 if (ret) { 341 dev_err(&hdev->pdev->dev, 342 "VF request to get the pf port media type failed %d", 343 ret); 344 return ret; 345 } 346 347 hdev->hw.mac.media_type = resp_msg[0]; 348 hdev->hw.mac.module_type = resp_msg[1]; 349 350 return 0; 351 } 352 353 static int hclgevf_alloc_tqps(struct hclgevf_dev *hdev) 354 { 355 struct hclgevf_tqp *tqp; 356 int i; 357 358 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 359 sizeof(struct hclgevf_tqp), GFP_KERNEL); 360 if (!hdev->htqp) 361 return -ENOMEM; 362 363 tqp = hdev->htqp; 364 365 for (i = 0; i < hdev->num_tqps; i++) { 366 tqp->dev = &hdev->pdev->dev; 367 tqp->index = i; 368 369 tqp->q.ae_algo = &ae_algovf; 370 tqp->q.buf_size = hdev->rx_buf_len; 371 tqp->q.tx_desc_num = hdev->num_tx_desc; 372 tqp->q.rx_desc_num = hdev->num_rx_desc; 373 tqp->q.io_base = hdev->hw.io_base + HCLGEVF_TQP_REG_OFFSET + 374 i * HCLGEVF_TQP_REG_SIZE; 375 376 tqp++; 377 } 378 379 return 0; 380 } 381 382 static int hclgevf_knic_setup(struct hclgevf_dev *hdev) 383 { 384 struct hnae3_handle *nic = &hdev->nic; 385 struct hnae3_knic_private_info *kinfo; 386 u16 new_tqps = hdev->num_tqps; 387 unsigned int i; 388 389 kinfo = &nic->kinfo; 390 kinfo->num_tc = 0; 391 kinfo->num_tx_desc = hdev->num_tx_desc; 392 kinfo->num_rx_desc = hdev->num_rx_desc; 393 kinfo->rx_buf_len = hdev->rx_buf_len; 394 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) 395 if (hdev->hw_tc_map & BIT(i)) 396 kinfo->num_tc++; 397 398 kinfo->rss_size 399 = min_t(u16, hdev->rss_size_max, new_tqps / kinfo->num_tc); 400 new_tqps = kinfo->rss_size * kinfo->num_tc; 401 kinfo->num_tqps = min(new_tqps, hdev->num_tqps); 402 403 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps, 404 sizeof(struct hnae3_queue *), GFP_KERNEL); 405 if (!kinfo->tqp) 406 return -ENOMEM; 407 408 for (i = 0; i < kinfo->num_tqps; i++) { 409 hdev->htqp[i].q.handle = &hdev->nic; 410 hdev->htqp[i].q.tqp_index = i; 411 kinfo->tqp[i] = &hdev->htqp[i].q; 412 } 413 414 return 0; 415 } 416 417 static void hclgevf_request_link_info(struct hclgevf_dev *hdev) 418 { 419 int status; 420 u8 resp_msg; 421 422 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_STATUS, 0, NULL, 423 0, false, &resp_msg, sizeof(resp_msg)); 424 if (status) 425 dev_err(&hdev->pdev->dev, 426 "VF failed to fetch link status(%d) from PF", status); 427 } 428 429 void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state) 430 { 431 struct hnae3_handle *rhandle = &hdev->roce; 432 struct hnae3_handle *handle = &hdev->nic; 433 struct hnae3_client *rclient; 434 struct hnae3_client *client; 435 436 client = handle->client; 437 rclient = hdev->roce_client; 438 439 link_state = 440 test_bit(HCLGEVF_STATE_DOWN, &hdev->state) ? 0 : link_state; 441 442 if (link_state != hdev->hw.mac.link) { 443 client->ops->link_status_change(handle, !!link_state); 444 if (rclient && rclient->ops->link_status_change) 445 rclient->ops->link_status_change(rhandle, !!link_state); 446 hdev->hw.mac.link = link_state; 447 } 448 } 449 450 static void hclgevf_update_link_mode(struct hclgevf_dev *hdev) 451 { 452 #define HCLGEVF_ADVERTISING 0 453 #define HCLGEVF_SUPPORTED 1 454 u8 send_msg; 455 u8 resp_msg; 456 457 send_msg = HCLGEVF_ADVERTISING; 458 hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_MODE, 0, 459 &send_msg, sizeof(send_msg), false, 460 &resp_msg, sizeof(resp_msg)); 461 send_msg = HCLGEVF_SUPPORTED; 462 hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_MODE, 0, 463 &send_msg, sizeof(send_msg), false, 464 &resp_msg, sizeof(resp_msg)); 465 } 466 467 static int hclgevf_set_handle_info(struct hclgevf_dev *hdev) 468 { 469 struct hnae3_handle *nic = &hdev->nic; 470 int ret; 471 472 nic->ae_algo = &ae_algovf; 473 nic->pdev = hdev->pdev; 474 nic->numa_node_mask = hdev->numa_node_mask; 475 nic->flags |= HNAE3_SUPPORT_VF; 476 477 ret = hclgevf_knic_setup(hdev); 478 if (ret) 479 dev_err(&hdev->pdev->dev, "VF knic setup failed %d\n", 480 ret); 481 return ret; 482 } 483 484 static void hclgevf_free_vector(struct hclgevf_dev *hdev, int vector_id) 485 { 486 if (hdev->vector_status[vector_id] == HCLGEVF_INVALID_VPORT) { 487 dev_warn(&hdev->pdev->dev, 488 "vector(vector_id %d) has been freed.\n", vector_id); 489 return; 490 } 491 492 hdev->vector_status[vector_id] = HCLGEVF_INVALID_VPORT; 493 hdev->num_msi_left += 1; 494 hdev->num_msi_used -= 1; 495 } 496 497 static int hclgevf_get_vector(struct hnae3_handle *handle, u16 vector_num, 498 struct hnae3_vector_info *vector_info) 499 { 500 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 501 struct hnae3_vector_info *vector = vector_info; 502 int alloc = 0; 503 int i, j; 504 505 vector_num = min(hdev->num_msi_left, vector_num); 506 507 for (j = 0; j < vector_num; j++) { 508 for (i = HCLGEVF_MISC_VECTOR_NUM + 1; i < hdev->num_msi; i++) { 509 if (hdev->vector_status[i] == HCLGEVF_INVALID_VPORT) { 510 vector->vector = pci_irq_vector(hdev->pdev, i); 511 vector->io_addr = hdev->hw.io_base + 512 HCLGEVF_VECTOR_REG_BASE + 513 (i - 1) * HCLGEVF_VECTOR_REG_OFFSET; 514 hdev->vector_status[i] = 0; 515 hdev->vector_irq[i] = vector->vector; 516 517 vector++; 518 alloc++; 519 520 break; 521 } 522 } 523 } 524 hdev->num_msi_left -= alloc; 525 hdev->num_msi_used += alloc; 526 527 return alloc; 528 } 529 530 static int hclgevf_get_vector_index(struct hclgevf_dev *hdev, int vector) 531 { 532 int i; 533 534 for (i = 0; i < hdev->num_msi; i++) 535 if (vector == hdev->vector_irq[i]) 536 return i; 537 538 return -EINVAL; 539 } 540 541 static int hclgevf_set_rss_algo_key(struct hclgevf_dev *hdev, 542 const u8 hfunc, const u8 *key) 543 { 544 struct hclgevf_rss_config_cmd *req; 545 unsigned int key_offset = 0; 546 struct hclgevf_desc desc; 547 int key_counts; 548 int key_size; 549 int ret; 550 551 key_counts = HCLGEVF_RSS_KEY_SIZE; 552 req = (struct hclgevf_rss_config_cmd *)desc.data; 553 554 while (key_counts) { 555 hclgevf_cmd_setup_basic_desc(&desc, 556 HCLGEVF_OPC_RSS_GENERIC_CONFIG, 557 false); 558 559 req->hash_config |= (hfunc & HCLGEVF_RSS_HASH_ALGO_MASK); 560 req->hash_config |= 561 (key_offset << HCLGEVF_RSS_HASH_KEY_OFFSET_B); 562 563 key_size = min(HCLGEVF_RSS_HASH_KEY_NUM, key_counts); 564 memcpy(req->hash_key, 565 key + key_offset * HCLGEVF_RSS_HASH_KEY_NUM, key_size); 566 567 key_counts -= key_size; 568 key_offset++; 569 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 570 if (ret) { 571 dev_err(&hdev->pdev->dev, 572 "Configure RSS config fail, status = %d\n", 573 ret); 574 return ret; 575 } 576 } 577 578 return 0; 579 } 580 581 static u32 hclgevf_get_rss_key_size(struct hnae3_handle *handle) 582 { 583 return HCLGEVF_RSS_KEY_SIZE; 584 } 585 586 static u32 hclgevf_get_rss_indir_size(struct hnae3_handle *handle) 587 { 588 return HCLGEVF_RSS_IND_TBL_SIZE; 589 } 590 591 static int hclgevf_set_rss_indir_table(struct hclgevf_dev *hdev) 592 { 593 const u8 *indir = hdev->rss_cfg.rss_indirection_tbl; 594 struct hclgevf_rss_indirection_table_cmd *req; 595 struct hclgevf_desc desc; 596 int status; 597 int i, j; 598 599 req = (struct hclgevf_rss_indirection_table_cmd *)desc.data; 600 601 for (i = 0; i < HCLGEVF_RSS_CFG_TBL_NUM; i++) { 602 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INDIR_TABLE, 603 false); 604 req->start_table_index = i * HCLGEVF_RSS_CFG_TBL_SIZE; 605 req->rss_set_bitmap = HCLGEVF_RSS_SET_BITMAP_MSK; 606 for (j = 0; j < HCLGEVF_RSS_CFG_TBL_SIZE; j++) 607 req->rss_result[j] = 608 indir[i * HCLGEVF_RSS_CFG_TBL_SIZE + j]; 609 610 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 611 if (status) { 612 dev_err(&hdev->pdev->dev, 613 "VF failed(=%d) to set RSS indirection table\n", 614 status); 615 return status; 616 } 617 } 618 619 return 0; 620 } 621 622 static int hclgevf_set_rss_tc_mode(struct hclgevf_dev *hdev, u16 rss_size) 623 { 624 struct hclgevf_rss_tc_mode_cmd *req; 625 u16 tc_offset[HCLGEVF_MAX_TC_NUM]; 626 u16 tc_valid[HCLGEVF_MAX_TC_NUM]; 627 u16 tc_size[HCLGEVF_MAX_TC_NUM]; 628 struct hclgevf_desc desc; 629 u16 roundup_size; 630 int status; 631 unsigned int i; 632 633 req = (struct hclgevf_rss_tc_mode_cmd *)desc.data; 634 635 roundup_size = roundup_pow_of_two(rss_size); 636 roundup_size = ilog2(roundup_size); 637 638 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 639 tc_valid[i] = !!(hdev->hw_tc_map & BIT(i)); 640 tc_size[i] = roundup_size; 641 tc_offset[i] = rss_size * i; 642 } 643 644 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_TC_MODE, false); 645 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 646 hnae3_set_bit(req->rss_tc_mode[i], HCLGEVF_RSS_TC_VALID_B, 647 (tc_valid[i] & 0x1)); 648 hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_SIZE_M, 649 HCLGEVF_RSS_TC_SIZE_S, tc_size[i]); 650 hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_OFFSET_M, 651 HCLGEVF_RSS_TC_OFFSET_S, tc_offset[i]); 652 } 653 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 654 if (status) 655 dev_err(&hdev->pdev->dev, 656 "VF failed(=%d) to set rss tc mode\n", status); 657 658 return status; 659 } 660 661 /* for revision 0x20, vf shared the same rss config with pf */ 662 static int hclgevf_get_rss_hash_key(struct hclgevf_dev *hdev) 663 { 664 #define HCLGEVF_RSS_MBX_RESP_LEN 8 665 666 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 667 u8 resp_msg[HCLGEVF_RSS_MBX_RESP_LEN]; 668 u16 msg_num, hash_key_index; 669 u8 index; 670 int ret; 671 672 msg_num = (HCLGEVF_RSS_KEY_SIZE + HCLGEVF_RSS_MBX_RESP_LEN - 1) / 673 HCLGEVF_RSS_MBX_RESP_LEN; 674 for (index = 0; index < msg_num; index++) { 675 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_RSS_KEY, 0, 676 &index, sizeof(index), 677 true, resp_msg, 678 HCLGEVF_RSS_MBX_RESP_LEN); 679 if (ret) { 680 dev_err(&hdev->pdev->dev, 681 "VF get rss hash key from PF failed, ret=%d", 682 ret); 683 return ret; 684 } 685 686 hash_key_index = HCLGEVF_RSS_MBX_RESP_LEN * index; 687 if (index == msg_num - 1) 688 memcpy(&rss_cfg->rss_hash_key[hash_key_index], 689 &resp_msg[0], 690 HCLGEVF_RSS_KEY_SIZE - hash_key_index); 691 else 692 memcpy(&rss_cfg->rss_hash_key[hash_key_index], 693 &resp_msg[0], HCLGEVF_RSS_MBX_RESP_LEN); 694 } 695 696 return 0; 697 } 698 699 static int hclgevf_get_rss(struct hnae3_handle *handle, u32 *indir, u8 *key, 700 u8 *hfunc) 701 { 702 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 703 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 704 int i, ret; 705 706 if (handle->pdev->revision >= 0x21) { 707 /* Get hash algorithm */ 708 if (hfunc) { 709 switch (rss_cfg->hash_algo) { 710 case HCLGEVF_RSS_HASH_ALGO_TOEPLITZ: 711 *hfunc = ETH_RSS_HASH_TOP; 712 break; 713 case HCLGEVF_RSS_HASH_ALGO_SIMPLE: 714 *hfunc = ETH_RSS_HASH_XOR; 715 break; 716 default: 717 *hfunc = ETH_RSS_HASH_UNKNOWN; 718 break; 719 } 720 } 721 722 /* Get the RSS Key required by the user */ 723 if (key) 724 memcpy(key, rss_cfg->rss_hash_key, 725 HCLGEVF_RSS_KEY_SIZE); 726 } else { 727 if (hfunc) 728 *hfunc = ETH_RSS_HASH_TOP; 729 if (key) { 730 ret = hclgevf_get_rss_hash_key(hdev); 731 if (ret) 732 return ret; 733 memcpy(key, rss_cfg->rss_hash_key, 734 HCLGEVF_RSS_KEY_SIZE); 735 } 736 } 737 738 if (indir) 739 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 740 indir[i] = rss_cfg->rss_indirection_tbl[i]; 741 742 return 0; 743 } 744 745 static int hclgevf_set_rss(struct hnae3_handle *handle, const u32 *indir, 746 const u8 *key, const u8 hfunc) 747 { 748 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 749 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 750 int ret, i; 751 752 if (handle->pdev->revision >= 0x21) { 753 /* Set the RSS Hash Key if specififed by the user */ 754 if (key) { 755 switch (hfunc) { 756 case ETH_RSS_HASH_TOP: 757 rss_cfg->hash_algo = 758 HCLGEVF_RSS_HASH_ALGO_TOEPLITZ; 759 break; 760 case ETH_RSS_HASH_XOR: 761 rss_cfg->hash_algo = 762 HCLGEVF_RSS_HASH_ALGO_SIMPLE; 763 break; 764 case ETH_RSS_HASH_NO_CHANGE: 765 break; 766 default: 767 return -EINVAL; 768 } 769 770 ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 771 key); 772 if (ret) 773 return ret; 774 775 /* Update the shadow RSS key with user specified qids */ 776 memcpy(rss_cfg->rss_hash_key, key, 777 HCLGEVF_RSS_KEY_SIZE); 778 } 779 } 780 781 /* update the shadow RSS table with user specified qids */ 782 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 783 rss_cfg->rss_indirection_tbl[i] = indir[i]; 784 785 /* update the hardware */ 786 return hclgevf_set_rss_indir_table(hdev); 787 } 788 789 static u8 hclgevf_get_rss_hash_bits(struct ethtool_rxnfc *nfc) 790 { 791 u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGEVF_S_PORT_BIT : 0; 792 793 if (nfc->data & RXH_L4_B_2_3) 794 hash_sets |= HCLGEVF_D_PORT_BIT; 795 else 796 hash_sets &= ~HCLGEVF_D_PORT_BIT; 797 798 if (nfc->data & RXH_IP_SRC) 799 hash_sets |= HCLGEVF_S_IP_BIT; 800 else 801 hash_sets &= ~HCLGEVF_S_IP_BIT; 802 803 if (nfc->data & RXH_IP_DST) 804 hash_sets |= HCLGEVF_D_IP_BIT; 805 else 806 hash_sets &= ~HCLGEVF_D_IP_BIT; 807 808 if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW) 809 hash_sets |= HCLGEVF_V_TAG_BIT; 810 811 return hash_sets; 812 } 813 814 static int hclgevf_set_rss_tuple(struct hnae3_handle *handle, 815 struct ethtool_rxnfc *nfc) 816 { 817 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 818 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 819 struct hclgevf_rss_input_tuple_cmd *req; 820 struct hclgevf_desc desc; 821 u8 tuple_sets; 822 int ret; 823 824 if (handle->pdev->revision == 0x20) 825 return -EOPNOTSUPP; 826 827 if (nfc->data & 828 ~(RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3)) 829 return -EINVAL; 830 831 req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 832 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 833 834 req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 835 req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 836 req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 837 req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 838 req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 839 req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 840 req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 841 req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 842 843 tuple_sets = hclgevf_get_rss_hash_bits(nfc); 844 switch (nfc->flow_type) { 845 case TCP_V4_FLOW: 846 req->ipv4_tcp_en = tuple_sets; 847 break; 848 case TCP_V6_FLOW: 849 req->ipv6_tcp_en = tuple_sets; 850 break; 851 case UDP_V4_FLOW: 852 req->ipv4_udp_en = tuple_sets; 853 break; 854 case UDP_V6_FLOW: 855 req->ipv6_udp_en = tuple_sets; 856 break; 857 case SCTP_V4_FLOW: 858 req->ipv4_sctp_en = tuple_sets; 859 break; 860 case SCTP_V6_FLOW: 861 if ((nfc->data & RXH_L4_B_0_1) || 862 (nfc->data & RXH_L4_B_2_3)) 863 return -EINVAL; 864 865 req->ipv6_sctp_en = tuple_sets; 866 break; 867 case IPV4_FLOW: 868 req->ipv4_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 869 break; 870 case IPV6_FLOW: 871 req->ipv6_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 872 break; 873 default: 874 return -EINVAL; 875 } 876 877 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 878 if (ret) { 879 dev_err(&hdev->pdev->dev, 880 "Set rss tuple fail, status = %d\n", ret); 881 return ret; 882 } 883 884 rss_cfg->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en; 885 rss_cfg->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en; 886 rss_cfg->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en; 887 rss_cfg->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en; 888 rss_cfg->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en; 889 rss_cfg->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en; 890 rss_cfg->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en; 891 rss_cfg->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en; 892 return 0; 893 } 894 895 static int hclgevf_get_rss_tuple(struct hnae3_handle *handle, 896 struct ethtool_rxnfc *nfc) 897 { 898 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 899 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 900 u8 tuple_sets; 901 902 if (handle->pdev->revision == 0x20) 903 return -EOPNOTSUPP; 904 905 nfc->data = 0; 906 907 switch (nfc->flow_type) { 908 case TCP_V4_FLOW: 909 tuple_sets = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 910 break; 911 case UDP_V4_FLOW: 912 tuple_sets = rss_cfg->rss_tuple_sets.ipv4_udp_en; 913 break; 914 case TCP_V6_FLOW: 915 tuple_sets = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 916 break; 917 case UDP_V6_FLOW: 918 tuple_sets = rss_cfg->rss_tuple_sets.ipv6_udp_en; 919 break; 920 case SCTP_V4_FLOW: 921 tuple_sets = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 922 break; 923 case SCTP_V6_FLOW: 924 tuple_sets = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 925 break; 926 case IPV4_FLOW: 927 case IPV6_FLOW: 928 tuple_sets = HCLGEVF_S_IP_BIT | HCLGEVF_D_IP_BIT; 929 break; 930 default: 931 return -EINVAL; 932 } 933 934 if (!tuple_sets) 935 return 0; 936 937 if (tuple_sets & HCLGEVF_D_PORT_BIT) 938 nfc->data |= RXH_L4_B_2_3; 939 if (tuple_sets & HCLGEVF_S_PORT_BIT) 940 nfc->data |= RXH_L4_B_0_1; 941 if (tuple_sets & HCLGEVF_D_IP_BIT) 942 nfc->data |= RXH_IP_DST; 943 if (tuple_sets & HCLGEVF_S_IP_BIT) 944 nfc->data |= RXH_IP_SRC; 945 946 return 0; 947 } 948 949 static int hclgevf_set_rss_input_tuple(struct hclgevf_dev *hdev, 950 struct hclgevf_rss_cfg *rss_cfg) 951 { 952 struct hclgevf_rss_input_tuple_cmd *req; 953 struct hclgevf_desc desc; 954 int ret; 955 956 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 957 958 req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 959 960 req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 961 req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 962 req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 963 req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 964 req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 965 req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 966 req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 967 req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 968 969 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 970 if (ret) 971 dev_err(&hdev->pdev->dev, 972 "Configure rss input fail, status = %d\n", ret); 973 return ret; 974 } 975 976 static int hclgevf_get_tc_size(struct hnae3_handle *handle) 977 { 978 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 979 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 980 981 return rss_cfg->rss_size; 982 } 983 984 static int hclgevf_bind_ring_to_vector(struct hnae3_handle *handle, bool en, 985 int vector_id, 986 struct hnae3_ring_chain_node *ring_chain) 987 { 988 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 989 struct hnae3_ring_chain_node *node; 990 struct hclge_mbx_vf_to_pf_cmd *req; 991 struct hclgevf_desc desc; 992 int i = 0; 993 int status; 994 u8 type; 995 996 req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data; 997 type = en ? HCLGE_MBX_MAP_RING_TO_VECTOR : 998 HCLGE_MBX_UNMAP_RING_TO_VECTOR; 999 1000 for (node = ring_chain; node; node = node->next) { 1001 int idx_offset = HCLGE_MBX_RING_MAP_BASIC_MSG_NUM + 1002 HCLGE_MBX_RING_NODE_VARIABLE_NUM * i; 1003 1004 if (i == 0) { 1005 hclgevf_cmd_setup_basic_desc(&desc, 1006 HCLGEVF_OPC_MBX_VF_TO_PF, 1007 false); 1008 req->msg[0] = type; 1009 req->msg[1] = vector_id; 1010 } 1011 1012 req->msg[idx_offset] = 1013 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B); 1014 req->msg[idx_offset + 1] = node->tqp_index; 1015 req->msg[idx_offset + 2] = hnae3_get_field(node->int_gl_idx, 1016 HNAE3_RING_GL_IDX_M, 1017 HNAE3_RING_GL_IDX_S); 1018 1019 i++; 1020 if ((i == (HCLGE_MBX_VF_MSG_DATA_NUM - 1021 HCLGE_MBX_RING_MAP_BASIC_MSG_NUM) / 1022 HCLGE_MBX_RING_NODE_VARIABLE_NUM) || 1023 !node->next) { 1024 req->msg[2] = i; 1025 1026 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1027 if (status) { 1028 dev_err(&hdev->pdev->dev, 1029 "Map TQP fail, status is %d.\n", 1030 status); 1031 return status; 1032 } 1033 i = 0; 1034 hclgevf_cmd_setup_basic_desc(&desc, 1035 HCLGEVF_OPC_MBX_VF_TO_PF, 1036 false); 1037 req->msg[0] = type; 1038 req->msg[1] = vector_id; 1039 } 1040 } 1041 1042 return 0; 1043 } 1044 1045 static int hclgevf_map_ring_to_vector(struct hnae3_handle *handle, int vector, 1046 struct hnae3_ring_chain_node *ring_chain) 1047 { 1048 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1049 int vector_id; 1050 1051 vector_id = hclgevf_get_vector_index(hdev, vector); 1052 if (vector_id < 0) { 1053 dev_err(&handle->pdev->dev, 1054 "Get vector index fail. ret =%d\n", vector_id); 1055 return vector_id; 1056 } 1057 1058 return hclgevf_bind_ring_to_vector(handle, true, vector_id, ring_chain); 1059 } 1060 1061 static int hclgevf_unmap_ring_from_vector( 1062 struct hnae3_handle *handle, 1063 int vector, 1064 struct hnae3_ring_chain_node *ring_chain) 1065 { 1066 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1067 int ret, vector_id; 1068 1069 if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 1070 return 0; 1071 1072 vector_id = hclgevf_get_vector_index(hdev, vector); 1073 if (vector_id < 0) { 1074 dev_err(&handle->pdev->dev, 1075 "Get vector index fail. ret =%d\n", vector_id); 1076 return vector_id; 1077 } 1078 1079 ret = hclgevf_bind_ring_to_vector(handle, false, vector_id, ring_chain); 1080 if (ret) 1081 dev_err(&handle->pdev->dev, 1082 "Unmap ring from vector fail. vector=%d, ret =%d\n", 1083 vector_id, 1084 ret); 1085 1086 return ret; 1087 } 1088 1089 static int hclgevf_put_vector(struct hnae3_handle *handle, int vector) 1090 { 1091 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1092 int vector_id; 1093 1094 vector_id = hclgevf_get_vector_index(hdev, vector); 1095 if (vector_id < 0) { 1096 dev_err(&handle->pdev->dev, 1097 "hclgevf_put_vector get vector index fail. ret =%d\n", 1098 vector_id); 1099 return vector_id; 1100 } 1101 1102 hclgevf_free_vector(hdev, vector_id); 1103 1104 return 0; 1105 } 1106 1107 static int hclgevf_cmd_set_promisc_mode(struct hclgevf_dev *hdev, 1108 bool en_uc_pmc, bool en_mc_pmc, 1109 bool en_bc_pmc) 1110 { 1111 struct hclge_mbx_vf_to_pf_cmd *req; 1112 struct hclgevf_desc desc; 1113 int ret; 1114 1115 req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data; 1116 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_MBX_VF_TO_PF, false); 1117 req->msg[0] = HCLGE_MBX_SET_PROMISC_MODE; 1118 req->msg[1] = en_bc_pmc ? 1 : 0; 1119 req->msg[2] = en_uc_pmc ? 1 : 0; 1120 req->msg[3] = en_mc_pmc ? 1 : 0; 1121 1122 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1123 if (ret) 1124 dev_err(&hdev->pdev->dev, 1125 "Set promisc mode fail, status is %d.\n", ret); 1126 1127 return ret; 1128 } 1129 1130 static int hclgevf_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc, 1131 bool en_mc_pmc) 1132 { 1133 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1134 struct pci_dev *pdev = hdev->pdev; 1135 bool en_bc_pmc; 1136 1137 en_bc_pmc = pdev->revision != 0x20; 1138 1139 return hclgevf_cmd_set_promisc_mode(hdev, en_uc_pmc, en_mc_pmc, 1140 en_bc_pmc); 1141 } 1142 1143 static int hclgevf_tqp_enable(struct hclgevf_dev *hdev, unsigned int tqp_id, 1144 int stream_id, bool enable) 1145 { 1146 struct hclgevf_cfg_com_tqp_queue_cmd *req; 1147 struct hclgevf_desc desc; 1148 int status; 1149 1150 req = (struct hclgevf_cfg_com_tqp_queue_cmd *)desc.data; 1151 1152 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_CFG_COM_TQP_QUEUE, 1153 false); 1154 req->tqp_id = cpu_to_le16(tqp_id & HCLGEVF_RING_ID_MASK); 1155 req->stream_id = cpu_to_le16(stream_id); 1156 if (enable) 1157 req->enable |= 1U << HCLGEVF_TQP_ENABLE_B; 1158 1159 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1160 if (status) 1161 dev_err(&hdev->pdev->dev, 1162 "TQP enable fail, status =%d.\n", status); 1163 1164 return status; 1165 } 1166 1167 static void hclgevf_reset_tqp_stats(struct hnae3_handle *handle) 1168 { 1169 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 1170 struct hclgevf_tqp *tqp; 1171 int i; 1172 1173 for (i = 0; i < kinfo->num_tqps; i++) { 1174 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 1175 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats)); 1176 } 1177 } 1178 1179 static void hclgevf_get_mac_addr(struct hnae3_handle *handle, u8 *p) 1180 { 1181 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1182 1183 ether_addr_copy(p, hdev->hw.mac.mac_addr); 1184 } 1185 1186 static int hclgevf_set_mac_addr(struct hnae3_handle *handle, void *p, 1187 bool is_first) 1188 { 1189 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1190 u8 *old_mac_addr = (u8 *)hdev->hw.mac.mac_addr; 1191 u8 *new_mac_addr = (u8 *)p; 1192 u8 msg_data[ETH_ALEN * 2]; 1193 u16 subcode; 1194 int status; 1195 1196 ether_addr_copy(msg_data, new_mac_addr); 1197 ether_addr_copy(&msg_data[ETH_ALEN], old_mac_addr); 1198 1199 subcode = is_first ? HCLGE_MBX_MAC_VLAN_UC_ADD : 1200 HCLGE_MBX_MAC_VLAN_UC_MODIFY; 1201 1202 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 1203 subcode, msg_data, sizeof(msg_data), 1204 true, NULL, 0); 1205 if (!status) 1206 ether_addr_copy(hdev->hw.mac.mac_addr, new_mac_addr); 1207 1208 return status; 1209 } 1210 1211 static int hclgevf_add_uc_addr(struct hnae3_handle *handle, 1212 const unsigned char *addr) 1213 { 1214 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1215 1216 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 1217 HCLGE_MBX_MAC_VLAN_UC_ADD, 1218 addr, ETH_ALEN, false, NULL, 0); 1219 } 1220 1221 static int hclgevf_rm_uc_addr(struct hnae3_handle *handle, 1222 const unsigned char *addr) 1223 { 1224 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1225 1226 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 1227 HCLGE_MBX_MAC_VLAN_UC_REMOVE, 1228 addr, ETH_ALEN, false, NULL, 0); 1229 } 1230 1231 static int hclgevf_add_mc_addr(struct hnae3_handle *handle, 1232 const unsigned char *addr) 1233 { 1234 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1235 1236 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 1237 HCLGE_MBX_MAC_VLAN_MC_ADD, 1238 addr, ETH_ALEN, false, NULL, 0); 1239 } 1240 1241 static int hclgevf_rm_mc_addr(struct hnae3_handle *handle, 1242 const unsigned char *addr) 1243 { 1244 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1245 1246 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 1247 HCLGE_MBX_MAC_VLAN_MC_REMOVE, 1248 addr, ETH_ALEN, false, NULL, 0); 1249 } 1250 1251 static int hclgevf_set_vlan_filter(struct hnae3_handle *handle, 1252 __be16 proto, u16 vlan_id, 1253 bool is_kill) 1254 { 1255 #define HCLGEVF_VLAN_MBX_MSG_LEN 5 1256 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1257 u8 msg_data[HCLGEVF_VLAN_MBX_MSG_LEN]; 1258 int ret; 1259 1260 if (vlan_id > HCLGEVF_MAX_VLAN_ID) 1261 return -EINVAL; 1262 1263 if (proto != htons(ETH_P_8021Q)) 1264 return -EPROTONOSUPPORT; 1265 1266 /* When device is resetting, firmware is unable to handle 1267 * mailbox. Just record the vlan id, and remove it after 1268 * reset finished. 1269 */ 1270 if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) && is_kill) { 1271 set_bit(vlan_id, hdev->vlan_del_fail_bmap); 1272 return -EBUSY; 1273 } 1274 1275 msg_data[0] = is_kill; 1276 memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id)); 1277 memcpy(&msg_data[3], &proto, sizeof(proto)); 1278 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 1279 HCLGE_MBX_VLAN_FILTER, msg_data, 1280 HCLGEVF_VLAN_MBX_MSG_LEN, true, NULL, 0); 1281 1282 /* when remove hw vlan filter failed, record the vlan id, 1283 * and try to remove it from hw later, to be consistence 1284 * with stack. 1285 */ 1286 if (is_kill && ret) 1287 set_bit(vlan_id, hdev->vlan_del_fail_bmap); 1288 1289 return ret; 1290 } 1291 1292 static void hclgevf_sync_vlan_filter(struct hclgevf_dev *hdev) 1293 { 1294 #define HCLGEVF_MAX_SYNC_COUNT 60 1295 struct hnae3_handle *handle = &hdev->nic; 1296 int ret, sync_cnt = 0; 1297 u16 vlan_id; 1298 1299 vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID); 1300 while (vlan_id != VLAN_N_VID) { 1301 ret = hclgevf_set_vlan_filter(handle, htons(ETH_P_8021Q), 1302 vlan_id, true); 1303 if (ret) 1304 return; 1305 1306 clear_bit(vlan_id, hdev->vlan_del_fail_bmap); 1307 sync_cnt++; 1308 if (sync_cnt >= HCLGEVF_MAX_SYNC_COUNT) 1309 return; 1310 1311 vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID); 1312 } 1313 } 1314 1315 static int hclgevf_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) 1316 { 1317 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1318 u8 msg_data; 1319 1320 msg_data = enable ? 1 : 0; 1321 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 1322 HCLGE_MBX_VLAN_RX_OFF_CFG, &msg_data, 1323 1, false, NULL, 0); 1324 } 1325 1326 static int hclgevf_reset_tqp(struct hnae3_handle *handle, u16 queue_id) 1327 { 1328 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1329 u8 msg_data[2]; 1330 int ret; 1331 1332 memcpy(msg_data, &queue_id, sizeof(queue_id)); 1333 1334 /* disable vf queue before send queue reset msg to PF */ 1335 ret = hclgevf_tqp_enable(hdev, queue_id, 0, false); 1336 if (ret) 1337 return ret; 1338 1339 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_QUEUE_RESET, 0, msg_data, 1340 sizeof(msg_data), true, NULL, 0); 1341 } 1342 1343 static int hclgevf_set_mtu(struct hnae3_handle *handle, int new_mtu) 1344 { 1345 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1346 1347 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MTU, 0, (u8 *)&new_mtu, 1348 sizeof(new_mtu), true, NULL, 0); 1349 } 1350 1351 static int hclgevf_notify_client(struct hclgevf_dev *hdev, 1352 enum hnae3_reset_notify_type type) 1353 { 1354 struct hnae3_client *client = hdev->nic_client; 1355 struct hnae3_handle *handle = &hdev->nic; 1356 int ret; 1357 1358 if (!test_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state) || 1359 !client) 1360 return 0; 1361 1362 if (!client->ops->reset_notify) 1363 return -EOPNOTSUPP; 1364 1365 ret = client->ops->reset_notify(handle, type); 1366 if (ret) 1367 dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n", 1368 type, ret); 1369 1370 return ret; 1371 } 1372 1373 static void hclgevf_flr_done(struct hnae3_ae_dev *ae_dev) 1374 { 1375 struct hclgevf_dev *hdev = ae_dev->priv; 1376 1377 set_bit(HNAE3_FLR_DONE, &hdev->flr_state); 1378 } 1379 1380 static int hclgevf_flr_poll_timeout(struct hclgevf_dev *hdev, 1381 unsigned long delay_us, 1382 unsigned long wait_cnt) 1383 { 1384 unsigned long cnt = 0; 1385 1386 while (!test_bit(HNAE3_FLR_DONE, &hdev->flr_state) && 1387 cnt++ < wait_cnt) 1388 usleep_range(delay_us, delay_us * 2); 1389 1390 if (!test_bit(HNAE3_FLR_DONE, &hdev->flr_state)) { 1391 dev_err(&hdev->pdev->dev, 1392 "flr wait timeout\n"); 1393 return -ETIMEDOUT; 1394 } 1395 1396 return 0; 1397 } 1398 1399 static int hclgevf_reset_wait(struct hclgevf_dev *hdev) 1400 { 1401 #define HCLGEVF_RESET_WAIT_US 20000 1402 #define HCLGEVF_RESET_WAIT_CNT 2000 1403 #define HCLGEVF_RESET_WAIT_TIMEOUT_US \ 1404 (HCLGEVF_RESET_WAIT_US * HCLGEVF_RESET_WAIT_CNT) 1405 1406 u32 val; 1407 int ret; 1408 1409 if (hdev->reset_type == HNAE3_FLR_RESET) 1410 return hclgevf_flr_poll_timeout(hdev, 1411 HCLGEVF_RESET_WAIT_US, 1412 HCLGEVF_RESET_WAIT_CNT); 1413 else if (hdev->reset_type == HNAE3_VF_RESET) 1414 ret = readl_poll_timeout(hdev->hw.io_base + 1415 HCLGEVF_VF_RST_ING, val, 1416 !(val & HCLGEVF_VF_RST_ING_BIT), 1417 HCLGEVF_RESET_WAIT_US, 1418 HCLGEVF_RESET_WAIT_TIMEOUT_US); 1419 else 1420 ret = readl_poll_timeout(hdev->hw.io_base + 1421 HCLGEVF_RST_ING, val, 1422 !(val & HCLGEVF_RST_ING_BITS), 1423 HCLGEVF_RESET_WAIT_US, 1424 HCLGEVF_RESET_WAIT_TIMEOUT_US); 1425 1426 /* hardware completion status should be available by this time */ 1427 if (ret) { 1428 dev_err(&hdev->pdev->dev, 1429 "could'nt get reset done status from h/w, timeout!\n"); 1430 return ret; 1431 } 1432 1433 /* we will wait a bit more to let reset of the stack to complete. This 1434 * might happen in case reset assertion was made by PF. Yes, this also 1435 * means we might end up waiting bit more even for VF reset. 1436 */ 1437 msleep(5000); 1438 1439 return 0; 1440 } 1441 1442 static void hclgevf_reset_handshake(struct hclgevf_dev *hdev, bool enable) 1443 { 1444 u32 reg_val; 1445 1446 reg_val = hclgevf_read_dev(&hdev->hw, HCLGEVF_NIC_CSQ_DEPTH_REG); 1447 if (enable) 1448 reg_val |= HCLGEVF_NIC_SW_RST_RDY; 1449 else 1450 reg_val &= ~HCLGEVF_NIC_SW_RST_RDY; 1451 1452 hclgevf_write_dev(&hdev->hw, HCLGEVF_NIC_CSQ_DEPTH_REG, 1453 reg_val); 1454 } 1455 1456 static int hclgevf_reset_stack(struct hclgevf_dev *hdev) 1457 { 1458 int ret; 1459 1460 /* uninitialize the nic client */ 1461 ret = hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT); 1462 if (ret) 1463 return ret; 1464 1465 /* re-initialize the hclge device */ 1466 ret = hclgevf_reset_hdev(hdev); 1467 if (ret) { 1468 dev_err(&hdev->pdev->dev, 1469 "hclge device re-init failed, VF is disabled!\n"); 1470 return ret; 1471 } 1472 1473 /* bring up the nic client again */ 1474 ret = hclgevf_notify_client(hdev, HNAE3_INIT_CLIENT); 1475 if (ret) 1476 return ret; 1477 1478 ret = hclgevf_notify_client(hdev, HNAE3_RESTORE_CLIENT); 1479 if (ret) 1480 return ret; 1481 1482 /* clear handshake status with IMP */ 1483 hclgevf_reset_handshake(hdev, false); 1484 1485 return 0; 1486 } 1487 1488 static int hclgevf_reset_prepare_wait(struct hclgevf_dev *hdev) 1489 { 1490 #define HCLGEVF_RESET_SYNC_TIME 100 1491 1492 int ret = 0; 1493 1494 switch (hdev->reset_type) { 1495 case HNAE3_VF_FUNC_RESET: 1496 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_RESET, 0, NULL, 1497 0, true, NULL, sizeof(u8)); 1498 hdev->rst_stats.vf_func_rst_cnt++; 1499 break; 1500 case HNAE3_FLR_RESET: 1501 set_bit(HNAE3_FLR_DOWN, &hdev->flr_state); 1502 hdev->rst_stats.flr_rst_cnt++; 1503 break; 1504 default: 1505 break; 1506 } 1507 1508 set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 1509 /* inform hardware that preparatory work is done */ 1510 msleep(HCLGEVF_RESET_SYNC_TIME); 1511 hclgevf_reset_handshake(hdev, true); 1512 dev_info(&hdev->pdev->dev, "prepare reset(%d) wait done, ret:%d\n", 1513 hdev->reset_type, ret); 1514 1515 return ret; 1516 } 1517 1518 static void hclgevf_reset_err_handle(struct hclgevf_dev *hdev) 1519 { 1520 /* recover handshake status with IMP when reset fail */ 1521 hclgevf_reset_handshake(hdev, true); 1522 hdev->rst_stats.rst_fail_cnt++; 1523 dev_err(&hdev->pdev->dev, "failed to reset VF(%d)\n", 1524 hdev->rst_stats.rst_fail_cnt); 1525 1526 if (hdev->rst_stats.rst_fail_cnt < HCLGEVF_RESET_MAX_FAIL_CNT) 1527 set_bit(hdev->reset_type, &hdev->reset_pending); 1528 1529 if (hclgevf_is_reset_pending(hdev)) { 1530 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1531 hclgevf_reset_task_schedule(hdev); 1532 } 1533 } 1534 1535 static int hclgevf_reset(struct hclgevf_dev *hdev) 1536 { 1537 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1538 int ret; 1539 1540 /* Initialize ae_dev reset status as well, in case enet layer wants to 1541 * know if device is undergoing reset 1542 */ 1543 ae_dev->reset_type = hdev->reset_type; 1544 hdev->rst_stats.rst_cnt++; 1545 rtnl_lock(); 1546 1547 /* bring down the nic to stop any ongoing TX/RX */ 1548 ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 1549 if (ret) 1550 goto err_reset_lock; 1551 1552 rtnl_unlock(); 1553 1554 ret = hclgevf_reset_prepare_wait(hdev); 1555 if (ret) 1556 goto err_reset; 1557 1558 /* check if VF could successfully fetch the hardware reset completion 1559 * status from the hardware 1560 */ 1561 ret = hclgevf_reset_wait(hdev); 1562 if (ret) { 1563 /* can't do much in this situation, will disable VF */ 1564 dev_err(&hdev->pdev->dev, 1565 "VF failed(=%d) to fetch H/W reset completion status\n", 1566 ret); 1567 goto err_reset; 1568 } 1569 1570 hdev->rst_stats.hw_rst_done_cnt++; 1571 1572 rtnl_lock(); 1573 1574 /* now, re-initialize the nic client and ae device */ 1575 ret = hclgevf_reset_stack(hdev); 1576 if (ret) { 1577 dev_err(&hdev->pdev->dev, "failed to reset VF stack\n"); 1578 goto err_reset_lock; 1579 } 1580 1581 /* bring up the nic to enable TX/RX again */ 1582 ret = hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 1583 if (ret) 1584 goto err_reset_lock; 1585 1586 rtnl_unlock(); 1587 1588 hdev->last_reset_time = jiffies; 1589 ae_dev->reset_type = HNAE3_NONE_RESET; 1590 hdev->rst_stats.rst_done_cnt++; 1591 hdev->rst_stats.rst_fail_cnt = 0; 1592 1593 return ret; 1594 err_reset_lock: 1595 rtnl_unlock(); 1596 err_reset: 1597 hclgevf_reset_err_handle(hdev); 1598 1599 return ret; 1600 } 1601 1602 static enum hnae3_reset_type hclgevf_get_reset_level(struct hclgevf_dev *hdev, 1603 unsigned long *addr) 1604 { 1605 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; 1606 1607 /* return the highest priority reset level amongst all */ 1608 if (test_bit(HNAE3_VF_RESET, addr)) { 1609 rst_level = HNAE3_VF_RESET; 1610 clear_bit(HNAE3_VF_RESET, addr); 1611 clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1612 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1613 } else if (test_bit(HNAE3_VF_FULL_RESET, addr)) { 1614 rst_level = HNAE3_VF_FULL_RESET; 1615 clear_bit(HNAE3_VF_FULL_RESET, addr); 1616 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1617 } else if (test_bit(HNAE3_VF_PF_FUNC_RESET, addr)) { 1618 rst_level = HNAE3_VF_PF_FUNC_RESET; 1619 clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1620 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1621 } else if (test_bit(HNAE3_VF_FUNC_RESET, addr)) { 1622 rst_level = HNAE3_VF_FUNC_RESET; 1623 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1624 } else if (test_bit(HNAE3_FLR_RESET, addr)) { 1625 rst_level = HNAE3_FLR_RESET; 1626 clear_bit(HNAE3_FLR_RESET, addr); 1627 } 1628 1629 return rst_level; 1630 } 1631 1632 static void hclgevf_reset_event(struct pci_dev *pdev, 1633 struct hnae3_handle *handle) 1634 { 1635 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 1636 struct hclgevf_dev *hdev = ae_dev->priv; 1637 1638 dev_info(&hdev->pdev->dev, "received reset request from VF enet\n"); 1639 1640 if (hdev->default_reset_request) 1641 hdev->reset_level = 1642 hclgevf_get_reset_level(hdev, 1643 &hdev->default_reset_request); 1644 else 1645 hdev->reset_level = HNAE3_VF_FUNC_RESET; 1646 1647 /* reset of this VF requested */ 1648 set_bit(HCLGEVF_RESET_REQUESTED, &hdev->reset_state); 1649 hclgevf_reset_task_schedule(hdev); 1650 1651 hdev->last_reset_time = jiffies; 1652 } 1653 1654 static void hclgevf_set_def_reset_request(struct hnae3_ae_dev *ae_dev, 1655 enum hnae3_reset_type rst_type) 1656 { 1657 struct hclgevf_dev *hdev = ae_dev->priv; 1658 1659 set_bit(rst_type, &hdev->default_reset_request); 1660 } 1661 1662 static void hclgevf_flr_prepare(struct hnae3_ae_dev *ae_dev) 1663 { 1664 #define HCLGEVF_FLR_WAIT_MS 100 1665 #define HCLGEVF_FLR_WAIT_CNT 50 1666 struct hclgevf_dev *hdev = ae_dev->priv; 1667 int cnt = 0; 1668 1669 clear_bit(HNAE3_FLR_DOWN, &hdev->flr_state); 1670 clear_bit(HNAE3_FLR_DONE, &hdev->flr_state); 1671 set_bit(HNAE3_FLR_RESET, &hdev->default_reset_request); 1672 hclgevf_reset_event(hdev->pdev, NULL); 1673 1674 while (!test_bit(HNAE3_FLR_DOWN, &hdev->flr_state) && 1675 cnt++ < HCLGEVF_FLR_WAIT_CNT) 1676 msleep(HCLGEVF_FLR_WAIT_MS); 1677 1678 if (!test_bit(HNAE3_FLR_DOWN, &hdev->flr_state)) 1679 dev_err(&hdev->pdev->dev, 1680 "flr wait down timeout: %d\n", cnt); 1681 } 1682 1683 static u32 hclgevf_get_fw_version(struct hnae3_handle *handle) 1684 { 1685 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1686 1687 return hdev->fw_version; 1688 } 1689 1690 static void hclgevf_get_misc_vector(struct hclgevf_dev *hdev) 1691 { 1692 struct hclgevf_misc_vector *vector = &hdev->misc_vector; 1693 1694 vector->vector_irq = pci_irq_vector(hdev->pdev, 1695 HCLGEVF_MISC_VECTOR_NUM); 1696 vector->addr = hdev->hw.io_base + HCLGEVF_MISC_VECTOR_REG_BASE; 1697 /* vector status always valid for Vector 0 */ 1698 hdev->vector_status[HCLGEVF_MISC_VECTOR_NUM] = 0; 1699 hdev->vector_irq[HCLGEVF_MISC_VECTOR_NUM] = vector->vector_irq; 1700 1701 hdev->num_msi_left -= 1; 1702 hdev->num_msi_used += 1; 1703 } 1704 1705 void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev) 1706 { 1707 if (!test_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state) && 1708 !test_bit(HCLGEVF_STATE_REMOVING, &hdev->state)) { 1709 set_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state); 1710 schedule_work(&hdev->rst_service_task); 1711 } 1712 } 1713 1714 void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev) 1715 { 1716 if (!test_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state) && 1717 !test_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) { 1718 set_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 1719 schedule_work(&hdev->mbx_service_task); 1720 } 1721 } 1722 1723 static void hclgevf_task_schedule(struct hclgevf_dev *hdev) 1724 { 1725 if (!test_bit(HCLGEVF_STATE_DOWN, &hdev->state) && 1726 !test_and_set_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state)) 1727 schedule_work(&hdev->service_task); 1728 } 1729 1730 static void hclgevf_deferred_task_schedule(struct hclgevf_dev *hdev) 1731 { 1732 /* if we have any pending mailbox event then schedule the mbx task */ 1733 if (hdev->mbx_event_pending) 1734 hclgevf_mbx_task_schedule(hdev); 1735 1736 if (test_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state)) 1737 hclgevf_reset_task_schedule(hdev); 1738 } 1739 1740 static void hclgevf_service_timer(struct timer_list *t) 1741 { 1742 struct hclgevf_dev *hdev = from_timer(hdev, t, service_timer); 1743 1744 mod_timer(&hdev->service_timer, jiffies + 1745 HCLGEVF_GENERAL_TASK_INTERVAL * HZ); 1746 1747 hdev->stats_timer++; 1748 hclgevf_task_schedule(hdev); 1749 } 1750 1751 static void hclgevf_reset_service_task(struct work_struct *work) 1752 { 1753 struct hclgevf_dev *hdev = 1754 container_of(work, struct hclgevf_dev, rst_service_task); 1755 int ret; 1756 1757 if (test_and_set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 1758 return; 1759 1760 clear_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state); 1761 1762 if (test_and_clear_bit(HCLGEVF_RESET_PENDING, 1763 &hdev->reset_state)) { 1764 /* PF has initmated that it is about to reset the hardware. 1765 * We now have to poll & check if hardware has actually 1766 * completed the reset sequence. On hardware reset completion, 1767 * VF needs to reset the client and ae device. 1768 */ 1769 hdev->reset_attempts = 0; 1770 1771 hdev->last_reset_time = jiffies; 1772 while ((hdev->reset_type = 1773 hclgevf_get_reset_level(hdev, &hdev->reset_pending)) 1774 != HNAE3_NONE_RESET) { 1775 ret = hclgevf_reset(hdev); 1776 if (ret) 1777 dev_err(&hdev->pdev->dev, 1778 "VF stack reset failed %d.\n", ret); 1779 } 1780 } else if (test_and_clear_bit(HCLGEVF_RESET_REQUESTED, 1781 &hdev->reset_state)) { 1782 /* we could be here when either of below happens: 1783 * 1. reset was initiated due to watchdog timeout caused by 1784 * a. IMP was earlier reset and our TX got choked down and 1785 * which resulted in watchdog reacting and inducing VF 1786 * reset. This also means our cmdq would be unreliable. 1787 * b. problem in TX due to other lower layer(example link 1788 * layer not functioning properly etc.) 1789 * 2. VF reset might have been initiated due to some config 1790 * change. 1791 * 1792 * NOTE: Theres no clear way to detect above cases than to react 1793 * to the response of PF for this reset request. PF will ack the 1794 * 1b and 2. cases but we will not get any intimation about 1a 1795 * from PF as cmdq would be in unreliable state i.e. mailbox 1796 * communication between PF and VF would be broken. 1797 * 1798 * if we are never geting into pending state it means either: 1799 * 1. PF is not receiving our request which could be due to IMP 1800 * reset 1801 * 2. PF is screwed 1802 * We cannot do much for 2. but to check first we can try reset 1803 * our PCIe + stack and see if it alleviates the problem. 1804 */ 1805 if (hdev->reset_attempts > 3) { 1806 /* prepare for full reset of stack + pcie interface */ 1807 set_bit(HNAE3_VF_FULL_RESET, &hdev->reset_pending); 1808 1809 /* "defer" schedule the reset task again */ 1810 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1811 } else { 1812 hdev->reset_attempts++; 1813 1814 set_bit(hdev->reset_level, &hdev->reset_pending); 1815 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1816 } 1817 hclgevf_reset_task_schedule(hdev); 1818 } 1819 1820 clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 1821 } 1822 1823 static void hclgevf_mailbox_service_task(struct work_struct *work) 1824 { 1825 struct hclgevf_dev *hdev; 1826 1827 hdev = container_of(work, struct hclgevf_dev, mbx_service_task); 1828 1829 if (test_and_set_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) 1830 return; 1831 1832 clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 1833 1834 hclgevf_mbx_async_handler(hdev); 1835 1836 clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 1837 } 1838 1839 static void hclgevf_keep_alive_timer(struct timer_list *t) 1840 { 1841 struct hclgevf_dev *hdev = from_timer(hdev, t, keep_alive_timer); 1842 1843 schedule_work(&hdev->keep_alive_task); 1844 mod_timer(&hdev->keep_alive_timer, jiffies + 1845 HCLGEVF_KEEP_ALIVE_TASK_INTERVAL * HZ); 1846 } 1847 1848 static void hclgevf_keep_alive_task(struct work_struct *work) 1849 { 1850 struct hclgevf_dev *hdev; 1851 u8 respmsg; 1852 int ret; 1853 1854 hdev = container_of(work, struct hclgevf_dev, keep_alive_task); 1855 1856 if (test_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state)) 1857 return; 1858 1859 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_KEEP_ALIVE, 0, NULL, 1860 0, false, &respmsg, sizeof(respmsg)); 1861 if (ret) 1862 dev_err(&hdev->pdev->dev, 1863 "VF sends keep alive cmd failed(=%d)\n", ret); 1864 } 1865 1866 static void hclgevf_service_task(struct work_struct *work) 1867 { 1868 struct hnae3_handle *handle; 1869 struct hclgevf_dev *hdev; 1870 1871 hdev = container_of(work, struct hclgevf_dev, service_task); 1872 handle = &hdev->nic; 1873 1874 if (hdev->stats_timer >= HCLGEVF_STATS_TIMER_INTERVAL) { 1875 hclgevf_tqps_update_stats(handle); 1876 hdev->stats_timer = 0; 1877 } 1878 1879 /* request the link status from the PF. PF would be able to tell VF 1880 * about such updates in future so we might remove this later 1881 */ 1882 hclgevf_request_link_info(hdev); 1883 1884 hclgevf_update_link_mode(hdev); 1885 1886 hclgevf_sync_vlan_filter(hdev); 1887 1888 hclgevf_deferred_task_schedule(hdev); 1889 1890 clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 1891 } 1892 1893 static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regclr) 1894 { 1895 hclgevf_write_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_SRC_REG, regclr); 1896 } 1897 1898 static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev, 1899 u32 *clearval) 1900 { 1901 u32 val, cmdq_stat_reg, rst_ing_reg; 1902 1903 /* fetch the events from their corresponding regs */ 1904 cmdq_stat_reg = hclgevf_read_dev(&hdev->hw, 1905 HCLGEVF_VECTOR0_CMDQ_STAT_REG); 1906 1907 if (BIT(HCLGEVF_VECTOR0_RST_INT_B) & cmdq_stat_reg) { 1908 rst_ing_reg = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 1909 dev_info(&hdev->pdev->dev, 1910 "receive reset interrupt 0x%x!\n", rst_ing_reg); 1911 set_bit(HNAE3_VF_RESET, &hdev->reset_pending); 1912 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1913 set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 1914 *clearval = ~(1U << HCLGEVF_VECTOR0_RST_INT_B); 1915 hdev->rst_stats.vf_rst_cnt++; 1916 /* set up VF hardware reset status, its PF will clear 1917 * this status when PF has initialized done. 1918 */ 1919 val = hclgevf_read_dev(&hdev->hw, HCLGEVF_VF_RST_ING); 1920 hclgevf_write_dev(&hdev->hw, HCLGEVF_VF_RST_ING, 1921 val | HCLGEVF_VF_RST_ING_BIT); 1922 return HCLGEVF_VECTOR0_EVENT_RST; 1923 } 1924 1925 /* check for vector0 mailbox(=CMDQ RX) event source */ 1926 if (BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) { 1927 /* for revision 0x21, clearing interrupt is writing bit 0 1928 * to the clear register, writing bit 1 means to keep the 1929 * old value. 1930 * for revision 0x20, the clear register is a read & write 1931 * register, so we should just write 0 to the bit we are 1932 * handling, and keep other bits as cmdq_stat_reg. 1933 */ 1934 if (hdev->pdev->revision >= 0x21) 1935 *clearval = ~(1U << HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 1936 else 1937 *clearval = cmdq_stat_reg & 1938 ~BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 1939 1940 return HCLGEVF_VECTOR0_EVENT_MBX; 1941 } 1942 1943 dev_dbg(&hdev->pdev->dev, "vector 0 interrupt from unknown source\n"); 1944 1945 return HCLGEVF_VECTOR0_EVENT_OTHER; 1946 } 1947 1948 static void hclgevf_enable_vector(struct hclgevf_misc_vector *vector, bool en) 1949 { 1950 writel(en ? 1 : 0, vector->addr); 1951 } 1952 1953 static irqreturn_t hclgevf_misc_irq_handle(int irq, void *data) 1954 { 1955 enum hclgevf_evt_cause event_cause; 1956 struct hclgevf_dev *hdev = data; 1957 u32 clearval; 1958 1959 hclgevf_enable_vector(&hdev->misc_vector, false); 1960 event_cause = hclgevf_check_evt_cause(hdev, &clearval); 1961 1962 switch (event_cause) { 1963 case HCLGEVF_VECTOR0_EVENT_RST: 1964 hclgevf_reset_task_schedule(hdev); 1965 break; 1966 case HCLGEVF_VECTOR0_EVENT_MBX: 1967 hclgevf_mbx_handler(hdev); 1968 break; 1969 default: 1970 break; 1971 } 1972 1973 if (event_cause != HCLGEVF_VECTOR0_EVENT_OTHER) { 1974 hclgevf_clear_event_cause(hdev, clearval); 1975 hclgevf_enable_vector(&hdev->misc_vector, true); 1976 } 1977 1978 return IRQ_HANDLED; 1979 } 1980 1981 static int hclgevf_configure(struct hclgevf_dev *hdev) 1982 { 1983 int ret; 1984 1985 /* get current port based vlan state from PF */ 1986 ret = hclgevf_get_port_base_vlan_filter_state(hdev); 1987 if (ret) 1988 return ret; 1989 1990 /* get queue configuration from PF */ 1991 ret = hclgevf_get_queue_info(hdev); 1992 if (ret) 1993 return ret; 1994 1995 /* get queue depth info from PF */ 1996 ret = hclgevf_get_queue_depth(hdev); 1997 if (ret) 1998 return ret; 1999 2000 ret = hclgevf_get_pf_media_type(hdev); 2001 if (ret) 2002 return ret; 2003 2004 /* get tc configuration from PF */ 2005 return hclgevf_get_tc_info(hdev); 2006 } 2007 2008 static int hclgevf_alloc_hdev(struct hnae3_ae_dev *ae_dev) 2009 { 2010 struct pci_dev *pdev = ae_dev->pdev; 2011 struct hclgevf_dev *hdev; 2012 2013 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 2014 if (!hdev) 2015 return -ENOMEM; 2016 2017 hdev->pdev = pdev; 2018 hdev->ae_dev = ae_dev; 2019 ae_dev->priv = hdev; 2020 2021 return 0; 2022 } 2023 2024 static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev) 2025 { 2026 struct hnae3_handle *roce = &hdev->roce; 2027 struct hnae3_handle *nic = &hdev->nic; 2028 2029 roce->rinfo.num_vectors = hdev->num_roce_msix; 2030 2031 if (hdev->num_msi_left < roce->rinfo.num_vectors || 2032 hdev->num_msi_left == 0) 2033 return -EINVAL; 2034 2035 roce->rinfo.base_vector = hdev->roce_base_vector; 2036 2037 roce->rinfo.netdev = nic->kinfo.netdev; 2038 roce->rinfo.roce_io_base = hdev->hw.io_base; 2039 2040 roce->pdev = nic->pdev; 2041 roce->ae_algo = nic->ae_algo; 2042 roce->numa_node_mask = nic->numa_node_mask; 2043 2044 return 0; 2045 } 2046 2047 static int hclgevf_config_gro(struct hclgevf_dev *hdev, bool en) 2048 { 2049 struct hclgevf_cfg_gro_status_cmd *req; 2050 struct hclgevf_desc desc; 2051 int ret; 2052 2053 if (!hnae3_dev_gro_supported(hdev)) 2054 return 0; 2055 2056 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_GRO_GENERIC_CONFIG, 2057 false); 2058 req = (struct hclgevf_cfg_gro_status_cmd *)desc.data; 2059 2060 req->gro_en = cpu_to_le16(en ? 1 : 0); 2061 2062 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 2063 if (ret) 2064 dev_err(&hdev->pdev->dev, 2065 "VF GRO hardware config cmd failed, ret = %d.\n", ret); 2066 2067 return ret; 2068 } 2069 2070 static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev) 2071 { 2072 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 2073 int ret; 2074 u32 i; 2075 2076 rss_cfg->rss_size = hdev->nic.kinfo.rss_size; 2077 2078 if (hdev->pdev->revision >= 0x21) { 2079 rss_cfg->hash_algo = HCLGEVF_RSS_HASH_ALGO_SIMPLE; 2080 memcpy(rss_cfg->rss_hash_key, hclgevf_hash_key, 2081 HCLGEVF_RSS_KEY_SIZE); 2082 2083 ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 2084 rss_cfg->rss_hash_key); 2085 if (ret) 2086 return ret; 2087 2088 rss_cfg->rss_tuple_sets.ipv4_tcp_en = 2089 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2090 rss_cfg->rss_tuple_sets.ipv4_udp_en = 2091 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2092 rss_cfg->rss_tuple_sets.ipv4_sctp_en = 2093 HCLGEVF_RSS_INPUT_TUPLE_SCTP; 2094 rss_cfg->rss_tuple_sets.ipv4_fragment_en = 2095 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2096 rss_cfg->rss_tuple_sets.ipv6_tcp_en = 2097 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2098 rss_cfg->rss_tuple_sets.ipv6_udp_en = 2099 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2100 rss_cfg->rss_tuple_sets.ipv6_sctp_en = 2101 HCLGEVF_RSS_INPUT_TUPLE_SCTP; 2102 rss_cfg->rss_tuple_sets.ipv6_fragment_en = 2103 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2104 2105 ret = hclgevf_set_rss_input_tuple(hdev, rss_cfg); 2106 if (ret) 2107 return ret; 2108 2109 } 2110 2111 /* Initialize RSS indirect table */ 2112 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 2113 rss_cfg->rss_indirection_tbl[i] = i % rss_cfg->rss_size; 2114 2115 ret = hclgevf_set_rss_indir_table(hdev); 2116 if (ret) 2117 return ret; 2118 2119 return hclgevf_set_rss_tc_mode(hdev, rss_cfg->rss_size); 2120 } 2121 2122 static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev) 2123 { 2124 return hclgevf_set_vlan_filter(&hdev->nic, htons(ETH_P_8021Q), 0, 2125 false); 2126 } 2127 2128 static void hclgevf_set_timer_task(struct hnae3_handle *handle, bool enable) 2129 { 2130 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2131 2132 if (enable) { 2133 mod_timer(&hdev->service_timer, jiffies + HZ); 2134 } else { 2135 del_timer_sync(&hdev->service_timer); 2136 cancel_work_sync(&hdev->service_task); 2137 clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 2138 } 2139 } 2140 2141 static int hclgevf_ae_start(struct hnae3_handle *handle) 2142 { 2143 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2144 2145 hclgevf_reset_tqp_stats(handle); 2146 2147 hclgevf_request_link_info(hdev); 2148 2149 hclgevf_update_link_mode(hdev); 2150 2151 clear_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2152 2153 return 0; 2154 } 2155 2156 static void hclgevf_ae_stop(struct hnae3_handle *handle) 2157 { 2158 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2159 int i; 2160 2161 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2162 2163 if (hdev->reset_type != HNAE3_VF_RESET) 2164 for (i = 0; i < handle->kinfo.num_tqps; i++) 2165 if (hclgevf_reset_tqp(handle, i)) 2166 break; 2167 2168 hclgevf_reset_tqp_stats(handle); 2169 hclgevf_update_link_status(hdev, 0); 2170 } 2171 2172 static int hclgevf_set_alive(struct hnae3_handle *handle, bool alive) 2173 { 2174 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2175 u8 msg_data; 2176 2177 msg_data = alive ? 1 : 0; 2178 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_ALIVE, 2179 0, &msg_data, 1, false, NULL, 0); 2180 } 2181 2182 static int hclgevf_client_start(struct hnae3_handle *handle) 2183 { 2184 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2185 int ret; 2186 2187 ret = hclgevf_set_alive(handle, true); 2188 if (ret) 2189 return ret; 2190 2191 mod_timer(&hdev->keep_alive_timer, jiffies + 2192 HCLGEVF_KEEP_ALIVE_TASK_INTERVAL * HZ); 2193 2194 return 0; 2195 } 2196 2197 static void hclgevf_client_stop(struct hnae3_handle *handle) 2198 { 2199 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2200 int ret; 2201 2202 ret = hclgevf_set_alive(handle, false); 2203 if (ret) 2204 dev_warn(&hdev->pdev->dev, 2205 "%s failed %d\n", __func__, ret); 2206 2207 del_timer_sync(&hdev->keep_alive_timer); 2208 cancel_work_sync(&hdev->keep_alive_task); 2209 } 2210 2211 static void hclgevf_state_init(struct hclgevf_dev *hdev) 2212 { 2213 /* setup tasks for the MBX */ 2214 INIT_WORK(&hdev->mbx_service_task, hclgevf_mailbox_service_task); 2215 clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 2216 clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 2217 2218 /* setup tasks for service timer */ 2219 timer_setup(&hdev->service_timer, hclgevf_service_timer, 0); 2220 2221 INIT_WORK(&hdev->service_task, hclgevf_service_task); 2222 clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 2223 2224 INIT_WORK(&hdev->rst_service_task, hclgevf_reset_service_task); 2225 2226 mutex_init(&hdev->mbx_resp.mbx_mutex); 2227 2228 /* bring the device down */ 2229 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2230 } 2231 2232 static void hclgevf_state_uninit(struct hclgevf_dev *hdev) 2233 { 2234 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2235 set_bit(HCLGEVF_STATE_REMOVING, &hdev->state); 2236 2237 if (hdev->keep_alive_timer.function) 2238 del_timer_sync(&hdev->keep_alive_timer); 2239 if (hdev->keep_alive_task.func) 2240 cancel_work_sync(&hdev->keep_alive_task); 2241 if (hdev->service_timer.function) 2242 del_timer_sync(&hdev->service_timer); 2243 if (hdev->service_task.func) 2244 cancel_work_sync(&hdev->service_task); 2245 if (hdev->mbx_service_task.func) 2246 cancel_work_sync(&hdev->mbx_service_task); 2247 if (hdev->rst_service_task.func) 2248 cancel_work_sync(&hdev->rst_service_task); 2249 2250 mutex_destroy(&hdev->mbx_resp.mbx_mutex); 2251 } 2252 2253 static int hclgevf_init_msi(struct hclgevf_dev *hdev) 2254 { 2255 struct pci_dev *pdev = hdev->pdev; 2256 int vectors; 2257 int i; 2258 2259 if (hnae3_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B)) 2260 vectors = pci_alloc_irq_vectors(pdev, 2261 hdev->roce_base_msix_offset + 1, 2262 hdev->num_msi, 2263 PCI_IRQ_MSIX); 2264 else 2265 vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi, 2266 PCI_IRQ_MSI | PCI_IRQ_MSIX); 2267 2268 if (vectors < 0) { 2269 dev_err(&pdev->dev, 2270 "failed(%d) to allocate MSI/MSI-X vectors\n", 2271 vectors); 2272 return vectors; 2273 } 2274 if (vectors < hdev->num_msi) 2275 dev_warn(&hdev->pdev->dev, 2276 "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n", 2277 hdev->num_msi, vectors); 2278 2279 hdev->num_msi = vectors; 2280 hdev->num_msi_left = vectors; 2281 hdev->base_msi_vector = pdev->irq; 2282 hdev->roce_base_vector = pdev->irq + hdev->roce_base_msix_offset; 2283 2284 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 2285 sizeof(u16), GFP_KERNEL); 2286 if (!hdev->vector_status) { 2287 pci_free_irq_vectors(pdev); 2288 return -ENOMEM; 2289 } 2290 2291 for (i = 0; i < hdev->num_msi; i++) 2292 hdev->vector_status[i] = HCLGEVF_INVALID_VPORT; 2293 2294 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 2295 sizeof(int), GFP_KERNEL); 2296 if (!hdev->vector_irq) { 2297 devm_kfree(&pdev->dev, hdev->vector_status); 2298 pci_free_irq_vectors(pdev); 2299 return -ENOMEM; 2300 } 2301 2302 return 0; 2303 } 2304 2305 static void hclgevf_uninit_msi(struct hclgevf_dev *hdev) 2306 { 2307 struct pci_dev *pdev = hdev->pdev; 2308 2309 devm_kfree(&pdev->dev, hdev->vector_status); 2310 devm_kfree(&pdev->dev, hdev->vector_irq); 2311 pci_free_irq_vectors(pdev); 2312 } 2313 2314 static int hclgevf_misc_irq_init(struct hclgevf_dev *hdev) 2315 { 2316 int ret; 2317 2318 hclgevf_get_misc_vector(hdev); 2319 2320 ret = request_irq(hdev->misc_vector.vector_irq, hclgevf_misc_irq_handle, 2321 0, "hclgevf_cmd", hdev); 2322 if (ret) { 2323 dev_err(&hdev->pdev->dev, "VF failed to request misc irq(%d)\n", 2324 hdev->misc_vector.vector_irq); 2325 return ret; 2326 } 2327 2328 hclgevf_clear_event_cause(hdev, 0); 2329 2330 /* enable misc. vector(vector 0) */ 2331 hclgevf_enable_vector(&hdev->misc_vector, true); 2332 2333 return ret; 2334 } 2335 2336 static void hclgevf_misc_irq_uninit(struct hclgevf_dev *hdev) 2337 { 2338 /* disable misc vector(vector 0) */ 2339 hclgevf_enable_vector(&hdev->misc_vector, false); 2340 synchronize_irq(hdev->misc_vector.vector_irq); 2341 free_irq(hdev->misc_vector.vector_irq, hdev); 2342 hclgevf_free_vector(hdev, 0); 2343 } 2344 2345 static void hclgevf_info_show(struct hclgevf_dev *hdev) 2346 { 2347 struct device *dev = &hdev->pdev->dev; 2348 2349 dev_info(dev, "VF info begin:\n"); 2350 2351 dev_info(dev, "Task queue pairs numbers: %d\n", hdev->num_tqps); 2352 dev_info(dev, "Desc num per TX queue: %d\n", hdev->num_tx_desc); 2353 dev_info(dev, "Desc num per RX queue: %d\n", hdev->num_rx_desc); 2354 dev_info(dev, "Numbers of vports: %d\n", hdev->num_alloc_vport); 2355 dev_info(dev, "HW tc map: %d\n", hdev->hw_tc_map); 2356 dev_info(dev, "PF media type of this VF: %d\n", 2357 hdev->hw.mac.media_type); 2358 2359 dev_info(dev, "VF info end.\n"); 2360 } 2361 2362 static int hclgevf_init_nic_client_instance(struct hnae3_ae_dev *ae_dev, 2363 struct hnae3_client *client) 2364 { 2365 struct hclgevf_dev *hdev = ae_dev->priv; 2366 int ret; 2367 2368 ret = client->ops->init_instance(&hdev->nic); 2369 if (ret) 2370 return ret; 2371 2372 set_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 2373 hnae3_set_client_init_flag(client, ae_dev, 1); 2374 2375 if (netif_msg_drv(&hdev->nic)) 2376 hclgevf_info_show(hdev); 2377 2378 return 0; 2379 } 2380 2381 static int hclgevf_init_roce_client_instance(struct hnae3_ae_dev *ae_dev, 2382 struct hnae3_client *client) 2383 { 2384 struct hclgevf_dev *hdev = ae_dev->priv; 2385 int ret; 2386 2387 if (!hnae3_dev_roce_supported(hdev) || !hdev->roce_client || 2388 !hdev->nic_client) 2389 return 0; 2390 2391 ret = hclgevf_init_roce_base_info(hdev); 2392 if (ret) 2393 return ret; 2394 2395 ret = client->ops->init_instance(&hdev->roce); 2396 if (ret) 2397 return ret; 2398 2399 hnae3_set_client_init_flag(client, ae_dev, 1); 2400 2401 return 0; 2402 } 2403 2404 static int hclgevf_init_client_instance(struct hnae3_client *client, 2405 struct hnae3_ae_dev *ae_dev) 2406 { 2407 struct hclgevf_dev *hdev = ae_dev->priv; 2408 int ret; 2409 2410 switch (client->type) { 2411 case HNAE3_CLIENT_KNIC: 2412 hdev->nic_client = client; 2413 hdev->nic.client = client; 2414 2415 ret = hclgevf_init_nic_client_instance(ae_dev, client); 2416 if (ret) 2417 goto clear_nic; 2418 2419 ret = hclgevf_init_roce_client_instance(ae_dev, 2420 hdev->roce_client); 2421 if (ret) 2422 goto clear_roce; 2423 2424 break; 2425 case HNAE3_CLIENT_ROCE: 2426 if (hnae3_dev_roce_supported(hdev)) { 2427 hdev->roce_client = client; 2428 hdev->roce.client = client; 2429 } 2430 2431 ret = hclgevf_init_roce_client_instance(ae_dev, client); 2432 if (ret) 2433 goto clear_roce; 2434 2435 break; 2436 default: 2437 return -EINVAL; 2438 } 2439 2440 return 0; 2441 2442 clear_nic: 2443 hdev->nic_client = NULL; 2444 hdev->nic.client = NULL; 2445 return ret; 2446 clear_roce: 2447 hdev->roce_client = NULL; 2448 hdev->roce.client = NULL; 2449 return ret; 2450 } 2451 2452 static void hclgevf_uninit_client_instance(struct hnae3_client *client, 2453 struct hnae3_ae_dev *ae_dev) 2454 { 2455 struct hclgevf_dev *hdev = ae_dev->priv; 2456 2457 /* un-init roce, if it exists */ 2458 if (hdev->roce_client) { 2459 hdev->roce_client->ops->uninit_instance(&hdev->roce, 0); 2460 hdev->roce_client = NULL; 2461 hdev->roce.client = NULL; 2462 } 2463 2464 /* un-init nic/unic, if this was not called by roce client */ 2465 if (client->ops->uninit_instance && hdev->nic_client && 2466 client->type != HNAE3_CLIENT_ROCE) { 2467 clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 2468 2469 client->ops->uninit_instance(&hdev->nic, 0); 2470 hdev->nic_client = NULL; 2471 hdev->nic.client = NULL; 2472 } 2473 } 2474 2475 static int hclgevf_pci_init(struct hclgevf_dev *hdev) 2476 { 2477 struct pci_dev *pdev = hdev->pdev; 2478 struct hclgevf_hw *hw; 2479 int ret; 2480 2481 ret = pci_enable_device(pdev); 2482 if (ret) { 2483 dev_err(&pdev->dev, "failed to enable PCI device\n"); 2484 return ret; 2485 } 2486 2487 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 2488 if (ret) { 2489 dev_err(&pdev->dev, "can't set consistent PCI DMA, exiting"); 2490 goto err_disable_device; 2491 } 2492 2493 ret = pci_request_regions(pdev, HCLGEVF_DRIVER_NAME); 2494 if (ret) { 2495 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 2496 goto err_disable_device; 2497 } 2498 2499 pci_set_master(pdev); 2500 hw = &hdev->hw; 2501 hw->hdev = hdev; 2502 hw->io_base = pci_iomap(pdev, 2, 0); 2503 if (!hw->io_base) { 2504 dev_err(&pdev->dev, "can't map configuration register space\n"); 2505 ret = -ENOMEM; 2506 goto err_clr_master; 2507 } 2508 2509 return 0; 2510 2511 err_clr_master: 2512 pci_clear_master(pdev); 2513 pci_release_regions(pdev); 2514 err_disable_device: 2515 pci_disable_device(pdev); 2516 2517 return ret; 2518 } 2519 2520 static void hclgevf_pci_uninit(struct hclgevf_dev *hdev) 2521 { 2522 struct pci_dev *pdev = hdev->pdev; 2523 2524 pci_iounmap(pdev, hdev->hw.io_base); 2525 pci_clear_master(pdev); 2526 pci_release_regions(pdev); 2527 pci_disable_device(pdev); 2528 } 2529 2530 static int hclgevf_query_vf_resource(struct hclgevf_dev *hdev) 2531 { 2532 struct hclgevf_query_res_cmd *req; 2533 struct hclgevf_desc desc; 2534 int ret; 2535 2536 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_VF_RSRC, true); 2537 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 2538 if (ret) { 2539 dev_err(&hdev->pdev->dev, 2540 "query vf resource failed, ret = %d.\n", ret); 2541 return ret; 2542 } 2543 2544 req = (struct hclgevf_query_res_cmd *)desc.data; 2545 2546 if (hnae3_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B)) { 2547 hdev->roce_base_msix_offset = 2548 hnae3_get_field(__le16_to_cpu(req->msixcap_localid_ba_rocee), 2549 HCLGEVF_MSIX_OFT_ROCEE_M, 2550 HCLGEVF_MSIX_OFT_ROCEE_S); 2551 hdev->num_roce_msix = 2552 hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number), 2553 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 2554 2555 /* VF should have NIC vectors and Roce vectors, NIC vectors 2556 * are queued before Roce vectors. The offset is fixed to 64. 2557 */ 2558 hdev->num_msi = hdev->num_roce_msix + 2559 hdev->roce_base_msix_offset; 2560 } else { 2561 hdev->num_msi = 2562 hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number), 2563 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 2564 } 2565 2566 return 0; 2567 } 2568 2569 static int hclgevf_pci_reset(struct hclgevf_dev *hdev) 2570 { 2571 struct pci_dev *pdev = hdev->pdev; 2572 int ret = 0; 2573 2574 if (hdev->reset_type == HNAE3_VF_FULL_RESET && 2575 test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2576 hclgevf_misc_irq_uninit(hdev); 2577 hclgevf_uninit_msi(hdev); 2578 clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2579 } 2580 2581 if (!test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2582 pci_set_master(pdev); 2583 ret = hclgevf_init_msi(hdev); 2584 if (ret) { 2585 dev_err(&pdev->dev, 2586 "failed(%d) to init MSI/MSI-X\n", ret); 2587 return ret; 2588 } 2589 2590 ret = hclgevf_misc_irq_init(hdev); 2591 if (ret) { 2592 hclgevf_uninit_msi(hdev); 2593 dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 2594 ret); 2595 return ret; 2596 } 2597 2598 set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2599 } 2600 2601 return ret; 2602 } 2603 2604 static int hclgevf_reset_hdev(struct hclgevf_dev *hdev) 2605 { 2606 struct pci_dev *pdev = hdev->pdev; 2607 int ret; 2608 2609 ret = hclgevf_pci_reset(hdev); 2610 if (ret) { 2611 dev_err(&pdev->dev, "pci reset failed %d\n", ret); 2612 return ret; 2613 } 2614 2615 ret = hclgevf_cmd_init(hdev); 2616 if (ret) { 2617 dev_err(&pdev->dev, "cmd failed %d\n", ret); 2618 return ret; 2619 } 2620 2621 ret = hclgevf_rss_init_hw(hdev); 2622 if (ret) { 2623 dev_err(&hdev->pdev->dev, 2624 "failed(%d) to initialize RSS\n", ret); 2625 return ret; 2626 } 2627 2628 ret = hclgevf_config_gro(hdev, true); 2629 if (ret) 2630 return ret; 2631 2632 ret = hclgevf_init_vlan_config(hdev); 2633 if (ret) { 2634 dev_err(&hdev->pdev->dev, 2635 "failed(%d) to initialize VLAN config\n", ret); 2636 return ret; 2637 } 2638 2639 dev_info(&hdev->pdev->dev, "Reset done\n"); 2640 2641 return 0; 2642 } 2643 2644 static int hclgevf_init_hdev(struct hclgevf_dev *hdev) 2645 { 2646 struct pci_dev *pdev = hdev->pdev; 2647 int ret; 2648 2649 ret = hclgevf_pci_init(hdev); 2650 if (ret) { 2651 dev_err(&pdev->dev, "PCI initialization failed\n"); 2652 return ret; 2653 } 2654 2655 ret = hclgevf_cmd_queue_init(hdev); 2656 if (ret) { 2657 dev_err(&pdev->dev, "Cmd queue init failed: %d\n", ret); 2658 goto err_cmd_queue_init; 2659 } 2660 2661 ret = hclgevf_cmd_init(hdev); 2662 if (ret) 2663 goto err_cmd_init; 2664 2665 /* Get vf resource */ 2666 ret = hclgevf_query_vf_resource(hdev); 2667 if (ret) { 2668 dev_err(&hdev->pdev->dev, 2669 "Query vf status error, ret = %d.\n", ret); 2670 goto err_cmd_init; 2671 } 2672 2673 ret = hclgevf_init_msi(hdev); 2674 if (ret) { 2675 dev_err(&pdev->dev, "failed(%d) to init MSI/MSI-X\n", ret); 2676 goto err_cmd_init; 2677 } 2678 2679 hclgevf_state_init(hdev); 2680 hdev->reset_level = HNAE3_VF_FUNC_RESET; 2681 2682 ret = hclgevf_misc_irq_init(hdev); 2683 if (ret) { 2684 dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 2685 ret); 2686 goto err_misc_irq_init; 2687 } 2688 2689 set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2690 2691 ret = hclgevf_configure(hdev); 2692 if (ret) { 2693 dev_err(&pdev->dev, "failed(%d) to fetch configuration\n", ret); 2694 goto err_config; 2695 } 2696 2697 ret = hclgevf_alloc_tqps(hdev); 2698 if (ret) { 2699 dev_err(&pdev->dev, "failed(%d) to allocate TQPs\n", ret); 2700 goto err_config; 2701 } 2702 2703 ret = hclgevf_set_handle_info(hdev); 2704 if (ret) { 2705 dev_err(&pdev->dev, "failed(%d) to set handle info\n", ret); 2706 goto err_config; 2707 } 2708 2709 ret = hclgevf_config_gro(hdev, true); 2710 if (ret) 2711 goto err_config; 2712 2713 /* Initialize RSS for this VF */ 2714 ret = hclgevf_rss_init_hw(hdev); 2715 if (ret) { 2716 dev_err(&hdev->pdev->dev, 2717 "failed(%d) to initialize RSS\n", ret); 2718 goto err_config; 2719 } 2720 2721 ret = hclgevf_init_vlan_config(hdev); 2722 if (ret) { 2723 dev_err(&hdev->pdev->dev, 2724 "failed(%d) to initialize VLAN config\n", ret); 2725 goto err_config; 2726 } 2727 2728 hdev->last_reset_time = jiffies; 2729 dev_info(&hdev->pdev->dev, "finished initializing %s driver\n", 2730 HCLGEVF_DRIVER_NAME); 2731 2732 return 0; 2733 2734 err_config: 2735 hclgevf_misc_irq_uninit(hdev); 2736 err_misc_irq_init: 2737 hclgevf_state_uninit(hdev); 2738 hclgevf_uninit_msi(hdev); 2739 err_cmd_init: 2740 hclgevf_cmd_uninit(hdev); 2741 err_cmd_queue_init: 2742 hclgevf_pci_uninit(hdev); 2743 clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2744 return ret; 2745 } 2746 2747 static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev) 2748 { 2749 hclgevf_state_uninit(hdev); 2750 2751 if (test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2752 hclgevf_misc_irq_uninit(hdev); 2753 hclgevf_uninit_msi(hdev); 2754 } 2755 2756 hclgevf_pci_uninit(hdev); 2757 hclgevf_cmd_uninit(hdev); 2758 } 2759 2760 static int hclgevf_init_ae_dev(struct hnae3_ae_dev *ae_dev) 2761 { 2762 struct pci_dev *pdev = ae_dev->pdev; 2763 struct hclgevf_dev *hdev; 2764 int ret; 2765 2766 ret = hclgevf_alloc_hdev(ae_dev); 2767 if (ret) { 2768 dev_err(&pdev->dev, "hclge device allocation failed\n"); 2769 return ret; 2770 } 2771 2772 ret = hclgevf_init_hdev(ae_dev->priv); 2773 if (ret) { 2774 dev_err(&pdev->dev, "hclge device initialization failed\n"); 2775 return ret; 2776 } 2777 2778 hdev = ae_dev->priv; 2779 timer_setup(&hdev->keep_alive_timer, hclgevf_keep_alive_timer, 0); 2780 INIT_WORK(&hdev->keep_alive_task, hclgevf_keep_alive_task); 2781 2782 return 0; 2783 } 2784 2785 static void hclgevf_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 2786 { 2787 struct hclgevf_dev *hdev = ae_dev->priv; 2788 2789 hclgevf_uninit_hdev(hdev); 2790 ae_dev->priv = NULL; 2791 } 2792 2793 static u32 hclgevf_get_max_channels(struct hclgevf_dev *hdev) 2794 { 2795 struct hnae3_handle *nic = &hdev->nic; 2796 struct hnae3_knic_private_info *kinfo = &nic->kinfo; 2797 2798 return min_t(u32, hdev->rss_size_max, 2799 hdev->num_tqps / kinfo->num_tc); 2800 } 2801 2802 /** 2803 * hclgevf_get_channels - Get the current channels enabled and max supported. 2804 * @handle: hardware information for network interface 2805 * @ch: ethtool channels structure 2806 * 2807 * We don't support separate tx and rx queues as channels. The other count 2808 * represents how many queues are being used for control. max_combined counts 2809 * how many queue pairs we can support. They may not be mapped 1 to 1 with 2810 * q_vectors since we support a lot more queue pairs than q_vectors. 2811 **/ 2812 static void hclgevf_get_channels(struct hnae3_handle *handle, 2813 struct ethtool_channels *ch) 2814 { 2815 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2816 2817 ch->max_combined = hclgevf_get_max_channels(hdev); 2818 ch->other_count = 0; 2819 ch->max_other = 0; 2820 ch->combined_count = handle->kinfo.rss_size; 2821 } 2822 2823 static void hclgevf_get_tqps_and_rss_info(struct hnae3_handle *handle, 2824 u16 *alloc_tqps, u16 *max_rss_size) 2825 { 2826 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2827 2828 *alloc_tqps = hdev->num_tqps; 2829 *max_rss_size = hdev->rss_size_max; 2830 } 2831 2832 static void hclgevf_update_rss_size(struct hnae3_handle *handle, 2833 u32 new_tqps_num) 2834 { 2835 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 2836 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2837 u16 max_rss_size; 2838 2839 kinfo->req_rss_size = new_tqps_num; 2840 2841 max_rss_size = min_t(u16, hdev->rss_size_max, 2842 hdev->num_tqps / kinfo->num_tc); 2843 2844 /* Use the user's configuration when it is not larger than 2845 * max_rss_size, otherwise, use the maximum specification value. 2846 */ 2847 if (kinfo->req_rss_size != kinfo->rss_size && kinfo->req_rss_size && 2848 kinfo->req_rss_size <= max_rss_size) 2849 kinfo->rss_size = kinfo->req_rss_size; 2850 else if (kinfo->rss_size > max_rss_size || 2851 (!kinfo->req_rss_size && kinfo->rss_size < max_rss_size)) 2852 kinfo->rss_size = max_rss_size; 2853 2854 kinfo->num_tqps = kinfo->num_tc * kinfo->rss_size; 2855 } 2856 2857 static int hclgevf_set_channels(struct hnae3_handle *handle, u32 new_tqps_num, 2858 bool rxfh_configured) 2859 { 2860 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2861 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 2862 u16 cur_rss_size = kinfo->rss_size; 2863 u16 cur_tqps = kinfo->num_tqps; 2864 u32 *rss_indir; 2865 unsigned int i; 2866 int ret; 2867 2868 hclgevf_update_rss_size(handle, new_tqps_num); 2869 2870 ret = hclgevf_set_rss_tc_mode(hdev, kinfo->rss_size); 2871 if (ret) 2872 return ret; 2873 2874 /* RSS indirection table has been configuared by user */ 2875 if (rxfh_configured) 2876 goto out; 2877 2878 /* Reinitializes the rss indirect table according to the new RSS size */ 2879 rss_indir = kcalloc(HCLGEVF_RSS_IND_TBL_SIZE, sizeof(u32), GFP_KERNEL); 2880 if (!rss_indir) 2881 return -ENOMEM; 2882 2883 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 2884 rss_indir[i] = i % kinfo->rss_size; 2885 2886 ret = hclgevf_set_rss(handle, rss_indir, NULL, 0); 2887 if (ret) 2888 dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n", 2889 ret); 2890 2891 kfree(rss_indir); 2892 2893 out: 2894 if (!ret) 2895 dev_info(&hdev->pdev->dev, 2896 "Channels changed, rss_size from %u to %u, tqps from %u to %u", 2897 cur_rss_size, kinfo->rss_size, 2898 cur_tqps, kinfo->rss_size * kinfo->num_tc); 2899 2900 return ret; 2901 } 2902 2903 static int hclgevf_get_status(struct hnae3_handle *handle) 2904 { 2905 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2906 2907 return hdev->hw.mac.link; 2908 } 2909 2910 static void hclgevf_get_ksettings_an_result(struct hnae3_handle *handle, 2911 u8 *auto_neg, u32 *speed, 2912 u8 *duplex) 2913 { 2914 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2915 2916 if (speed) 2917 *speed = hdev->hw.mac.speed; 2918 if (duplex) 2919 *duplex = hdev->hw.mac.duplex; 2920 if (auto_neg) 2921 *auto_neg = AUTONEG_DISABLE; 2922 } 2923 2924 void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed, 2925 u8 duplex) 2926 { 2927 hdev->hw.mac.speed = speed; 2928 hdev->hw.mac.duplex = duplex; 2929 } 2930 2931 static int hclgevf_gro_en(struct hnae3_handle *handle, bool enable) 2932 { 2933 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2934 2935 return hclgevf_config_gro(hdev, enable); 2936 } 2937 2938 static void hclgevf_get_media_type(struct hnae3_handle *handle, u8 *media_type, 2939 u8 *module_type) 2940 { 2941 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2942 2943 if (media_type) 2944 *media_type = hdev->hw.mac.media_type; 2945 2946 if (module_type) 2947 *module_type = hdev->hw.mac.module_type; 2948 } 2949 2950 static bool hclgevf_get_hw_reset_stat(struct hnae3_handle *handle) 2951 { 2952 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2953 2954 return !!hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 2955 } 2956 2957 static bool hclgevf_ae_dev_resetting(struct hnae3_handle *handle) 2958 { 2959 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2960 2961 return test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 2962 } 2963 2964 static unsigned long hclgevf_ae_dev_reset_cnt(struct hnae3_handle *handle) 2965 { 2966 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2967 2968 return hdev->rst_stats.hw_rst_done_cnt; 2969 } 2970 2971 static void hclgevf_get_link_mode(struct hnae3_handle *handle, 2972 unsigned long *supported, 2973 unsigned long *advertising) 2974 { 2975 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2976 2977 *supported = hdev->hw.mac.supported; 2978 *advertising = hdev->hw.mac.advertising; 2979 } 2980 2981 #define MAX_SEPARATE_NUM 4 2982 #define SEPARATOR_VALUE 0xFFFFFFFF 2983 #define REG_NUM_PER_LINE 4 2984 #define REG_LEN_PER_LINE (REG_NUM_PER_LINE * sizeof(u32)) 2985 2986 static int hclgevf_get_regs_len(struct hnae3_handle *handle) 2987 { 2988 int cmdq_lines, common_lines, ring_lines, tqp_intr_lines; 2989 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2990 2991 cmdq_lines = sizeof(cmdq_reg_addr_list) / REG_LEN_PER_LINE + 1; 2992 common_lines = sizeof(common_reg_addr_list) / REG_LEN_PER_LINE + 1; 2993 ring_lines = sizeof(ring_reg_addr_list) / REG_LEN_PER_LINE + 1; 2994 tqp_intr_lines = sizeof(tqp_intr_reg_addr_list) / REG_LEN_PER_LINE + 1; 2995 2996 return (cmdq_lines + common_lines + ring_lines * hdev->num_tqps + 2997 tqp_intr_lines * (hdev->num_msi_used - 1)) * REG_LEN_PER_LINE; 2998 } 2999 3000 static void hclgevf_get_regs(struct hnae3_handle *handle, u32 *version, 3001 void *data) 3002 { 3003 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3004 int i, j, reg_um, separator_num; 3005 u32 *reg = data; 3006 3007 *version = hdev->fw_version; 3008 3009 /* fetching per-VF registers values from VF PCIe register space */ 3010 reg_um = sizeof(cmdq_reg_addr_list) / sizeof(u32); 3011 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 3012 for (i = 0; i < reg_um; i++) 3013 *reg++ = hclgevf_read_dev(&hdev->hw, cmdq_reg_addr_list[i]); 3014 for (i = 0; i < separator_num; i++) 3015 *reg++ = SEPARATOR_VALUE; 3016 3017 reg_um = sizeof(common_reg_addr_list) / sizeof(u32); 3018 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 3019 for (i = 0; i < reg_um; i++) 3020 *reg++ = hclgevf_read_dev(&hdev->hw, common_reg_addr_list[i]); 3021 for (i = 0; i < separator_num; i++) 3022 *reg++ = SEPARATOR_VALUE; 3023 3024 reg_um = sizeof(ring_reg_addr_list) / sizeof(u32); 3025 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 3026 for (j = 0; j < hdev->num_tqps; j++) { 3027 for (i = 0; i < reg_um; i++) 3028 *reg++ = hclgevf_read_dev(&hdev->hw, 3029 ring_reg_addr_list[i] + 3030 0x200 * j); 3031 for (i = 0; i < separator_num; i++) 3032 *reg++ = SEPARATOR_VALUE; 3033 } 3034 3035 reg_um = sizeof(tqp_intr_reg_addr_list) / sizeof(u32); 3036 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 3037 for (j = 0; j < hdev->num_msi_used - 1; j++) { 3038 for (i = 0; i < reg_um; i++) 3039 *reg++ = hclgevf_read_dev(&hdev->hw, 3040 tqp_intr_reg_addr_list[i] + 3041 4 * j); 3042 for (i = 0; i < separator_num; i++) 3043 *reg++ = SEPARATOR_VALUE; 3044 } 3045 } 3046 3047 void hclgevf_update_port_base_vlan_info(struct hclgevf_dev *hdev, u16 state, 3048 u8 *port_base_vlan_info, u8 data_size) 3049 { 3050 struct hnae3_handle *nic = &hdev->nic; 3051 3052 rtnl_lock(); 3053 hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 3054 rtnl_unlock(); 3055 3056 /* send msg to PF and wait update port based vlan info */ 3057 hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 3058 HCLGE_MBX_PORT_BASE_VLAN_CFG, 3059 port_base_vlan_info, data_size, 3060 false, NULL, 0); 3061 3062 if (state == HNAE3_PORT_BASE_VLAN_DISABLE) 3063 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_DISABLE; 3064 else 3065 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_ENABLE; 3066 3067 rtnl_lock(); 3068 hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 3069 rtnl_unlock(); 3070 } 3071 3072 static const struct hnae3_ae_ops hclgevf_ops = { 3073 .init_ae_dev = hclgevf_init_ae_dev, 3074 .uninit_ae_dev = hclgevf_uninit_ae_dev, 3075 .flr_prepare = hclgevf_flr_prepare, 3076 .flr_done = hclgevf_flr_done, 3077 .init_client_instance = hclgevf_init_client_instance, 3078 .uninit_client_instance = hclgevf_uninit_client_instance, 3079 .start = hclgevf_ae_start, 3080 .stop = hclgevf_ae_stop, 3081 .client_start = hclgevf_client_start, 3082 .client_stop = hclgevf_client_stop, 3083 .map_ring_to_vector = hclgevf_map_ring_to_vector, 3084 .unmap_ring_from_vector = hclgevf_unmap_ring_from_vector, 3085 .get_vector = hclgevf_get_vector, 3086 .put_vector = hclgevf_put_vector, 3087 .reset_queue = hclgevf_reset_tqp, 3088 .get_mac_addr = hclgevf_get_mac_addr, 3089 .set_mac_addr = hclgevf_set_mac_addr, 3090 .add_uc_addr = hclgevf_add_uc_addr, 3091 .rm_uc_addr = hclgevf_rm_uc_addr, 3092 .add_mc_addr = hclgevf_add_mc_addr, 3093 .rm_mc_addr = hclgevf_rm_mc_addr, 3094 .get_stats = hclgevf_get_stats, 3095 .update_stats = hclgevf_update_stats, 3096 .get_strings = hclgevf_get_strings, 3097 .get_sset_count = hclgevf_get_sset_count, 3098 .get_rss_key_size = hclgevf_get_rss_key_size, 3099 .get_rss_indir_size = hclgevf_get_rss_indir_size, 3100 .get_rss = hclgevf_get_rss, 3101 .set_rss = hclgevf_set_rss, 3102 .get_rss_tuple = hclgevf_get_rss_tuple, 3103 .set_rss_tuple = hclgevf_set_rss_tuple, 3104 .get_tc_size = hclgevf_get_tc_size, 3105 .get_fw_version = hclgevf_get_fw_version, 3106 .set_vlan_filter = hclgevf_set_vlan_filter, 3107 .enable_hw_strip_rxvtag = hclgevf_en_hw_strip_rxvtag, 3108 .reset_event = hclgevf_reset_event, 3109 .set_default_reset_request = hclgevf_set_def_reset_request, 3110 .set_channels = hclgevf_set_channels, 3111 .get_channels = hclgevf_get_channels, 3112 .get_tqps_and_rss_info = hclgevf_get_tqps_and_rss_info, 3113 .get_regs_len = hclgevf_get_regs_len, 3114 .get_regs = hclgevf_get_regs, 3115 .get_status = hclgevf_get_status, 3116 .get_ksettings_an_result = hclgevf_get_ksettings_an_result, 3117 .get_media_type = hclgevf_get_media_type, 3118 .get_hw_reset_stat = hclgevf_get_hw_reset_stat, 3119 .ae_dev_resetting = hclgevf_ae_dev_resetting, 3120 .ae_dev_reset_cnt = hclgevf_ae_dev_reset_cnt, 3121 .set_gro_en = hclgevf_gro_en, 3122 .set_mtu = hclgevf_set_mtu, 3123 .get_global_queue_id = hclgevf_get_qid_global, 3124 .set_timer_task = hclgevf_set_timer_task, 3125 .get_link_mode = hclgevf_get_link_mode, 3126 .set_promisc_mode = hclgevf_set_promisc_mode, 3127 }; 3128 3129 static struct hnae3_ae_algo ae_algovf = { 3130 .ops = &hclgevf_ops, 3131 .pdev_id_table = ae_algovf_pci_tbl, 3132 }; 3133 3134 static int hclgevf_init(void) 3135 { 3136 pr_info("%s is initializing\n", HCLGEVF_NAME); 3137 3138 hnae3_register_ae_algo(&ae_algovf); 3139 3140 return 0; 3141 } 3142 3143 static void hclgevf_exit(void) 3144 { 3145 hnae3_unregister_ae_algo(&ae_algovf); 3146 } 3147 module_init(hclgevf_init); 3148 module_exit(hclgevf_exit); 3149 3150 MODULE_LICENSE("GPL"); 3151 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 3152 MODULE_DESCRIPTION("HCLGEVF Driver"); 3153 MODULE_VERSION(HCLGEVF_MOD_VERSION); 3154