1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright (c) 2016-2017 Hisilicon Limited.
3 
4 #include <linux/etherdevice.h>
5 #include <linux/iopoll.h>
6 #include <net/rtnetlink.h>
7 #include "hclgevf_cmd.h"
8 #include "hclgevf_main.h"
9 #include "hclge_mbx.h"
10 #include "hnae3.h"
11 #include "hclgevf_devlink.h"
12 
13 #define HCLGEVF_NAME	"hclgevf"
14 
15 #define HCLGEVF_RESET_MAX_FAIL_CNT	5
16 
17 static int hclgevf_reset_hdev(struct hclgevf_dev *hdev);
18 static void hclgevf_task_schedule(struct hclgevf_dev *hdev,
19 				  unsigned long delay);
20 
21 static struct hnae3_ae_algo ae_algovf;
22 
23 static struct workqueue_struct *hclgevf_wq;
24 
25 static const struct pci_device_id ae_algovf_pci_tbl[] = {
26 	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_VF), 0},
27 	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF),
28 	 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
29 	/* required last entry */
30 	{0, }
31 };
32 
33 static const u8 hclgevf_hash_key[] = {
34 	0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2,
35 	0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0,
36 	0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4,
37 	0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C,
38 	0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA
39 };
40 
41 MODULE_DEVICE_TABLE(pci, ae_algovf_pci_tbl);
42 
43 static const u32 cmdq_reg_addr_list[] = {HCLGEVF_NIC_CSQ_BASEADDR_L_REG,
44 					 HCLGEVF_NIC_CSQ_BASEADDR_H_REG,
45 					 HCLGEVF_NIC_CSQ_DEPTH_REG,
46 					 HCLGEVF_NIC_CSQ_TAIL_REG,
47 					 HCLGEVF_NIC_CSQ_HEAD_REG,
48 					 HCLGEVF_NIC_CRQ_BASEADDR_L_REG,
49 					 HCLGEVF_NIC_CRQ_BASEADDR_H_REG,
50 					 HCLGEVF_NIC_CRQ_DEPTH_REG,
51 					 HCLGEVF_NIC_CRQ_TAIL_REG,
52 					 HCLGEVF_NIC_CRQ_HEAD_REG,
53 					 HCLGEVF_VECTOR0_CMDQ_SRC_REG,
54 					 HCLGEVF_VECTOR0_CMDQ_STATE_REG,
55 					 HCLGEVF_CMDQ_INTR_EN_REG,
56 					 HCLGEVF_CMDQ_INTR_GEN_REG};
57 
58 static const u32 common_reg_addr_list[] = {HCLGEVF_MISC_VECTOR_REG_BASE,
59 					   HCLGEVF_RST_ING,
60 					   HCLGEVF_GRO_EN_REG};
61 
62 static const u32 ring_reg_addr_list[] = {HCLGEVF_RING_RX_ADDR_L_REG,
63 					 HCLGEVF_RING_RX_ADDR_H_REG,
64 					 HCLGEVF_RING_RX_BD_NUM_REG,
65 					 HCLGEVF_RING_RX_BD_LENGTH_REG,
66 					 HCLGEVF_RING_RX_MERGE_EN_REG,
67 					 HCLGEVF_RING_RX_TAIL_REG,
68 					 HCLGEVF_RING_RX_HEAD_REG,
69 					 HCLGEVF_RING_RX_FBD_NUM_REG,
70 					 HCLGEVF_RING_RX_OFFSET_REG,
71 					 HCLGEVF_RING_RX_FBD_OFFSET_REG,
72 					 HCLGEVF_RING_RX_STASH_REG,
73 					 HCLGEVF_RING_RX_BD_ERR_REG,
74 					 HCLGEVF_RING_TX_ADDR_L_REG,
75 					 HCLGEVF_RING_TX_ADDR_H_REG,
76 					 HCLGEVF_RING_TX_BD_NUM_REG,
77 					 HCLGEVF_RING_TX_PRIORITY_REG,
78 					 HCLGEVF_RING_TX_TC_REG,
79 					 HCLGEVF_RING_TX_MERGE_EN_REG,
80 					 HCLGEVF_RING_TX_TAIL_REG,
81 					 HCLGEVF_RING_TX_HEAD_REG,
82 					 HCLGEVF_RING_TX_FBD_NUM_REG,
83 					 HCLGEVF_RING_TX_OFFSET_REG,
84 					 HCLGEVF_RING_TX_EBD_NUM_REG,
85 					 HCLGEVF_RING_TX_EBD_OFFSET_REG,
86 					 HCLGEVF_RING_TX_BD_ERR_REG,
87 					 HCLGEVF_RING_EN_REG};
88 
89 static const u32 tqp_intr_reg_addr_list[] = {HCLGEVF_TQP_INTR_CTRL_REG,
90 					     HCLGEVF_TQP_INTR_GL0_REG,
91 					     HCLGEVF_TQP_INTR_GL1_REG,
92 					     HCLGEVF_TQP_INTR_GL2_REG,
93 					     HCLGEVF_TQP_INTR_RL_REG};
94 
95 static struct hclgevf_dev *hclgevf_ae_get_hdev(struct hnae3_handle *handle)
96 {
97 	if (!handle->client)
98 		return container_of(handle, struct hclgevf_dev, nic);
99 	else if (handle->client->type == HNAE3_CLIENT_ROCE)
100 		return container_of(handle, struct hclgevf_dev, roce);
101 	else
102 		return container_of(handle, struct hclgevf_dev, nic);
103 }
104 
105 static int hclgevf_tqps_update_stats(struct hnae3_handle *handle)
106 {
107 	struct hnae3_knic_private_info *kinfo = &handle->kinfo;
108 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
109 	struct hclgevf_desc desc;
110 	struct hclgevf_tqp *tqp;
111 	int status;
112 	int i;
113 
114 	for (i = 0; i < kinfo->num_tqps; i++) {
115 		tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q);
116 		hclgevf_cmd_setup_basic_desc(&desc,
117 					     HCLGEVF_OPC_QUERY_RX_STATUS,
118 					     true);
119 
120 		desc.data[0] = cpu_to_le32(tqp->index & 0x1ff);
121 		status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
122 		if (status) {
123 			dev_err(&hdev->pdev->dev,
124 				"Query tqp stat fail, status = %d,queue = %d\n",
125 				status,	i);
126 			return status;
127 		}
128 		tqp->tqp_stats.rcb_rx_ring_pktnum_rcd +=
129 			le32_to_cpu(desc.data[1]);
130 
131 		hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_TX_STATUS,
132 					     true);
133 
134 		desc.data[0] = cpu_to_le32(tqp->index & 0x1ff);
135 		status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
136 		if (status) {
137 			dev_err(&hdev->pdev->dev,
138 				"Query tqp stat fail, status = %d,queue = %d\n",
139 				status, i);
140 			return status;
141 		}
142 		tqp->tqp_stats.rcb_tx_ring_pktnum_rcd +=
143 			le32_to_cpu(desc.data[1]);
144 	}
145 
146 	return 0;
147 }
148 
149 static u64 *hclgevf_tqps_get_stats(struct hnae3_handle *handle, u64 *data)
150 {
151 	struct hnae3_knic_private_info *kinfo = &handle->kinfo;
152 	struct hclgevf_tqp *tqp;
153 	u64 *buff = data;
154 	int i;
155 
156 	for (i = 0; i < kinfo->num_tqps; i++) {
157 		tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q);
158 		*buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd;
159 	}
160 	for (i = 0; i < kinfo->num_tqps; i++) {
161 		tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q);
162 		*buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd;
163 	}
164 
165 	return buff;
166 }
167 
168 static int hclgevf_tqps_get_sset_count(struct hnae3_handle *handle, int strset)
169 {
170 	struct hnae3_knic_private_info *kinfo = &handle->kinfo;
171 
172 	return kinfo->num_tqps * 2;
173 }
174 
175 static u8 *hclgevf_tqps_get_strings(struct hnae3_handle *handle, u8 *data)
176 {
177 	struct hnae3_knic_private_info *kinfo = &handle->kinfo;
178 	u8 *buff = data;
179 	int i;
180 
181 	for (i = 0; i < kinfo->num_tqps; i++) {
182 		struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i],
183 						       struct hclgevf_tqp, q);
184 		snprintf(buff, ETH_GSTRING_LEN, "txq%u_pktnum_rcd",
185 			 tqp->index);
186 		buff += ETH_GSTRING_LEN;
187 	}
188 
189 	for (i = 0; i < kinfo->num_tqps; i++) {
190 		struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i],
191 						       struct hclgevf_tqp, q);
192 		snprintf(buff, ETH_GSTRING_LEN, "rxq%u_pktnum_rcd",
193 			 tqp->index);
194 		buff += ETH_GSTRING_LEN;
195 	}
196 
197 	return buff;
198 }
199 
200 static void hclgevf_update_stats(struct hnae3_handle *handle,
201 				 struct net_device_stats *net_stats)
202 {
203 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
204 	int status;
205 
206 	status = hclgevf_tqps_update_stats(handle);
207 	if (status)
208 		dev_err(&hdev->pdev->dev,
209 			"VF update of TQPS stats fail, status = %d.\n",
210 			status);
211 }
212 
213 static int hclgevf_get_sset_count(struct hnae3_handle *handle, int strset)
214 {
215 	if (strset == ETH_SS_TEST)
216 		return -EOPNOTSUPP;
217 	else if (strset == ETH_SS_STATS)
218 		return hclgevf_tqps_get_sset_count(handle, strset);
219 
220 	return 0;
221 }
222 
223 static void hclgevf_get_strings(struct hnae3_handle *handle, u32 strset,
224 				u8 *data)
225 {
226 	u8 *p = (char *)data;
227 
228 	if (strset == ETH_SS_STATS)
229 		p = hclgevf_tqps_get_strings(handle, p);
230 }
231 
232 static void hclgevf_get_stats(struct hnae3_handle *handle, u64 *data)
233 {
234 	hclgevf_tqps_get_stats(handle, data);
235 }
236 
237 static void hclgevf_build_send_msg(struct hclge_vf_to_pf_msg *msg, u8 code,
238 				   u8 subcode)
239 {
240 	if (msg) {
241 		memset(msg, 0, sizeof(struct hclge_vf_to_pf_msg));
242 		msg->code = code;
243 		msg->subcode = subcode;
244 	}
245 }
246 
247 static int hclgevf_get_basic_info(struct hclgevf_dev *hdev)
248 {
249 	struct hnae3_ae_dev *ae_dev = hdev->ae_dev;
250 	u8 resp_msg[HCLGE_MBX_MAX_RESP_DATA_SIZE];
251 	struct hclge_basic_info *basic_info;
252 	struct hclge_vf_to_pf_msg send_msg;
253 	unsigned long caps;
254 	int status;
255 
256 	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_BASIC_INFO, 0);
257 	status = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg,
258 				      sizeof(resp_msg));
259 	if (status) {
260 		dev_err(&hdev->pdev->dev,
261 			"failed to get basic info from pf, ret = %d", status);
262 		return status;
263 	}
264 
265 	basic_info = (struct hclge_basic_info *)resp_msg;
266 
267 	hdev->hw_tc_map = basic_info->hw_tc_map;
268 	hdev->mbx_api_version = basic_info->mbx_api_version;
269 	caps = basic_info->pf_caps;
270 	if (test_bit(HNAE3_PF_SUPPORT_VLAN_FLTR_MDF_B, &caps))
271 		set_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps);
272 
273 	return 0;
274 }
275 
276 static int hclgevf_get_port_base_vlan_filter_state(struct hclgevf_dev *hdev)
277 {
278 	struct hnae3_handle *nic = &hdev->nic;
279 	struct hclge_vf_to_pf_msg send_msg;
280 	u8 resp_msg;
281 	int ret;
282 
283 	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN,
284 			       HCLGE_MBX_GET_PORT_BASE_VLAN_STATE);
285 	ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, &resp_msg,
286 				   sizeof(u8));
287 	if (ret) {
288 		dev_err(&hdev->pdev->dev,
289 			"VF request to get port based vlan state failed %d",
290 			ret);
291 		return ret;
292 	}
293 
294 	nic->port_base_vlan_state = resp_msg;
295 
296 	return 0;
297 }
298 
299 static int hclgevf_get_queue_info(struct hclgevf_dev *hdev)
300 {
301 #define HCLGEVF_TQPS_RSS_INFO_LEN	6
302 #define HCLGEVF_TQPS_ALLOC_OFFSET	0
303 #define HCLGEVF_TQPS_RSS_SIZE_OFFSET	2
304 #define HCLGEVF_TQPS_RX_BUFFER_LEN_OFFSET	4
305 
306 	u8 resp_msg[HCLGEVF_TQPS_RSS_INFO_LEN];
307 	struct hclge_vf_to_pf_msg send_msg;
308 	int status;
309 
310 	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QINFO, 0);
311 	status = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg,
312 				      HCLGEVF_TQPS_RSS_INFO_LEN);
313 	if (status) {
314 		dev_err(&hdev->pdev->dev,
315 			"VF request to get tqp info from PF failed %d",
316 			status);
317 		return status;
318 	}
319 
320 	memcpy(&hdev->num_tqps, &resp_msg[HCLGEVF_TQPS_ALLOC_OFFSET],
321 	       sizeof(u16));
322 	memcpy(&hdev->rss_size_max, &resp_msg[HCLGEVF_TQPS_RSS_SIZE_OFFSET],
323 	       sizeof(u16));
324 	memcpy(&hdev->rx_buf_len, &resp_msg[HCLGEVF_TQPS_RX_BUFFER_LEN_OFFSET],
325 	       sizeof(u16));
326 
327 	return 0;
328 }
329 
330 static int hclgevf_get_queue_depth(struct hclgevf_dev *hdev)
331 {
332 #define HCLGEVF_TQPS_DEPTH_INFO_LEN	4
333 #define HCLGEVF_TQPS_NUM_TX_DESC_OFFSET	0
334 #define HCLGEVF_TQPS_NUM_RX_DESC_OFFSET	2
335 
336 	u8 resp_msg[HCLGEVF_TQPS_DEPTH_INFO_LEN];
337 	struct hclge_vf_to_pf_msg send_msg;
338 	int ret;
339 
340 	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QDEPTH, 0);
341 	ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg,
342 				   HCLGEVF_TQPS_DEPTH_INFO_LEN);
343 	if (ret) {
344 		dev_err(&hdev->pdev->dev,
345 			"VF request to get tqp depth info from PF failed %d",
346 			ret);
347 		return ret;
348 	}
349 
350 	memcpy(&hdev->num_tx_desc, &resp_msg[HCLGEVF_TQPS_NUM_TX_DESC_OFFSET],
351 	       sizeof(u16));
352 	memcpy(&hdev->num_rx_desc, &resp_msg[HCLGEVF_TQPS_NUM_RX_DESC_OFFSET],
353 	       sizeof(u16));
354 
355 	return 0;
356 }
357 
358 static u16 hclgevf_get_qid_global(struct hnae3_handle *handle, u16 queue_id)
359 {
360 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
361 	struct hclge_vf_to_pf_msg send_msg;
362 	u16 qid_in_pf = 0;
363 	u8 resp_data[2];
364 	int ret;
365 
366 	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QID_IN_PF, 0);
367 	memcpy(send_msg.data, &queue_id, sizeof(queue_id));
368 	ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_data,
369 				   sizeof(resp_data));
370 	if (!ret)
371 		qid_in_pf = *(u16 *)resp_data;
372 
373 	return qid_in_pf;
374 }
375 
376 static int hclgevf_get_pf_media_type(struct hclgevf_dev *hdev)
377 {
378 	struct hclge_vf_to_pf_msg send_msg;
379 	u8 resp_msg[2];
380 	int ret;
381 
382 	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_MEDIA_TYPE, 0);
383 	ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg,
384 				   sizeof(resp_msg));
385 	if (ret) {
386 		dev_err(&hdev->pdev->dev,
387 			"VF request to get the pf port media type failed %d",
388 			ret);
389 		return ret;
390 	}
391 
392 	hdev->hw.mac.media_type = resp_msg[0];
393 	hdev->hw.mac.module_type = resp_msg[1];
394 
395 	return 0;
396 }
397 
398 static int hclgevf_alloc_tqps(struct hclgevf_dev *hdev)
399 {
400 	struct hclgevf_tqp *tqp;
401 	int i;
402 
403 	hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps,
404 				  sizeof(struct hclgevf_tqp), GFP_KERNEL);
405 	if (!hdev->htqp)
406 		return -ENOMEM;
407 
408 	tqp = hdev->htqp;
409 
410 	for (i = 0; i < hdev->num_tqps; i++) {
411 		tqp->dev = &hdev->pdev->dev;
412 		tqp->index = i;
413 
414 		tqp->q.ae_algo = &ae_algovf;
415 		tqp->q.buf_size = hdev->rx_buf_len;
416 		tqp->q.tx_desc_num = hdev->num_tx_desc;
417 		tqp->q.rx_desc_num = hdev->num_rx_desc;
418 
419 		/* need an extended offset to configure queues >=
420 		 * HCLGEVF_TQP_MAX_SIZE_DEV_V2.
421 		 */
422 		if (i < HCLGEVF_TQP_MAX_SIZE_DEV_V2)
423 			tqp->q.io_base = hdev->hw.io_base +
424 					 HCLGEVF_TQP_REG_OFFSET +
425 					 i * HCLGEVF_TQP_REG_SIZE;
426 		else
427 			tqp->q.io_base = hdev->hw.io_base +
428 					 HCLGEVF_TQP_REG_OFFSET +
429 					 HCLGEVF_TQP_EXT_REG_OFFSET +
430 					 (i - HCLGEVF_TQP_MAX_SIZE_DEV_V2) *
431 					 HCLGEVF_TQP_REG_SIZE;
432 
433 		tqp++;
434 	}
435 
436 	return 0;
437 }
438 
439 static int hclgevf_knic_setup(struct hclgevf_dev *hdev)
440 {
441 	struct hnae3_handle *nic = &hdev->nic;
442 	struct hnae3_knic_private_info *kinfo;
443 	u16 new_tqps = hdev->num_tqps;
444 	unsigned int i;
445 	u8 num_tc = 0;
446 
447 	kinfo = &nic->kinfo;
448 	kinfo->num_tx_desc = hdev->num_tx_desc;
449 	kinfo->num_rx_desc = hdev->num_rx_desc;
450 	kinfo->rx_buf_len = hdev->rx_buf_len;
451 	for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++)
452 		if (hdev->hw_tc_map & BIT(i))
453 			num_tc++;
454 
455 	num_tc = num_tc ? num_tc : 1;
456 	kinfo->tc_info.num_tc = num_tc;
457 	kinfo->rss_size = min_t(u16, hdev->rss_size_max, new_tqps / num_tc);
458 	new_tqps = kinfo->rss_size * num_tc;
459 	kinfo->num_tqps = min(new_tqps, hdev->num_tqps);
460 
461 	kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps,
462 				  sizeof(struct hnae3_queue *), GFP_KERNEL);
463 	if (!kinfo->tqp)
464 		return -ENOMEM;
465 
466 	for (i = 0; i < kinfo->num_tqps; i++) {
467 		hdev->htqp[i].q.handle = &hdev->nic;
468 		hdev->htqp[i].q.tqp_index = i;
469 		kinfo->tqp[i] = &hdev->htqp[i].q;
470 	}
471 
472 	/* after init the max rss_size and tqps, adjust the default tqp numbers
473 	 * and rss size with the actual vector numbers
474 	 */
475 	kinfo->num_tqps = min_t(u16, hdev->num_nic_msix - 1, kinfo->num_tqps);
476 	kinfo->rss_size = min_t(u16, kinfo->num_tqps / num_tc,
477 				kinfo->rss_size);
478 
479 	return 0;
480 }
481 
482 static void hclgevf_request_link_info(struct hclgevf_dev *hdev)
483 {
484 	struct hclge_vf_to_pf_msg send_msg;
485 	int status;
486 
487 	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_LINK_STATUS, 0);
488 	status = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
489 	if (status)
490 		dev_err(&hdev->pdev->dev,
491 			"VF failed to fetch link status(%d) from PF", status);
492 }
493 
494 void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state)
495 {
496 	struct hnae3_handle *rhandle = &hdev->roce;
497 	struct hnae3_handle *handle = &hdev->nic;
498 	struct hnae3_client *rclient;
499 	struct hnae3_client *client;
500 
501 	if (test_and_set_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state))
502 		return;
503 
504 	client = handle->client;
505 	rclient = hdev->roce_client;
506 
507 	link_state =
508 		test_bit(HCLGEVF_STATE_DOWN, &hdev->state) ? 0 : link_state;
509 	if (link_state != hdev->hw.mac.link) {
510 		hdev->hw.mac.link = link_state;
511 		client->ops->link_status_change(handle, !!link_state);
512 		if (rclient && rclient->ops->link_status_change)
513 			rclient->ops->link_status_change(rhandle, !!link_state);
514 	}
515 
516 	clear_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state);
517 }
518 
519 static void hclgevf_update_link_mode(struct hclgevf_dev *hdev)
520 {
521 #define HCLGEVF_ADVERTISING	0
522 #define HCLGEVF_SUPPORTED	1
523 
524 	struct hclge_vf_to_pf_msg send_msg;
525 
526 	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_LINK_MODE, 0);
527 	send_msg.data[0] = HCLGEVF_ADVERTISING;
528 	hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
529 	send_msg.data[0] = HCLGEVF_SUPPORTED;
530 	hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
531 }
532 
533 static int hclgevf_set_handle_info(struct hclgevf_dev *hdev)
534 {
535 	struct hnae3_handle *nic = &hdev->nic;
536 	int ret;
537 
538 	nic->ae_algo = &ae_algovf;
539 	nic->pdev = hdev->pdev;
540 	nic->numa_node_mask = hdev->numa_node_mask;
541 	nic->flags |= HNAE3_SUPPORT_VF;
542 	nic->kinfo.io_base = hdev->hw.io_base;
543 
544 	ret = hclgevf_knic_setup(hdev);
545 	if (ret)
546 		dev_err(&hdev->pdev->dev, "VF knic setup failed %d\n",
547 			ret);
548 	return ret;
549 }
550 
551 static void hclgevf_free_vector(struct hclgevf_dev *hdev, int vector_id)
552 {
553 	if (hdev->vector_status[vector_id] == HCLGEVF_INVALID_VPORT) {
554 		dev_warn(&hdev->pdev->dev,
555 			 "vector(vector_id %d) has been freed.\n", vector_id);
556 		return;
557 	}
558 
559 	hdev->vector_status[vector_id] = HCLGEVF_INVALID_VPORT;
560 	hdev->num_msi_left += 1;
561 	hdev->num_msi_used -= 1;
562 }
563 
564 static int hclgevf_get_vector(struct hnae3_handle *handle, u16 vector_num,
565 			      struct hnae3_vector_info *vector_info)
566 {
567 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
568 	struct hnae3_vector_info *vector = vector_info;
569 	int alloc = 0;
570 	int i, j;
571 
572 	vector_num = min_t(u16, hdev->num_nic_msix - 1, vector_num);
573 	vector_num = min(hdev->num_msi_left, vector_num);
574 
575 	for (j = 0; j < vector_num; j++) {
576 		for (i = HCLGEVF_MISC_VECTOR_NUM + 1; i < hdev->num_msi; i++) {
577 			if (hdev->vector_status[i] == HCLGEVF_INVALID_VPORT) {
578 				vector->vector = pci_irq_vector(hdev->pdev, i);
579 				vector->io_addr = hdev->hw.io_base +
580 					HCLGEVF_VECTOR_REG_BASE +
581 					(i - 1) * HCLGEVF_VECTOR_REG_OFFSET;
582 				hdev->vector_status[i] = 0;
583 				hdev->vector_irq[i] = vector->vector;
584 
585 				vector++;
586 				alloc++;
587 
588 				break;
589 			}
590 		}
591 	}
592 	hdev->num_msi_left -= alloc;
593 	hdev->num_msi_used += alloc;
594 
595 	return alloc;
596 }
597 
598 static int hclgevf_get_vector_index(struct hclgevf_dev *hdev, int vector)
599 {
600 	int i;
601 
602 	for (i = 0; i < hdev->num_msi; i++)
603 		if (vector == hdev->vector_irq[i])
604 			return i;
605 
606 	return -EINVAL;
607 }
608 
609 static int hclgevf_set_rss_algo_key(struct hclgevf_dev *hdev,
610 				    const u8 hfunc, const u8 *key)
611 {
612 	struct hclgevf_rss_config_cmd *req;
613 	unsigned int key_offset = 0;
614 	struct hclgevf_desc desc;
615 	int key_counts;
616 	int key_size;
617 	int ret;
618 
619 	key_counts = HCLGEVF_RSS_KEY_SIZE;
620 	req = (struct hclgevf_rss_config_cmd *)desc.data;
621 
622 	while (key_counts) {
623 		hclgevf_cmd_setup_basic_desc(&desc,
624 					     HCLGEVF_OPC_RSS_GENERIC_CONFIG,
625 					     false);
626 
627 		req->hash_config |= (hfunc & HCLGEVF_RSS_HASH_ALGO_MASK);
628 		req->hash_config |=
629 			(key_offset << HCLGEVF_RSS_HASH_KEY_OFFSET_B);
630 
631 		key_size = min(HCLGEVF_RSS_HASH_KEY_NUM, key_counts);
632 		memcpy(req->hash_key,
633 		       key + key_offset * HCLGEVF_RSS_HASH_KEY_NUM, key_size);
634 
635 		key_counts -= key_size;
636 		key_offset++;
637 		ret = hclgevf_cmd_send(&hdev->hw, &desc, 1);
638 		if (ret) {
639 			dev_err(&hdev->pdev->dev,
640 				"Configure RSS config fail, status = %d\n",
641 				ret);
642 			return ret;
643 		}
644 	}
645 
646 	return 0;
647 }
648 
649 static u32 hclgevf_get_rss_key_size(struct hnae3_handle *handle)
650 {
651 	return HCLGEVF_RSS_KEY_SIZE;
652 }
653 
654 static int hclgevf_set_rss_indir_table(struct hclgevf_dev *hdev)
655 {
656 	const u8 *indir = hdev->rss_cfg.rss_indirection_tbl;
657 	struct hclgevf_rss_indirection_table_cmd *req;
658 	struct hclgevf_desc desc;
659 	int rss_cfg_tbl_num;
660 	int status;
661 	int i, j;
662 
663 	req = (struct hclgevf_rss_indirection_table_cmd *)desc.data;
664 	rss_cfg_tbl_num = hdev->ae_dev->dev_specs.rss_ind_tbl_size /
665 			  HCLGEVF_RSS_CFG_TBL_SIZE;
666 
667 	for (i = 0; i < rss_cfg_tbl_num; i++) {
668 		hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INDIR_TABLE,
669 					     false);
670 		req->start_table_index =
671 			cpu_to_le16(i * HCLGEVF_RSS_CFG_TBL_SIZE);
672 		req->rss_set_bitmap = cpu_to_le16(HCLGEVF_RSS_SET_BITMAP_MSK);
673 		for (j = 0; j < HCLGEVF_RSS_CFG_TBL_SIZE; j++)
674 			req->rss_result[j] =
675 				indir[i * HCLGEVF_RSS_CFG_TBL_SIZE + j];
676 
677 		status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
678 		if (status) {
679 			dev_err(&hdev->pdev->dev,
680 				"VF failed(=%d) to set RSS indirection table\n",
681 				status);
682 			return status;
683 		}
684 	}
685 
686 	return 0;
687 }
688 
689 static int hclgevf_set_rss_tc_mode(struct hclgevf_dev *hdev,  u16 rss_size)
690 {
691 	struct hclgevf_rss_tc_mode_cmd *req;
692 	u16 tc_offset[HCLGEVF_MAX_TC_NUM];
693 	u16 tc_valid[HCLGEVF_MAX_TC_NUM];
694 	u16 tc_size[HCLGEVF_MAX_TC_NUM];
695 	struct hclgevf_desc desc;
696 	u16 roundup_size;
697 	unsigned int i;
698 	int status;
699 
700 	req = (struct hclgevf_rss_tc_mode_cmd *)desc.data;
701 
702 	roundup_size = roundup_pow_of_two(rss_size);
703 	roundup_size = ilog2(roundup_size);
704 
705 	for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) {
706 		tc_valid[i] = !!(hdev->hw_tc_map & BIT(i));
707 		tc_size[i] = roundup_size;
708 		tc_offset[i] = rss_size * i;
709 	}
710 
711 	hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_TC_MODE, false);
712 	for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) {
713 		u16 mode = 0;
714 
715 		hnae3_set_bit(mode, HCLGEVF_RSS_TC_VALID_B,
716 			      (tc_valid[i] & 0x1));
717 		hnae3_set_field(mode, HCLGEVF_RSS_TC_SIZE_M,
718 				HCLGEVF_RSS_TC_SIZE_S, tc_size[i]);
719 		hnae3_set_bit(mode, HCLGEVF_RSS_TC_SIZE_MSB_B,
720 			      tc_size[i] >> HCLGEVF_RSS_TC_SIZE_MSB_OFFSET &
721 			      0x1);
722 		hnae3_set_field(mode, HCLGEVF_RSS_TC_OFFSET_M,
723 				HCLGEVF_RSS_TC_OFFSET_S, tc_offset[i]);
724 
725 		req->rss_tc_mode[i] = cpu_to_le16(mode);
726 	}
727 	status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
728 	if (status)
729 		dev_err(&hdev->pdev->dev,
730 			"VF failed(=%d) to set rss tc mode\n", status);
731 
732 	return status;
733 }
734 
735 /* for revision 0x20, vf shared the same rss config with pf */
736 static int hclgevf_get_rss_hash_key(struct hclgevf_dev *hdev)
737 {
738 #define HCLGEVF_RSS_MBX_RESP_LEN	8
739 	struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
740 	u8 resp_msg[HCLGEVF_RSS_MBX_RESP_LEN];
741 	struct hclge_vf_to_pf_msg send_msg;
742 	u16 msg_num, hash_key_index;
743 	u8 index;
744 	int ret;
745 
746 	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_RSS_KEY, 0);
747 	msg_num = (HCLGEVF_RSS_KEY_SIZE + HCLGEVF_RSS_MBX_RESP_LEN - 1) /
748 			HCLGEVF_RSS_MBX_RESP_LEN;
749 	for (index = 0; index < msg_num; index++) {
750 		send_msg.data[0] = index;
751 		ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg,
752 					   HCLGEVF_RSS_MBX_RESP_LEN);
753 		if (ret) {
754 			dev_err(&hdev->pdev->dev,
755 				"VF get rss hash key from PF failed, ret=%d",
756 				ret);
757 			return ret;
758 		}
759 
760 		hash_key_index = HCLGEVF_RSS_MBX_RESP_LEN * index;
761 		if (index == msg_num - 1)
762 			memcpy(&rss_cfg->rss_hash_key[hash_key_index],
763 			       &resp_msg[0],
764 			       HCLGEVF_RSS_KEY_SIZE - hash_key_index);
765 		else
766 			memcpy(&rss_cfg->rss_hash_key[hash_key_index],
767 			       &resp_msg[0], HCLGEVF_RSS_MBX_RESP_LEN);
768 	}
769 
770 	return 0;
771 }
772 
773 static int hclgevf_get_rss(struct hnae3_handle *handle, u32 *indir, u8 *key,
774 			   u8 *hfunc)
775 {
776 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
777 	struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
778 	int i, ret;
779 
780 	if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) {
781 		/* Get hash algorithm */
782 		if (hfunc) {
783 			switch (rss_cfg->hash_algo) {
784 			case HCLGEVF_RSS_HASH_ALGO_TOEPLITZ:
785 				*hfunc = ETH_RSS_HASH_TOP;
786 				break;
787 			case HCLGEVF_RSS_HASH_ALGO_SIMPLE:
788 				*hfunc = ETH_RSS_HASH_XOR;
789 				break;
790 			default:
791 				*hfunc = ETH_RSS_HASH_UNKNOWN;
792 				break;
793 			}
794 		}
795 
796 		/* Get the RSS Key required by the user */
797 		if (key)
798 			memcpy(key, rss_cfg->rss_hash_key,
799 			       HCLGEVF_RSS_KEY_SIZE);
800 	} else {
801 		if (hfunc)
802 			*hfunc = ETH_RSS_HASH_TOP;
803 		if (key) {
804 			ret = hclgevf_get_rss_hash_key(hdev);
805 			if (ret)
806 				return ret;
807 			memcpy(key, rss_cfg->rss_hash_key,
808 			       HCLGEVF_RSS_KEY_SIZE);
809 		}
810 	}
811 
812 	if (indir)
813 		for (i = 0; i < hdev->ae_dev->dev_specs.rss_ind_tbl_size; i++)
814 			indir[i] = rss_cfg->rss_indirection_tbl[i];
815 
816 	return 0;
817 }
818 
819 static int hclgevf_parse_rss_hfunc(struct hclgevf_dev *hdev, const u8 hfunc,
820 				   u8 *hash_algo)
821 {
822 	switch (hfunc) {
823 	case ETH_RSS_HASH_TOP:
824 		*hash_algo = HCLGEVF_RSS_HASH_ALGO_TOEPLITZ;
825 		return 0;
826 	case ETH_RSS_HASH_XOR:
827 		*hash_algo = HCLGEVF_RSS_HASH_ALGO_SIMPLE;
828 		return 0;
829 	case ETH_RSS_HASH_NO_CHANGE:
830 		*hash_algo = hdev->rss_cfg.hash_algo;
831 		return 0;
832 	default:
833 		return -EINVAL;
834 	}
835 }
836 
837 static int hclgevf_set_rss(struct hnae3_handle *handle, const u32 *indir,
838 			   const u8 *key, const u8 hfunc)
839 {
840 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
841 	struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
842 	u8 hash_algo;
843 	int ret, i;
844 
845 	if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) {
846 		ret = hclgevf_parse_rss_hfunc(hdev, hfunc, &hash_algo);
847 		if (ret)
848 			return ret;
849 
850 		/* Set the RSS Hash Key if specififed by the user */
851 		if (key) {
852 			ret = hclgevf_set_rss_algo_key(hdev, hash_algo, key);
853 			if (ret) {
854 				dev_err(&hdev->pdev->dev,
855 					"invalid hfunc type %u\n", hfunc);
856 				return ret;
857 			}
858 
859 			/* Update the shadow RSS key with user specified qids */
860 			memcpy(rss_cfg->rss_hash_key, key,
861 			       HCLGEVF_RSS_KEY_SIZE);
862 		} else {
863 			ret = hclgevf_set_rss_algo_key(hdev, hash_algo,
864 						       rss_cfg->rss_hash_key);
865 			if (ret)
866 				return ret;
867 		}
868 		rss_cfg->hash_algo = hash_algo;
869 	}
870 
871 	/* update the shadow RSS table with user specified qids */
872 	for (i = 0; i < hdev->ae_dev->dev_specs.rss_ind_tbl_size; i++)
873 		rss_cfg->rss_indirection_tbl[i] = indir[i];
874 
875 	/* update the hardware */
876 	return hclgevf_set_rss_indir_table(hdev);
877 }
878 
879 static u8 hclgevf_get_rss_hash_bits(struct ethtool_rxnfc *nfc)
880 {
881 	u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGEVF_S_PORT_BIT : 0;
882 
883 	if (nfc->data & RXH_L4_B_2_3)
884 		hash_sets |= HCLGEVF_D_PORT_BIT;
885 	else
886 		hash_sets &= ~HCLGEVF_D_PORT_BIT;
887 
888 	if (nfc->data & RXH_IP_SRC)
889 		hash_sets |= HCLGEVF_S_IP_BIT;
890 	else
891 		hash_sets &= ~HCLGEVF_S_IP_BIT;
892 
893 	if (nfc->data & RXH_IP_DST)
894 		hash_sets |= HCLGEVF_D_IP_BIT;
895 	else
896 		hash_sets &= ~HCLGEVF_D_IP_BIT;
897 
898 	if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW)
899 		hash_sets |= HCLGEVF_V_TAG_BIT;
900 
901 	return hash_sets;
902 }
903 
904 static int hclgevf_init_rss_tuple_cmd(struct hnae3_handle *handle,
905 				      struct ethtool_rxnfc *nfc,
906 				      struct hclgevf_rss_input_tuple_cmd *req)
907 {
908 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
909 	struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
910 	u8 tuple_sets;
911 
912 	req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en;
913 	req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en;
914 	req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en;
915 	req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en;
916 	req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en;
917 	req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en;
918 	req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en;
919 	req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en;
920 
921 	tuple_sets = hclgevf_get_rss_hash_bits(nfc);
922 	switch (nfc->flow_type) {
923 	case TCP_V4_FLOW:
924 		req->ipv4_tcp_en = tuple_sets;
925 		break;
926 	case TCP_V6_FLOW:
927 		req->ipv6_tcp_en = tuple_sets;
928 		break;
929 	case UDP_V4_FLOW:
930 		req->ipv4_udp_en = tuple_sets;
931 		break;
932 	case UDP_V6_FLOW:
933 		req->ipv6_udp_en = tuple_sets;
934 		break;
935 	case SCTP_V4_FLOW:
936 		req->ipv4_sctp_en = tuple_sets;
937 		break;
938 	case SCTP_V6_FLOW:
939 		if (hdev->ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2 &&
940 		    (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)))
941 			return -EINVAL;
942 
943 		req->ipv6_sctp_en = tuple_sets;
944 		break;
945 	case IPV4_FLOW:
946 		req->ipv4_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER;
947 		break;
948 	case IPV6_FLOW:
949 		req->ipv6_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER;
950 		break;
951 	default:
952 		return -EINVAL;
953 	}
954 
955 	return 0;
956 }
957 
958 static int hclgevf_set_rss_tuple(struct hnae3_handle *handle,
959 				 struct ethtool_rxnfc *nfc)
960 {
961 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
962 	struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
963 	struct hclgevf_rss_input_tuple_cmd *req;
964 	struct hclgevf_desc desc;
965 	int ret;
966 
967 	if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)
968 		return -EOPNOTSUPP;
969 
970 	if (nfc->data &
971 	    ~(RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3))
972 		return -EINVAL;
973 
974 	req = (struct hclgevf_rss_input_tuple_cmd *)desc.data;
975 	hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false);
976 
977 	ret = hclgevf_init_rss_tuple_cmd(handle, nfc, req);
978 	if (ret) {
979 		dev_err(&hdev->pdev->dev,
980 			"failed to init rss tuple cmd, ret = %d\n", ret);
981 		return ret;
982 	}
983 
984 	ret = hclgevf_cmd_send(&hdev->hw, &desc, 1);
985 	if (ret) {
986 		dev_err(&hdev->pdev->dev,
987 			"Set rss tuple fail, status = %d\n", ret);
988 		return ret;
989 	}
990 
991 	rss_cfg->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en;
992 	rss_cfg->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en;
993 	rss_cfg->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en;
994 	rss_cfg->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en;
995 	rss_cfg->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en;
996 	rss_cfg->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en;
997 	rss_cfg->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en;
998 	rss_cfg->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en;
999 	return 0;
1000 }
1001 
1002 static int hclgevf_get_rss_tuple_by_flow_type(struct hclgevf_dev *hdev,
1003 					      int flow_type, u8 *tuple_sets)
1004 {
1005 	switch (flow_type) {
1006 	case TCP_V4_FLOW:
1007 		*tuple_sets = hdev->rss_cfg.rss_tuple_sets.ipv4_tcp_en;
1008 		break;
1009 	case UDP_V4_FLOW:
1010 		*tuple_sets = hdev->rss_cfg.rss_tuple_sets.ipv4_udp_en;
1011 		break;
1012 	case TCP_V6_FLOW:
1013 		*tuple_sets = hdev->rss_cfg.rss_tuple_sets.ipv6_tcp_en;
1014 		break;
1015 	case UDP_V6_FLOW:
1016 		*tuple_sets = hdev->rss_cfg.rss_tuple_sets.ipv6_udp_en;
1017 		break;
1018 	case SCTP_V4_FLOW:
1019 		*tuple_sets = hdev->rss_cfg.rss_tuple_sets.ipv4_sctp_en;
1020 		break;
1021 	case SCTP_V6_FLOW:
1022 		*tuple_sets = hdev->rss_cfg.rss_tuple_sets.ipv6_sctp_en;
1023 		break;
1024 	case IPV4_FLOW:
1025 	case IPV6_FLOW:
1026 		*tuple_sets = HCLGEVF_S_IP_BIT | HCLGEVF_D_IP_BIT;
1027 		break;
1028 	default:
1029 		return -EINVAL;
1030 	}
1031 
1032 	return 0;
1033 }
1034 
1035 static u64 hclgevf_convert_rss_tuple(u8 tuple_sets)
1036 {
1037 	u64 tuple_data = 0;
1038 
1039 	if (tuple_sets & HCLGEVF_D_PORT_BIT)
1040 		tuple_data |= RXH_L4_B_2_3;
1041 	if (tuple_sets & HCLGEVF_S_PORT_BIT)
1042 		tuple_data |= RXH_L4_B_0_1;
1043 	if (tuple_sets & HCLGEVF_D_IP_BIT)
1044 		tuple_data |= RXH_IP_DST;
1045 	if (tuple_sets & HCLGEVF_S_IP_BIT)
1046 		tuple_data |= RXH_IP_SRC;
1047 
1048 	return tuple_data;
1049 }
1050 
1051 static int hclgevf_get_rss_tuple(struct hnae3_handle *handle,
1052 				 struct ethtool_rxnfc *nfc)
1053 {
1054 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1055 	u8 tuple_sets;
1056 	int ret;
1057 
1058 	if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)
1059 		return -EOPNOTSUPP;
1060 
1061 	nfc->data = 0;
1062 
1063 	ret = hclgevf_get_rss_tuple_by_flow_type(hdev, nfc->flow_type,
1064 						 &tuple_sets);
1065 	if (ret || !tuple_sets)
1066 		return ret;
1067 
1068 	nfc->data = hclgevf_convert_rss_tuple(tuple_sets);
1069 
1070 	return 0;
1071 }
1072 
1073 static int hclgevf_set_rss_input_tuple(struct hclgevf_dev *hdev,
1074 				       struct hclgevf_rss_cfg *rss_cfg)
1075 {
1076 	struct hclgevf_rss_input_tuple_cmd *req;
1077 	struct hclgevf_desc desc;
1078 	int ret;
1079 
1080 	hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false);
1081 
1082 	req = (struct hclgevf_rss_input_tuple_cmd *)desc.data;
1083 
1084 	req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en;
1085 	req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en;
1086 	req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en;
1087 	req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en;
1088 	req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en;
1089 	req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en;
1090 	req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en;
1091 	req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en;
1092 
1093 	ret = hclgevf_cmd_send(&hdev->hw, &desc, 1);
1094 	if (ret)
1095 		dev_err(&hdev->pdev->dev,
1096 			"Configure rss input fail, status = %d\n", ret);
1097 	return ret;
1098 }
1099 
1100 static int hclgevf_get_tc_size(struct hnae3_handle *handle)
1101 {
1102 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1103 	struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
1104 
1105 	return rss_cfg->rss_size;
1106 }
1107 
1108 static int hclgevf_bind_ring_to_vector(struct hnae3_handle *handle, bool en,
1109 				       int vector_id,
1110 				       struct hnae3_ring_chain_node *ring_chain)
1111 {
1112 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1113 	struct hclge_vf_to_pf_msg send_msg;
1114 	struct hnae3_ring_chain_node *node;
1115 	int status;
1116 	int i = 0;
1117 
1118 	memset(&send_msg, 0, sizeof(send_msg));
1119 	send_msg.code = en ? HCLGE_MBX_MAP_RING_TO_VECTOR :
1120 		HCLGE_MBX_UNMAP_RING_TO_VECTOR;
1121 	send_msg.vector_id = vector_id;
1122 
1123 	for (node = ring_chain; node; node = node->next) {
1124 		send_msg.param[i].ring_type =
1125 				hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B);
1126 
1127 		send_msg.param[i].tqp_index = node->tqp_index;
1128 		send_msg.param[i].int_gl_index =
1129 					hnae3_get_field(node->int_gl_idx,
1130 							HNAE3_RING_GL_IDX_M,
1131 							HNAE3_RING_GL_IDX_S);
1132 
1133 		i++;
1134 		if (i == HCLGE_MBX_MAX_RING_CHAIN_PARAM_NUM || !node->next) {
1135 			send_msg.ring_num = i;
1136 
1137 			status = hclgevf_send_mbx_msg(hdev, &send_msg, false,
1138 						      NULL, 0);
1139 			if (status) {
1140 				dev_err(&hdev->pdev->dev,
1141 					"Map TQP fail, status is %d.\n",
1142 					status);
1143 				return status;
1144 			}
1145 			i = 0;
1146 		}
1147 	}
1148 
1149 	return 0;
1150 }
1151 
1152 static int hclgevf_map_ring_to_vector(struct hnae3_handle *handle, int vector,
1153 				      struct hnae3_ring_chain_node *ring_chain)
1154 {
1155 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1156 	int vector_id;
1157 
1158 	vector_id = hclgevf_get_vector_index(hdev, vector);
1159 	if (vector_id < 0) {
1160 		dev_err(&handle->pdev->dev,
1161 			"Get vector index fail. ret =%d\n", vector_id);
1162 		return vector_id;
1163 	}
1164 
1165 	return hclgevf_bind_ring_to_vector(handle, true, vector_id, ring_chain);
1166 }
1167 
1168 static int hclgevf_unmap_ring_from_vector(
1169 				struct hnae3_handle *handle,
1170 				int vector,
1171 				struct hnae3_ring_chain_node *ring_chain)
1172 {
1173 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1174 	int ret, vector_id;
1175 
1176 	if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state))
1177 		return 0;
1178 
1179 	vector_id = hclgevf_get_vector_index(hdev, vector);
1180 	if (vector_id < 0) {
1181 		dev_err(&handle->pdev->dev,
1182 			"Get vector index fail. ret =%d\n", vector_id);
1183 		return vector_id;
1184 	}
1185 
1186 	ret = hclgevf_bind_ring_to_vector(handle, false, vector_id, ring_chain);
1187 	if (ret)
1188 		dev_err(&handle->pdev->dev,
1189 			"Unmap ring from vector fail. vector=%d, ret =%d\n",
1190 			vector_id,
1191 			ret);
1192 
1193 	return ret;
1194 }
1195 
1196 static int hclgevf_put_vector(struct hnae3_handle *handle, int vector)
1197 {
1198 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1199 	int vector_id;
1200 
1201 	vector_id = hclgevf_get_vector_index(hdev, vector);
1202 	if (vector_id < 0) {
1203 		dev_err(&handle->pdev->dev,
1204 			"hclgevf_put_vector get vector index fail. ret =%d\n",
1205 			vector_id);
1206 		return vector_id;
1207 	}
1208 
1209 	hclgevf_free_vector(hdev, vector_id);
1210 
1211 	return 0;
1212 }
1213 
1214 static int hclgevf_cmd_set_promisc_mode(struct hclgevf_dev *hdev,
1215 					bool en_uc_pmc, bool en_mc_pmc,
1216 					bool en_bc_pmc)
1217 {
1218 	struct hnae3_handle *handle = &hdev->nic;
1219 	struct hclge_vf_to_pf_msg send_msg;
1220 	int ret;
1221 
1222 	memset(&send_msg, 0, sizeof(send_msg));
1223 	send_msg.code = HCLGE_MBX_SET_PROMISC_MODE;
1224 	send_msg.en_bc = en_bc_pmc ? 1 : 0;
1225 	send_msg.en_uc = en_uc_pmc ? 1 : 0;
1226 	send_msg.en_mc = en_mc_pmc ? 1 : 0;
1227 	send_msg.en_limit_promisc = test_bit(HNAE3_PFLAG_LIMIT_PROMISC,
1228 					     &handle->priv_flags) ? 1 : 0;
1229 
1230 	ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
1231 	if (ret)
1232 		dev_err(&hdev->pdev->dev,
1233 			"Set promisc mode fail, status is %d.\n", ret);
1234 
1235 	return ret;
1236 }
1237 
1238 static int hclgevf_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc,
1239 				    bool en_mc_pmc)
1240 {
1241 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1242 	bool en_bc_pmc;
1243 
1244 	en_bc_pmc = hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2;
1245 
1246 	return hclgevf_cmd_set_promisc_mode(hdev, en_uc_pmc, en_mc_pmc,
1247 					    en_bc_pmc);
1248 }
1249 
1250 static void hclgevf_request_update_promisc_mode(struct hnae3_handle *handle)
1251 {
1252 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1253 
1254 	set_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state);
1255 	hclgevf_task_schedule(hdev, 0);
1256 }
1257 
1258 static void hclgevf_sync_promisc_mode(struct hclgevf_dev *hdev)
1259 {
1260 	struct hnae3_handle *handle = &hdev->nic;
1261 	bool en_uc_pmc = handle->netdev_flags & HNAE3_UPE;
1262 	bool en_mc_pmc = handle->netdev_flags & HNAE3_MPE;
1263 	int ret;
1264 
1265 	if (test_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state)) {
1266 		ret = hclgevf_set_promisc_mode(handle, en_uc_pmc, en_mc_pmc);
1267 		if (!ret)
1268 			clear_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state);
1269 	}
1270 }
1271 
1272 static int hclgevf_tqp_enable_cmd_send(struct hclgevf_dev *hdev, u16 tqp_id,
1273 				       u16 stream_id, bool enable)
1274 {
1275 	struct hclgevf_cfg_com_tqp_queue_cmd *req;
1276 	struct hclgevf_desc desc;
1277 
1278 	req = (struct hclgevf_cfg_com_tqp_queue_cmd *)desc.data;
1279 
1280 	hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_CFG_COM_TQP_QUEUE,
1281 				     false);
1282 	req->tqp_id = cpu_to_le16(tqp_id & HCLGEVF_RING_ID_MASK);
1283 	req->stream_id = cpu_to_le16(stream_id);
1284 	if (enable)
1285 		req->enable |= 1U << HCLGEVF_TQP_ENABLE_B;
1286 
1287 	return hclgevf_cmd_send(&hdev->hw, &desc, 1);
1288 }
1289 
1290 static int hclgevf_tqp_enable(struct hnae3_handle *handle, bool enable)
1291 {
1292 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1293 	int ret;
1294 	u16 i;
1295 
1296 	for (i = 0; i < handle->kinfo.num_tqps; i++) {
1297 		ret = hclgevf_tqp_enable_cmd_send(hdev, i, 0, enable);
1298 		if (ret)
1299 			return ret;
1300 	}
1301 
1302 	return 0;
1303 }
1304 
1305 static void hclgevf_reset_tqp_stats(struct hnae3_handle *handle)
1306 {
1307 	struct hnae3_knic_private_info *kinfo = &handle->kinfo;
1308 	struct hclgevf_tqp *tqp;
1309 	int i;
1310 
1311 	for (i = 0; i < kinfo->num_tqps; i++) {
1312 		tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q);
1313 		memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats));
1314 	}
1315 }
1316 
1317 static int hclgevf_get_host_mac_addr(struct hclgevf_dev *hdev, u8 *p)
1318 {
1319 	struct hclge_vf_to_pf_msg send_msg;
1320 	u8 host_mac[ETH_ALEN];
1321 	int status;
1322 
1323 	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_MAC_ADDR, 0);
1324 	status = hclgevf_send_mbx_msg(hdev, &send_msg, true, host_mac,
1325 				      ETH_ALEN);
1326 	if (status) {
1327 		dev_err(&hdev->pdev->dev,
1328 			"fail to get VF MAC from host %d", status);
1329 		return status;
1330 	}
1331 
1332 	ether_addr_copy(p, host_mac);
1333 
1334 	return 0;
1335 }
1336 
1337 static void hclgevf_get_mac_addr(struct hnae3_handle *handle, u8 *p)
1338 {
1339 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1340 	u8 host_mac_addr[ETH_ALEN];
1341 
1342 	if (hclgevf_get_host_mac_addr(hdev, host_mac_addr))
1343 		return;
1344 
1345 	hdev->has_pf_mac = !is_zero_ether_addr(host_mac_addr);
1346 	if (hdev->has_pf_mac)
1347 		ether_addr_copy(p, host_mac_addr);
1348 	else
1349 		ether_addr_copy(p, hdev->hw.mac.mac_addr);
1350 }
1351 
1352 static int hclgevf_set_mac_addr(struct hnae3_handle *handle, const void *p,
1353 				bool is_first)
1354 {
1355 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1356 	u8 *old_mac_addr = (u8 *)hdev->hw.mac.mac_addr;
1357 	struct hclge_vf_to_pf_msg send_msg;
1358 	u8 *new_mac_addr = (u8 *)p;
1359 	int status;
1360 
1361 	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_UNICAST, 0);
1362 	send_msg.subcode = HCLGE_MBX_MAC_VLAN_UC_MODIFY;
1363 	ether_addr_copy(send_msg.data, new_mac_addr);
1364 	if (is_first && !hdev->has_pf_mac)
1365 		eth_zero_addr(&send_msg.data[ETH_ALEN]);
1366 	else
1367 		ether_addr_copy(&send_msg.data[ETH_ALEN], old_mac_addr);
1368 	status = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0);
1369 	if (!status)
1370 		ether_addr_copy(hdev->hw.mac.mac_addr, new_mac_addr);
1371 
1372 	return status;
1373 }
1374 
1375 static struct hclgevf_mac_addr_node *
1376 hclgevf_find_mac_node(struct list_head *list, const u8 *mac_addr)
1377 {
1378 	struct hclgevf_mac_addr_node *mac_node, *tmp;
1379 
1380 	list_for_each_entry_safe(mac_node, tmp, list, node)
1381 		if (ether_addr_equal(mac_addr, mac_node->mac_addr))
1382 			return mac_node;
1383 
1384 	return NULL;
1385 }
1386 
1387 static void hclgevf_update_mac_node(struct hclgevf_mac_addr_node *mac_node,
1388 				    enum HCLGEVF_MAC_NODE_STATE state)
1389 {
1390 	switch (state) {
1391 	/* from set_rx_mode or tmp_add_list */
1392 	case HCLGEVF_MAC_TO_ADD:
1393 		if (mac_node->state == HCLGEVF_MAC_TO_DEL)
1394 			mac_node->state = HCLGEVF_MAC_ACTIVE;
1395 		break;
1396 	/* only from set_rx_mode */
1397 	case HCLGEVF_MAC_TO_DEL:
1398 		if (mac_node->state == HCLGEVF_MAC_TO_ADD) {
1399 			list_del(&mac_node->node);
1400 			kfree(mac_node);
1401 		} else {
1402 			mac_node->state = HCLGEVF_MAC_TO_DEL;
1403 		}
1404 		break;
1405 	/* only from tmp_add_list, the mac_node->state won't be
1406 	 * HCLGEVF_MAC_ACTIVE
1407 	 */
1408 	case HCLGEVF_MAC_ACTIVE:
1409 		if (mac_node->state == HCLGEVF_MAC_TO_ADD)
1410 			mac_node->state = HCLGEVF_MAC_ACTIVE;
1411 		break;
1412 	}
1413 }
1414 
1415 static int hclgevf_update_mac_list(struct hnae3_handle *handle,
1416 				   enum HCLGEVF_MAC_NODE_STATE state,
1417 				   enum HCLGEVF_MAC_ADDR_TYPE mac_type,
1418 				   const unsigned char *addr)
1419 {
1420 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1421 	struct hclgevf_mac_addr_node *mac_node;
1422 	struct list_head *list;
1423 
1424 	list = (mac_type == HCLGEVF_MAC_ADDR_UC) ?
1425 	       &hdev->mac_table.uc_mac_list : &hdev->mac_table.mc_mac_list;
1426 
1427 	spin_lock_bh(&hdev->mac_table.mac_list_lock);
1428 
1429 	/* if the mac addr is already in the mac list, no need to add a new
1430 	 * one into it, just check the mac addr state, convert it to a new
1431 	 * new state, or just remove it, or do nothing.
1432 	 */
1433 	mac_node = hclgevf_find_mac_node(list, addr);
1434 	if (mac_node) {
1435 		hclgevf_update_mac_node(mac_node, state);
1436 		spin_unlock_bh(&hdev->mac_table.mac_list_lock);
1437 		return 0;
1438 	}
1439 	/* if this address is never added, unnecessary to delete */
1440 	if (state == HCLGEVF_MAC_TO_DEL) {
1441 		spin_unlock_bh(&hdev->mac_table.mac_list_lock);
1442 		return -ENOENT;
1443 	}
1444 
1445 	mac_node = kzalloc(sizeof(*mac_node), GFP_ATOMIC);
1446 	if (!mac_node) {
1447 		spin_unlock_bh(&hdev->mac_table.mac_list_lock);
1448 		return -ENOMEM;
1449 	}
1450 
1451 	mac_node->state = state;
1452 	ether_addr_copy(mac_node->mac_addr, addr);
1453 	list_add_tail(&mac_node->node, list);
1454 
1455 	spin_unlock_bh(&hdev->mac_table.mac_list_lock);
1456 	return 0;
1457 }
1458 
1459 static int hclgevf_add_uc_addr(struct hnae3_handle *handle,
1460 			       const unsigned char *addr)
1461 {
1462 	return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_ADD,
1463 				       HCLGEVF_MAC_ADDR_UC, addr);
1464 }
1465 
1466 static int hclgevf_rm_uc_addr(struct hnae3_handle *handle,
1467 			      const unsigned char *addr)
1468 {
1469 	return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_DEL,
1470 				       HCLGEVF_MAC_ADDR_UC, addr);
1471 }
1472 
1473 static int hclgevf_add_mc_addr(struct hnae3_handle *handle,
1474 			       const unsigned char *addr)
1475 {
1476 	return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_ADD,
1477 				       HCLGEVF_MAC_ADDR_MC, addr);
1478 }
1479 
1480 static int hclgevf_rm_mc_addr(struct hnae3_handle *handle,
1481 			      const unsigned char *addr)
1482 {
1483 	return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_DEL,
1484 				       HCLGEVF_MAC_ADDR_MC, addr);
1485 }
1486 
1487 static int hclgevf_add_del_mac_addr(struct hclgevf_dev *hdev,
1488 				    struct hclgevf_mac_addr_node *mac_node,
1489 				    enum HCLGEVF_MAC_ADDR_TYPE mac_type)
1490 {
1491 	struct hclge_vf_to_pf_msg send_msg;
1492 	u8 code, subcode;
1493 
1494 	if (mac_type == HCLGEVF_MAC_ADDR_UC) {
1495 		code = HCLGE_MBX_SET_UNICAST;
1496 		if (mac_node->state == HCLGEVF_MAC_TO_ADD)
1497 			subcode = HCLGE_MBX_MAC_VLAN_UC_ADD;
1498 		else
1499 			subcode = HCLGE_MBX_MAC_VLAN_UC_REMOVE;
1500 	} else {
1501 		code = HCLGE_MBX_SET_MULTICAST;
1502 		if (mac_node->state == HCLGEVF_MAC_TO_ADD)
1503 			subcode = HCLGE_MBX_MAC_VLAN_MC_ADD;
1504 		else
1505 			subcode = HCLGE_MBX_MAC_VLAN_MC_REMOVE;
1506 	}
1507 
1508 	hclgevf_build_send_msg(&send_msg, code, subcode);
1509 	ether_addr_copy(send_msg.data, mac_node->mac_addr);
1510 	return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
1511 }
1512 
1513 static void hclgevf_config_mac_list(struct hclgevf_dev *hdev,
1514 				    struct list_head *list,
1515 				    enum HCLGEVF_MAC_ADDR_TYPE mac_type)
1516 {
1517 	struct hclgevf_mac_addr_node *mac_node, *tmp;
1518 	int ret;
1519 
1520 	list_for_each_entry_safe(mac_node, tmp, list, node) {
1521 		ret = hclgevf_add_del_mac_addr(hdev, mac_node, mac_type);
1522 		if  (ret) {
1523 			dev_err(&hdev->pdev->dev,
1524 				"failed to configure mac %pM, state = %d, ret = %d\n",
1525 				mac_node->mac_addr, mac_node->state, ret);
1526 			return;
1527 		}
1528 		if (mac_node->state == HCLGEVF_MAC_TO_ADD) {
1529 			mac_node->state = HCLGEVF_MAC_ACTIVE;
1530 		} else {
1531 			list_del(&mac_node->node);
1532 			kfree(mac_node);
1533 		}
1534 	}
1535 }
1536 
1537 static void hclgevf_sync_from_add_list(struct list_head *add_list,
1538 				       struct list_head *mac_list)
1539 {
1540 	struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node;
1541 
1542 	list_for_each_entry_safe(mac_node, tmp, add_list, node) {
1543 		/* if the mac address from tmp_add_list is not in the
1544 		 * uc/mc_mac_list, it means have received a TO_DEL request
1545 		 * during the time window of sending mac config request to PF
1546 		 * If mac_node state is ACTIVE, then change its state to TO_DEL,
1547 		 * then it will be removed at next time. If is TO_ADD, it means
1548 		 * send TO_ADD request failed, so just remove the mac node.
1549 		 */
1550 		new_node = hclgevf_find_mac_node(mac_list, mac_node->mac_addr);
1551 		if (new_node) {
1552 			hclgevf_update_mac_node(new_node, mac_node->state);
1553 			list_del(&mac_node->node);
1554 			kfree(mac_node);
1555 		} else if (mac_node->state == HCLGEVF_MAC_ACTIVE) {
1556 			mac_node->state = HCLGEVF_MAC_TO_DEL;
1557 			list_move_tail(&mac_node->node, mac_list);
1558 		} else {
1559 			list_del(&mac_node->node);
1560 			kfree(mac_node);
1561 		}
1562 	}
1563 }
1564 
1565 static void hclgevf_sync_from_del_list(struct list_head *del_list,
1566 				       struct list_head *mac_list)
1567 {
1568 	struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node;
1569 
1570 	list_for_each_entry_safe(mac_node, tmp, del_list, node) {
1571 		new_node = hclgevf_find_mac_node(mac_list, mac_node->mac_addr);
1572 		if (new_node) {
1573 			/* If the mac addr is exist in the mac list, it means
1574 			 * received a new request TO_ADD during the time window
1575 			 * of sending mac addr configurrequest to PF, so just
1576 			 * change the mac state to ACTIVE.
1577 			 */
1578 			new_node->state = HCLGEVF_MAC_ACTIVE;
1579 			list_del(&mac_node->node);
1580 			kfree(mac_node);
1581 		} else {
1582 			list_move_tail(&mac_node->node, mac_list);
1583 		}
1584 	}
1585 }
1586 
1587 static void hclgevf_clear_list(struct list_head *list)
1588 {
1589 	struct hclgevf_mac_addr_node *mac_node, *tmp;
1590 
1591 	list_for_each_entry_safe(mac_node, tmp, list, node) {
1592 		list_del(&mac_node->node);
1593 		kfree(mac_node);
1594 	}
1595 }
1596 
1597 static void hclgevf_sync_mac_list(struct hclgevf_dev *hdev,
1598 				  enum HCLGEVF_MAC_ADDR_TYPE mac_type)
1599 {
1600 	struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node;
1601 	struct list_head tmp_add_list, tmp_del_list;
1602 	struct list_head *list;
1603 
1604 	INIT_LIST_HEAD(&tmp_add_list);
1605 	INIT_LIST_HEAD(&tmp_del_list);
1606 
1607 	/* move the mac addr to the tmp_add_list and tmp_del_list, then
1608 	 * we can add/delete these mac addr outside the spin lock
1609 	 */
1610 	list = (mac_type == HCLGEVF_MAC_ADDR_UC) ?
1611 		&hdev->mac_table.uc_mac_list : &hdev->mac_table.mc_mac_list;
1612 
1613 	spin_lock_bh(&hdev->mac_table.mac_list_lock);
1614 
1615 	list_for_each_entry_safe(mac_node, tmp, list, node) {
1616 		switch (mac_node->state) {
1617 		case HCLGEVF_MAC_TO_DEL:
1618 			list_move_tail(&mac_node->node, &tmp_del_list);
1619 			break;
1620 		case HCLGEVF_MAC_TO_ADD:
1621 			new_node = kzalloc(sizeof(*new_node), GFP_ATOMIC);
1622 			if (!new_node)
1623 				goto stop_traverse;
1624 
1625 			ether_addr_copy(new_node->mac_addr, mac_node->mac_addr);
1626 			new_node->state = mac_node->state;
1627 			list_add_tail(&new_node->node, &tmp_add_list);
1628 			break;
1629 		default:
1630 			break;
1631 		}
1632 	}
1633 
1634 stop_traverse:
1635 	spin_unlock_bh(&hdev->mac_table.mac_list_lock);
1636 
1637 	/* delete first, in order to get max mac table space for adding */
1638 	hclgevf_config_mac_list(hdev, &tmp_del_list, mac_type);
1639 	hclgevf_config_mac_list(hdev, &tmp_add_list, mac_type);
1640 
1641 	/* if some mac addresses were added/deleted fail, move back to the
1642 	 * mac_list, and retry at next time.
1643 	 */
1644 	spin_lock_bh(&hdev->mac_table.mac_list_lock);
1645 
1646 	hclgevf_sync_from_del_list(&tmp_del_list, list);
1647 	hclgevf_sync_from_add_list(&tmp_add_list, list);
1648 
1649 	spin_unlock_bh(&hdev->mac_table.mac_list_lock);
1650 }
1651 
1652 static void hclgevf_sync_mac_table(struct hclgevf_dev *hdev)
1653 {
1654 	hclgevf_sync_mac_list(hdev, HCLGEVF_MAC_ADDR_UC);
1655 	hclgevf_sync_mac_list(hdev, HCLGEVF_MAC_ADDR_MC);
1656 }
1657 
1658 static void hclgevf_uninit_mac_list(struct hclgevf_dev *hdev)
1659 {
1660 	spin_lock_bh(&hdev->mac_table.mac_list_lock);
1661 
1662 	hclgevf_clear_list(&hdev->mac_table.uc_mac_list);
1663 	hclgevf_clear_list(&hdev->mac_table.mc_mac_list);
1664 
1665 	spin_unlock_bh(&hdev->mac_table.mac_list_lock);
1666 }
1667 
1668 static int hclgevf_enable_vlan_filter(struct hnae3_handle *handle, bool enable)
1669 {
1670 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1671 	struct hnae3_ae_dev *ae_dev = hdev->ae_dev;
1672 	struct hclge_vf_to_pf_msg send_msg;
1673 
1674 	if (!test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps))
1675 		return -EOPNOTSUPP;
1676 
1677 	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN,
1678 			       HCLGE_MBX_ENABLE_VLAN_FILTER);
1679 	send_msg.data[0] = enable ? 1 : 0;
1680 
1681 	return hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0);
1682 }
1683 
1684 static int hclgevf_set_vlan_filter(struct hnae3_handle *handle,
1685 				   __be16 proto, u16 vlan_id,
1686 				   bool is_kill)
1687 {
1688 #define HCLGEVF_VLAN_MBX_IS_KILL_OFFSET	0
1689 #define HCLGEVF_VLAN_MBX_VLAN_ID_OFFSET	1
1690 #define HCLGEVF_VLAN_MBX_PROTO_OFFSET	3
1691 
1692 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1693 	struct hclge_vf_to_pf_msg send_msg;
1694 	int ret;
1695 
1696 	if (vlan_id > HCLGEVF_MAX_VLAN_ID)
1697 		return -EINVAL;
1698 
1699 	if (proto != htons(ETH_P_8021Q))
1700 		return -EPROTONOSUPPORT;
1701 
1702 	/* When device is resetting or reset failed, firmware is unable to
1703 	 * handle mailbox. Just record the vlan id, and remove it after
1704 	 * reset finished.
1705 	 */
1706 	if ((test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) ||
1707 	     test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) && is_kill) {
1708 		set_bit(vlan_id, hdev->vlan_del_fail_bmap);
1709 		return -EBUSY;
1710 	}
1711 
1712 	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN,
1713 			       HCLGE_MBX_VLAN_FILTER);
1714 	send_msg.data[HCLGEVF_VLAN_MBX_IS_KILL_OFFSET] = is_kill;
1715 	memcpy(&send_msg.data[HCLGEVF_VLAN_MBX_VLAN_ID_OFFSET], &vlan_id,
1716 	       sizeof(vlan_id));
1717 	memcpy(&send_msg.data[HCLGEVF_VLAN_MBX_PROTO_OFFSET], &proto,
1718 	       sizeof(proto));
1719 	/* when remove hw vlan filter failed, record the vlan id,
1720 	 * and try to remove it from hw later, to be consistence
1721 	 * with stack.
1722 	 */
1723 	ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0);
1724 	if (is_kill && ret)
1725 		set_bit(vlan_id, hdev->vlan_del_fail_bmap);
1726 
1727 	return ret;
1728 }
1729 
1730 static void hclgevf_sync_vlan_filter(struct hclgevf_dev *hdev)
1731 {
1732 #define HCLGEVF_MAX_SYNC_COUNT	60
1733 	struct hnae3_handle *handle = &hdev->nic;
1734 	int ret, sync_cnt = 0;
1735 	u16 vlan_id;
1736 
1737 	vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID);
1738 	while (vlan_id != VLAN_N_VID) {
1739 		ret = hclgevf_set_vlan_filter(handle, htons(ETH_P_8021Q),
1740 					      vlan_id, true);
1741 		if (ret)
1742 			return;
1743 
1744 		clear_bit(vlan_id, hdev->vlan_del_fail_bmap);
1745 		sync_cnt++;
1746 		if (sync_cnt >= HCLGEVF_MAX_SYNC_COUNT)
1747 			return;
1748 
1749 		vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID);
1750 	}
1751 }
1752 
1753 static int hclgevf_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable)
1754 {
1755 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1756 	struct hclge_vf_to_pf_msg send_msg;
1757 
1758 	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN,
1759 			       HCLGE_MBX_VLAN_RX_OFF_CFG);
1760 	send_msg.data[0] = enable ? 1 : 0;
1761 	return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
1762 }
1763 
1764 static int hclgevf_reset_tqp(struct hnae3_handle *handle)
1765 {
1766 #define HCLGEVF_RESET_ALL_QUEUE_DONE	1U
1767 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1768 	struct hclge_vf_to_pf_msg send_msg;
1769 	u8 return_status = 0;
1770 	int ret;
1771 	u16 i;
1772 
1773 	/* disable vf queue before send queue reset msg to PF */
1774 	ret = hclgevf_tqp_enable(handle, false);
1775 	if (ret) {
1776 		dev_err(&hdev->pdev->dev, "failed to disable tqp, ret = %d\n",
1777 			ret);
1778 		return ret;
1779 	}
1780 
1781 	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_QUEUE_RESET, 0);
1782 
1783 	ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, &return_status,
1784 				   sizeof(return_status));
1785 	if (ret || return_status == HCLGEVF_RESET_ALL_QUEUE_DONE)
1786 		return ret;
1787 
1788 	for (i = 1; i < handle->kinfo.num_tqps; i++) {
1789 		hclgevf_build_send_msg(&send_msg, HCLGE_MBX_QUEUE_RESET, 0);
1790 		memcpy(send_msg.data, &i, sizeof(i));
1791 		ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0);
1792 		if (ret)
1793 			return ret;
1794 	}
1795 
1796 	return 0;
1797 }
1798 
1799 static int hclgevf_set_mtu(struct hnae3_handle *handle, int new_mtu)
1800 {
1801 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1802 	struct hclge_vf_to_pf_msg send_msg;
1803 
1804 	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_MTU, 0);
1805 	memcpy(send_msg.data, &new_mtu, sizeof(new_mtu));
1806 	return hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0);
1807 }
1808 
1809 static int hclgevf_notify_client(struct hclgevf_dev *hdev,
1810 				 enum hnae3_reset_notify_type type)
1811 {
1812 	struct hnae3_client *client = hdev->nic_client;
1813 	struct hnae3_handle *handle = &hdev->nic;
1814 	int ret;
1815 
1816 	if (!test_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state) ||
1817 	    !client)
1818 		return 0;
1819 
1820 	if (!client->ops->reset_notify)
1821 		return -EOPNOTSUPP;
1822 
1823 	ret = client->ops->reset_notify(handle, type);
1824 	if (ret)
1825 		dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n",
1826 			type, ret);
1827 
1828 	return ret;
1829 }
1830 
1831 static int hclgevf_notify_roce_client(struct hclgevf_dev *hdev,
1832 				      enum hnae3_reset_notify_type type)
1833 {
1834 	struct hnae3_client *client = hdev->roce_client;
1835 	struct hnae3_handle *handle = &hdev->roce;
1836 	int ret;
1837 
1838 	if (!test_bit(HCLGEVF_STATE_ROCE_REGISTERED, &hdev->state) || !client)
1839 		return 0;
1840 
1841 	if (!client->ops->reset_notify)
1842 		return -EOPNOTSUPP;
1843 
1844 	ret = client->ops->reset_notify(handle, type);
1845 	if (ret)
1846 		dev_err(&hdev->pdev->dev, "notify roce client failed %d(%d)",
1847 			type, ret);
1848 	return ret;
1849 }
1850 
1851 static int hclgevf_reset_wait(struct hclgevf_dev *hdev)
1852 {
1853 #define HCLGEVF_RESET_WAIT_US	20000
1854 #define HCLGEVF_RESET_WAIT_CNT	2000
1855 #define HCLGEVF_RESET_WAIT_TIMEOUT_US	\
1856 	(HCLGEVF_RESET_WAIT_US * HCLGEVF_RESET_WAIT_CNT)
1857 
1858 	u32 val;
1859 	int ret;
1860 
1861 	if (hdev->reset_type == HNAE3_VF_RESET)
1862 		ret = readl_poll_timeout(hdev->hw.io_base +
1863 					 HCLGEVF_VF_RST_ING, val,
1864 					 !(val & HCLGEVF_VF_RST_ING_BIT),
1865 					 HCLGEVF_RESET_WAIT_US,
1866 					 HCLGEVF_RESET_WAIT_TIMEOUT_US);
1867 	else
1868 		ret = readl_poll_timeout(hdev->hw.io_base +
1869 					 HCLGEVF_RST_ING, val,
1870 					 !(val & HCLGEVF_RST_ING_BITS),
1871 					 HCLGEVF_RESET_WAIT_US,
1872 					 HCLGEVF_RESET_WAIT_TIMEOUT_US);
1873 
1874 	/* hardware completion status should be available by this time */
1875 	if (ret) {
1876 		dev_err(&hdev->pdev->dev,
1877 			"couldn't get reset done status from h/w, timeout!\n");
1878 		return ret;
1879 	}
1880 
1881 	/* we will wait a bit more to let reset of the stack to complete. This
1882 	 * might happen in case reset assertion was made by PF. Yes, this also
1883 	 * means we might end up waiting bit more even for VF reset.
1884 	 */
1885 	msleep(5000);
1886 
1887 	return 0;
1888 }
1889 
1890 static void hclgevf_reset_handshake(struct hclgevf_dev *hdev, bool enable)
1891 {
1892 	u32 reg_val;
1893 
1894 	reg_val = hclgevf_read_dev(&hdev->hw, HCLGEVF_NIC_CSQ_DEPTH_REG);
1895 	if (enable)
1896 		reg_val |= HCLGEVF_NIC_SW_RST_RDY;
1897 	else
1898 		reg_val &= ~HCLGEVF_NIC_SW_RST_RDY;
1899 
1900 	hclgevf_write_dev(&hdev->hw, HCLGEVF_NIC_CSQ_DEPTH_REG,
1901 			  reg_val);
1902 }
1903 
1904 static int hclgevf_reset_stack(struct hclgevf_dev *hdev)
1905 {
1906 	int ret;
1907 
1908 	/* uninitialize the nic client */
1909 	ret = hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT);
1910 	if (ret)
1911 		return ret;
1912 
1913 	/* re-initialize the hclge device */
1914 	ret = hclgevf_reset_hdev(hdev);
1915 	if (ret) {
1916 		dev_err(&hdev->pdev->dev,
1917 			"hclge device re-init failed, VF is disabled!\n");
1918 		return ret;
1919 	}
1920 
1921 	/* bring up the nic client again */
1922 	ret = hclgevf_notify_client(hdev, HNAE3_INIT_CLIENT);
1923 	if (ret)
1924 		return ret;
1925 
1926 	/* clear handshake status with IMP */
1927 	hclgevf_reset_handshake(hdev, false);
1928 
1929 	/* bring up the nic to enable TX/RX again */
1930 	return hclgevf_notify_client(hdev, HNAE3_UP_CLIENT);
1931 }
1932 
1933 static int hclgevf_reset_prepare_wait(struct hclgevf_dev *hdev)
1934 {
1935 #define HCLGEVF_RESET_SYNC_TIME 100
1936 
1937 	if (hdev->reset_type == HNAE3_VF_FUNC_RESET) {
1938 		struct hclge_vf_to_pf_msg send_msg;
1939 		int ret;
1940 
1941 		hclgevf_build_send_msg(&send_msg, HCLGE_MBX_RESET, 0);
1942 		ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0);
1943 		if (ret) {
1944 			dev_err(&hdev->pdev->dev,
1945 				"failed to assert VF reset, ret = %d\n", ret);
1946 			return ret;
1947 		}
1948 		hdev->rst_stats.vf_func_rst_cnt++;
1949 	}
1950 
1951 	set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state);
1952 	/* inform hardware that preparatory work is done */
1953 	msleep(HCLGEVF_RESET_SYNC_TIME);
1954 	hclgevf_reset_handshake(hdev, true);
1955 	dev_info(&hdev->pdev->dev, "prepare reset(%d) wait done\n",
1956 		 hdev->reset_type);
1957 
1958 	return 0;
1959 }
1960 
1961 static void hclgevf_dump_rst_info(struct hclgevf_dev *hdev)
1962 {
1963 	dev_info(&hdev->pdev->dev, "VF function reset count: %u\n",
1964 		 hdev->rst_stats.vf_func_rst_cnt);
1965 	dev_info(&hdev->pdev->dev, "FLR reset count: %u\n",
1966 		 hdev->rst_stats.flr_rst_cnt);
1967 	dev_info(&hdev->pdev->dev, "VF reset count: %u\n",
1968 		 hdev->rst_stats.vf_rst_cnt);
1969 	dev_info(&hdev->pdev->dev, "reset done count: %u\n",
1970 		 hdev->rst_stats.rst_done_cnt);
1971 	dev_info(&hdev->pdev->dev, "HW reset done count: %u\n",
1972 		 hdev->rst_stats.hw_rst_done_cnt);
1973 	dev_info(&hdev->pdev->dev, "reset count: %u\n",
1974 		 hdev->rst_stats.rst_cnt);
1975 	dev_info(&hdev->pdev->dev, "reset fail count: %u\n",
1976 		 hdev->rst_stats.rst_fail_cnt);
1977 	dev_info(&hdev->pdev->dev, "vector0 interrupt enable status: 0x%x\n",
1978 		 hclgevf_read_dev(&hdev->hw, HCLGEVF_MISC_VECTOR_REG_BASE));
1979 	dev_info(&hdev->pdev->dev, "vector0 interrupt status: 0x%x\n",
1980 		 hclgevf_read_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_STATE_REG));
1981 	dev_info(&hdev->pdev->dev, "handshake status: 0x%x\n",
1982 		 hclgevf_read_dev(&hdev->hw, HCLGEVF_NIC_CSQ_DEPTH_REG));
1983 	dev_info(&hdev->pdev->dev, "function reset status: 0x%x\n",
1984 		 hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING));
1985 	dev_info(&hdev->pdev->dev, "hdev state: 0x%lx\n", hdev->state);
1986 }
1987 
1988 static void hclgevf_reset_err_handle(struct hclgevf_dev *hdev)
1989 {
1990 	/* recover handshake status with IMP when reset fail */
1991 	hclgevf_reset_handshake(hdev, true);
1992 	hdev->rst_stats.rst_fail_cnt++;
1993 	dev_err(&hdev->pdev->dev, "failed to reset VF(%u)\n",
1994 		hdev->rst_stats.rst_fail_cnt);
1995 
1996 	if (hdev->rst_stats.rst_fail_cnt < HCLGEVF_RESET_MAX_FAIL_CNT)
1997 		set_bit(hdev->reset_type, &hdev->reset_pending);
1998 
1999 	if (hclgevf_is_reset_pending(hdev)) {
2000 		set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state);
2001 		hclgevf_reset_task_schedule(hdev);
2002 	} else {
2003 		set_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state);
2004 		hclgevf_dump_rst_info(hdev);
2005 	}
2006 }
2007 
2008 static int hclgevf_reset_prepare(struct hclgevf_dev *hdev)
2009 {
2010 	int ret;
2011 
2012 	hdev->rst_stats.rst_cnt++;
2013 
2014 	/* perform reset of the stack & ae device for a client */
2015 	ret = hclgevf_notify_roce_client(hdev, HNAE3_DOWN_CLIENT);
2016 	if (ret)
2017 		return ret;
2018 
2019 	rtnl_lock();
2020 	/* bring down the nic to stop any ongoing TX/RX */
2021 	ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT);
2022 	rtnl_unlock();
2023 	if (ret)
2024 		return ret;
2025 
2026 	return hclgevf_reset_prepare_wait(hdev);
2027 }
2028 
2029 static int hclgevf_reset_rebuild(struct hclgevf_dev *hdev)
2030 {
2031 	int ret;
2032 
2033 	hdev->rst_stats.hw_rst_done_cnt++;
2034 	ret = hclgevf_notify_roce_client(hdev, HNAE3_UNINIT_CLIENT);
2035 	if (ret)
2036 		return ret;
2037 
2038 	rtnl_lock();
2039 	/* now, re-initialize the nic client and ae device */
2040 	ret = hclgevf_reset_stack(hdev);
2041 	rtnl_unlock();
2042 	if (ret) {
2043 		dev_err(&hdev->pdev->dev, "failed to reset VF stack\n");
2044 		return ret;
2045 	}
2046 
2047 	ret = hclgevf_notify_roce_client(hdev, HNAE3_INIT_CLIENT);
2048 	/* ignore RoCE notify error if it fails HCLGEVF_RESET_MAX_FAIL_CNT - 1
2049 	 * times
2050 	 */
2051 	if (ret &&
2052 	    hdev->rst_stats.rst_fail_cnt < HCLGEVF_RESET_MAX_FAIL_CNT - 1)
2053 		return ret;
2054 
2055 	ret = hclgevf_notify_roce_client(hdev, HNAE3_UP_CLIENT);
2056 	if (ret)
2057 		return ret;
2058 
2059 	hdev->last_reset_time = jiffies;
2060 	hdev->rst_stats.rst_done_cnt++;
2061 	hdev->rst_stats.rst_fail_cnt = 0;
2062 	clear_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state);
2063 
2064 	return 0;
2065 }
2066 
2067 static void hclgevf_reset(struct hclgevf_dev *hdev)
2068 {
2069 	if (hclgevf_reset_prepare(hdev))
2070 		goto err_reset;
2071 
2072 	/* check if VF could successfully fetch the hardware reset completion
2073 	 * status from the hardware
2074 	 */
2075 	if (hclgevf_reset_wait(hdev)) {
2076 		/* can't do much in this situation, will disable VF */
2077 		dev_err(&hdev->pdev->dev,
2078 			"failed to fetch H/W reset completion status\n");
2079 		goto err_reset;
2080 	}
2081 
2082 	if (hclgevf_reset_rebuild(hdev))
2083 		goto err_reset;
2084 
2085 	return;
2086 
2087 err_reset:
2088 	hclgevf_reset_err_handle(hdev);
2089 }
2090 
2091 static enum hnae3_reset_type hclgevf_get_reset_level(struct hclgevf_dev *hdev,
2092 						     unsigned long *addr)
2093 {
2094 	enum hnae3_reset_type rst_level = HNAE3_NONE_RESET;
2095 
2096 	/* return the highest priority reset level amongst all */
2097 	if (test_bit(HNAE3_VF_RESET, addr)) {
2098 		rst_level = HNAE3_VF_RESET;
2099 		clear_bit(HNAE3_VF_RESET, addr);
2100 		clear_bit(HNAE3_VF_PF_FUNC_RESET, addr);
2101 		clear_bit(HNAE3_VF_FUNC_RESET, addr);
2102 	} else if (test_bit(HNAE3_VF_FULL_RESET, addr)) {
2103 		rst_level = HNAE3_VF_FULL_RESET;
2104 		clear_bit(HNAE3_VF_FULL_RESET, addr);
2105 		clear_bit(HNAE3_VF_FUNC_RESET, addr);
2106 	} else if (test_bit(HNAE3_VF_PF_FUNC_RESET, addr)) {
2107 		rst_level = HNAE3_VF_PF_FUNC_RESET;
2108 		clear_bit(HNAE3_VF_PF_FUNC_RESET, addr);
2109 		clear_bit(HNAE3_VF_FUNC_RESET, addr);
2110 	} else if (test_bit(HNAE3_VF_FUNC_RESET, addr)) {
2111 		rst_level = HNAE3_VF_FUNC_RESET;
2112 		clear_bit(HNAE3_VF_FUNC_RESET, addr);
2113 	} else if (test_bit(HNAE3_FLR_RESET, addr)) {
2114 		rst_level = HNAE3_FLR_RESET;
2115 		clear_bit(HNAE3_FLR_RESET, addr);
2116 	}
2117 
2118 	return rst_level;
2119 }
2120 
2121 static void hclgevf_reset_event(struct pci_dev *pdev,
2122 				struct hnae3_handle *handle)
2123 {
2124 	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2125 	struct hclgevf_dev *hdev = ae_dev->priv;
2126 
2127 	dev_info(&hdev->pdev->dev, "received reset request from VF enet\n");
2128 
2129 	if (hdev->default_reset_request)
2130 		hdev->reset_level =
2131 			hclgevf_get_reset_level(hdev,
2132 						&hdev->default_reset_request);
2133 	else
2134 		hdev->reset_level = HNAE3_VF_FUNC_RESET;
2135 
2136 	/* reset of this VF requested */
2137 	set_bit(HCLGEVF_RESET_REQUESTED, &hdev->reset_state);
2138 	hclgevf_reset_task_schedule(hdev);
2139 
2140 	hdev->last_reset_time = jiffies;
2141 }
2142 
2143 static void hclgevf_set_def_reset_request(struct hnae3_ae_dev *ae_dev,
2144 					  enum hnae3_reset_type rst_type)
2145 {
2146 	struct hclgevf_dev *hdev = ae_dev->priv;
2147 
2148 	set_bit(rst_type, &hdev->default_reset_request);
2149 }
2150 
2151 static void hclgevf_enable_vector(struct hclgevf_misc_vector *vector, bool en)
2152 {
2153 	writel(en ? 1 : 0, vector->addr);
2154 }
2155 
2156 static void hclgevf_reset_prepare_general(struct hnae3_ae_dev *ae_dev,
2157 					  enum hnae3_reset_type rst_type)
2158 {
2159 #define HCLGEVF_RESET_RETRY_WAIT_MS	500
2160 #define HCLGEVF_RESET_RETRY_CNT		5
2161 
2162 	struct hclgevf_dev *hdev = ae_dev->priv;
2163 	int retry_cnt = 0;
2164 	int ret;
2165 
2166 retry:
2167 	down(&hdev->reset_sem);
2168 	set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state);
2169 	hdev->reset_type = rst_type;
2170 	ret = hclgevf_reset_prepare(hdev);
2171 	if (ret) {
2172 		dev_err(&hdev->pdev->dev, "fail to prepare to reset, ret=%d\n",
2173 			ret);
2174 		if (hdev->reset_pending ||
2175 		    retry_cnt++ < HCLGEVF_RESET_RETRY_CNT) {
2176 			dev_err(&hdev->pdev->dev,
2177 				"reset_pending:0x%lx, retry_cnt:%d\n",
2178 				hdev->reset_pending, retry_cnt);
2179 			clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state);
2180 			up(&hdev->reset_sem);
2181 			msleep(HCLGEVF_RESET_RETRY_WAIT_MS);
2182 			goto retry;
2183 		}
2184 	}
2185 
2186 	/* disable misc vector before reset done */
2187 	hclgevf_enable_vector(&hdev->misc_vector, false);
2188 
2189 	if (hdev->reset_type == HNAE3_FLR_RESET)
2190 		hdev->rst_stats.flr_rst_cnt++;
2191 }
2192 
2193 static void hclgevf_reset_done(struct hnae3_ae_dev *ae_dev)
2194 {
2195 	struct hclgevf_dev *hdev = ae_dev->priv;
2196 	int ret;
2197 
2198 	hclgevf_enable_vector(&hdev->misc_vector, true);
2199 
2200 	ret = hclgevf_reset_rebuild(hdev);
2201 	if (ret)
2202 		dev_warn(&hdev->pdev->dev, "fail to rebuild, ret=%d\n",
2203 			 ret);
2204 
2205 	hdev->reset_type = HNAE3_NONE_RESET;
2206 	clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state);
2207 	up(&hdev->reset_sem);
2208 }
2209 
2210 static u32 hclgevf_get_fw_version(struct hnae3_handle *handle)
2211 {
2212 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2213 
2214 	return hdev->fw_version;
2215 }
2216 
2217 static void hclgevf_get_misc_vector(struct hclgevf_dev *hdev)
2218 {
2219 	struct hclgevf_misc_vector *vector = &hdev->misc_vector;
2220 
2221 	vector->vector_irq = pci_irq_vector(hdev->pdev,
2222 					    HCLGEVF_MISC_VECTOR_NUM);
2223 	vector->addr = hdev->hw.io_base + HCLGEVF_MISC_VECTOR_REG_BASE;
2224 	/* vector status always valid for Vector 0 */
2225 	hdev->vector_status[HCLGEVF_MISC_VECTOR_NUM] = 0;
2226 	hdev->vector_irq[HCLGEVF_MISC_VECTOR_NUM] = vector->vector_irq;
2227 
2228 	hdev->num_msi_left -= 1;
2229 	hdev->num_msi_used += 1;
2230 }
2231 
2232 void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev)
2233 {
2234 	if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) &&
2235 	    test_bit(HCLGEVF_STATE_SERVICE_INITED, &hdev->state) &&
2236 	    !test_and_set_bit(HCLGEVF_STATE_RST_SERVICE_SCHED,
2237 			      &hdev->state))
2238 		mod_delayed_work(hclgevf_wq, &hdev->service_task, 0);
2239 }
2240 
2241 void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev)
2242 {
2243 	if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) &&
2244 	    !test_and_set_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED,
2245 			      &hdev->state))
2246 		mod_delayed_work(hclgevf_wq, &hdev->service_task, 0);
2247 }
2248 
2249 static void hclgevf_task_schedule(struct hclgevf_dev *hdev,
2250 				  unsigned long delay)
2251 {
2252 	if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) &&
2253 	    !test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state))
2254 		mod_delayed_work(hclgevf_wq, &hdev->service_task, delay);
2255 }
2256 
2257 static void hclgevf_reset_service_task(struct hclgevf_dev *hdev)
2258 {
2259 #define	HCLGEVF_MAX_RESET_ATTEMPTS_CNT	3
2260 
2261 	if (!test_and_clear_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state))
2262 		return;
2263 
2264 	down(&hdev->reset_sem);
2265 	set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state);
2266 
2267 	if (test_and_clear_bit(HCLGEVF_RESET_PENDING,
2268 			       &hdev->reset_state)) {
2269 		/* PF has intimated that it is about to reset the hardware.
2270 		 * We now have to poll & check if hardware has actually
2271 		 * completed the reset sequence. On hardware reset completion,
2272 		 * VF needs to reset the client and ae device.
2273 		 */
2274 		hdev->reset_attempts = 0;
2275 
2276 		hdev->last_reset_time = jiffies;
2277 		hdev->reset_type =
2278 			hclgevf_get_reset_level(hdev, &hdev->reset_pending);
2279 		if (hdev->reset_type != HNAE3_NONE_RESET)
2280 			hclgevf_reset(hdev);
2281 	} else if (test_and_clear_bit(HCLGEVF_RESET_REQUESTED,
2282 				      &hdev->reset_state)) {
2283 		/* we could be here when either of below happens:
2284 		 * 1. reset was initiated due to watchdog timeout caused by
2285 		 *    a. IMP was earlier reset and our TX got choked down and
2286 		 *       which resulted in watchdog reacting and inducing VF
2287 		 *       reset. This also means our cmdq would be unreliable.
2288 		 *    b. problem in TX due to other lower layer(example link
2289 		 *       layer not functioning properly etc.)
2290 		 * 2. VF reset might have been initiated due to some config
2291 		 *    change.
2292 		 *
2293 		 * NOTE: Theres no clear way to detect above cases than to react
2294 		 * to the response of PF for this reset request. PF will ack the
2295 		 * 1b and 2. cases but we will not get any intimation about 1a
2296 		 * from PF as cmdq would be in unreliable state i.e. mailbox
2297 		 * communication between PF and VF would be broken.
2298 		 *
2299 		 * if we are never geting into pending state it means either:
2300 		 * 1. PF is not receiving our request which could be due to IMP
2301 		 *    reset
2302 		 * 2. PF is screwed
2303 		 * We cannot do much for 2. but to check first we can try reset
2304 		 * our PCIe + stack and see if it alleviates the problem.
2305 		 */
2306 		if (hdev->reset_attempts > HCLGEVF_MAX_RESET_ATTEMPTS_CNT) {
2307 			/* prepare for full reset of stack + pcie interface */
2308 			set_bit(HNAE3_VF_FULL_RESET, &hdev->reset_pending);
2309 
2310 			/* "defer" schedule the reset task again */
2311 			set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state);
2312 		} else {
2313 			hdev->reset_attempts++;
2314 
2315 			set_bit(hdev->reset_level, &hdev->reset_pending);
2316 			set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state);
2317 		}
2318 		hclgevf_reset_task_schedule(hdev);
2319 	}
2320 
2321 	hdev->reset_type = HNAE3_NONE_RESET;
2322 	clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state);
2323 	up(&hdev->reset_sem);
2324 }
2325 
2326 static void hclgevf_mailbox_service_task(struct hclgevf_dev *hdev)
2327 {
2328 	if (!test_and_clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state))
2329 		return;
2330 
2331 	if (test_and_set_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state))
2332 		return;
2333 
2334 	hclgevf_mbx_async_handler(hdev);
2335 
2336 	clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state);
2337 }
2338 
2339 static void hclgevf_keep_alive(struct hclgevf_dev *hdev)
2340 {
2341 	struct hclge_vf_to_pf_msg send_msg;
2342 	int ret;
2343 
2344 	if (test_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state))
2345 		return;
2346 
2347 	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_KEEP_ALIVE, 0);
2348 	ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
2349 	if (ret)
2350 		dev_err(&hdev->pdev->dev,
2351 			"VF sends keep alive cmd failed(=%d)\n", ret);
2352 }
2353 
2354 static void hclgevf_periodic_service_task(struct hclgevf_dev *hdev)
2355 {
2356 	unsigned long delta = round_jiffies_relative(HZ);
2357 	struct hnae3_handle *handle = &hdev->nic;
2358 
2359 	if (test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state))
2360 		return;
2361 
2362 	if (time_is_after_jiffies(hdev->last_serv_processed + HZ)) {
2363 		delta = jiffies - hdev->last_serv_processed;
2364 
2365 		if (delta < round_jiffies_relative(HZ)) {
2366 			delta = round_jiffies_relative(HZ) - delta;
2367 			goto out;
2368 		}
2369 	}
2370 
2371 	hdev->serv_processed_cnt++;
2372 	if (!(hdev->serv_processed_cnt % HCLGEVF_KEEP_ALIVE_TASK_INTERVAL))
2373 		hclgevf_keep_alive(hdev);
2374 
2375 	if (test_bit(HCLGEVF_STATE_DOWN, &hdev->state)) {
2376 		hdev->last_serv_processed = jiffies;
2377 		goto out;
2378 	}
2379 
2380 	if (!(hdev->serv_processed_cnt % HCLGEVF_STATS_TIMER_INTERVAL))
2381 		hclgevf_tqps_update_stats(handle);
2382 
2383 	/* VF does not need to request link status when this bit is set, because
2384 	 * PF will push its link status to VFs when link status changed.
2385 	 */
2386 	if (!test_bit(HCLGEVF_STATE_PF_PUSH_LINK_STATUS, &hdev->state))
2387 		hclgevf_request_link_info(hdev);
2388 
2389 	hclgevf_update_link_mode(hdev);
2390 
2391 	hclgevf_sync_vlan_filter(hdev);
2392 
2393 	hclgevf_sync_mac_table(hdev);
2394 
2395 	hclgevf_sync_promisc_mode(hdev);
2396 
2397 	hdev->last_serv_processed = jiffies;
2398 
2399 out:
2400 	hclgevf_task_schedule(hdev, delta);
2401 }
2402 
2403 static void hclgevf_service_task(struct work_struct *work)
2404 {
2405 	struct hclgevf_dev *hdev = container_of(work, struct hclgevf_dev,
2406 						service_task.work);
2407 
2408 	hclgevf_reset_service_task(hdev);
2409 	hclgevf_mailbox_service_task(hdev);
2410 	hclgevf_periodic_service_task(hdev);
2411 
2412 	/* Handle reset and mbx again in case periodical task delays the
2413 	 * handling by calling hclgevf_task_schedule() in
2414 	 * hclgevf_periodic_service_task()
2415 	 */
2416 	hclgevf_reset_service_task(hdev);
2417 	hclgevf_mailbox_service_task(hdev);
2418 }
2419 
2420 static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regclr)
2421 {
2422 	hclgevf_write_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_SRC_REG, regclr);
2423 }
2424 
2425 static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev,
2426 						      u32 *clearval)
2427 {
2428 	u32 val, cmdq_stat_reg, rst_ing_reg;
2429 
2430 	/* fetch the events from their corresponding regs */
2431 	cmdq_stat_reg = hclgevf_read_dev(&hdev->hw,
2432 					 HCLGEVF_VECTOR0_CMDQ_STATE_REG);
2433 	if (BIT(HCLGEVF_VECTOR0_RST_INT_B) & cmdq_stat_reg) {
2434 		rst_ing_reg = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING);
2435 		dev_info(&hdev->pdev->dev,
2436 			 "receive reset interrupt 0x%x!\n", rst_ing_reg);
2437 		set_bit(HNAE3_VF_RESET, &hdev->reset_pending);
2438 		set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state);
2439 		set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state);
2440 		*clearval = ~(1U << HCLGEVF_VECTOR0_RST_INT_B);
2441 		hdev->rst_stats.vf_rst_cnt++;
2442 		/* set up VF hardware reset status, its PF will clear
2443 		 * this status when PF has initialized done.
2444 		 */
2445 		val = hclgevf_read_dev(&hdev->hw, HCLGEVF_VF_RST_ING);
2446 		hclgevf_write_dev(&hdev->hw, HCLGEVF_VF_RST_ING,
2447 				  val | HCLGEVF_VF_RST_ING_BIT);
2448 		return HCLGEVF_VECTOR0_EVENT_RST;
2449 	}
2450 
2451 	/* check for vector0 mailbox(=CMDQ RX) event source */
2452 	if (BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) {
2453 		/* for revision 0x21, clearing interrupt is writing bit 0
2454 		 * to the clear register, writing bit 1 means to keep the
2455 		 * old value.
2456 		 * for revision 0x20, the clear register is a read & write
2457 		 * register, so we should just write 0 to the bit we are
2458 		 * handling, and keep other bits as cmdq_stat_reg.
2459 		 */
2460 		if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2)
2461 			*clearval = ~(1U << HCLGEVF_VECTOR0_RX_CMDQ_INT_B);
2462 		else
2463 			*clearval = cmdq_stat_reg &
2464 				    ~BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B);
2465 
2466 		return HCLGEVF_VECTOR0_EVENT_MBX;
2467 	}
2468 
2469 	/* print other vector0 event source */
2470 	dev_info(&hdev->pdev->dev,
2471 		 "vector 0 interrupt from unknown source, cmdq_src = %#x\n",
2472 		 cmdq_stat_reg);
2473 
2474 	return HCLGEVF_VECTOR0_EVENT_OTHER;
2475 }
2476 
2477 static irqreturn_t hclgevf_misc_irq_handle(int irq, void *data)
2478 {
2479 	enum hclgevf_evt_cause event_cause;
2480 	struct hclgevf_dev *hdev = data;
2481 	u32 clearval;
2482 
2483 	hclgevf_enable_vector(&hdev->misc_vector, false);
2484 	event_cause = hclgevf_check_evt_cause(hdev, &clearval);
2485 	if (event_cause != HCLGEVF_VECTOR0_EVENT_OTHER)
2486 		hclgevf_clear_event_cause(hdev, clearval);
2487 
2488 	switch (event_cause) {
2489 	case HCLGEVF_VECTOR0_EVENT_RST:
2490 		hclgevf_reset_task_schedule(hdev);
2491 		break;
2492 	case HCLGEVF_VECTOR0_EVENT_MBX:
2493 		hclgevf_mbx_handler(hdev);
2494 		break;
2495 	default:
2496 		break;
2497 	}
2498 
2499 	if (event_cause != HCLGEVF_VECTOR0_EVENT_OTHER)
2500 		hclgevf_enable_vector(&hdev->misc_vector, true);
2501 
2502 	return IRQ_HANDLED;
2503 }
2504 
2505 static int hclgevf_configure(struct hclgevf_dev *hdev)
2506 {
2507 	int ret;
2508 
2509 	hdev->gro_en = true;
2510 
2511 	ret = hclgevf_get_basic_info(hdev);
2512 	if (ret)
2513 		return ret;
2514 
2515 	/* get current port based vlan state from PF */
2516 	ret = hclgevf_get_port_base_vlan_filter_state(hdev);
2517 	if (ret)
2518 		return ret;
2519 
2520 	/* get queue configuration from PF */
2521 	ret = hclgevf_get_queue_info(hdev);
2522 	if (ret)
2523 		return ret;
2524 
2525 	/* get queue depth info from PF */
2526 	ret = hclgevf_get_queue_depth(hdev);
2527 	if (ret)
2528 		return ret;
2529 
2530 	return hclgevf_get_pf_media_type(hdev);
2531 }
2532 
2533 static int hclgevf_alloc_hdev(struct hnae3_ae_dev *ae_dev)
2534 {
2535 	struct pci_dev *pdev = ae_dev->pdev;
2536 	struct hclgevf_dev *hdev;
2537 
2538 	hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL);
2539 	if (!hdev)
2540 		return -ENOMEM;
2541 
2542 	hdev->pdev = pdev;
2543 	hdev->ae_dev = ae_dev;
2544 	ae_dev->priv = hdev;
2545 
2546 	return 0;
2547 }
2548 
2549 static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev)
2550 {
2551 	struct hnae3_handle *roce = &hdev->roce;
2552 	struct hnae3_handle *nic = &hdev->nic;
2553 
2554 	roce->rinfo.num_vectors = hdev->num_roce_msix;
2555 
2556 	if (hdev->num_msi_left < roce->rinfo.num_vectors ||
2557 	    hdev->num_msi_left == 0)
2558 		return -EINVAL;
2559 
2560 	roce->rinfo.base_vector = hdev->roce_base_msix_offset;
2561 
2562 	roce->rinfo.netdev = nic->kinfo.netdev;
2563 	roce->rinfo.roce_io_base = hdev->hw.io_base;
2564 	roce->rinfo.roce_mem_base = hdev->hw.mem_base;
2565 
2566 	roce->pdev = nic->pdev;
2567 	roce->ae_algo = nic->ae_algo;
2568 	roce->numa_node_mask = nic->numa_node_mask;
2569 
2570 	return 0;
2571 }
2572 
2573 static int hclgevf_config_gro(struct hclgevf_dev *hdev)
2574 {
2575 	struct hclgevf_cfg_gro_status_cmd *req;
2576 	struct hclgevf_desc desc;
2577 	int ret;
2578 
2579 	if (!hnae3_dev_gro_supported(hdev))
2580 		return 0;
2581 
2582 	hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_GRO_GENERIC_CONFIG,
2583 				     false);
2584 	req = (struct hclgevf_cfg_gro_status_cmd *)desc.data;
2585 
2586 	req->gro_en = hdev->gro_en ? 1 : 0;
2587 
2588 	ret = hclgevf_cmd_send(&hdev->hw, &desc, 1);
2589 	if (ret)
2590 		dev_err(&hdev->pdev->dev,
2591 			"VF GRO hardware config cmd failed, ret = %d.\n", ret);
2592 
2593 	return ret;
2594 }
2595 
2596 static int hclgevf_rss_init_cfg(struct hclgevf_dev *hdev)
2597 {
2598 	u16 rss_ind_tbl_size = hdev->ae_dev->dev_specs.rss_ind_tbl_size;
2599 	struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
2600 	struct hclgevf_rss_tuple_cfg *tuple_sets;
2601 	u32 i;
2602 
2603 	rss_cfg->hash_algo = HCLGEVF_RSS_HASH_ALGO_TOEPLITZ;
2604 	rss_cfg->rss_size = hdev->nic.kinfo.rss_size;
2605 	tuple_sets = &rss_cfg->rss_tuple_sets;
2606 	if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) {
2607 		u8 *rss_ind_tbl;
2608 
2609 		rss_cfg->hash_algo = HCLGEVF_RSS_HASH_ALGO_SIMPLE;
2610 
2611 		rss_ind_tbl = devm_kcalloc(&hdev->pdev->dev, rss_ind_tbl_size,
2612 					   sizeof(*rss_ind_tbl), GFP_KERNEL);
2613 		if (!rss_ind_tbl)
2614 			return -ENOMEM;
2615 
2616 		rss_cfg->rss_indirection_tbl = rss_ind_tbl;
2617 		memcpy(rss_cfg->rss_hash_key, hclgevf_hash_key,
2618 		       HCLGEVF_RSS_KEY_SIZE);
2619 
2620 		tuple_sets->ipv4_tcp_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER;
2621 		tuple_sets->ipv4_udp_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER;
2622 		tuple_sets->ipv4_sctp_en = HCLGEVF_RSS_INPUT_TUPLE_SCTP;
2623 		tuple_sets->ipv4_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER;
2624 		tuple_sets->ipv6_tcp_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER;
2625 		tuple_sets->ipv6_udp_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER;
2626 		tuple_sets->ipv6_sctp_en =
2627 			hdev->ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2 ?
2628 					HCLGEVF_RSS_INPUT_TUPLE_SCTP_NO_PORT :
2629 					HCLGEVF_RSS_INPUT_TUPLE_SCTP;
2630 		tuple_sets->ipv6_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER;
2631 	}
2632 
2633 	/* Initialize RSS indirect table */
2634 	for (i = 0; i < rss_ind_tbl_size; i++)
2635 		rss_cfg->rss_indirection_tbl[i] = i % rss_cfg->rss_size;
2636 
2637 	return 0;
2638 }
2639 
2640 static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev)
2641 {
2642 	struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
2643 	int ret;
2644 
2645 	if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) {
2646 		ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo,
2647 					       rss_cfg->rss_hash_key);
2648 		if (ret)
2649 			return ret;
2650 
2651 		ret = hclgevf_set_rss_input_tuple(hdev, rss_cfg);
2652 		if (ret)
2653 			return ret;
2654 	}
2655 
2656 	ret = hclgevf_set_rss_indir_table(hdev);
2657 	if (ret)
2658 		return ret;
2659 
2660 	return hclgevf_set_rss_tc_mode(hdev, rss_cfg->rss_size);
2661 }
2662 
2663 static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev)
2664 {
2665 	struct hnae3_handle *nic = &hdev->nic;
2666 	int ret;
2667 
2668 	ret = hclgevf_en_hw_strip_rxvtag(nic, true);
2669 	if (ret) {
2670 		dev_err(&hdev->pdev->dev,
2671 			"failed to enable rx vlan offload, ret = %d\n", ret);
2672 		return ret;
2673 	}
2674 
2675 	return hclgevf_set_vlan_filter(&hdev->nic, htons(ETH_P_8021Q), 0,
2676 				       false);
2677 }
2678 
2679 static void hclgevf_flush_link_update(struct hclgevf_dev *hdev)
2680 {
2681 #define HCLGEVF_FLUSH_LINK_TIMEOUT	100000
2682 
2683 	unsigned long last = hdev->serv_processed_cnt;
2684 	int i = 0;
2685 
2686 	while (test_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state) &&
2687 	       i++ < HCLGEVF_FLUSH_LINK_TIMEOUT &&
2688 	       last == hdev->serv_processed_cnt)
2689 		usleep_range(1, 1);
2690 }
2691 
2692 static void hclgevf_set_timer_task(struct hnae3_handle *handle, bool enable)
2693 {
2694 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2695 
2696 	if (enable) {
2697 		hclgevf_task_schedule(hdev, 0);
2698 	} else {
2699 		set_bit(HCLGEVF_STATE_DOWN, &hdev->state);
2700 
2701 		/* flush memory to make sure DOWN is seen by service task */
2702 		smp_mb__before_atomic();
2703 		hclgevf_flush_link_update(hdev);
2704 	}
2705 }
2706 
2707 static int hclgevf_ae_start(struct hnae3_handle *handle)
2708 {
2709 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2710 
2711 	clear_bit(HCLGEVF_STATE_DOWN, &hdev->state);
2712 	clear_bit(HCLGEVF_STATE_PF_PUSH_LINK_STATUS, &hdev->state);
2713 
2714 	hclgevf_reset_tqp_stats(handle);
2715 
2716 	hclgevf_request_link_info(hdev);
2717 
2718 	hclgevf_update_link_mode(hdev);
2719 
2720 	return 0;
2721 }
2722 
2723 static void hclgevf_ae_stop(struct hnae3_handle *handle)
2724 {
2725 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2726 
2727 	set_bit(HCLGEVF_STATE_DOWN, &hdev->state);
2728 
2729 	if (hdev->reset_type != HNAE3_VF_RESET)
2730 		hclgevf_reset_tqp(handle);
2731 
2732 	hclgevf_reset_tqp_stats(handle);
2733 	hclgevf_update_link_status(hdev, 0);
2734 }
2735 
2736 static int hclgevf_set_alive(struct hnae3_handle *handle, bool alive)
2737 {
2738 #define HCLGEVF_STATE_ALIVE	1
2739 #define HCLGEVF_STATE_NOT_ALIVE	0
2740 
2741 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2742 	struct hclge_vf_to_pf_msg send_msg;
2743 
2744 	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_ALIVE, 0);
2745 	send_msg.data[0] = alive ? HCLGEVF_STATE_ALIVE :
2746 				HCLGEVF_STATE_NOT_ALIVE;
2747 	return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
2748 }
2749 
2750 static int hclgevf_client_start(struct hnae3_handle *handle)
2751 {
2752 	return hclgevf_set_alive(handle, true);
2753 }
2754 
2755 static void hclgevf_client_stop(struct hnae3_handle *handle)
2756 {
2757 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2758 	int ret;
2759 
2760 	ret = hclgevf_set_alive(handle, false);
2761 	if (ret)
2762 		dev_warn(&hdev->pdev->dev,
2763 			 "%s failed %d\n", __func__, ret);
2764 }
2765 
2766 static void hclgevf_state_init(struct hclgevf_dev *hdev)
2767 {
2768 	clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state);
2769 	clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state);
2770 	clear_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state);
2771 
2772 	INIT_DELAYED_WORK(&hdev->service_task, hclgevf_service_task);
2773 
2774 	mutex_init(&hdev->mbx_resp.mbx_mutex);
2775 	sema_init(&hdev->reset_sem, 1);
2776 
2777 	spin_lock_init(&hdev->mac_table.mac_list_lock);
2778 	INIT_LIST_HEAD(&hdev->mac_table.uc_mac_list);
2779 	INIT_LIST_HEAD(&hdev->mac_table.mc_mac_list);
2780 
2781 	/* bring the device down */
2782 	set_bit(HCLGEVF_STATE_DOWN, &hdev->state);
2783 }
2784 
2785 static void hclgevf_state_uninit(struct hclgevf_dev *hdev)
2786 {
2787 	set_bit(HCLGEVF_STATE_DOWN, &hdev->state);
2788 	set_bit(HCLGEVF_STATE_REMOVING, &hdev->state);
2789 
2790 	if (hdev->service_task.work.func)
2791 		cancel_delayed_work_sync(&hdev->service_task);
2792 
2793 	mutex_destroy(&hdev->mbx_resp.mbx_mutex);
2794 }
2795 
2796 static int hclgevf_init_msi(struct hclgevf_dev *hdev)
2797 {
2798 	struct pci_dev *pdev = hdev->pdev;
2799 	int vectors;
2800 	int i;
2801 
2802 	if (hnae3_dev_roce_supported(hdev))
2803 		vectors = pci_alloc_irq_vectors(pdev,
2804 						hdev->roce_base_msix_offset + 1,
2805 						hdev->num_msi,
2806 						PCI_IRQ_MSIX);
2807 	else
2808 		vectors = pci_alloc_irq_vectors(pdev, HNAE3_MIN_VECTOR_NUM,
2809 						hdev->num_msi,
2810 						PCI_IRQ_MSI | PCI_IRQ_MSIX);
2811 
2812 	if (vectors < 0) {
2813 		dev_err(&pdev->dev,
2814 			"failed(%d) to allocate MSI/MSI-X vectors\n",
2815 			vectors);
2816 		return vectors;
2817 	}
2818 	if (vectors < hdev->num_msi)
2819 		dev_warn(&hdev->pdev->dev,
2820 			 "requested %u MSI/MSI-X, but allocated %d MSI/MSI-X\n",
2821 			 hdev->num_msi, vectors);
2822 
2823 	hdev->num_msi = vectors;
2824 	hdev->num_msi_left = vectors;
2825 
2826 	hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
2827 					   sizeof(u16), GFP_KERNEL);
2828 	if (!hdev->vector_status) {
2829 		pci_free_irq_vectors(pdev);
2830 		return -ENOMEM;
2831 	}
2832 
2833 	for (i = 0; i < hdev->num_msi; i++)
2834 		hdev->vector_status[i] = HCLGEVF_INVALID_VPORT;
2835 
2836 	hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi,
2837 					sizeof(int), GFP_KERNEL);
2838 	if (!hdev->vector_irq) {
2839 		devm_kfree(&pdev->dev, hdev->vector_status);
2840 		pci_free_irq_vectors(pdev);
2841 		return -ENOMEM;
2842 	}
2843 
2844 	return 0;
2845 }
2846 
2847 static void hclgevf_uninit_msi(struct hclgevf_dev *hdev)
2848 {
2849 	struct pci_dev *pdev = hdev->pdev;
2850 
2851 	devm_kfree(&pdev->dev, hdev->vector_status);
2852 	devm_kfree(&pdev->dev, hdev->vector_irq);
2853 	pci_free_irq_vectors(pdev);
2854 }
2855 
2856 static int hclgevf_misc_irq_init(struct hclgevf_dev *hdev)
2857 {
2858 	int ret;
2859 
2860 	hclgevf_get_misc_vector(hdev);
2861 
2862 	snprintf(hdev->misc_vector.name, HNAE3_INT_NAME_LEN, "%s-misc-%s",
2863 		 HCLGEVF_NAME, pci_name(hdev->pdev));
2864 	ret = request_irq(hdev->misc_vector.vector_irq, hclgevf_misc_irq_handle,
2865 			  0, hdev->misc_vector.name, hdev);
2866 	if (ret) {
2867 		dev_err(&hdev->pdev->dev, "VF failed to request misc irq(%d)\n",
2868 			hdev->misc_vector.vector_irq);
2869 		return ret;
2870 	}
2871 
2872 	hclgevf_clear_event_cause(hdev, 0);
2873 
2874 	/* enable misc. vector(vector 0) */
2875 	hclgevf_enable_vector(&hdev->misc_vector, true);
2876 
2877 	return ret;
2878 }
2879 
2880 static void hclgevf_misc_irq_uninit(struct hclgevf_dev *hdev)
2881 {
2882 	/* disable misc vector(vector 0) */
2883 	hclgevf_enable_vector(&hdev->misc_vector, false);
2884 	synchronize_irq(hdev->misc_vector.vector_irq);
2885 	free_irq(hdev->misc_vector.vector_irq, hdev);
2886 	hclgevf_free_vector(hdev, 0);
2887 }
2888 
2889 static void hclgevf_info_show(struct hclgevf_dev *hdev)
2890 {
2891 	struct device *dev = &hdev->pdev->dev;
2892 
2893 	dev_info(dev, "VF info begin:\n");
2894 
2895 	dev_info(dev, "Task queue pairs numbers: %u\n", hdev->num_tqps);
2896 	dev_info(dev, "Desc num per TX queue: %u\n", hdev->num_tx_desc);
2897 	dev_info(dev, "Desc num per RX queue: %u\n", hdev->num_rx_desc);
2898 	dev_info(dev, "Numbers of vports: %u\n", hdev->num_alloc_vport);
2899 	dev_info(dev, "HW tc map: 0x%x\n", hdev->hw_tc_map);
2900 	dev_info(dev, "PF media type of this VF: %u\n",
2901 		 hdev->hw.mac.media_type);
2902 
2903 	dev_info(dev, "VF info end.\n");
2904 }
2905 
2906 static int hclgevf_init_nic_client_instance(struct hnae3_ae_dev *ae_dev,
2907 					    struct hnae3_client *client)
2908 {
2909 	struct hclgevf_dev *hdev = ae_dev->priv;
2910 	int rst_cnt = hdev->rst_stats.rst_cnt;
2911 	int ret;
2912 
2913 	ret = client->ops->init_instance(&hdev->nic);
2914 	if (ret)
2915 		return ret;
2916 
2917 	set_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state);
2918 	if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) ||
2919 	    rst_cnt != hdev->rst_stats.rst_cnt) {
2920 		clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state);
2921 
2922 		client->ops->uninit_instance(&hdev->nic, 0);
2923 		return -EBUSY;
2924 	}
2925 
2926 	hnae3_set_client_init_flag(client, ae_dev, 1);
2927 
2928 	if (netif_msg_drv(&hdev->nic))
2929 		hclgevf_info_show(hdev);
2930 
2931 	return 0;
2932 }
2933 
2934 static int hclgevf_init_roce_client_instance(struct hnae3_ae_dev *ae_dev,
2935 					     struct hnae3_client *client)
2936 {
2937 	struct hclgevf_dev *hdev = ae_dev->priv;
2938 	int ret;
2939 
2940 	if (!hnae3_dev_roce_supported(hdev) || !hdev->roce_client ||
2941 	    !hdev->nic_client)
2942 		return 0;
2943 
2944 	ret = hclgevf_init_roce_base_info(hdev);
2945 	if (ret)
2946 		return ret;
2947 
2948 	ret = client->ops->init_instance(&hdev->roce);
2949 	if (ret)
2950 		return ret;
2951 
2952 	set_bit(HCLGEVF_STATE_ROCE_REGISTERED, &hdev->state);
2953 	hnae3_set_client_init_flag(client, ae_dev, 1);
2954 
2955 	return 0;
2956 }
2957 
2958 static int hclgevf_init_client_instance(struct hnae3_client *client,
2959 					struct hnae3_ae_dev *ae_dev)
2960 {
2961 	struct hclgevf_dev *hdev = ae_dev->priv;
2962 	int ret;
2963 
2964 	switch (client->type) {
2965 	case HNAE3_CLIENT_KNIC:
2966 		hdev->nic_client = client;
2967 		hdev->nic.client = client;
2968 
2969 		ret = hclgevf_init_nic_client_instance(ae_dev, client);
2970 		if (ret)
2971 			goto clear_nic;
2972 
2973 		ret = hclgevf_init_roce_client_instance(ae_dev,
2974 							hdev->roce_client);
2975 		if (ret)
2976 			goto clear_roce;
2977 
2978 		break;
2979 	case HNAE3_CLIENT_ROCE:
2980 		if (hnae3_dev_roce_supported(hdev)) {
2981 			hdev->roce_client = client;
2982 			hdev->roce.client = client;
2983 		}
2984 
2985 		ret = hclgevf_init_roce_client_instance(ae_dev, client);
2986 		if (ret)
2987 			goto clear_roce;
2988 
2989 		break;
2990 	default:
2991 		return -EINVAL;
2992 	}
2993 
2994 	return 0;
2995 
2996 clear_nic:
2997 	hdev->nic_client = NULL;
2998 	hdev->nic.client = NULL;
2999 	return ret;
3000 clear_roce:
3001 	hdev->roce_client = NULL;
3002 	hdev->roce.client = NULL;
3003 	return ret;
3004 }
3005 
3006 static void hclgevf_uninit_client_instance(struct hnae3_client *client,
3007 					   struct hnae3_ae_dev *ae_dev)
3008 {
3009 	struct hclgevf_dev *hdev = ae_dev->priv;
3010 
3011 	/* un-init roce, if it exists */
3012 	if (hdev->roce_client) {
3013 		while (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state))
3014 			msleep(HCLGEVF_WAIT_RESET_DONE);
3015 		clear_bit(HCLGEVF_STATE_ROCE_REGISTERED, &hdev->state);
3016 
3017 		hdev->roce_client->ops->uninit_instance(&hdev->roce, 0);
3018 		hdev->roce_client = NULL;
3019 		hdev->roce.client = NULL;
3020 	}
3021 
3022 	/* un-init nic/unic, if this was not called by roce client */
3023 	if (client->ops->uninit_instance && hdev->nic_client &&
3024 	    client->type != HNAE3_CLIENT_ROCE) {
3025 		while (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state))
3026 			msleep(HCLGEVF_WAIT_RESET_DONE);
3027 		clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state);
3028 
3029 		client->ops->uninit_instance(&hdev->nic, 0);
3030 		hdev->nic_client = NULL;
3031 		hdev->nic.client = NULL;
3032 	}
3033 }
3034 
3035 static int hclgevf_dev_mem_map(struct hclgevf_dev *hdev)
3036 {
3037 #define HCLGEVF_MEM_BAR		4
3038 
3039 	struct pci_dev *pdev = hdev->pdev;
3040 	struct hclgevf_hw *hw = &hdev->hw;
3041 
3042 	/* for device does not have device memory, return directly */
3043 	if (!(pci_select_bars(pdev, IORESOURCE_MEM) & BIT(HCLGEVF_MEM_BAR)))
3044 		return 0;
3045 
3046 	hw->mem_base = devm_ioremap_wc(&pdev->dev,
3047 				       pci_resource_start(pdev,
3048 							  HCLGEVF_MEM_BAR),
3049 				       pci_resource_len(pdev, HCLGEVF_MEM_BAR));
3050 	if (!hw->mem_base) {
3051 		dev_err(&pdev->dev, "failed to map device memory\n");
3052 		return -EFAULT;
3053 	}
3054 
3055 	return 0;
3056 }
3057 
3058 static int hclgevf_pci_init(struct hclgevf_dev *hdev)
3059 {
3060 	struct pci_dev *pdev = hdev->pdev;
3061 	struct hclgevf_hw *hw;
3062 	int ret;
3063 
3064 	ret = pci_enable_device(pdev);
3065 	if (ret) {
3066 		dev_err(&pdev->dev, "failed to enable PCI device\n");
3067 		return ret;
3068 	}
3069 
3070 	ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
3071 	if (ret) {
3072 		dev_err(&pdev->dev, "can't set consistent PCI DMA, exiting");
3073 		goto err_disable_device;
3074 	}
3075 
3076 	ret = pci_request_regions(pdev, HCLGEVF_DRIVER_NAME);
3077 	if (ret) {
3078 		dev_err(&pdev->dev, "PCI request regions failed %d\n", ret);
3079 		goto err_disable_device;
3080 	}
3081 
3082 	pci_set_master(pdev);
3083 	hw = &hdev->hw;
3084 	hw->hdev = hdev;
3085 	hw->io_base = pci_iomap(pdev, 2, 0);
3086 	if (!hw->io_base) {
3087 		dev_err(&pdev->dev, "can't map configuration register space\n");
3088 		ret = -ENOMEM;
3089 		goto err_clr_master;
3090 	}
3091 
3092 	ret = hclgevf_dev_mem_map(hdev);
3093 	if (ret)
3094 		goto err_unmap_io_base;
3095 
3096 	return 0;
3097 
3098 err_unmap_io_base:
3099 	pci_iounmap(pdev, hdev->hw.io_base);
3100 err_clr_master:
3101 	pci_clear_master(pdev);
3102 	pci_release_regions(pdev);
3103 err_disable_device:
3104 	pci_disable_device(pdev);
3105 
3106 	return ret;
3107 }
3108 
3109 static void hclgevf_pci_uninit(struct hclgevf_dev *hdev)
3110 {
3111 	struct pci_dev *pdev = hdev->pdev;
3112 
3113 	if (hdev->hw.mem_base)
3114 		devm_iounmap(&pdev->dev, hdev->hw.mem_base);
3115 
3116 	pci_iounmap(pdev, hdev->hw.io_base);
3117 	pci_clear_master(pdev);
3118 	pci_release_regions(pdev);
3119 	pci_disable_device(pdev);
3120 }
3121 
3122 static int hclgevf_query_vf_resource(struct hclgevf_dev *hdev)
3123 {
3124 	struct hclgevf_query_res_cmd *req;
3125 	struct hclgevf_desc desc;
3126 	int ret;
3127 
3128 	hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_VF_RSRC, true);
3129 	ret = hclgevf_cmd_send(&hdev->hw, &desc, 1);
3130 	if (ret) {
3131 		dev_err(&hdev->pdev->dev,
3132 			"query vf resource failed, ret = %d.\n", ret);
3133 		return ret;
3134 	}
3135 
3136 	req = (struct hclgevf_query_res_cmd *)desc.data;
3137 
3138 	if (hnae3_dev_roce_supported(hdev)) {
3139 		hdev->roce_base_msix_offset =
3140 		hnae3_get_field(le16_to_cpu(req->msixcap_localid_ba_rocee),
3141 				HCLGEVF_MSIX_OFT_ROCEE_M,
3142 				HCLGEVF_MSIX_OFT_ROCEE_S);
3143 		hdev->num_roce_msix =
3144 		hnae3_get_field(le16_to_cpu(req->vf_intr_vector_number),
3145 				HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S);
3146 
3147 		/* nic's msix numbers is always equals to the roce's. */
3148 		hdev->num_nic_msix = hdev->num_roce_msix;
3149 
3150 		/* VF should have NIC vectors and Roce vectors, NIC vectors
3151 		 * are queued before Roce vectors. The offset is fixed to 64.
3152 		 */
3153 		hdev->num_msi = hdev->num_roce_msix +
3154 				hdev->roce_base_msix_offset;
3155 	} else {
3156 		hdev->num_msi =
3157 		hnae3_get_field(le16_to_cpu(req->vf_intr_vector_number),
3158 				HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S);
3159 
3160 		hdev->num_nic_msix = hdev->num_msi;
3161 	}
3162 
3163 	if (hdev->num_nic_msix < HNAE3_MIN_VECTOR_NUM) {
3164 		dev_err(&hdev->pdev->dev,
3165 			"Just %u msi resources, not enough for vf(min:2).\n",
3166 			hdev->num_nic_msix);
3167 		return -EINVAL;
3168 	}
3169 
3170 	return 0;
3171 }
3172 
3173 static void hclgevf_set_default_dev_specs(struct hclgevf_dev *hdev)
3174 {
3175 #define HCLGEVF_MAX_NON_TSO_BD_NUM			8U
3176 
3177 	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
3178 
3179 	ae_dev->dev_specs.max_non_tso_bd_num =
3180 					HCLGEVF_MAX_NON_TSO_BD_NUM;
3181 	ae_dev->dev_specs.rss_ind_tbl_size = HCLGEVF_RSS_IND_TBL_SIZE;
3182 	ae_dev->dev_specs.rss_key_size = HCLGEVF_RSS_KEY_SIZE;
3183 	ae_dev->dev_specs.max_int_gl = HCLGEVF_DEF_MAX_INT_GL;
3184 	ae_dev->dev_specs.max_frm_size = HCLGEVF_MAC_MAX_FRAME;
3185 }
3186 
3187 static void hclgevf_parse_dev_specs(struct hclgevf_dev *hdev,
3188 				    struct hclgevf_desc *desc)
3189 {
3190 	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
3191 	struct hclgevf_dev_specs_0_cmd *req0;
3192 	struct hclgevf_dev_specs_1_cmd *req1;
3193 
3194 	req0 = (struct hclgevf_dev_specs_0_cmd *)desc[0].data;
3195 	req1 = (struct hclgevf_dev_specs_1_cmd *)desc[1].data;
3196 
3197 	ae_dev->dev_specs.max_non_tso_bd_num = req0->max_non_tso_bd_num;
3198 	ae_dev->dev_specs.rss_ind_tbl_size =
3199 					le16_to_cpu(req0->rss_ind_tbl_size);
3200 	ae_dev->dev_specs.int_ql_max = le16_to_cpu(req0->int_ql_max);
3201 	ae_dev->dev_specs.rss_key_size = le16_to_cpu(req0->rss_key_size);
3202 	ae_dev->dev_specs.max_int_gl = le16_to_cpu(req1->max_int_gl);
3203 	ae_dev->dev_specs.max_frm_size = le16_to_cpu(req1->max_frm_size);
3204 }
3205 
3206 static void hclgevf_check_dev_specs(struct hclgevf_dev *hdev)
3207 {
3208 	struct hnae3_dev_specs *dev_specs = &hdev->ae_dev->dev_specs;
3209 
3210 	if (!dev_specs->max_non_tso_bd_num)
3211 		dev_specs->max_non_tso_bd_num = HCLGEVF_MAX_NON_TSO_BD_NUM;
3212 	if (!dev_specs->rss_ind_tbl_size)
3213 		dev_specs->rss_ind_tbl_size = HCLGEVF_RSS_IND_TBL_SIZE;
3214 	if (!dev_specs->rss_key_size)
3215 		dev_specs->rss_key_size = HCLGEVF_RSS_KEY_SIZE;
3216 	if (!dev_specs->max_int_gl)
3217 		dev_specs->max_int_gl = HCLGEVF_DEF_MAX_INT_GL;
3218 	if (!dev_specs->max_frm_size)
3219 		dev_specs->max_frm_size = HCLGEVF_MAC_MAX_FRAME;
3220 }
3221 
3222 static int hclgevf_query_dev_specs(struct hclgevf_dev *hdev)
3223 {
3224 	struct hclgevf_desc desc[HCLGEVF_QUERY_DEV_SPECS_BD_NUM];
3225 	int ret;
3226 	int i;
3227 
3228 	/* set default specifications as devices lower than version V3 do not
3229 	 * support querying specifications from firmware.
3230 	 */
3231 	if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3) {
3232 		hclgevf_set_default_dev_specs(hdev);
3233 		return 0;
3234 	}
3235 
3236 	for (i = 0; i < HCLGEVF_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
3237 		hclgevf_cmd_setup_basic_desc(&desc[i],
3238 					     HCLGEVF_OPC_QUERY_DEV_SPECS, true);
3239 		desc[i].flag |= cpu_to_le16(HCLGEVF_CMD_FLAG_NEXT);
3240 	}
3241 	hclgevf_cmd_setup_basic_desc(&desc[i], HCLGEVF_OPC_QUERY_DEV_SPECS,
3242 				     true);
3243 
3244 	ret = hclgevf_cmd_send(&hdev->hw, desc, HCLGEVF_QUERY_DEV_SPECS_BD_NUM);
3245 	if (ret)
3246 		return ret;
3247 
3248 	hclgevf_parse_dev_specs(hdev, desc);
3249 	hclgevf_check_dev_specs(hdev);
3250 
3251 	return 0;
3252 }
3253 
3254 static int hclgevf_pci_reset(struct hclgevf_dev *hdev)
3255 {
3256 	struct pci_dev *pdev = hdev->pdev;
3257 	int ret = 0;
3258 
3259 	if (hdev->reset_type == HNAE3_VF_FULL_RESET &&
3260 	    test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) {
3261 		hclgevf_misc_irq_uninit(hdev);
3262 		hclgevf_uninit_msi(hdev);
3263 		clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state);
3264 	}
3265 
3266 	if (!test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) {
3267 		pci_set_master(pdev);
3268 		ret = hclgevf_init_msi(hdev);
3269 		if (ret) {
3270 			dev_err(&pdev->dev,
3271 				"failed(%d) to init MSI/MSI-X\n", ret);
3272 			return ret;
3273 		}
3274 
3275 		ret = hclgevf_misc_irq_init(hdev);
3276 		if (ret) {
3277 			hclgevf_uninit_msi(hdev);
3278 			dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n",
3279 				ret);
3280 			return ret;
3281 		}
3282 
3283 		set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state);
3284 	}
3285 
3286 	return ret;
3287 }
3288 
3289 static int hclgevf_clear_vport_list(struct hclgevf_dev *hdev)
3290 {
3291 	struct hclge_vf_to_pf_msg send_msg;
3292 
3293 	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_HANDLE_VF_TBL,
3294 			       HCLGE_MBX_VPORT_LIST_CLEAR);
3295 	return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
3296 }
3297 
3298 static void hclgevf_init_rxd_adv_layout(struct hclgevf_dev *hdev)
3299 {
3300 	if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev))
3301 		hclgevf_write_dev(&hdev->hw, HCLGEVF_RXD_ADV_LAYOUT_EN_REG, 1);
3302 }
3303 
3304 static void hclgevf_uninit_rxd_adv_layout(struct hclgevf_dev *hdev)
3305 {
3306 	if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev))
3307 		hclgevf_write_dev(&hdev->hw, HCLGEVF_RXD_ADV_LAYOUT_EN_REG, 0);
3308 }
3309 
3310 static int hclgevf_reset_hdev(struct hclgevf_dev *hdev)
3311 {
3312 	struct pci_dev *pdev = hdev->pdev;
3313 	int ret;
3314 
3315 	ret = hclgevf_pci_reset(hdev);
3316 	if (ret) {
3317 		dev_err(&pdev->dev, "pci reset failed %d\n", ret);
3318 		return ret;
3319 	}
3320 
3321 	ret = hclgevf_cmd_init(hdev);
3322 	if (ret) {
3323 		dev_err(&pdev->dev, "cmd failed %d\n", ret);
3324 		return ret;
3325 	}
3326 
3327 	ret = hclgevf_rss_init_hw(hdev);
3328 	if (ret) {
3329 		dev_err(&hdev->pdev->dev,
3330 			"failed(%d) to initialize RSS\n", ret);
3331 		return ret;
3332 	}
3333 
3334 	ret = hclgevf_config_gro(hdev);
3335 	if (ret)
3336 		return ret;
3337 
3338 	ret = hclgevf_init_vlan_config(hdev);
3339 	if (ret) {
3340 		dev_err(&hdev->pdev->dev,
3341 			"failed(%d) to initialize VLAN config\n", ret);
3342 		return ret;
3343 	}
3344 
3345 	set_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state);
3346 
3347 	hclgevf_init_rxd_adv_layout(hdev);
3348 
3349 	dev_info(&hdev->pdev->dev, "Reset done\n");
3350 
3351 	return 0;
3352 }
3353 
3354 static int hclgevf_init_hdev(struct hclgevf_dev *hdev)
3355 {
3356 	struct pci_dev *pdev = hdev->pdev;
3357 	int ret;
3358 
3359 	ret = hclgevf_pci_init(hdev);
3360 	if (ret)
3361 		return ret;
3362 
3363 	ret = hclgevf_devlink_init(hdev);
3364 	if (ret)
3365 		goto err_devlink_init;
3366 
3367 	ret = hclgevf_cmd_queue_init(hdev);
3368 	if (ret)
3369 		goto err_cmd_queue_init;
3370 
3371 	ret = hclgevf_cmd_init(hdev);
3372 	if (ret)
3373 		goto err_cmd_init;
3374 
3375 	/* Get vf resource */
3376 	ret = hclgevf_query_vf_resource(hdev);
3377 	if (ret)
3378 		goto err_cmd_init;
3379 
3380 	ret = hclgevf_query_dev_specs(hdev);
3381 	if (ret) {
3382 		dev_err(&pdev->dev,
3383 			"failed to query dev specifications, ret = %d\n", ret);
3384 		goto err_cmd_init;
3385 	}
3386 
3387 	ret = hclgevf_init_msi(hdev);
3388 	if (ret) {
3389 		dev_err(&pdev->dev, "failed(%d) to init MSI/MSI-X\n", ret);
3390 		goto err_cmd_init;
3391 	}
3392 
3393 	hclgevf_state_init(hdev);
3394 	hdev->reset_level = HNAE3_VF_FUNC_RESET;
3395 	hdev->reset_type = HNAE3_NONE_RESET;
3396 
3397 	ret = hclgevf_misc_irq_init(hdev);
3398 	if (ret)
3399 		goto err_misc_irq_init;
3400 
3401 	set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state);
3402 
3403 	ret = hclgevf_configure(hdev);
3404 	if (ret) {
3405 		dev_err(&pdev->dev, "failed(%d) to fetch configuration\n", ret);
3406 		goto err_config;
3407 	}
3408 
3409 	ret = hclgevf_alloc_tqps(hdev);
3410 	if (ret) {
3411 		dev_err(&pdev->dev, "failed(%d) to allocate TQPs\n", ret);
3412 		goto err_config;
3413 	}
3414 
3415 	ret = hclgevf_set_handle_info(hdev);
3416 	if (ret)
3417 		goto err_config;
3418 
3419 	ret = hclgevf_config_gro(hdev);
3420 	if (ret)
3421 		goto err_config;
3422 
3423 	/* Initialize RSS for this VF */
3424 	ret = hclgevf_rss_init_cfg(hdev);
3425 	if (ret) {
3426 		dev_err(&pdev->dev, "failed to init rss cfg, ret = %d\n", ret);
3427 		goto err_config;
3428 	}
3429 
3430 	ret = hclgevf_rss_init_hw(hdev);
3431 	if (ret) {
3432 		dev_err(&hdev->pdev->dev,
3433 			"failed(%d) to initialize RSS\n", ret);
3434 		goto err_config;
3435 	}
3436 
3437 	/* ensure vf tbl list as empty before init*/
3438 	ret = hclgevf_clear_vport_list(hdev);
3439 	if (ret) {
3440 		dev_err(&pdev->dev,
3441 			"failed to clear tbl list configuration, ret = %d.\n",
3442 			ret);
3443 		goto err_config;
3444 	}
3445 
3446 	ret = hclgevf_init_vlan_config(hdev);
3447 	if (ret) {
3448 		dev_err(&hdev->pdev->dev,
3449 			"failed(%d) to initialize VLAN config\n", ret);
3450 		goto err_config;
3451 	}
3452 
3453 	hclgevf_init_rxd_adv_layout(hdev);
3454 
3455 	set_bit(HCLGEVF_STATE_SERVICE_INITED, &hdev->state);
3456 
3457 	hdev->last_reset_time = jiffies;
3458 	dev_info(&hdev->pdev->dev, "finished initializing %s driver\n",
3459 		 HCLGEVF_DRIVER_NAME);
3460 
3461 	hclgevf_task_schedule(hdev, round_jiffies_relative(HZ));
3462 
3463 	return 0;
3464 
3465 err_config:
3466 	hclgevf_misc_irq_uninit(hdev);
3467 err_misc_irq_init:
3468 	hclgevf_state_uninit(hdev);
3469 	hclgevf_uninit_msi(hdev);
3470 err_cmd_init:
3471 	hclgevf_cmd_uninit(hdev);
3472 err_cmd_queue_init:
3473 	hclgevf_devlink_uninit(hdev);
3474 err_devlink_init:
3475 	hclgevf_pci_uninit(hdev);
3476 	clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state);
3477 	return ret;
3478 }
3479 
3480 static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev)
3481 {
3482 	struct hclge_vf_to_pf_msg send_msg;
3483 
3484 	hclgevf_state_uninit(hdev);
3485 	hclgevf_uninit_rxd_adv_layout(hdev);
3486 
3487 	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_VF_UNINIT, 0);
3488 	hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
3489 
3490 	if (test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) {
3491 		hclgevf_misc_irq_uninit(hdev);
3492 		hclgevf_uninit_msi(hdev);
3493 	}
3494 
3495 	hclgevf_cmd_uninit(hdev);
3496 	hclgevf_devlink_uninit(hdev);
3497 	hclgevf_pci_uninit(hdev);
3498 	hclgevf_uninit_mac_list(hdev);
3499 }
3500 
3501 static int hclgevf_init_ae_dev(struct hnae3_ae_dev *ae_dev)
3502 {
3503 	struct pci_dev *pdev = ae_dev->pdev;
3504 	int ret;
3505 
3506 	ret = hclgevf_alloc_hdev(ae_dev);
3507 	if (ret) {
3508 		dev_err(&pdev->dev, "hclge device allocation failed\n");
3509 		return ret;
3510 	}
3511 
3512 	ret = hclgevf_init_hdev(ae_dev->priv);
3513 	if (ret) {
3514 		dev_err(&pdev->dev, "hclge device initialization failed\n");
3515 		return ret;
3516 	}
3517 
3518 	return 0;
3519 }
3520 
3521 static void hclgevf_uninit_ae_dev(struct hnae3_ae_dev *ae_dev)
3522 {
3523 	struct hclgevf_dev *hdev = ae_dev->priv;
3524 
3525 	hclgevf_uninit_hdev(hdev);
3526 	ae_dev->priv = NULL;
3527 }
3528 
3529 static u32 hclgevf_get_max_channels(struct hclgevf_dev *hdev)
3530 {
3531 	struct hnae3_handle *nic = &hdev->nic;
3532 	struct hnae3_knic_private_info *kinfo = &nic->kinfo;
3533 
3534 	return min_t(u32, hdev->rss_size_max,
3535 		     hdev->num_tqps / kinfo->tc_info.num_tc);
3536 }
3537 
3538 /**
3539  * hclgevf_get_channels - Get the current channels enabled and max supported.
3540  * @handle: hardware information for network interface
3541  * @ch: ethtool channels structure
3542  *
3543  * We don't support separate tx and rx queues as channels. The other count
3544  * represents how many queues are being used for control. max_combined counts
3545  * how many queue pairs we can support. They may not be mapped 1 to 1 with
3546  * q_vectors since we support a lot more queue pairs than q_vectors.
3547  **/
3548 static void hclgevf_get_channels(struct hnae3_handle *handle,
3549 				 struct ethtool_channels *ch)
3550 {
3551 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3552 
3553 	ch->max_combined = hclgevf_get_max_channels(hdev);
3554 	ch->other_count = 0;
3555 	ch->max_other = 0;
3556 	ch->combined_count = handle->kinfo.rss_size;
3557 }
3558 
3559 static void hclgevf_get_tqps_and_rss_info(struct hnae3_handle *handle,
3560 					  u16 *alloc_tqps, u16 *max_rss_size)
3561 {
3562 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3563 
3564 	*alloc_tqps = hdev->num_tqps;
3565 	*max_rss_size = hdev->rss_size_max;
3566 }
3567 
3568 static void hclgevf_update_rss_size(struct hnae3_handle *handle,
3569 				    u32 new_tqps_num)
3570 {
3571 	struct hnae3_knic_private_info *kinfo = &handle->kinfo;
3572 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3573 	u16 max_rss_size;
3574 
3575 	kinfo->req_rss_size = new_tqps_num;
3576 
3577 	max_rss_size = min_t(u16, hdev->rss_size_max,
3578 			     hdev->num_tqps / kinfo->tc_info.num_tc);
3579 
3580 	/* Use the user's configuration when it is not larger than
3581 	 * max_rss_size, otherwise, use the maximum specification value.
3582 	 */
3583 	if (kinfo->req_rss_size != kinfo->rss_size && kinfo->req_rss_size &&
3584 	    kinfo->req_rss_size <= max_rss_size)
3585 		kinfo->rss_size = kinfo->req_rss_size;
3586 	else if (kinfo->rss_size > max_rss_size ||
3587 		 (!kinfo->req_rss_size && kinfo->rss_size < max_rss_size))
3588 		kinfo->rss_size = max_rss_size;
3589 
3590 	kinfo->num_tqps = kinfo->tc_info.num_tc * kinfo->rss_size;
3591 }
3592 
3593 static int hclgevf_set_channels(struct hnae3_handle *handle, u32 new_tqps_num,
3594 				bool rxfh_configured)
3595 {
3596 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3597 	struct hnae3_knic_private_info *kinfo = &handle->kinfo;
3598 	u16 cur_rss_size = kinfo->rss_size;
3599 	u16 cur_tqps = kinfo->num_tqps;
3600 	u32 *rss_indir;
3601 	unsigned int i;
3602 	int ret;
3603 
3604 	hclgevf_update_rss_size(handle, new_tqps_num);
3605 
3606 	ret = hclgevf_set_rss_tc_mode(hdev, kinfo->rss_size);
3607 	if (ret)
3608 		return ret;
3609 
3610 	/* RSS indirection table has been configured by user */
3611 	if (rxfh_configured)
3612 		goto out;
3613 
3614 	/* Reinitializes the rss indirect table according to the new RSS size */
3615 	rss_indir = kcalloc(hdev->ae_dev->dev_specs.rss_ind_tbl_size,
3616 			    sizeof(u32), GFP_KERNEL);
3617 	if (!rss_indir)
3618 		return -ENOMEM;
3619 
3620 	for (i = 0; i < hdev->ae_dev->dev_specs.rss_ind_tbl_size; i++)
3621 		rss_indir[i] = i % kinfo->rss_size;
3622 
3623 	hdev->rss_cfg.rss_size = kinfo->rss_size;
3624 
3625 	ret = hclgevf_set_rss(handle, rss_indir, NULL, 0);
3626 	if (ret)
3627 		dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n",
3628 			ret);
3629 
3630 	kfree(rss_indir);
3631 
3632 out:
3633 	if (!ret)
3634 		dev_info(&hdev->pdev->dev,
3635 			 "Channels changed, rss_size from %u to %u, tqps from %u to %u",
3636 			 cur_rss_size, kinfo->rss_size,
3637 			 cur_tqps, kinfo->rss_size * kinfo->tc_info.num_tc);
3638 
3639 	return ret;
3640 }
3641 
3642 static int hclgevf_get_status(struct hnae3_handle *handle)
3643 {
3644 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3645 
3646 	return hdev->hw.mac.link;
3647 }
3648 
3649 static void hclgevf_get_ksettings_an_result(struct hnae3_handle *handle,
3650 					    u8 *auto_neg, u32 *speed,
3651 					    u8 *duplex)
3652 {
3653 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3654 
3655 	if (speed)
3656 		*speed = hdev->hw.mac.speed;
3657 	if (duplex)
3658 		*duplex = hdev->hw.mac.duplex;
3659 	if (auto_neg)
3660 		*auto_neg = AUTONEG_DISABLE;
3661 }
3662 
3663 void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed,
3664 				 u8 duplex)
3665 {
3666 	hdev->hw.mac.speed = speed;
3667 	hdev->hw.mac.duplex = duplex;
3668 }
3669 
3670 static int hclgevf_gro_en(struct hnae3_handle *handle, bool enable)
3671 {
3672 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3673 	bool gro_en_old = hdev->gro_en;
3674 	int ret;
3675 
3676 	hdev->gro_en = enable;
3677 	ret = hclgevf_config_gro(hdev);
3678 	if (ret)
3679 		hdev->gro_en = gro_en_old;
3680 
3681 	return ret;
3682 }
3683 
3684 static void hclgevf_get_media_type(struct hnae3_handle *handle, u8 *media_type,
3685 				   u8 *module_type)
3686 {
3687 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3688 
3689 	if (media_type)
3690 		*media_type = hdev->hw.mac.media_type;
3691 
3692 	if (module_type)
3693 		*module_type = hdev->hw.mac.module_type;
3694 }
3695 
3696 static bool hclgevf_get_hw_reset_stat(struct hnae3_handle *handle)
3697 {
3698 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3699 
3700 	return !!hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING);
3701 }
3702 
3703 static bool hclgevf_get_cmdq_stat(struct hnae3_handle *handle)
3704 {
3705 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3706 
3707 	return test_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state);
3708 }
3709 
3710 static bool hclgevf_ae_dev_resetting(struct hnae3_handle *handle)
3711 {
3712 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3713 
3714 	return test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state);
3715 }
3716 
3717 static unsigned long hclgevf_ae_dev_reset_cnt(struct hnae3_handle *handle)
3718 {
3719 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3720 
3721 	return hdev->rst_stats.hw_rst_done_cnt;
3722 }
3723 
3724 static void hclgevf_get_link_mode(struct hnae3_handle *handle,
3725 				  unsigned long *supported,
3726 				  unsigned long *advertising)
3727 {
3728 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3729 
3730 	*supported = hdev->hw.mac.supported;
3731 	*advertising = hdev->hw.mac.advertising;
3732 }
3733 
3734 #define MAX_SEPARATE_NUM	4
3735 #define SEPARATOR_VALUE		0xFDFCFBFA
3736 #define REG_NUM_PER_LINE	4
3737 #define REG_LEN_PER_LINE	(REG_NUM_PER_LINE * sizeof(u32))
3738 
3739 static int hclgevf_get_regs_len(struct hnae3_handle *handle)
3740 {
3741 	int cmdq_lines, common_lines, ring_lines, tqp_intr_lines;
3742 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3743 
3744 	cmdq_lines = sizeof(cmdq_reg_addr_list) / REG_LEN_PER_LINE + 1;
3745 	common_lines = sizeof(common_reg_addr_list) / REG_LEN_PER_LINE + 1;
3746 	ring_lines = sizeof(ring_reg_addr_list) / REG_LEN_PER_LINE + 1;
3747 	tqp_intr_lines = sizeof(tqp_intr_reg_addr_list) / REG_LEN_PER_LINE + 1;
3748 
3749 	return (cmdq_lines + common_lines + ring_lines * hdev->num_tqps +
3750 		tqp_intr_lines * (hdev->num_msi_used - 1)) * REG_LEN_PER_LINE;
3751 }
3752 
3753 static void hclgevf_get_regs(struct hnae3_handle *handle, u32 *version,
3754 			     void *data)
3755 {
3756 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3757 	int i, j, reg_um, separator_num;
3758 	u32 *reg = data;
3759 
3760 	*version = hdev->fw_version;
3761 
3762 	/* fetching per-VF registers values from VF PCIe register space */
3763 	reg_um = sizeof(cmdq_reg_addr_list) / sizeof(u32);
3764 	separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
3765 	for (i = 0; i < reg_um; i++)
3766 		*reg++ = hclgevf_read_dev(&hdev->hw, cmdq_reg_addr_list[i]);
3767 	for (i = 0; i < separator_num; i++)
3768 		*reg++ = SEPARATOR_VALUE;
3769 
3770 	reg_um = sizeof(common_reg_addr_list) / sizeof(u32);
3771 	separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
3772 	for (i = 0; i < reg_um; i++)
3773 		*reg++ = hclgevf_read_dev(&hdev->hw, common_reg_addr_list[i]);
3774 	for (i = 0; i < separator_num; i++)
3775 		*reg++ = SEPARATOR_VALUE;
3776 
3777 	reg_um = sizeof(ring_reg_addr_list) / sizeof(u32);
3778 	separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
3779 	for (j = 0; j < hdev->num_tqps; j++) {
3780 		for (i = 0; i < reg_um; i++)
3781 			*reg++ = hclgevf_read_dev(&hdev->hw,
3782 						  ring_reg_addr_list[i] +
3783 						  0x200 * j);
3784 		for (i = 0; i < separator_num; i++)
3785 			*reg++ = SEPARATOR_VALUE;
3786 	}
3787 
3788 	reg_um = sizeof(tqp_intr_reg_addr_list) / sizeof(u32);
3789 	separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
3790 	for (j = 0; j < hdev->num_msi_used - 1; j++) {
3791 		for (i = 0; i < reg_um; i++)
3792 			*reg++ = hclgevf_read_dev(&hdev->hw,
3793 						  tqp_intr_reg_addr_list[i] +
3794 						  4 * j);
3795 		for (i = 0; i < separator_num; i++)
3796 			*reg++ = SEPARATOR_VALUE;
3797 	}
3798 }
3799 
3800 void hclgevf_update_port_base_vlan_info(struct hclgevf_dev *hdev, u16 state,
3801 					u8 *port_base_vlan_info, u8 data_size)
3802 {
3803 	struct hnae3_handle *nic = &hdev->nic;
3804 	struct hclge_vf_to_pf_msg send_msg;
3805 	int ret;
3806 
3807 	rtnl_lock();
3808 
3809 	if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) ||
3810 	    test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) {
3811 		dev_warn(&hdev->pdev->dev,
3812 			 "is resetting when updating port based vlan info\n");
3813 		rtnl_unlock();
3814 		return;
3815 	}
3816 
3817 	ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT);
3818 	if (ret) {
3819 		rtnl_unlock();
3820 		return;
3821 	}
3822 
3823 	/* send msg to PF and wait update port based vlan info */
3824 	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN,
3825 			       HCLGE_MBX_PORT_BASE_VLAN_CFG);
3826 	memcpy(send_msg.data, port_base_vlan_info, data_size);
3827 	ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
3828 	if (!ret) {
3829 		if (state == HNAE3_PORT_BASE_VLAN_DISABLE)
3830 			nic->port_base_vlan_state = state;
3831 		else
3832 			nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_ENABLE;
3833 	}
3834 
3835 	hclgevf_notify_client(hdev, HNAE3_UP_CLIENT);
3836 	rtnl_unlock();
3837 }
3838 
3839 static const struct hnae3_ae_ops hclgevf_ops = {
3840 	.init_ae_dev = hclgevf_init_ae_dev,
3841 	.uninit_ae_dev = hclgevf_uninit_ae_dev,
3842 	.reset_prepare = hclgevf_reset_prepare_general,
3843 	.reset_done = hclgevf_reset_done,
3844 	.init_client_instance = hclgevf_init_client_instance,
3845 	.uninit_client_instance = hclgevf_uninit_client_instance,
3846 	.start = hclgevf_ae_start,
3847 	.stop = hclgevf_ae_stop,
3848 	.client_start = hclgevf_client_start,
3849 	.client_stop = hclgevf_client_stop,
3850 	.map_ring_to_vector = hclgevf_map_ring_to_vector,
3851 	.unmap_ring_from_vector = hclgevf_unmap_ring_from_vector,
3852 	.get_vector = hclgevf_get_vector,
3853 	.put_vector = hclgevf_put_vector,
3854 	.reset_queue = hclgevf_reset_tqp,
3855 	.get_mac_addr = hclgevf_get_mac_addr,
3856 	.set_mac_addr = hclgevf_set_mac_addr,
3857 	.add_uc_addr = hclgevf_add_uc_addr,
3858 	.rm_uc_addr = hclgevf_rm_uc_addr,
3859 	.add_mc_addr = hclgevf_add_mc_addr,
3860 	.rm_mc_addr = hclgevf_rm_mc_addr,
3861 	.get_stats = hclgevf_get_stats,
3862 	.update_stats = hclgevf_update_stats,
3863 	.get_strings = hclgevf_get_strings,
3864 	.get_sset_count = hclgevf_get_sset_count,
3865 	.get_rss_key_size = hclgevf_get_rss_key_size,
3866 	.get_rss = hclgevf_get_rss,
3867 	.set_rss = hclgevf_set_rss,
3868 	.get_rss_tuple = hclgevf_get_rss_tuple,
3869 	.set_rss_tuple = hclgevf_set_rss_tuple,
3870 	.get_tc_size = hclgevf_get_tc_size,
3871 	.get_fw_version = hclgevf_get_fw_version,
3872 	.set_vlan_filter = hclgevf_set_vlan_filter,
3873 	.enable_vlan_filter = hclgevf_enable_vlan_filter,
3874 	.enable_hw_strip_rxvtag = hclgevf_en_hw_strip_rxvtag,
3875 	.reset_event = hclgevf_reset_event,
3876 	.set_default_reset_request = hclgevf_set_def_reset_request,
3877 	.set_channels = hclgevf_set_channels,
3878 	.get_channels = hclgevf_get_channels,
3879 	.get_tqps_and_rss_info = hclgevf_get_tqps_and_rss_info,
3880 	.get_regs_len = hclgevf_get_regs_len,
3881 	.get_regs = hclgevf_get_regs,
3882 	.get_status = hclgevf_get_status,
3883 	.get_ksettings_an_result = hclgevf_get_ksettings_an_result,
3884 	.get_media_type = hclgevf_get_media_type,
3885 	.get_hw_reset_stat = hclgevf_get_hw_reset_stat,
3886 	.ae_dev_resetting = hclgevf_ae_dev_resetting,
3887 	.ae_dev_reset_cnt = hclgevf_ae_dev_reset_cnt,
3888 	.set_gro_en = hclgevf_gro_en,
3889 	.set_mtu = hclgevf_set_mtu,
3890 	.get_global_queue_id = hclgevf_get_qid_global,
3891 	.set_timer_task = hclgevf_set_timer_task,
3892 	.get_link_mode = hclgevf_get_link_mode,
3893 	.set_promisc_mode = hclgevf_set_promisc_mode,
3894 	.request_update_promisc_mode = hclgevf_request_update_promisc_mode,
3895 	.get_cmdq_stat = hclgevf_get_cmdq_stat,
3896 };
3897 
3898 static struct hnae3_ae_algo ae_algovf = {
3899 	.ops = &hclgevf_ops,
3900 	.pdev_id_table = ae_algovf_pci_tbl,
3901 };
3902 
3903 static int hclgevf_init(void)
3904 {
3905 	pr_info("%s is initializing\n", HCLGEVF_NAME);
3906 
3907 	hclgevf_wq = alloc_workqueue("%s", WQ_UNBOUND, 0, HCLGEVF_NAME);
3908 	if (!hclgevf_wq) {
3909 		pr_err("%s: failed to create workqueue\n", HCLGEVF_NAME);
3910 		return -ENOMEM;
3911 	}
3912 
3913 	hnae3_register_ae_algo(&ae_algovf);
3914 
3915 	return 0;
3916 }
3917 
3918 static void hclgevf_exit(void)
3919 {
3920 	hnae3_unregister_ae_algo(&ae_algovf);
3921 	destroy_workqueue(hclgevf_wq);
3922 }
3923 module_init(hclgevf_init);
3924 module_exit(hclgevf_exit);
3925 
3926 MODULE_LICENSE("GPL");
3927 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
3928 MODULE_DESCRIPTION("HCLGEVF Driver");
3929 MODULE_VERSION(HCLGEVF_MOD_VERSION);
3930