1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/etherdevice.h> 5 #include <linux/iopoll.h> 6 #include <net/rtnetlink.h> 7 #include "hclgevf_cmd.h" 8 #include "hclgevf_main.h" 9 #include "hclge_mbx.h" 10 #include "hnae3.h" 11 12 #define HCLGEVF_NAME "hclgevf" 13 14 #define HCLGEVF_RESET_MAX_FAIL_CNT 5 15 16 static int hclgevf_reset_hdev(struct hclgevf_dev *hdev); 17 static struct hnae3_ae_algo ae_algovf; 18 19 static struct workqueue_struct *hclgevf_wq; 20 21 static const struct pci_device_id ae_algovf_pci_tbl[] = { 22 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0}, 23 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF), 0}, 24 /* required last entry */ 25 {0, } 26 }; 27 28 static const u8 hclgevf_hash_key[] = { 29 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2, 30 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0, 31 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4, 32 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C, 33 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA 34 }; 35 36 MODULE_DEVICE_TABLE(pci, ae_algovf_pci_tbl); 37 38 static const u32 cmdq_reg_addr_list[] = {HCLGEVF_CMDQ_TX_ADDR_L_REG, 39 HCLGEVF_CMDQ_TX_ADDR_H_REG, 40 HCLGEVF_CMDQ_TX_DEPTH_REG, 41 HCLGEVF_CMDQ_TX_TAIL_REG, 42 HCLGEVF_CMDQ_TX_HEAD_REG, 43 HCLGEVF_CMDQ_RX_ADDR_L_REG, 44 HCLGEVF_CMDQ_RX_ADDR_H_REG, 45 HCLGEVF_CMDQ_RX_DEPTH_REG, 46 HCLGEVF_CMDQ_RX_TAIL_REG, 47 HCLGEVF_CMDQ_RX_HEAD_REG, 48 HCLGEVF_VECTOR0_CMDQ_SRC_REG, 49 HCLGEVF_CMDQ_INTR_STS_REG, 50 HCLGEVF_CMDQ_INTR_EN_REG, 51 HCLGEVF_CMDQ_INTR_GEN_REG}; 52 53 static const u32 common_reg_addr_list[] = {HCLGEVF_MISC_VECTOR_REG_BASE, 54 HCLGEVF_RST_ING, 55 HCLGEVF_GRO_EN_REG}; 56 57 static const u32 ring_reg_addr_list[] = {HCLGEVF_RING_RX_ADDR_L_REG, 58 HCLGEVF_RING_RX_ADDR_H_REG, 59 HCLGEVF_RING_RX_BD_NUM_REG, 60 HCLGEVF_RING_RX_BD_LENGTH_REG, 61 HCLGEVF_RING_RX_MERGE_EN_REG, 62 HCLGEVF_RING_RX_TAIL_REG, 63 HCLGEVF_RING_RX_HEAD_REG, 64 HCLGEVF_RING_RX_FBD_NUM_REG, 65 HCLGEVF_RING_RX_OFFSET_REG, 66 HCLGEVF_RING_RX_FBD_OFFSET_REG, 67 HCLGEVF_RING_RX_STASH_REG, 68 HCLGEVF_RING_RX_BD_ERR_REG, 69 HCLGEVF_RING_TX_ADDR_L_REG, 70 HCLGEVF_RING_TX_ADDR_H_REG, 71 HCLGEVF_RING_TX_BD_NUM_REG, 72 HCLGEVF_RING_TX_PRIORITY_REG, 73 HCLGEVF_RING_TX_TC_REG, 74 HCLGEVF_RING_TX_MERGE_EN_REG, 75 HCLGEVF_RING_TX_TAIL_REG, 76 HCLGEVF_RING_TX_HEAD_REG, 77 HCLGEVF_RING_TX_FBD_NUM_REG, 78 HCLGEVF_RING_TX_OFFSET_REG, 79 HCLGEVF_RING_TX_EBD_NUM_REG, 80 HCLGEVF_RING_TX_EBD_OFFSET_REG, 81 HCLGEVF_RING_TX_BD_ERR_REG, 82 HCLGEVF_RING_EN_REG}; 83 84 static const u32 tqp_intr_reg_addr_list[] = {HCLGEVF_TQP_INTR_CTRL_REG, 85 HCLGEVF_TQP_INTR_GL0_REG, 86 HCLGEVF_TQP_INTR_GL1_REG, 87 HCLGEVF_TQP_INTR_GL2_REG, 88 HCLGEVF_TQP_INTR_RL_REG}; 89 90 static struct hclgevf_dev *hclgevf_ae_get_hdev(struct hnae3_handle *handle) 91 { 92 if (!handle->client) 93 return container_of(handle, struct hclgevf_dev, nic); 94 else if (handle->client->type == HNAE3_CLIENT_ROCE) 95 return container_of(handle, struct hclgevf_dev, roce); 96 else 97 return container_of(handle, struct hclgevf_dev, nic); 98 } 99 100 static int hclgevf_tqps_update_stats(struct hnae3_handle *handle) 101 { 102 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 103 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 104 struct hclgevf_desc desc; 105 struct hclgevf_tqp *tqp; 106 int status; 107 int i; 108 109 for (i = 0; i < kinfo->num_tqps; i++) { 110 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 111 hclgevf_cmd_setup_basic_desc(&desc, 112 HCLGEVF_OPC_QUERY_RX_STATUS, 113 true); 114 115 desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 116 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 117 if (status) { 118 dev_err(&hdev->pdev->dev, 119 "Query tqp stat fail, status = %d,queue = %d\n", 120 status, i); 121 return status; 122 } 123 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd += 124 le32_to_cpu(desc.data[1]); 125 126 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_TX_STATUS, 127 true); 128 129 desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 130 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 131 if (status) { 132 dev_err(&hdev->pdev->dev, 133 "Query tqp stat fail, status = %d,queue = %d\n", 134 status, i); 135 return status; 136 } 137 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd += 138 le32_to_cpu(desc.data[1]); 139 } 140 141 return 0; 142 } 143 144 static u64 *hclgevf_tqps_get_stats(struct hnae3_handle *handle, u64 *data) 145 { 146 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 147 struct hclgevf_tqp *tqp; 148 u64 *buff = data; 149 int i; 150 151 for (i = 0; i < kinfo->num_tqps; i++) { 152 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 153 *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd; 154 } 155 for (i = 0; i < kinfo->num_tqps; i++) { 156 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 157 *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd; 158 } 159 160 return buff; 161 } 162 163 static int hclgevf_tqps_get_sset_count(struct hnae3_handle *handle, int strset) 164 { 165 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 166 167 return kinfo->num_tqps * 2; 168 } 169 170 static u8 *hclgevf_tqps_get_strings(struct hnae3_handle *handle, u8 *data) 171 { 172 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 173 u8 *buff = data; 174 int i = 0; 175 176 for (i = 0; i < kinfo->num_tqps; i++) { 177 struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 178 struct hclgevf_tqp, q); 179 snprintf(buff, ETH_GSTRING_LEN, "txq%d_pktnum_rcd", 180 tqp->index); 181 buff += ETH_GSTRING_LEN; 182 } 183 184 for (i = 0; i < kinfo->num_tqps; i++) { 185 struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 186 struct hclgevf_tqp, q); 187 snprintf(buff, ETH_GSTRING_LEN, "rxq%d_pktnum_rcd", 188 tqp->index); 189 buff += ETH_GSTRING_LEN; 190 } 191 192 return buff; 193 } 194 195 static void hclgevf_update_stats(struct hnae3_handle *handle, 196 struct net_device_stats *net_stats) 197 { 198 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 199 int status; 200 201 status = hclgevf_tqps_update_stats(handle); 202 if (status) 203 dev_err(&hdev->pdev->dev, 204 "VF update of TQPS stats fail, status = %d.\n", 205 status); 206 } 207 208 static int hclgevf_get_sset_count(struct hnae3_handle *handle, int strset) 209 { 210 if (strset == ETH_SS_TEST) 211 return -EOPNOTSUPP; 212 else if (strset == ETH_SS_STATS) 213 return hclgevf_tqps_get_sset_count(handle, strset); 214 215 return 0; 216 } 217 218 static void hclgevf_get_strings(struct hnae3_handle *handle, u32 strset, 219 u8 *data) 220 { 221 u8 *p = (char *)data; 222 223 if (strset == ETH_SS_STATS) 224 p = hclgevf_tqps_get_strings(handle, p); 225 } 226 227 static void hclgevf_get_stats(struct hnae3_handle *handle, u64 *data) 228 { 229 hclgevf_tqps_get_stats(handle, data); 230 } 231 232 static int hclgevf_get_tc_info(struct hclgevf_dev *hdev) 233 { 234 u8 resp_msg; 235 int status; 236 237 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_TCINFO, 0, NULL, 0, 238 true, &resp_msg, sizeof(resp_msg)); 239 if (status) { 240 dev_err(&hdev->pdev->dev, 241 "VF request to get TC info from PF failed %d", 242 status); 243 return status; 244 } 245 246 hdev->hw_tc_map = resp_msg; 247 248 return 0; 249 } 250 251 static int hclgevf_get_port_base_vlan_filter_state(struct hclgevf_dev *hdev) 252 { 253 struct hnae3_handle *nic = &hdev->nic; 254 u8 resp_msg; 255 int ret; 256 257 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 258 HCLGE_MBX_GET_PORT_BASE_VLAN_STATE, 259 NULL, 0, true, &resp_msg, sizeof(u8)); 260 if (ret) { 261 dev_err(&hdev->pdev->dev, 262 "VF request to get port based vlan state failed %d", 263 ret); 264 return ret; 265 } 266 267 nic->port_base_vlan_state = resp_msg; 268 269 return 0; 270 } 271 272 static int hclgevf_get_queue_info(struct hclgevf_dev *hdev) 273 { 274 #define HCLGEVF_TQPS_RSS_INFO_LEN 6 275 u8 resp_msg[HCLGEVF_TQPS_RSS_INFO_LEN]; 276 int status; 277 278 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QINFO, 0, NULL, 0, 279 true, resp_msg, 280 HCLGEVF_TQPS_RSS_INFO_LEN); 281 if (status) { 282 dev_err(&hdev->pdev->dev, 283 "VF request to get tqp info from PF failed %d", 284 status); 285 return status; 286 } 287 288 memcpy(&hdev->num_tqps, &resp_msg[0], sizeof(u16)); 289 memcpy(&hdev->rss_size_max, &resp_msg[2], sizeof(u16)); 290 memcpy(&hdev->rx_buf_len, &resp_msg[4], sizeof(u16)); 291 292 return 0; 293 } 294 295 static int hclgevf_get_queue_depth(struct hclgevf_dev *hdev) 296 { 297 #define HCLGEVF_TQPS_DEPTH_INFO_LEN 4 298 u8 resp_msg[HCLGEVF_TQPS_DEPTH_INFO_LEN]; 299 int ret; 300 301 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QDEPTH, 0, NULL, 0, 302 true, resp_msg, 303 HCLGEVF_TQPS_DEPTH_INFO_LEN); 304 if (ret) { 305 dev_err(&hdev->pdev->dev, 306 "VF request to get tqp depth info from PF failed %d", 307 ret); 308 return ret; 309 } 310 311 memcpy(&hdev->num_tx_desc, &resp_msg[0], sizeof(u16)); 312 memcpy(&hdev->num_rx_desc, &resp_msg[2], sizeof(u16)); 313 314 return 0; 315 } 316 317 static u16 hclgevf_get_qid_global(struct hnae3_handle *handle, u16 queue_id) 318 { 319 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 320 u8 msg_data[2], resp_data[2]; 321 u16 qid_in_pf = 0; 322 int ret; 323 324 memcpy(&msg_data[0], &queue_id, sizeof(queue_id)); 325 326 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QID_IN_PF, 0, msg_data, 327 sizeof(msg_data), true, resp_data, 328 sizeof(resp_data)); 329 if (!ret) 330 qid_in_pf = *(u16 *)resp_data; 331 332 return qid_in_pf; 333 } 334 335 static int hclgevf_get_pf_media_type(struct hclgevf_dev *hdev) 336 { 337 u8 resp_msg[2]; 338 int ret; 339 340 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_MEDIA_TYPE, 0, NULL, 0, 341 true, resp_msg, sizeof(resp_msg)); 342 if (ret) { 343 dev_err(&hdev->pdev->dev, 344 "VF request to get the pf port media type failed %d", 345 ret); 346 return ret; 347 } 348 349 hdev->hw.mac.media_type = resp_msg[0]; 350 hdev->hw.mac.module_type = resp_msg[1]; 351 352 return 0; 353 } 354 355 static int hclgevf_alloc_tqps(struct hclgevf_dev *hdev) 356 { 357 struct hclgevf_tqp *tqp; 358 int i; 359 360 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 361 sizeof(struct hclgevf_tqp), GFP_KERNEL); 362 if (!hdev->htqp) 363 return -ENOMEM; 364 365 tqp = hdev->htqp; 366 367 for (i = 0; i < hdev->num_tqps; i++) { 368 tqp->dev = &hdev->pdev->dev; 369 tqp->index = i; 370 371 tqp->q.ae_algo = &ae_algovf; 372 tqp->q.buf_size = hdev->rx_buf_len; 373 tqp->q.tx_desc_num = hdev->num_tx_desc; 374 tqp->q.rx_desc_num = hdev->num_rx_desc; 375 tqp->q.io_base = hdev->hw.io_base + HCLGEVF_TQP_REG_OFFSET + 376 i * HCLGEVF_TQP_REG_SIZE; 377 378 tqp++; 379 } 380 381 return 0; 382 } 383 384 static int hclgevf_knic_setup(struct hclgevf_dev *hdev) 385 { 386 struct hnae3_handle *nic = &hdev->nic; 387 struct hnae3_knic_private_info *kinfo; 388 u16 new_tqps = hdev->num_tqps; 389 unsigned int i; 390 391 kinfo = &nic->kinfo; 392 kinfo->num_tc = 0; 393 kinfo->num_tx_desc = hdev->num_tx_desc; 394 kinfo->num_rx_desc = hdev->num_rx_desc; 395 kinfo->rx_buf_len = hdev->rx_buf_len; 396 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) 397 if (hdev->hw_tc_map & BIT(i)) 398 kinfo->num_tc++; 399 400 kinfo->rss_size 401 = min_t(u16, hdev->rss_size_max, new_tqps / kinfo->num_tc); 402 new_tqps = kinfo->rss_size * kinfo->num_tc; 403 kinfo->num_tqps = min(new_tqps, hdev->num_tqps); 404 405 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps, 406 sizeof(struct hnae3_queue *), GFP_KERNEL); 407 if (!kinfo->tqp) 408 return -ENOMEM; 409 410 for (i = 0; i < kinfo->num_tqps; i++) { 411 hdev->htqp[i].q.handle = &hdev->nic; 412 hdev->htqp[i].q.tqp_index = i; 413 kinfo->tqp[i] = &hdev->htqp[i].q; 414 } 415 416 /* after init the max rss_size and tqps, adjust the default tqp numbers 417 * and rss size with the actual vector numbers 418 */ 419 kinfo->num_tqps = min_t(u16, hdev->num_nic_msix - 1, kinfo->num_tqps); 420 kinfo->rss_size = min_t(u16, kinfo->num_tqps / kinfo->num_tc, 421 kinfo->rss_size); 422 423 return 0; 424 } 425 426 static void hclgevf_request_link_info(struct hclgevf_dev *hdev) 427 { 428 int status; 429 u8 resp_msg; 430 431 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_STATUS, 0, NULL, 432 0, false, &resp_msg, sizeof(resp_msg)); 433 if (status) 434 dev_err(&hdev->pdev->dev, 435 "VF failed to fetch link status(%d) from PF", status); 436 } 437 438 void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state) 439 { 440 struct hnae3_handle *rhandle = &hdev->roce; 441 struct hnae3_handle *handle = &hdev->nic; 442 struct hnae3_client *rclient; 443 struct hnae3_client *client; 444 445 if (test_and_set_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state)) 446 return; 447 448 client = handle->client; 449 rclient = hdev->roce_client; 450 451 link_state = 452 test_bit(HCLGEVF_STATE_DOWN, &hdev->state) ? 0 : link_state; 453 454 if (link_state != hdev->hw.mac.link) { 455 client->ops->link_status_change(handle, !!link_state); 456 if (rclient && rclient->ops->link_status_change) 457 rclient->ops->link_status_change(rhandle, !!link_state); 458 hdev->hw.mac.link = link_state; 459 } 460 461 clear_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state); 462 } 463 464 static void hclgevf_update_link_mode(struct hclgevf_dev *hdev) 465 { 466 #define HCLGEVF_ADVERTISING 0 467 #define HCLGEVF_SUPPORTED 1 468 u8 send_msg; 469 u8 resp_msg; 470 471 send_msg = HCLGEVF_ADVERTISING; 472 hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_MODE, 0, 473 &send_msg, sizeof(send_msg), false, 474 &resp_msg, sizeof(resp_msg)); 475 send_msg = HCLGEVF_SUPPORTED; 476 hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_MODE, 0, 477 &send_msg, sizeof(send_msg), false, 478 &resp_msg, sizeof(resp_msg)); 479 } 480 481 static int hclgevf_set_handle_info(struct hclgevf_dev *hdev) 482 { 483 struct hnae3_handle *nic = &hdev->nic; 484 int ret; 485 486 nic->ae_algo = &ae_algovf; 487 nic->pdev = hdev->pdev; 488 nic->numa_node_mask = hdev->numa_node_mask; 489 nic->flags |= HNAE3_SUPPORT_VF; 490 491 ret = hclgevf_knic_setup(hdev); 492 if (ret) 493 dev_err(&hdev->pdev->dev, "VF knic setup failed %d\n", 494 ret); 495 return ret; 496 } 497 498 static void hclgevf_free_vector(struct hclgevf_dev *hdev, int vector_id) 499 { 500 if (hdev->vector_status[vector_id] == HCLGEVF_INVALID_VPORT) { 501 dev_warn(&hdev->pdev->dev, 502 "vector(vector_id %d) has been freed.\n", vector_id); 503 return; 504 } 505 506 hdev->vector_status[vector_id] = HCLGEVF_INVALID_VPORT; 507 hdev->num_msi_left += 1; 508 hdev->num_msi_used -= 1; 509 } 510 511 static int hclgevf_get_vector(struct hnae3_handle *handle, u16 vector_num, 512 struct hnae3_vector_info *vector_info) 513 { 514 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 515 struct hnae3_vector_info *vector = vector_info; 516 int alloc = 0; 517 int i, j; 518 519 vector_num = min_t(u16, hdev->num_nic_msix - 1, vector_num); 520 vector_num = min(hdev->num_msi_left, vector_num); 521 522 for (j = 0; j < vector_num; j++) { 523 for (i = HCLGEVF_MISC_VECTOR_NUM + 1; i < hdev->num_msi; i++) { 524 if (hdev->vector_status[i] == HCLGEVF_INVALID_VPORT) { 525 vector->vector = pci_irq_vector(hdev->pdev, i); 526 vector->io_addr = hdev->hw.io_base + 527 HCLGEVF_VECTOR_REG_BASE + 528 (i - 1) * HCLGEVF_VECTOR_REG_OFFSET; 529 hdev->vector_status[i] = 0; 530 hdev->vector_irq[i] = vector->vector; 531 532 vector++; 533 alloc++; 534 535 break; 536 } 537 } 538 } 539 hdev->num_msi_left -= alloc; 540 hdev->num_msi_used += alloc; 541 542 return alloc; 543 } 544 545 static int hclgevf_get_vector_index(struct hclgevf_dev *hdev, int vector) 546 { 547 int i; 548 549 for (i = 0; i < hdev->num_msi; i++) 550 if (vector == hdev->vector_irq[i]) 551 return i; 552 553 return -EINVAL; 554 } 555 556 static int hclgevf_set_rss_algo_key(struct hclgevf_dev *hdev, 557 const u8 hfunc, const u8 *key) 558 { 559 struct hclgevf_rss_config_cmd *req; 560 unsigned int key_offset = 0; 561 struct hclgevf_desc desc; 562 int key_counts; 563 int key_size; 564 int ret; 565 566 key_counts = HCLGEVF_RSS_KEY_SIZE; 567 req = (struct hclgevf_rss_config_cmd *)desc.data; 568 569 while (key_counts) { 570 hclgevf_cmd_setup_basic_desc(&desc, 571 HCLGEVF_OPC_RSS_GENERIC_CONFIG, 572 false); 573 574 req->hash_config |= (hfunc & HCLGEVF_RSS_HASH_ALGO_MASK); 575 req->hash_config |= 576 (key_offset << HCLGEVF_RSS_HASH_KEY_OFFSET_B); 577 578 key_size = min(HCLGEVF_RSS_HASH_KEY_NUM, key_counts); 579 memcpy(req->hash_key, 580 key + key_offset * HCLGEVF_RSS_HASH_KEY_NUM, key_size); 581 582 key_counts -= key_size; 583 key_offset++; 584 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 585 if (ret) { 586 dev_err(&hdev->pdev->dev, 587 "Configure RSS config fail, status = %d\n", 588 ret); 589 return ret; 590 } 591 } 592 593 return 0; 594 } 595 596 static u32 hclgevf_get_rss_key_size(struct hnae3_handle *handle) 597 { 598 return HCLGEVF_RSS_KEY_SIZE; 599 } 600 601 static u32 hclgevf_get_rss_indir_size(struct hnae3_handle *handle) 602 { 603 return HCLGEVF_RSS_IND_TBL_SIZE; 604 } 605 606 static int hclgevf_set_rss_indir_table(struct hclgevf_dev *hdev) 607 { 608 const u8 *indir = hdev->rss_cfg.rss_indirection_tbl; 609 struct hclgevf_rss_indirection_table_cmd *req; 610 struct hclgevf_desc desc; 611 int status; 612 int i, j; 613 614 req = (struct hclgevf_rss_indirection_table_cmd *)desc.data; 615 616 for (i = 0; i < HCLGEVF_RSS_CFG_TBL_NUM; i++) { 617 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INDIR_TABLE, 618 false); 619 req->start_table_index = i * HCLGEVF_RSS_CFG_TBL_SIZE; 620 req->rss_set_bitmap = HCLGEVF_RSS_SET_BITMAP_MSK; 621 for (j = 0; j < HCLGEVF_RSS_CFG_TBL_SIZE; j++) 622 req->rss_result[j] = 623 indir[i * HCLGEVF_RSS_CFG_TBL_SIZE + j]; 624 625 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 626 if (status) { 627 dev_err(&hdev->pdev->dev, 628 "VF failed(=%d) to set RSS indirection table\n", 629 status); 630 return status; 631 } 632 } 633 634 return 0; 635 } 636 637 static int hclgevf_set_rss_tc_mode(struct hclgevf_dev *hdev, u16 rss_size) 638 { 639 struct hclgevf_rss_tc_mode_cmd *req; 640 u16 tc_offset[HCLGEVF_MAX_TC_NUM]; 641 u16 tc_valid[HCLGEVF_MAX_TC_NUM]; 642 u16 tc_size[HCLGEVF_MAX_TC_NUM]; 643 struct hclgevf_desc desc; 644 u16 roundup_size; 645 int status; 646 unsigned int i; 647 648 req = (struct hclgevf_rss_tc_mode_cmd *)desc.data; 649 650 roundup_size = roundup_pow_of_two(rss_size); 651 roundup_size = ilog2(roundup_size); 652 653 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 654 tc_valid[i] = !!(hdev->hw_tc_map & BIT(i)); 655 tc_size[i] = roundup_size; 656 tc_offset[i] = rss_size * i; 657 } 658 659 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_TC_MODE, false); 660 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 661 hnae3_set_bit(req->rss_tc_mode[i], HCLGEVF_RSS_TC_VALID_B, 662 (tc_valid[i] & 0x1)); 663 hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_SIZE_M, 664 HCLGEVF_RSS_TC_SIZE_S, tc_size[i]); 665 hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_OFFSET_M, 666 HCLGEVF_RSS_TC_OFFSET_S, tc_offset[i]); 667 } 668 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 669 if (status) 670 dev_err(&hdev->pdev->dev, 671 "VF failed(=%d) to set rss tc mode\n", status); 672 673 return status; 674 } 675 676 /* for revision 0x20, vf shared the same rss config with pf */ 677 static int hclgevf_get_rss_hash_key(struct hclgevf_dev *hdev) 678 { 679 #define HCLGEVF_RSS_MBX_RESP_LEN 8 680 681 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 682 u8 resp_msg[HCLGEVF_RSS_MBX_RESP_LEN]; 683 u16 msg_num, hash_key_index; 684 u8 index; 685 int ret; 686 687 msg_num = (HCLGEVF_RSS_KEY_SIZE + HCLGEVF_RSS_MBX_RESP_LEN - 1) / 688 HCLGEVF_RSS_MBX_RESP_LEN; 689 for (index = 0; index < msg_num; index++) { 690 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_RSS_KEY, 0, 691 &index, sizeof(index), 692 true, resp_msg, 693 HCLGEVF_RSS_MBX_RESP_LEN); 694 if (ret) { 695 dev_err(&hdev->pdev->dev, 696 "VF get rss hash key from PF failed, ret=%d", 697 ret); 698 return ret; 699 } 700 701 hash_key_index = HCLGEVF_RSS_MBX_RESP_LEN * index; 702 if (index == msg_num - 1) 703 memcpy(&rss_cfg->rss_hash_key[hash_key_index], 704 &resp_msg[0], 705 HCLGEVF_RSS_KEY_SIZE - hash_key_index); 706 else 707 memcpy(&rss_cfg->rss_hash_key[hash_key_index], 708 &resp_msg[0], HCLGEVF_RSS_MBX_RESP_LEN); 709 } 710 711 return 0; 712 } 713 714 static int hclgevf_get_rss(struct hnae3_handle *handle, u32 *indir, u8 *key, 715 u8 *hfunc) 716 { 717 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 718 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 719 int i, ret; 720 721 if (handle->pdev->revision >= 0x21) { 722 /* Get hash algorithm */ 723 if (hfunc) { 724 switch (rss_cfg->hash_algo) { 725 case HCLGEVF_RSS_HASH_ALGO_TOEPLITZ: 726 *hfunc = ETH_RSS_HASH_TOP; 727 break; 728 case HCLGEVF_RSS_HASH_ALGO_SIMPLE: 729 *hfunc = ETH_RSS_HASH_XOR; 730 break; 731 default: 732 *hfunc = ETH_RSS_HASH_UNKNOWN; 733 break; 734 } 735 } 736 737 /* Get the RSS Key required by the user */ 738 if (key) 739 memcpy(key, rss_cfg->rss_hash_key, 740 HCLGEVF_RSS_KEY_SIZE); 741 } else { 742 if (hfunc) 743 *hfunc = ETH_RSS_HASH_TOP; 744 if (key) { 745 ret = hclgevf_get_rss_hash_key(hdev); 746 if (ret) 747 return ret; 748 memcpy(key, rss_cfg->rss_hash_key, 749 HCLGEVF_RSS_KEY_SIZE); 750 } 751 } 752 753 if (indir) 754 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 755 indir[i] = rss_cfg->rss_indirection_tbl[i]; 756 757 return 0; 758 } 759 760 static int hclgevf_set_rss(struct hnae3_handle *handle, const u32 *indir, 761 const u8 *key, const u8 hfunc) 762 { 763 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 764 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 765 int ret, i; 766 767 if (handle->pdev->revision >= 0x21) { 768 /* Set the RSS Hash Key if specififed by the user */ 769 if (key) { 770 switch (hfunc) { 771 case ETH_RSS_HASH_TOP: 772 rss_cfg->hash_algo = 773 HCLGEVF_RSS_HASH_ALGO_TOEPLITZ; 774 break; 775 case ETH_RSS_HASH_XOR: 776 rss_cfg->hash_algo = 777 HCLGEVF_RSS_HASH_ALGO_SIMPLE; 778 break; 779 case ETH_RSS_HASH_NO_CHANGE: 780 break; 781 default: 782 return -EINVAL; 783 } 784 785 ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 786 key); 787 if (ret) 788 return ret; 789 790 /* Update the shadow RSS key with user specified qids */ 791 memcpy(rss_cfg->rss_hash_key, key, 792 HCLGEVF_RSS_KEY_SIZE); 793 } 794 } 795 796 /* update the shadow RSS table with user specified qids */ 797 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 798 rss_cfg->rss_indirection_tbl[i] = indir[i]; 799 800 /* update the hardware */ 801 return hclgevf_set_rss_indir_table(hdev); 802 } 803 804 static u8 hclgevf_get_rss_hash_bits(struct ethtool_rxnfc *nfc) 805 { 806 u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGEVF_S_PORT_BIT : 0; 807 808 if (nfc->data & RXH_L4_B_2_3) 809 hash_sets |= HCLGEVF_D_PORT_BIT; 810 else 811 hash_sets &= ~HCLGEVF_D_PORT_BIT; 812 813 if (nfc->data & RXH_IP_SRC) 814 hash_sets |= HCLGEVF_S_IP_BIT; 815 else 816 hash_sets &= ~HCLGEVF_S_IP_BIT; 817 818 if (nfc->data & RXH_IP_DST) 819 hash_sets |= HCLGEVF_D_IP_BIT; 820 else 821 hash_sets &= ~HCLGEVF_D_IP_BIT; 822 823 if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW) 824 hash_sets |= HCLGEVF_V_TAG_BIT; 825 826 return hash_sets; 827 } 828 829 static int hclgevf_set_rss_tuple(struct hnae3_handle *handle, 830 struct ethtool_rxnfc *nfc) 831 { 832 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 833 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 834 struct hclgevf_rss_input_tuple_cmd *req; 835 struct hclgevf_desc desc; 836 u8 tuple_sets; 837 int ret; 838 839 if (handle->pdev->revision == 0x20) 840 return -EOPNOTSUPP; 841 842 if (nfc->data & 843 ~(RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3)) 844 return -EINVAL; 845 846 req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 847 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 848 849 req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 850 req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 851 req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 852 req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 853 req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 854 req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 855 req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 856 req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 857 858 tuple_sets = hclgevf_get_rss_hash_bits(nfc); 859 switch (nfc->flow_type) { 860 case TCP_V4_FLOW: 861 req->ipv4_tcp_en = tuple_sets; 862 break; 863 case TCP_V6_FLOW: 864 req->ipv6_tcp_en = tuple_sets; 865 break; 866 case UDP_V4_FLOW: 867 req->ipv4_udp_en = tuple_sets; 868 break; 869 case UDP_V6_FLOW: 870 req->ipv6_udp_en = tuple_sets; 871 break; 872 case SCTP_V4_FLOW: 873 req->ipv4_sctp_en = tuple_sets; 874 break; 875 case SCTP_V6_FLOW: 876 if ((nfc->data & RXH_L4_B_0_1) || 877 (nfc->data & RXH_L4_B_2_3)) 878 return -EINVAL; 879 880 req->ipv6_sctp_en = tuple_sets; 881 break; 882 case IPV4_FLOW: 883 req->ipv4_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 884 break; 885 case IPV6_FLOW: 886 req->ipv6_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 887 break; 888 default: 889 return -EINVAL; 890 } 891 892 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 893 if (ret) { 894 dev_err(&hdev->pdev->dev, 895 "Set rss tuple fail, status = %d\n", ret); 896 return ret; 897 } 898 899 rss_cfg->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en; 900 rss_cfg->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en; 901 rss_cfg->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en; 902 rss_cfg->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en; 903 rss_cfg->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en; 904 rss_cfg->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en; 905 rss_cfg->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en; 906 rss_cfg->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en; 907 return 0; 908 } 909 910 static int hclgevf_get_rss_tuple(struct hnae3_handle *handle, 911 struct ethtool_rxnfc *nfc) 912 { 913 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 914 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 915 u8 tuple_sets; 916 917 if (handle->pdev->revision == 0x20) 918 return -EOPNOTSUPP; 919 920 nfc->data = 0; 921 922 switch (nfc->flow_type) { 923 case TCP_V4_FLOW: 924 tuple_sets = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 925 break; 926 case UDP_V4_FLOW: 927 tuple_sets = rss_cfg->rss_tuple_sets.ipv4_udp_en; 928 break; 929 case TCP_V6_FLOW: 930 tuple_sets = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 931 break; 932 case UDP_V6_FLOW: 933 tuple_sets = rss_cfg->rss_tuple_sets.ipv6_udp_en; 934 break; 935 case SCTP_V4_FLOW: 936 tuple_sets = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 937 break; 938 case SCTP_V6_FLOW: 939 tuple_sets = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 940 break; 941 case IPV4_FLOW: 942 case IPV6_FLOW: 943 tuple_sets = HCLGEVF_S_IP_BIT | HCLGEVF_D_IP_BIT; 944 break; 945 default: 946 return -EINVAL; 947 } 948 949 if (!tuple_sets) 950 return 0; 951 952 if (tuple_sets & HCLGEVF_D_PORT_BIT) 953 nfc->data |= RXH_L4_B_2_3; 954 if (tuple_sets & HCLGEVF_S_PORT_BIT) 955 nfc->data |= RXH_L4_B_0_1; 956 if (tuple_sets & HCLGEVF_D_IP_BIT) 957 nfc->data |= RXH_IP_DST; 958 if (tuple_sets & HCLGEVF_S_IP_BIT) 959 nfc->data |= RXH_IP_SRC; 960 961 return 0; 962 } 963 964 static int hclgevf_set_rss_input_tuple(struct hclgevf_dev *hdev, 965 struct hclgevf_rss_cfg *rss_cfg) 966 { 967 struct hclgevf_rss_input_tuple_cmd *req; 968 struct hclgevf_desc desc; 969 int ret; 970 971 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 972 973 req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 974 975 req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 976 req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 977 req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 978 req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 979 req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 980 req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 981 req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 982 req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 983 984 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 985 if (ret) 986 dev_err(&hdev->pdev->dev, 987 "Configure rss input fail, status = %d\n", ret); 988 return ret; 989 } 990 991 static int hclgevf_get_tc_size(struct hnae3_handle *handle) 992 { 993 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 994 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 995 996 return rss_cfg->rss_size; 997 } 998 999 static int hclgevf_bind_ring_to_vector(struct hnae3_handle *handle, bool en, 1000 int vector_id, 1001 struct hnae3_ring_chain_node *ring_chain) 1002 { 1003 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1004 struct hnae3_ring_chain_node *node; 1005 struct hclge_mbx_vf_to_pf_cmd *req; 1006 struct hclgevf_desc desc; 1007 int i = 0; 1008 int status; 1009 u8 type; 1010 1011 req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data; 1012 type = en ? HCLGE_MBX_MAP_RING_TO_VECTOR : 1013 HCLGE_MBX_UNMAP_RING_TO_VECTOR; 1014 1015 for (node = ring_chain; node; node = node->next) { 1016 int idx_offset = HCLGE_MBX_RING_MAP_BASIC_MSG_NUM + 1017 HCLGE_MBX_RING_NODE_VARIABLE_NUM * i; 1018 1019 if (i == 0) { 1020 hclgevf_cmd_setup_basic_desc(&desc, 1021 HCLGEVF_OPC_MBX_VF_TO_PF, 1022 false); 1023 req->msg[0] = type; 1024 req->msg[1] = vector_id; 1025 } 1026 1027 req->msg[idx_offset] = 1028 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B); 1029 req->msg[idx_offset + 1] = node->tqp_index; 1030 req->msg[idx_offset + 2] = hnae3_get_field(node->int_gl_idx, 1031 HNAE3_RING_GL_IDX_M, 1032 HNAE3_RING_GL_IDX_S); 1033 1034 i++; 1035 if ((i == (HCLGE_MBX_VF_MSG_DATA_NUM - 1036 HCLGE_MBX_RING_MAP_BASIC_MSG_NUM) / 1037 HCLGE_MBX_RING_NODE_VARIABLE_NUM) || 1038 !node->next) { 1039 req->msg[2] = i; 1040 1041 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1042 if (status) { 1043 dev_err(&hdev->pdev->dev, 1044 "Map TQP fail, status is %d.\n", 1045 status); 1046 return status; 1047 } 1048 i = 0; 1049 hclgevf_cmd_setup_basic_desc(&desc, 1050 HCLGEVF_OPC_MBX_VF_TO_PF, 1051 false); 1052 req->msg[0] = type; 1053 req->msg[1] = vector_id; 1054 } 1055 } 1056 1057 return 0; 1058 } 1059 1060 static int hclgevf_map_ring_to_vector(struct hnae3_handle *handle, int vector, 1061 struct hnae3_ring_chain_node *ring_chain) 1062 { 1063 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1064 int vector_id; 1065 1066 vector_id = hclgevf_get_vector_index(hdev, vector); 1067 if (vector_id < 0) { 1068 dev_err(&handle->pdev->dev, 1069 "Get vector index fail. ret =%d\n", vector_id); 1070 return vector_id; 1071 } 1072 1073 return hclgevf_bind_ring_to_vector(handle, true, vector_id, ring_chain); 1074 } 1075 1076 static int hclgevf_unmap_ring_from_vector( 1077 struct hnae3_handle *handle, 1078 int vector, 1079 struct hnae3_ring_chain_node *ring_chain) 1080 { 1081 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1082 int ret, vector_id; 1083 1084 if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 1085 return 0; 1086 1087 vector_id = hclgevf_get_vector_index(hdev, vector); 1088 if (vector_id < 0) { 1089 dev_err(&handle->pdev->dev, 1090 "Get vector index fail. ret =%d\n", vector_id); 1091 return vector_id; 1092 } 1093 1094 ret = hclgevf_bind_ring_to_vector(handle, false, vector_id, ring_chain); 1095 if (ret) 1096 dev_err(&handle->pdev->dev, 1097 "Unmap ring from vector fail. vector=%d, ret =%d\n", 1098 vector_id, 1099 ret); 1100 1101 return ret; 1102 } 1103 1104 static int hclgevf_put_vector(struct hnae3_handle *handle, int vector) 1105 { 1106 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1107 int vector_id; 1108 1109 vector_id = hclgevf_get_vector_index(hdev, vector); 1110 if (vector_id < 0) { 1111 dev_err(&handle->pdev->dev, 1112 "hclgevf_put_vector get vector index fail. ret =%d\n", 1113 vector_id); 1114 return vector_id; 1115 } 1116 1117 hclgevf_free_vector(hdev, vector_id); 1118 1119 return 0; 1120 } 1121 1122 static int hclgevf_cmd_set_promisc_mode(struct hclgevf_dev *hdev, 1123 bool en_uc_pmc, bool en_mc_pmc, 1124 bool en_bc_pmc) 1125 { 1126 struct hclge_mbx_vf_to_pf_cmd *req; 1127 struct hclgevf_desc desc; 1128 int ret; 1129 1130 req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data; 1131 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_MBX_VF_TO_PF, false); 1132 req->msg[0] = HCLGE_MBX_SET_PROMISC_MODE; 1133 req->msg[1] = en_bc_pmc ? 1 : 0; 1134 req->msg[2] = en_uc_pmc ? 1 : 0; 1135 req->msg[3] = en_mc_pmc ? 1 : 0; 1136 1137 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1138 if (ret) 1139 dev_err(&hdev->pdev->dev, 1140 "Set promisc mode fail, status is %d.\n", ret); 1141 1142 return ret; 1143 } 1144 1145 static int hclgevf_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc, 1146 bool en_mc_pmc) 1147 { 1148 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1149 struct pci_dev *pdev = hdev->pdev; 1150 bool en_bc_pmc; 1151 1152 en_bc_pmc = pdev->revision != 0x20; 1153 1154 return hclgevf_cmd_set_promisc_mode(hdev, en_uc_pmc, en_mc_pmc, 1155 en_bc_pmc); 1156 } 1157 1158 static int hclgevf_tqp_enable(struct hclgevf_dev *hdev, unsigned int tqp_id, 1159 int stream_id, bool enable) 1160 { 1161 struct hclgevf_cfg_com_tqp_queue_cmd *req; 1162 struct hclgevf_desc desc; 1163 int status; 1164 1165 req = (struct hclgevf_cfg_com_tqp_queue_cmd *)desc.data; 1166 1167 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_CFG_COM_TQP_QUEUE, 1168 false); 1169 req->tqp_id = cpu_to_le16(tqp_id & HCLGEVF_RING_ID_MASK); 1170 req->stream_id = cpu_to_le16(stream_id); 1171 if (enable) 1172 req->enable |= 1U << HCLGEVF_TQP_ENABLE_B; 1173 1174 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1175 if (status) 1176 dev_err(&hdev->pdev->dev, 1177 "TQP enable fail, status =%d.\n", status); 1178 1179 return status; 1180 } 1181 1182 static void hclgevf_reset_tqp_stats(struct hnae3_handle *handle) 1183 { 1184 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 1185 struct hclgevf_tqp *tqp; 1186 int i; 1187 1188 for (i = 0; i < kinfo->num_tqps; i++) { 1189 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 1190 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats)); 1191 } 1192 } 1193 1194 static int hclgevf_get_host_mac_addr(struct hclgevf_dev *hdev, u8 *p) 1195 { 1196 u8 host_mac[ETH_ALEN]; 1197 int status; 1198 1199 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_MAC_ADDR, 0, NULL, 0, 1200 true, host_mac, ETH_ALEN); 1201 if (status) { 1202 dev_err(&hdev->pdev->dev, 1203 "fail to get VF MAC from host %d", status); 1204 return status; 1205 } 1206 1207 ether_addr_copy(p, host_mac); 1208 1209 return 0; 1210 } 1211 1212 static void hclgevf_get_mac_addr(struct hnae3_handle *handle, u8 *p) 1213 { 1214 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1215 u8 host_mac_addr[ETH_ALEN]; 1216 1217 if (hclgevf_get_host_mac_addr(hdev, host_mac_addr)) 1218 return; 1219 1220 hdev->has_pf_mac = !is_zero_ether_addr(host_mac_addr); 1221 if (hdev->has_pf_mac) 1222 ether_addr_copy(p, host_mac_addr); 1223 else 1224 ether_addr_copy(p, hdev->hw.mac.mac_addr); 1225 } 1226 1227 static int hclgevf_set_mac_addr(struct hnae3_handle *handle, void *p, 1228 bool is_first) 1229 { 1230 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1231 u8 *old_mac_addr = (u8 *)hdev->hw.mac.mac_addr; 1232 u8 *new_mac_addr = (u8 *)p; 1233 u8 msg_data[ETH_ALEN * 2]; 1234 u16 subcode; 1235 int status; 1236 1237 ether_addr_copy(msg_data, new_mac_addr); 1238 ether_addr_copy(&msg_data[ETH_ALEN], old_mac_addr); 1239 1240 subcode = is_first ? HCLGE_MBX_MAC_VLAN_UC_ADD : 1241 HCLGE_MBX_MAC_VLAN_UC_MODIFY; 1242 1243 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 1244 subcode, msg_data, sizeof(msg_data), 1245 true, NULL, 0); 1246 if (!status) 1247 ether_addr_copy(hdev->hw.mac.mac_addr, new_mac_addr); 1248 1249 return status; 1250 } 1251 1252 static int hclgevf_add_uc_addr(struct hnae3_handle *handle, 1253 const unsigned char *addr) 1254 { 1255 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1256 1257 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 1258 HCLGE_MBX_MAC_VLAN_UC_ADD, 1259 addr, ETH_ALEN, false, NULL, 0); 1260 } 1261 1262 static int hclgevf_rm_uc_addr(struct hnae3_handle *handle, 1263 const unsigned char *addr) 1264 { 1265 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1266 1267 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 1268 HCLGE_MBX_MAC_VLAN_UC_REMOVE, 1269 addr, ETH_ALEN, false, NULL, 0); 1270 } 1271 1272 static int hclgevf_add_mc_addr(struct hnae3_handle *handle, 1273 const unsigned char *addr) 1274 { 1275 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1276 1277 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 1278 HCLGE_MBX_MAC_VLAN_MC_ADD, 1279 addr, ETH_ALEN, false, NULL, 0); 1280 } 1281 1282 static int hclgevf_rm_mc_addr(struct hnae3_handle *handle, 1283 const unsigned char *addr) 1284 { 1285 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1286 1287 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 1288 HCLGE_MBX_MAC_VLAN_MC_REMOVE, 1289 addr, ETH_ALEN, false, NULL, 0); 1290 } 1291 1292 static int hclgevf_set_vlan_filter(struct hnae3_handle *handle, 1293 __be16 proto, u16 vlan_id, 1294 bool is_kill) 1295 { 1296 #define HCLGEVF_VLAN_MBX_MSG_LEN 5 1297 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1298 u8 msg_data[HCLGEVF_VLAN_MBX_MSG_LEN]; 1299 int ret; 1300 1301 if (vlan_id > HCLGEVF_MAX_VLAN_ID) 1302 return -EINVAL; 1303 1304 if (proto != htons(ETH_P_8021Q)) 1305 return -EPROTONOSUPPORT; 1306 1307 /* When device is resetting, firmware is unable to handle 1308 * mailbox. Just record the vlan id, and remove it after 1309 * reset finished. 1310 */ 1311 if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) && is_kill) { 1312 set_bit(vlan_id, hdev->vlan_del_fail_bmap); 1313 return -EBUSY; 1314 } 1315 1316 msg_data[0] = is_kill; 1317 memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id)); 1318 memcpy(&msg_data[3], &proto, sizeof(proto)); 1319 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 1320 HCLGE_MBX_VLAN_FILTER, msg_data, 1321 HCLGEVF_VLAN_MBX_MSG_LEN, true, NULL, 0); 1322 1323 /* when remove hw vlan filter failed, record the vlan id, 1324 * and try to remove it from hw later, to be consistence 1325 * with stack. 1326 */ 1327 if (is_kill && ret) 1328 set_bit(vlan_id, hdev->vlan_del_fail_bmap); 1329 1330 return ret; 1331 } 1332 1333 static void hclgevf_sync_vlan_filter(struct hclgevf_dev *hdev) 1334 { 1335 #define HCLGEVF_MAX_SYNC_COUNT 60 1336 struct hnae3_handle *handle = &hdev->nic; 1337 int ret, sync_cnt = 0; 1338 u16 vlan_id; 1339 1340 vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID); 1341 while (vlan_id != VLAN_N_VID) { 1342 ret = hclgevf_set_vlan_filter(handle, htons(ETH_P_8021Q), 1343 vlan_id, true); 1344 if (ret) 1345 return; 1346 1347 clear_bit(vlan_id, hdev->vlan_del_fail_bmap); 1348 sync_cnt++; 1349 if (sync_cnt >= HCLGEVF_MAX_SYNC_COUNT) 1350 return; 1351 1352 vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID); 1353 } 1354 } 1355 1356 static int hclgevf_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) 1357 { 1358 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1359 u8 msg_data; 1360 1361 msg_data = enable ? 1 : 0; 1362 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 1363 HCLGE_MBX_VLAN_RX_OFF_CFG, &msg_data, 1364 1, false, NULL, 0); 1365 } 1366 1367 static int hclgevf_reset_tqp(struct hnae3_handle *handle, u16 queue_id) 1368 { 1369 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1370 u8 msg_data[2]; 1371 int ret; 1372 1373 memcpy(msg_data, &queue_id, sizeof(queue_id)); 1374 1375 /* disable vf queue before send queue reset msg to PF */ 1376 ret = hclgevf_tqp_enable(hdev, queue_id, 0, false); 1377 if (ret) 1378 return ret; 1379 1380 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_QUEUE_RESET, 0, msg_data, 1381 sizeof(msg_data), true, NULL, 0); 1382 } 1383 1384 static int hclgevf_set_mtu(struct hnae3_handle *handle, int new_mtu) 1385 { 1386 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1387 1388 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MTU, 0, (u8 *)&new_mtu, 1389 sizeof(new_mtu), true, NULL, 0); 1390 } 1391 1392 static int hclgevf_notify_client(struct hclgevf_dev *hdev, 1393 enum hnae3_reset_notify_type type) 1394 { 1395 struct hnae3_client *client = hdev->nic_client; 1396 struct hnae3_handle *handle = &hdev->nic; 1397 int ret; 1398 1399 if (!test_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state) || 1400 !client) 1401 return 0; 1402 1403 if (!client->ops->reset_notify) 1404 return -EOPNOTSUPP; 1405 1406 ret = client->ops->reset_notify(handle, type); 1407 if (ret) 1408 dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n", 1409 type, ret); 1410 1411 return ret; 1412 } 1413 1414 static void hclgevf_flr_done(struct hnae3_ae_dev *ae_dev) 1415 { 1416 struct hclgevf_dev *hdev = ae_dev->priv; 1417 1418 set_bit(HNAE3_FLR_DONE, &hdev->flr_state); 1419 } 1420 1421 static int hclgevf_flr_poll_timeout(struct hclgevf_dev *hdev, 1422 unsigned long delay_us, 1423 unsigned long wait_cnt) 1424 { 1425 unsigned long cnt = 0; 1426 1427 while (!test_bit(HNAE3_FLR_DONE, &hdev->flr_state) && 1428 cnt++ < wait_cnt) 1429 usleep_range(delay_us, delay_us * 2); 1430 1431 if (!test_bit(HNAE3_FLR_DONE, &hdev->flr_state)) { 1432 dev_err(&hdev->pdev->dev, 1433 "flr wait timeout\n"); 1434 return -ETIMEDOUT; 1435 } 1436 1437 return 0; 1438 } 1439 1440 static int hclgevf_reset_wait(struct hclgevf_dev *hdev) 1441 { 1442 #define HCLGEVF_RESET_WAIT_US 20000 1443 #define HCLGEVF_RESET_WAIT_CNT 2000 1444 #define HCLGEVF_RESET_WAIT_TIMEOUT_US \ 1445 (HCLGEVF_RESET_WAIT_US * HCLGEVF_RESET_WAIT_CNT) 1446 1447 u32 val; 1448 int ret; 1449 1450 if (hdev->reset_type == HNAE3_FLR_RESET) 1451 return hclgevf_flr_poll_timeout(hdev, 1452 HCLGEVF_RESET_WAIT_US, 1453 HCLGEVF_RESET_WAIT_CNT); 1454 else if (hdev->reset_type == HNAE3_VF_RESET) 1455 ret = readl_poll_timeout(hdev->hw.io_base + 1456 HCLGEVF_VF_RST_ING, val, 1457 !(val & HCLGEVF_VF_RST_ING_BIT), 1458 HCLGEVF_RESET_WAIT_US, 1459 HCLGEVF_RESET_WAIT_TIMEOUT_US); 1460 else 1461 ret = readl_poll_timeout(hdev->hw.io_base + 1462 HCLGEVF_RST_ING, val, 1463 !(val & HCLGEVF_RST_ING_BITS), 1464 HCLGEVF_RESET_WAIT_US, 1465 HCLGEVF_RESET_WAIT_TIMEOUT_US); 1466 1467 /* hardware completion status should be available by this time */ 1468 if (ret) { 1469 dev_err(&hdev->pdev->dev, 1470 "could'nt get reset done status from h/w, timeout!\n"); 1471 return ret; 1472 } 1473 1474 /* we will wait a bit more to let reset of the stack to complete. This 1475 * might happen in case reset assertion was made by PF. Yes, this also 1476 * means we might end up waiting bit more even for VF reset. 1477 */ 1478 msleep(5000); 1479 1480 return 0; 1481 } 1482 1483 static void hclgevf_reset_handshake(struct hclgevf_dev *hdev, bool enable) 1484 { 1485 u32 reg_val; 1486 1487 reg_val = hclgevf_read_dev(&hdev->hw, HCLGEVF_NIC_CSQ_DEPTH_REG); 1488 if (enable) 1489 reg_val |= HCLGEVF_NIC_SW_RST_RDY; 1490 else 1491 reg_val &= ~HCLGEVF_NIC_SW_RST_RDY; 1492 1493 hclgevf_write_dev(&hdev->hw, HCLGEVF_NIC_CSQ_DEPTH_REG, 1494 reg_val); 1495 } 1496 1497 static int hclgevf_reset_stack(struct hclgevf_dev *hdev) 1498 { 1499 int ret; 1500 1501 /* uninitialize the nic client */ 1502 ret = hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT); 1503 if (ret) 1504 return ret; 1505 1506 /* re-initialize the hclge device */ 1507 ret = hclgevf_reset_hdev(hdev); 1508 if (ret) { 1509 dev_err(&hdev->pdev->dev, 1510 "hclge device re-init failed, VF is disabled!\n"); 1511 return ret; 1512 } 1513 1514 /* bring up the nic client again */ 1515 ret = hclgevf_notify_client(hdev, HNAE3_INIT_CLIENT); 1516 if (ret) 1517 return ret; 1518 1519 ret = hclgevf_notify_client(hdev, HNAE3_RESTORE_CLIENT); 1520 if (ret) 1521 return ret; 1522 1523 /* clear handshake status with IMP */ 1524 hclgevf_reset_handshake(hdev, false); 1525 1526 return 0; 1527 } 1528 1529 static int hclgevf_reset_prepare_wait(struct hclgevf_dev *hdev) 1530 { 1531 #define HCLGEVF_RESET_SYNC_TIME 100 1532 1533 int ret = 0; 1534 1535 switch (hdev->reset_type) { 1536 case HNAE3_VF_FUNC_RESET: 1537 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_RESET, 0, NULL, 1538 0, true, NULL, sizeof(u8)); 1539 hdev->rst_stats.vf_func_rst_cnt++; 1540 break; 1541 case HNAE3_FLR_RESET: 1542 set_bit(HNAE3_FLR_DOWN, &hdev->flr_state); 1543 hdev->rst_stats.flr_rst_cnt++; 1544 break; 1545 default: 1546 break; 1547 } 1548 1549 set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 1550 /* inform hardware that preparatory work is done */ 1551 msleep(HCLGEVF_RESET_SYNC_TIME); 1552 hclgevf_reset_handshake(hdev, true); 1553 dev_info(&hdev->pdev->dev, "prepare reset(%d) wait done, ret:%d\n", 1554 hdev->reset_type, ret); 1555 1556 return ret; 1557 } 1558 1559 static void hclgevf_dump_rst_info(struct hclgevf_dev *hdev) 1560 { 1561 dev_info(&hdev->pdev->dev, "VF function reset count: %u\n", 1562 hdev->rst_stats.vf_func_rst_cnt); 1563 dev_info(&hdev->pdev->dev, "FLR reset count: %u\n", 1564 hdev->rst_stats.flr_rst_cnt); 1565 dev_info(&hdev->pdev->dev, "VF reset count: %u\n", 1566 hdev->rst_stats.vf_rst_cnt); 1567 dev_info(&hdev->pdev->dev, "reset done count: %u\n", 1568 hdev->rst_stats.rst_done_cnt); 1569 dev_info(&hdev->pdev->dev, "HW reset done count: %u\n", 1570 hdev->rst_stats.hw_rst_done_cnt); 1571 dev_info(&hdev->pdev->dev, "reset count: %u\n", 1572 hdev->rst_stats.rst_cnt); 1573 dev_info(&hdev->pdev->dev, "reset fail count: %u\n", 1574 hdev->rst_stats.rst_fail_cnt); 1575 dev_info(&hdev->pdev->dev, "vector0 interrupt enable status: 0x%x\n", 1576 hclgevf_read_dev(&hdev->hw, HCLGEVF_MISC_VECTOR_REG_BASE)); 1577 dev_info(&hdev->pdev->dev, "vector0 interrupt status: 0x%x\n", 1578 hclgevf_read_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_STAT_REG)); 1579 dev_info(&hdev->pdev->dev, "handshake status: 0x%x\n", 1580 hclgevf_read_dev(&hdev->hw, HCLGEVF_CMDQ_TX_DEPTH_REG)); 1581 dev_info(&hdev->pdev->dev, "function reset status: 0x%x\n", 1582 hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING)); 1583 dev_info(&hdev->pdev->dev, "hdev state: 0x%lx\n", hdev->state); 1584 } 1585 1586 static void hclgevf_reset_err_handle(struct hclgevf_dev *hdev) 1587 { 1588 /* recover handshake status with IMP when reset fail */ 1589 hclgevf_reset_handshake(hdev, true); 1590 hdev->rst_stats.rst_fail_cnt++; 1591 dev_err(&hdev->pdev->dev, "failed to reset VF(%u)\n", 1592 hdev->rst_stats.rst_fail_cnt); 1593 1594 if (hdev->rst_stats.rst_fail_cnt < HCLGEVF_RESET_MAX_FAIL_CNT) 1595 set_bit(hdev->reset_type, &hdev->reset_pending); 1596 1597 if (hclgevf_is_reset_pending(hdev)) { 1598 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1599 hclgevf_reset_task_schedule(hdev); 1600 } else { 1601 set_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state); 1602 hclgevf_dump_rst_info(hdev); 1603 } 1604 } 1605 1606 static int hclgevf_reset(struct hclgevf_dev *hdev) 1607 { 1608 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1609 int ret; 1610 1611 /* Initialize ae_dev reset status as well, in case enet layer wants to 1612 * know if device is undergoing reset 1613 */ 1614 ae_dev->reset_type = hdev->reset_type; 1615 hdev->rst_stats.rst_cnt++; 1616 rtnl_lock(); 1617 1618 /* bring down the nic to stop any ongoing TX/RX */ 1619 ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 1620 if (ret) 1621 goto err_reset_lock; 1622 1623 rtnl_unlock(); 1624 1625 ret = hclgevf_reset_prepare_wait(hdev); 1626 if (ret) 1627 goto err_reset; 1628 1629 /* check if VF could successfully fetch the hardware reset completion 1630 * status from the hardware 1631 */ 1632 ret = hclgevf_reset_wait(hdev); 1633 if (ret) { 1634 /* can't do much in this situation, will disable VF */ 1635 dev_err(&hdev->pdev->dev, 1636 "VF failed(=%d) to fetch H/W reset completion status\n", 1637 ret); 1638 goto err_reset; 1639 } 1640 1641 hdev->rst_stats.hw_rst_done_cnt++; 1642 1643 rtnl_lock(); 1644 1645 /* now, re-initialize the nic client and ae device */ 1646 ret = hclgevf_reset_stack(hdev); 1647 if (ret) { 1648 dev_err(&hdev->pdev->dev, "failed to reset VF stack\n"); 1649 goto err_reset_lock; 1650 } 1651 1652 /* bring up the nic to enable TX/RX again */ 1653 ret = hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 1654 if (ret) 1655 goto err_reset_lock; 1656 1657 rtnl_unlock(); 1658 1659 hdev->last_reset_time = jiffies; 1660 ae_dev->reset_type = HNAE3_NONE_RESET; 1661 hdev->rst_stats.rst_done_cnt++; 1662 hdev->rst_stats.rst_fail_cnt = 0; 1663 clear_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state); 1664 1665 return ret; 1666 err_reset_lock: 1667 rtnl_unlock(); 1668 err_reset: 1669 hclgevf_reset_err_handle(hdev); 1670 1671 return ret; 1672 } 1673 1674 static enum hnae3_reset_type hclgevf_get_reset_level(struct hclgevf_dev *hdev, 1675 unsigned long *addr) 1676 { 1677 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; 1678 1679 /* return the highest priority reset level amongst all */ 1680 if (test_bit(HNAE3_VF_RESET, addr)) { 1681 rst_level = HNAE3_VF_RESET; 1682 clear_bit(HNAE3_VF_RESET, addr); 1683 clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1684 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1685 } else if (test_bit(HNAE3_VF_FULL_RESET, addr)) { 1686 rst_level = HNAE3_VF_FULL_RESET; 1687 clear_bit(HNAE3_VF_FULL_RESET, addr); 1688 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1689 } else if (test_bit(HNAE3_VF_PF_FUNC_RESET, addr)) { 1690 rst_level = HNAE3_VF_PF_FUNC_RESET; 1691 clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1692 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1693 } else if (test_bit(HNAE3_VF_FUNC_RESET, addr)) { 1694 rst_level = HNAE3_VF_FUNC_RESET; 1695 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1696 } else if (test_bit(HNAE3_FLR_RESET, addr)) { 1697 rst_level = HNAE3_FLR_RESET; 1698 clear_bit(HNAE3_FLR_RESET, addr); 1699 } 1700 1701 return rst_level; 1702 } 1703 1704 static void hclgevf_reset_event(struct pci_dev *pdev, 1705 struct hnae3_handle *handle) 1706 { 1707 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 1708 struct hclgevf_dev *hdev = ae_dev->priv; 1709 1710 dev_info(&hdev->pdev->dev, "received reset request from VF enet\n"); 1711 1712 if (hdev->default_reset_request) 1713 hdev->reset_level = 1714 hclgevf_get_reset_level(hdev, 1715 &hdev->default_reset_request); 1716 else 1717 hdev->reset_level = HNAE3_VF_FUNC_RESET; 1718 1719 /* reset of this VF requested */ 1720 set_bit(HCLGEVF_RESET_REQUESTED, &hdev->reset_state); 1721 hclgevf_reset_task_schedule(hdev); 1722 1723 hdev->last_reset_time = jiffies; 1724 } 1725 1726 static void hclgevf_set_def_reset_request(struct hnae3_ae_dev *ae_dev, 1727 enum hnae3_reset_type rst_type) 1728 { 1729 struct hclgevf_dev *hdev = ae_dev->priv; 1730 1731 set_bit(rst_type, &hdev->default_reset_request); 1732 } 1733 1734 static void hclgevf_flr_prepare(struct hnae3_ae_dev *ae_dev) 1735 { 1736 #define HCLGEVF_FLR_WAIT_MS 100 1737 #define HCLGEVF_FLR_WAIT_CNT 50 1738 struct hclgevf_dev *hdev = ae_dev->priv; 1739 int cnt = 0; 1740 1741 clear_bit(HNAE3_FLR_DOWN, &hdev->flr_state); 1742 clear_bit(HNAE3_FLR_DONE, &hdev->flr_state); 1743 set_bit(HNAE3_FLR_RESET, &hdev->default_reset_request); 1744 hclgevf_reset_event(hdev->pdev, NULL); 1745 1746 while (!test_bit(HNAE3_FLR_DOWN, &hdev->flr_state) && 1747 cnt++ < HCLGEVF_FLR_WAIT_CNT) 1748 msleep(HCLGEVF_FLR_WAIT_MS); 1749 1750 if (!test_bit(HNAE3_FLR_DOWN, &hdev->flr_state)) 1751 dev_err(&hdev->pdev->dev, 1752 "flr wait down timeout: %d\n", cnt); 1753 } 1754 1755 static u32 hclgevf_get_fw_version(struct hnae3_handle *handle) 1756 { 1757 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1758 1759 return hdev->fw_version; 1760 } 1761 1762 static void hclgevf_get_misc_vector(struct hclgevf_dev *hdev) 1763 { 1764 struct hclgevf_misc_vector *vector = &hdev->misc_vector; 1765 1766 vector->vector_irq = pci_irq_vector(hdev->pdev, 1767 HCLGEVF_MISC_VECTOR_NUM); 1768 vector->addr = hdev->hw.io_base + HCLGEVF_MISC_VECTOR_REG_BASE; 1769 /* vector status always valid for Vector 0 */ 1770 hdev->vector_status[HCLGEVF_MISC_VECTOR_NUM] = 0; 1771 hdev->vector_irq[HCLGEVF_MISC_VECTOR_NUM] = vector->vector_irq; 1772 1773 hdev->num_msi_left -= 1; 1774 hdev->num_msi_used += 1; 1775 } 1776 1777 void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev) 1778 { 1779 if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) && 1780 !test_and_set_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, 1781 &hdev->state)) 1782 mod_delayed_work(hclgevf_wq, &hdev->service_task, 0); 1783 } 1784 1785 void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev) 1786 { 1787 if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) && 1788 !test_and_set_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, 1789 &hdev->state)) 1790 mod_delayed_work(hclgevf_wq, &hdev->service_task, 0); 1791 } 1792 1793 static void hclgevf_task_schedule(struct hclgevf_dev *hdev, 1794 unsigned long delay) 1795 { 1796 if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) && 1797 !test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) 1798 mod_delayed_work(hclgevf_wq, &hdev->service_task, delay); 1799 } 1800 1801 static void hclgevf_reset_service_task(struct hclgevf_dev *hdev) 1802 { 1803 #define HCLGEVF_MAX_RESET_ATTEMPTS_CNT 3 1804 1805 int ret; 1806 1807 if (!test_and_clear_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state)) 1808 return; 1809 1810 if (test_and_set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 1811 return; 1812 1813 if (test_and_clear_bit(HCLGEVF_RESET_PENDING, 1814 &hdev->reset_state)) { 1815 /* PF has initmated that it is about to reset the hardware. 1816 * We now have to poll & check if hardware has actually 1817 * completed the reset sequence. On hardware reset completion, 1818 * VF needs to reset the client and ae device. 1819 */ 1820 hdev->reset_attempts = 0; 1821 1822 hdev->last_reset_time = jiffies; 1823 while ((hdev->reset_type = 1824 hclgevf_get_reset_level(hdev, &hdev->reset_pending)) 1825 != HNAE3_NONE_RESET) { 1826 ret = hclgevf_reset(hdev); 1827 if (ret) 1828 dev_err(&hdev->pdev->dev, 1829 "VF stack reset failed %d.\n", ret); 1830 } 1831 } else if (test_and_clear_bit(HCLGEVF_RESET_REQUESTED, 1832 &hdev->reset_state)) { 1833 /* we could be here when either of below happens: 1834 * 1. reset was initiated due to watchdog timeout caused by 1835 * a. IMP was earlier reset and our TX got choked down and 1836 * which resulted in watchdog reacting and inducing VF 1837 * reset. This also means our cmdq would be unreliable. 1838 * b. problem in TX due to other lower layer(example link 1839 * layer not functioning properly etc.) 1840 * 2. VF reset might have been initiated due to some config 1841 * change. 1842 * 1843 * NOTE: Theres no clear way to detect above cases than to react 1844 * to the response of PF for this reset request. PF will ack the 1845 * 1b and 2. cases but we will not get any intimation about 1a 1846 * from PF as cmdq would be in unreliable state i.e. mailbox 1847 * communication between PF and VF would be broken. 1848 * 1849 * if we are never geting into pending state it means either: 1850 * 1. PF is not receiving our request which could be due to IMP 1851 * reset 1852 * 2. PF is screwed 1853 * We cannot do much for 2. but to check first we can try reset 1854 * our PCIe + stack and see if it alleviates the problem. 1855 */ 1856 if (hdev->reset_attempts > HCLGEVF_MAX_RESET_ATTEMPTS_CNT) { 1857 /* prepare for full reset of stack + pcie interface */ 1858 set_bit(HNAE3_VF_FULL_RESET, &hdev->reset_pending); 1859 1860 /* "defer" schedule the reset task again */ 1861 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1862 } else { 1863 hdev->reset_attempts++; 1864 1865 set_bit(hdev->reset_level, &hdev->reset_pending); 1866 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1867 } 1868 hclgevf_reset_task_schedule(hdev); 1869 } 1870 1871 clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 1872 } 1873 1874 static void hclgevf_mailbox_service_task(struct hclgevf_dev *hdev) 1875 { 1876 if (!test_and_clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state)) 1877 return; 1878 1879 if (test_and_set_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) 1880 return; 1881 1882 hclgevf_mbx_async_handler(hdev); 1883 1884 clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 1885 } 1886 1887 static void hclgevf_keep_alive(struct hclgevf_dev *hdev) 1888 { 1889 u8 respmsg; 1890 int ret; 1891 1892 if (test_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state)) 1893 return; 1894 1895 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_KEEP_ALIVE, 0, NULL, 1896 0, false, &respmsg, sizeof(respmsg)); 1897 if (ret) 1898 dev_err(&hdev->pdev->dev, 1899 "VF sends keep alive cmd failed(=%d)\n", ret); 1900 } 1901 1902 static void hclgevf_periodic_service_task(struct hclgevf_dev *hdev) 1903 { 1904 unsigned long delta = round_jiffies_relative(HZ); 1905 struct hnae3_handle *handle = &hdev->nic; 1906 1907 if (time_is_after_jiffies(hdev->last_serv_processed + HZ)) { 1908 delta = jiffies - hdev->last_serv_processed; 1909 1910 if (delta < round_jiffies_relative(HZ)) { 1911 delta = round_jiffies_relative(HZ) - delta; 1912 goto out; 1913 } 1914 } 1915 1916 hdev->serv_processed_cnt++; 1917 if (!(hdev->serv_processed_cnt % HCLGEVF_KEEP_ALIVE_TASK_INTERVAL)) 1918 hclgevf_keep_alive(hdev); 1919 1920 if (test_bit(HCLGEVF_STATE_DOWN, &hdev->state)) { 1921 hdev->last_serv_processed = jiffies; 1922 goto out; 1923 } 1924 1925 if (!(hdev->serv_processed_cnt % HCLGEVF_STATS_TIMER_INTERVAL)) 1926 hclgevf_tqps_update_stats(handle); 1927 1928 /* request the link status from the PF. PF would be able to tell VF 1929 * about such updates in future so we might remove this later 1930 */ 1931 hclgevf_request_link_info(hdev); 1932 1933 hclgevf_update_link_mode(hdev); 1934 1935 hclgevf_sync_vlan_filter(hdev); 1936 1937 hdev->last_serv_processed = jiffies; 1938 1939 out: 1940 hclgevf_task_schedule(hdev, delta); 1941 } 1942 1943 static void hclgevf_service_task(struct work_struct *work) 1944 { 1945 struct hclgevf_dev *hdev = container_of(work, struct hclgevf_dev, 1946 service_task.work); 1947 1948 hclgevf_reset_service_task(hdev); 1949 hclgevf_mailbox_service_task(hdev); 1950 hclgevf_periodic_service_task(hdev); 1951 1952 /* Handle reset and mbx again in case periodical task delays the 1953 * handling by calling hclgevf_task_schedule() in 1954 * hclgevf_periodic_service_task() 1955 */ 1956 hclgevf_reset_service_task(hdev); 1957 hclgevf_mailbox_service_task(hdev); 1958 } 1959 1960 static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regclr) 1961 { 1962 hclgevf_write_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_SRC_REG, regclr); 1963 } 1964 1965 static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev, 1966 u32 *clearval) 1967 { 1968 u32 val, cmdq_stat_reg, rst_ing_reg; 1969 1970 /* fetch the events from their corresponding regs */ 1971 cmdq_stat_reg = hclgevf_read_dev(&hdev->hw, 1972 HCLGEVF_VECTOR0_CMDQ_STAT_REG); 1973 1974 if (BIT(HCLGEVF_VECTOR0_RST_INT_B) & cmdq_stat_reg) { 1975 rst_ing_reg = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 1976 dev_info(&hdev->pdev->dev, 1977 "receive reset interrupt 0x%x!\n", rst_ing_reg); 1978 set_bit(HNAE3_VF_RESET, &hdev->reset_pending); 1979 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1980 set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 1981 *clearval = ~(1U << HCLGEVF_VECTOR0_RST_INT_B); 1982 hdev->rst_stats.vf_rst_cnt++; 1983 /* set up VF hardware reset status, its PF will clear 1984 * this status when PF has initialized done. 1985 */ 1986 val = hclgevf_read_dev(&hdev->hw, HCLGEVF_VF_RST_ING); 1987 hclgevf_write_dev(&hdev->hw, HCLGEVF_VF_RST_ING, 1988 val | HCLGEVF_VF_RST_ING_BIT); 1989 return HCLGEVF_VECTOR0_EVENT_RST; 1990 } 1991 1992 /* check for vector0 mailbox(=CMDQ RX) event source */ 1993 if (BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) { 1994 /* for revision 0x21, clearing interrupt is writing bit 0 1995 * to the clear register, writing bit 1 means to keep the 1996 * old value. 1997 * for revision 0x20, the clear register is a read & write 1998 * register, so we should just write 0 to the bit we are 1999 * handling, and keep other bits as cmdq_stat_reg. 2000 */ 2001 if (hdev->pdev->revision >= 0x21) 2002 *clearval = ~(1U << HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 2003 else 2004 *clearval = cmdq_stat_reg & 2005 ~BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 2006 2007 return HCLGEVF_VECTOR0_EVENT_MBX; 2008 } 2009 2010 dev_dbg(&hdev->pdev->dev, "vector 0 interrupt from unknown source\n"); 2011 2012 return HCLGEVF_VECTOR0_EVENT_OTHER; 2013 } 2014 2015 static void hclgevf_enable_vector(struct hclgevf_misc_vector *vector, bool en) 2016 { 2017 writel(en ? 1 : 0, vector->addr); 2018 } 2019 2020 static irqreturn_t hclgevf_misc_irq_handle(int irq, void *data) 2021 { 2022 enum hclgevf_evt_cause event_cause; 2023 struct hclgevf_dev *hdev = data; 2024 u32 clearval; 2025 2026 hclgevf_enable_vector(&hdev->misc_vector, false); 2027 event_cause = hclgevf_check_evt_cause(hdev, &clearval); 2028 2029 switch (event_cause) { 2030 case HCLGEVF_VECTOR0_EVENT_RST: 2031 hclgevf_reset_task_schedule(hdev); 2032 break; 2033 case HCLGEVF_VECTOR0_EVENT_MBX: 2034 hclgevf_mbx_handler(hdev); 2035 break; 2036 default: 2037 break; 2038 } 2039 2040 if (event_cause != HCLGEVF_VECTOR0_EVENT_OTHER) { 2041 hclgevf_clear_event_cause(hdev, clearval); 2042 hclgevf_enable_vector(&hdev->misc_vector, true); 2043 } 2044 2045 return IRQ_HANDLED; 2046 } 2047 2048 static int hclgevf_configure(struct hclgevf_dev *hdev) 2049 { 2050 int ret; 2051 2052 /* get current port based vlan state from PF */ 2053 ret = hclgevf_get_port_base_vlan_filter_state(hdev); 2054 if (ret) 2055 return ret; 2056 2057 /* get queue configuration from PF */ 2058 ret = hclgevf_get_queue_info(hdev); 2059 if (ret) 2060 return ret; 2061 2062 /* get queue depth info from PF */ 2063 ret = hclgevf_get_queue_depth(hdev); 2064 if (ret) 2065 return ret; 2066 2067 ret = hclgevf_get_pf_media_type(hdev); 2068 if (ret) 2069 return ret; 2070 2071 /* get tc configuration from PF */ 2072 return hclgevf_get_tc_info(hdev); 2073 } 2074 2075 static int hclgevf_alloc_hdev(struct hnae3_ae_dev *ae_dev) 2076 { 2077 struct pci_dev *pdev = ae_dev->pdev; 2078 struct hclgevf_dev *hdev; 2079 2080 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 2081 if (!hdev) 2082 return -ENOMEM; 2083 2084 hdev->pdev = pdev; 2085 hdev->ae_dev = ae_dev; 2086 ae_dev->priv = hdev; 2087 2088 return 0; 2089 } 2090 2091 static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev) 2092 { 2093 struct hnae3_handle *roce = &hdev->roce; 2094 struct hnae3_handle *nic = &hdev->nic; 2095 2096 roce->rinfo.num_vectors = hdev->num_roce_msix; 2097 2098 if (hdev->num_msi_left < roce->rinfo.num_vectors || 2099 hdev->num_msi_left == 0) 2100 return -EINVAL; 2101 2102 roce->rinfo.base_vector = hdev->roce_base_vector; 2103 2104 roce->rinfo.netdev = nic->kinfo.netdev; 2105 roce->rinfo.roce_io_base = hdev->hw.io_base; 2106 2107 roce->pdev = nic->pdev; 2108 roce->ae_algo = nic->ae_algo; 2109 roce->numa_node_mask = nic->numa_node_mask; 2110 2111 return 0; 2112 } 2113 2114 static int hclgevf_config_gro(struct hclgevf_dev *hdev, bool en) 2115 { 2116 struct hclgevf_cfg_gro_status_cmd *req; 2117 struct hclgevf_desc desc; 2118 int ret; 2119 2120 if (!hnae3_dev_gro_supported(hdev)) 2121 return 0; 2122 2123 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_GRO_GENERIC_CONFIG, 2124 false); 2125 req = (struct hclgevf_cfg_gro_status_cmd *)desc.data; 2126 2127 req->gro_en = cpu_to_le16(en ? 1 : 0); 2128 2129 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 2130 if (ret) 2131 dev_err(&hdev->pdev->dev, 2132 "VF GRO hardware config cmd failed, ret = %d.\n", ret); 2133 2134 return ret; 2135 } 2136 2137 static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev) 2138 { 2139 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 2140 int ret; 2141 u32 i; 2142 2143 rss_cfg->rss_size = hdev->nic.kinfo.rss_size; 2144 2145 if (hdev->pdev->revision >= 0x21) { 2146 rss_cfg->hash_algo = HCLGEVF_RSS_HASH_ALGO_SIMPLE; 2147 memcpy(rss_cfg->rss_hash_key, hclgevf_hash_key, 2148 HCLGEVF_RSS_KEY_SIZE); 2149 2150 ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 2151 rss_cfg->rss_hash_key); 2152 if (ret) 2153 return ret; 2154 2155 rss_cfg->rss_tuple_sets.ipv4_tcp_en = 2156 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2157 rss_cfg->rss_tuple_sets.ipv4_udp_en = 2158 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2159 rss_cfg->rss_tuple_sets.ipv4_sctp_en = 2160 HCLGEVF_RSS_INPUT_TUPLE_SCTP; 2161 rss_cfg->rss_tuple_sets.ipv4_fragment_en = 2162 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2163 rss_cfg->rss_tuple_sets.ipv6_tcp_en = 2164 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2165 rss_cfg->rss_tuple_sets.ipv6_udp_en = 2166 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2167 rss_cfg->rss_tuple_sets.ipv6_sctp_en = 2168 HCLGEVF_RSS_INPUT_TUPLE_SCTP; 2169 rss_cfg->rss_tuple_sets.ipv6_fragment_en = 2170 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2171 2172 ret = hclgevf_set_rss_input_tuple(hdev, rss_cfg); 2173 if (ret) 2174 return ret; 2175 } 2176 2177 /* Initialize RSS indirect table */ 2178 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 2179 rss_cfg->rss_indirection_tbl[i] = i % rss_cfg->rss_size; 2180 2181 ret = hclgevf_set_rss_indir_table(hdev); 2182 if (ret) 2183 return ret; 2184 2185 return hclgevf_set_rss_tc_mode(hdev, rss_cfg->rss_size); 2186 } 2187 2188 static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev) 2189 { 2190 return hclgevf_set_vlan_filter(&hdev->nic, htons(ETH_P_8021Q), 0, 2191 false); 2192 } 2193 2194 static void hclgevf_flush_link_update(struct hclgevf_dev *hdev) 2195 { 2196 #define HCLGEVF_FLUSH_LINK_TIMEOUT 100000 2197 2198 unsigned long last = hdev->serv_processed_cnt; 2199 int i = 0; 2200 2201 while (test_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state) && 2202 i++ < HCLGEVF_FLUSH_LINK_TIMEOUT && 2203 last == hdev->serv_processed_cnt) 2204 usleep_range(1, 1); 2205 } 2206 2207 static void hclgevf_set_timer_task(struct hnae3_handle *handle, bool enable) 2208 { 2209 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2210 2211 if (enable) { 2212 hclgevf_task_schedule(hdev, 0); 2213 } else { 2214 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2215 2216 /* flush memory to make sure DOWN is seen by service task */ 2217 smp_mb__before_atomic(); 2218 hclgevf_flush_link_update(hdev); 2219 } 2220 } 2221 2222 static int hclgevf_ae_start(struct hnae3_handle *handle) 2223 { 2224 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2225 2226 hclgevf_reset_tqp_stats(handle); 2227 2228 hclgevf_request_link_info(hdev); 2229 2230 hclgevf_update_link_mode(hdev); 2231 2232 clear_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2233 2234 return 0; 2235 } 2236 2237 static void hclgevf_ae_stop(struct hnae3_handle *handle) 2238 { 2239 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2240 int i; 2241 2242 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2243 2244 if (hdev->reset_type != HNAE3_VF_RESET) 2245 for (i = 0; i < handle->kinfo.num_tqps; i++) 2246 if (hclgevf_reset_tqp(handle, i)) 2247 break; 2248 2249 hclgevf_reset_tqp_stats(handle); 2250 hclgevf_update_link_status(hdev, 0); 2251 } 2252 2253 static int hclgevf_set_alive(struct hnae3_handle *handle, bool alive) 2254 { 2255 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2256 u8 msg_data; 2257 2258 msg_data = alive ? 1 : 0; 2259 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_ALIVE, 2260 0, &msg_data, 1, false, NULL, 0); 2261 } 2262 2263 static int hclgevf_client_start(struct hnae3_handle *handle) 2264 { 2265 int ret; 2266 2267 ret = hclgevf_set_alive(handle, true); 2268 if (ret) 2269 return ret; 2270 2271 return 0; 2272 } 2273 2274 static void hclgevf_client_stop(struct hnae3_handle *handle) 2275 { 2276 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2277 int ret; 2278 2279 ret = hclgevf_set_alive(handle, false); 2280 if (ret) 2281 dev_warn(&hdev->pdev->dev, 2282 "%s failed %d\n", __func__, ret); 2283 } 2284 2285 static void hclgevf_state_init(struct hclgevf_dev *hdev) 2286 { 2287 clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 2288 clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 2289 clear_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state); 2290 2291 INIT_DELAYED_WORK(&hdev->service_task, hclgevf_service_task); 2292 2293 mutex_init(&hdev->mbx_resp.mbx_mutex); 2294 2295 /* bring the device down */ 2296 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2297 } 2298 2299 static void hclgevf_state_uninit(struct hclgevf_dev *hdev) 2300 { 2301 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2302 set_bit(HCLGEVF_STATE_REMOVING, &hdev->state); 2303 2304 if (hdev->service_task.work.func) 2305 cancel_delayed_work_sync(&hdev->service_task); 2306 2307 mutex_destroy(&hdev->mbx_resp.mbx_mutex); 2308 } 2309 2310 static int hclgevf_init_msi(struct hclgevf_dev *hdev) 2311 { 2312 struct pci_dev *pdev = hdev->pdev; 2313 int vectors; 2314 int i; 2315 2316 if (hnae3_dev_roce_supported(hdev)) 2317 vectors = pci_alloc_irq_vectors(pdev, 2318 hdev->roce_base_msix_offset + 1, 2319 hdev->num_msi, 2320 PCI_IRQ_MSIX); 2321 else 2322 vectors = pci_alloc_irq_vectors(pdev, HNAE3_MIN_VECTOR_NUM, 2323 hdev->num_msi, 2324 PCI_IRQ_MSI | PCI_IRQ_MSIX); 2325 2326 if (vectors < 0) { 2327 dev_err(&pdev->dev, 2328 "failed(%d) to allocate MSI/MSI-X vectors\n", 2329 vectors); 2330 return vectors; 2331 } 2332 if (vectors < hdev->num_msi) 2333 dev_warn(&hdev->pdev->dev, 2334 "requested %u MSI/MSI-X, but allocated %d MSI/MSI-X\n", 2335 hdev->num_msi, vectors); 2336 2337 hdev->num_msi = vectors; 2338 hdev->num_msi_left = vectors; 2339 2340 hdev->base_msi_vector = pdev->irq; 2341 hdev->roce_base_vector = pdev->irq + hdev->roce_base_msix_offset; 2342 2343 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 2344 sizeof(u16), GFP_KERNEL); 2345 if (!hdev->vector_status) { 2346 pci_free_irq_vectors(pdev); 2347 return -ENOMEM; 2348 } 2349 2350 for (i = 0; i < hdev->num_msi; i++) 2351 hdev->vector_status[i] = HCLGEVF_INVALID_VPORT; 2352 2353 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 2354 sizeof(int), GFP_KERNEL); 2355 if (!hdev->vector_irq) { 2356 devm_kfree(&pdev->dev, hdev->vector_status); 2357 pci_free_irq_vectors(pdev); 2358 return -ENOMEM; 2359 } 2360 2361 return 0; 2362 } 2363 2364 static void hclgevf_uninit_msi(struct hclgevf_dev *hdev) 2365 { 2366 struct pci_dev *pdev = hdev->pdev; 2367 2368 devm_kfree(&pdev->dev, hdev->vector_status); 2369 devm_kfree(&pdev->dev, hdev->vector_irq); 2370 pci_free_irq_vectors(pdev); 2371 } 2372 2373 static int hclgevf_misc_irq_init(struct hclgevf_dev *hdev) 2374 { 2375 int ret; 2376 2377 hclgevf_get_misc_vector(hdev); 2378 2379 ret = request_irq(hdev->misc_vector.vector_irq, hclgevf_misc_irq_handle, 2380 0, "hclgevf_cmd", hdev); 2381 if (ret) { 2382 dev_err(&hdev->pdev->dev, "VF failed to request misc irq(%d)\n", 2383 hdev->misc_vector.vector_irq); 2384 return ret; 2385 } 2386 2387 hclgevf_clear_event_cause(hdev, 0); 2388 2389 /* enable misc. vector(vector 0) */ 2390 hclgevf_enable_vector(&hdev->misc_vector, true); 2391 2392 return ret; 2393 } 2394 2395 static void hclgevf_misc_irq_uninit(struct hclgevf_dev *hdev) 2396 { 2397 /* disable misc vector(vector 0) */ 2398 hclgevf_enable_vector(&hdev->misc_vector, false); 2399 synchronize_irq(hdev->misc_vector.vector_irq); 2400 free_irq(hdev->misc_vector.vector_irq, hdev); 2401 hclgevf_free_vector(hdev, 0); 2402 } 2403 2404 static void hclgevf_info_show(struct hclgevf_dev *hdev) 2405 { 2406 struct device *dev = &hdev->pdev->dev; 2407 2408 dev_info(dev, "VF info begin:\n"); 2409 2410 dev_info(dev, "Task queue pairs numbers: %u\n", hdev->num_tqps); 2411 dev_info(dev, "Desc num per TX queue: %u\n", hdev->num_tx_desc); 2412 dev_info(dev, "Desc num per RX queue: %u\n", hdev->num_rx_desc); 2413 dev_info(dev, "Numbers of vports: %u\n", hdev->num_alloc_vport); 2414 dev_info(dev, "HW tc map: 0x%x\n", hdev->hw_tc_map); 2415 dev_info(dev, "PF media type of this VF: %u\n", 2416 hdev->hw.mac.media_type); 2417 2418 dev_info(dev, "VF info end.\n"); 2419 } 2420 2421 static int hclgevf_init_nic_client_instance(struct hnae3_ae_dev *ae_dev, 2422 struct hnae3_client *client) 2423 { 2424 struct hclgevf_dev *hdev = ae_dev->priv; 2425 int ret; 2426 2427 ret = client->ops->init_instance(&hdev->nic); 2428 if (ret) 2429 return ret; 2430 2431 set_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 2432 hnae3_set_client_init_flag(client, ae_dev, 1); 2433 2434 if (netif_msg_drv(&hdev->nic)) 2435 hclgevf_info_show(hdev); 2436 2437 return 0; 2438 } 2439 2440 static int hclgevf_init_roce_client_instance(struct hnae3_ae_dev *ae_dev, 2441 struct hnae3_client *client) 2442 { 2443 struct hclgevf_dev *hdev = ae_dev->priv; 2444 int ret; 2445 2446 if (!hnae3_dev_roce_supported(hdev) || !hdev->roce_client || 2447 !hdev->nic_client) 2448 return 0; 2449 2450 ret = hclgevf_init_roce_base_info(hdev); 2451 if (ret) 2452 return ret; 2453 2454 ret = client->ops->init_instance(&hdev->roce); 2455 if (ret) 2456 return ret; 2457 2458 hnae3_set_client_init_flag(client, ae_dev, 1); 2459 2460 return 0; 2461 } 2462 2463 static int hclgevf_init_client_instance(struct hnae3_client *client, 2464 struct hnae3_ae_dev *ae_dev) 2465 { 2466 struct hclgevf_dev *hdev = ae_dev->priv; 2467 int ret; 2468 2469 switch (client->type) { 2470 case HNAE3_CLIENT_KNIC: 2471 hdev->nic_client = client; 2472 hdev->nic.client = client; 2473 2474 ret = hclgevf_init_nic_client_instance(ae_dev, client); 2475 if (ret) 2476 goto clear_nic; 2477 2478 ret = hclgevf_init_roce_client_instance(ae_dev, 2479 hdev->roce_client); 2480 if (ret) 2481 goto clear_roce; 2482 2483 break; 2484 case HNAE3_CLIENT_ROCE: 2485 if (hnae3_dev_roce_supported(hdev)) { 2486 hdev->roce_client = client; 2487 hdev->roce.client = client; 2488 } 2489 2490 ret = hclgevf_init_roce_client_instance(ae_dev, client); 2491 if (ret) 2492 goto clear_roce; 2493 2494 break; 2495 default: 2496 return -EINVAL; 2497 } 2498 2499 return 0; 2500 2501 clear_nic: 2502 hdev->nic_client = NULL; 2503 hdev->nic.client = NULL; 2504 return ret; 2505 clear_roce: 2506 hdev->roce_client = NULL; 2507 hdev->roce.client = NULL; 2508 return ret; 2509 } 2510 2511 static void hclgevf_uninit_client_instance(struct hnae3_client *client, 2512 struct hnae3_ae_dev *ae_dev) 2513 { 2514 struct hclgevf_dev *hdev = ae_dev->priv; 2515 2516 /* un-init roce, if it exists */ 2517 if (hdev->roce_client) { 2518 hdev->roce_client->ops->uninit_instance(&hdev->roce, 0); 2519 hdev->roce_client = NULL; 2520 hdev->roce.client = NULL; 2521 } 2522 2523 /* un-init nic/unic, if this was not called by roce client */ 2524 if (client->ops->uninit_instance && hdev->nic_client && 2525 client->type != HNAE3_CLIENT_ROCE) { 2526 clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 2527 2528 client->ops->uninit_instance(&hdev->nic, 0); 2529 hdev->nic_client = NULL; 2530 hdev->nic.client = NULL; 2531 } 2532 } 2533 2534 static int hclgevf_pci_init(struct hclgevf_dev *hdev) 2535 { 2536 struct pci_dev *pdev = hdev->pdev; 2537 struct hclgevf_hw *hw; 2538 int ret; 2539 2540 ret = pci_enable_device(pdev); 2541 if (ret) { 2542 dev_err(&pdev->dev, "failed to enable PCI device\n"); 2543 return ret; 2544 } 2545 2546 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 2547 if (ret) { 2548 dev_err(&pdev->dev, "can't set consistent PCI DMA, exiting"); 2549 goto err_disable_device; 2550 } 2551 2552 ret = pci_request_regions(pdev, HCLGEVF_DRIVER_NAME); 2553 if (ret) { 2554 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 2555 goto err_disable_device; 2556 } 2557 2558 pci_set_master(pdev); 2559 hw = &hdev->hw; 2560 hw->hdev = hdev; 2561 hw->io_base = pci_iomap(pdev, 2, 0); 2562 if (!hw->io_base) { 2563 dev_err(&pdev->dev, "can't map configuration register space\n"); 2564 ret = -ENOMEM; 2565 goto err_clr_master; 2566 } 2567 2568 return 0; 2569 2570 err_clr_master: 2571 pci_clear_master(pdev); 2572 pci_release_regions(pdev); 2573 err_disable_device: 2574 pci_disable_device(pdev); 2575 2576 return ret; 2577 } 2578 2579 static void hclgevf_pci_uninit(struct hclgevf_dev *hdev) 2580 { 2581 struct pci_dev *pdev = hdev->pdev; 2582 2583 pci_iounmap(pdev, hdev->hw.io_base); 2584 pci_clear_master(pdev); 2585 pci_release_regions(pdev); 2586 pci_disable_device(pdev); 2587 } 2588 2589 static int hclgevf_query_vf_resource(struct hclgevf_dev *hdev) 2590 { 2591 struct hclgevf_query_res_cmd *req; 2592 struct hclgevf_desc desc; 2593 int ret; 2594 2595 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_VF_RSRC, true); 2596 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 2597 if (ret) { 2598 dev_err(&hdev->pdev->dev, 2599 "query vf resource failed, ret = %d.\n", ret); 2600 return ret; 2601 } 2602 2603 req = (struct hclgevf_query_res_cmd *)desc.data; 2604 2605 if (hnae3_dev_roce_supported(hdev)) { 2606 hdev->roce_base_msix_offset = 2607 hnae3_get_field(__le16_to_cpu(req->msixcap_localid_ba_rocee), 2608 HCLGEVF_MSIX_OFT_ROCEE_M, 2609 HCLGEVF_MSIX_OFT_ROCEE_S); 2610 hdev->num_roce_msix = 2611 hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number), 2612 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 2613 2614 /* nic's msix numbers is always equals to the roce's. */ 2615 hdev->num_nic_msix = hdev->num_roce_msix; 2616 2617 /* VF should have NIC vectors and Roce vectors, NIC vectors 2618 * are queued before Roce vectors. The offset is fixed to 64. 2619 */ 2620 hdev->num_msi = hdev->num_roce_msix + 2621 hdev->roce_base_msix_offset; 2622 } else { 2623 hdev->num_msi = 2624 hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number), 2625 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 2626 2627 hdev->num_nic_msix = hdev->num_msi; 2628 } 2629 2630 if (hdev->num_nic_msix < HNAE3_MIN_VECTOR_NUM) { 2631 dev_err(&hdev->pdev->dev, 2632 "Just %u msi resources, not enough for vf(min:2).\n", 2633 hdev->num_nic_msix); 2634 return -EINVAL; 2635 } 2636 2637 return 0; 2638 } 2639 2640 static int hclgevf_pci_reset(struct hclgevf_dev *hdev) 2641 { 2642 struct pci_dev *pdev = hdev->pdev; 2643 int ret = 0; 2644 2645 if (hdev->reset_type == HNAE3_VF_FULL_RESET && 2646 test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2647 hclgevf_misc_irq_uninit(hdev); 2648 hclgevf_uninit_msi(hdev); 2649 clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2650 } 2651 2652 if (!test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2653 pci_set_master(pdev); 2654 ret = hclgevf_init_msi(hdev); 2655 if (ret) { 2656 dev_err(&pdev->dev, 2657 "failed(%d) to init MSI/MSI-X\n", ret); 2658 return ret; 2659 } 2660 2661 ret = hclgevf_misc_irq_init(hdev); 2662 if (ret) { 2663 hclgevf_uninit_msi(hdev); 2664 dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 2665 ret); 2666 return ret; 2667 } 2668 2669 set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2670 } 2671 2672 return ret; 2673 } 2674 2675 static int hclgevf_reset_hdev(struct hclgevf_dev *hdev) 2676 { 2677 struct pci_dev *pdev = hdev->pdev; 2678 int ret; 2679 2680 ret = hclgevf_pci_reset(hdev); 2681 if (ret) { 2682 dev_err(&pdev->dev, "pci reset failed %d\n", ret); 2683 return ret; 2684 } 2685 2686 ret = hclgevf_cmd_init(hdev); 2687 if (ret) { 2688 dev_err(&pdev->dev, "cmd failed %d\n", ret); 2689 return ret; 2690 } 2691 2692 ret = hclgevf_rss_init_hw(hdev); 2693 if (ret) { 2694 dev_err(&hdev->pdev->dev, 2695 "failed(%d) to initialize RSS\n", ret); 2696 return ret; 2697 } 2698 2699 ret = hclgevf_config_gro(hdev, true); 2700 if (ret) 2701 return ret; 2702 2703 ret = hclgevf_init_vlan_config(hdev); 2704 if (ret) { 2705 dev_err(&hdev->pdev->dev, 2706 "failed(%d) to initialize VLAN config\n", ret); 2707 return ret; 2708 } 2709 2710 dev_info(&hdev->pdev->dev, "Reset done\n"); 2711 2712 return 0; 2713 } 2714 2715 static int hclgevf_init_hdev(struct hclgevf_dev *hdev) 2716 { 2717 struct pci_dev *pdev = hdev->pdev; 2718 int ret; 2719 2720 ret = hclgevf_pci_init(hdev); 2721 if (ret) { 2722 dev_err(&pdev->dev, "PCI initialization failed\n"); 2723 return ret; 2724 } 2725 2726 ret = hclgevf_cmd_queue_init(hdev); 2727 if (ret) { 2728 dev_err(&pdev->dev, "Cmd queue init failed: %d\n", ret); 2729 goto err_cmd_queue_init; 2730 } 2731 2732 ret = hclgevf_cmd_init(hdev); 2733 if (ret) 2734 goto err_cmd_init; 2735 2736 /* Get vf resource */ 2737 ret = hclgevf_query_vf_resource(hdev); 2738 if (ret) { 2739 dev_err(&hdev->pdev->dev, 2740 "Query vf status error, ret = %d.\n", ret); 2741 goto err_cmd_init; 2742 } 2743 2744 ret = hclgevf_init_msi(hdev); 2745 if (ret) { 2746 dev_err(&pdev->dev, "failed(%d) to init MSI/MSI-X\n", ret); 2747 goto err_cmd_init; 2748 } 2749 2750 hclgevf_state_init(hdev); 2751 hdev->reset_level = HNAE3_VF_FUNC_RESET; 2752 2753 ret = hclgevf_misc_irq_init(hdev); 2754 if (ret) { 2755 dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 2756 ret); 2757 goto err_misc_irq_init; 2758 } 2759 2760 set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2761 2762 ret = hclgevf_configure(hdev); 2763 if (ret) { 2764 dev_err(&pdev->dev, "failed(%d) to fetch configuration\n", ret); 2765 goto err_config; 2766 } 2767 2768 ret = hclgevf_alloc_tqps(hdev); 2769 if (ret) { 2770 dev_err(&pdev->dev, "failed(%d) to allocate TQPs\n", ret); 2771 goto err_config; 2772 } 2773 2774 ret = hclgevf_set_handle_info(hdev); 2775 if (ret) { 2776 dev_err(&pdev->dev, "failed(%d) to set handle info\n", ret); 2777 goto err_config; 2778 } 2779 2780 ret = hclgevf_config_gro(hdev, true); 2781 if (ret) 2782 goto err_config; 2783 2784 /* Initialize RSS for this VF */ 2785 ret = hclgevf_rss_init_hw(hdev); 2786 if (ret) { 2787 dev_err(&hdev->pdev->dev, 2788 "failed(%d) to initialize RSS\n", ret); 2789 goto err_config; 2790 } 2791 2792 ret = hclgevf_init_vlan_config(hdev); 2793 if (ret) { 2794 dev_err(&hdev->pdev->dev, 2795 "failed(%d) to initialize VLAN config\n", ret); 2796 goto err_config; 2797 } 2798 2799 hdev->last_reset_time = jiffies; 2800 dev_info(&hdev->pdev->dev, "finished initializing %s driver\n", 2801 HCLGEVF_DRIVER_NAME); 2802 2803 hclgevf_task_schedule(hdev, round_jiffies_relative(HZ)); 2804 2805 return 0; 2806 2807 err_config: 2808 hclgevf_misc_irq_uninit(hdev); 2809 err_misc_irq_init: 2810 hclgevf_state_uninit(hdev); 2811 hclgevf_uninit_msi(hdev); 2812 err_cmd_init: 2813 hclgevf_cmd_uninit(hdev); 2814 err_cmd_queue_init: 2815 hclgevf_pci_uninit(hdev); 2816 clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2817 return ret; 2818 } 2819 2820 static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev) 2821 { 2822 hclgevf_state_uninit(hdev); 2823 2824 if (test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2825 hclgevf_misc_irq_uninit(hdev); 2826 hclgevf_uninit_msi(hdev); 2827 } 2828 2829 hclgevf_pci_uninit(hdev); 2830 hclgevf_cmd_uninit(hdev); 2831 } 2832 2833 static int hclgevf_init_ae_dev(struct hnae3_ae_dev *ae_dev) 2834 { 2835 struct pci_dev *pdev = ae_dev->pdev; 2836 int ret; 2837 2838 ret = hclgevf_alloc_hdev(ae_dev); 2839 if (ret) { 2840 dev_err(&pdev->dev, "hclge device allocation failed\n"); 2841 return ret; 2842 } 2843 2844 ret = hclgevf_init_hdev(ae_dev->priv); 2845 if (ret) { 2846 dev_err(&pdev->dev, "hclge device initialization failed\n"); 2847 return ret; 2848 } 2849 2850 return 0; 2851 } 2852 2853 static void hclgevf_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 2854 { 2855 struct hclgevf_dev *hdev = ae_dev->priv; 2856 2857 hclgevf_uninit_hdev(hdev); 2858 ae_dev->priv = NULL; 2859 } 2860 2861 static u32 hclgevf_get_max_channels(struct hclgevf_dev *hdev) 2862 { 2863 struct hnae3_handle *nic = &hdev->nic; 2864 struct hnae3_knic_private_info *kinfo = &nic->kinfo; 2865 2866 return min_t(u32, hdev->rss_size_max, 2867 hdev->num_tqps / kinfo->num_tc); 2868 } 2869 2870 /** 2871 * hclgevf_get_channels - Get the current channels enabled and max supported. 2872 * @handle: hardware information for network interface 2873 * @ch: ethtool channels structure 2874 * 2875 * We don't support separate tx and rx queues as channels. The other count 2876 * represents how many queues are being used for control. max_combined counts 2877 * how many queue pairs we can support. They may not be mapped 1 to 1 with 2878 * q_vectors since we support a lot more queue pairs than q_vectors. 2879 **/ 2880 static void hclgevf_get_channels(struct hnae3_handle *handle, 2881 struct ethtool_channels *ch) 2882 { 2883 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2884 2885 ch->max_combined = hclgevf_get_max_channels(hdev); 2886 ch->other_count = 0; 2887 ch->max_other = 0; 2888 ch->combined_count = handle->kinfo.rss_size; 2889 } 2890 2891 static void hclgevf_get_tqps_and_rss_info(struct hnae3_handle *handle, 2892 u16 *alloc_tqps, u16 *max_rss_size) 2893 { 2894 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2895 2896 *alloc_tqps = hdev->num_tqps; 2897 *max_rss_size = hdev->rss_size_max; 2898 } 2899 2900 static void hclgevf_update_rss_size(struct hnae3_handle *handle, 2901 u32 new_tqps_num) 2902 { 2903 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 2904 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2905 u16 max_rss_size; 2906 2907 kinfo->req_rss_size = new_tqps_num; 2908 2909 max_rss_size = min_t(u16, hdev->rss_size_max, 2910 hdev->num_tqps / kinfo->num_tc); 2911 2912 /* Use the user's configuration when it is not larger than 2913 * max_rss_size, otherwise, use the maximum specification value. 2914 */ 2915 if (kinfo->req_rss_size != kinfo->rss_size && kinfo->req_rss_size && 2916 kinfo->req_rss_size <= max_rss_size) 2917 kinfo->rss_size = kinfo->req_rss_size; 2918 else if (kinfo->rss_size > max_rss_size || 2919 (!kinfo->req_rss_size && kinfo->rss_size < max_rss_size)) 2920 kinfo->rss_size = max_rss_size; 2921 2922 kinfo->num_tqps = kinfo->num_tc * kinfo->rss_size; 2923 } 2924 2925 static int hclgevf_set_channels(struct hnae3_handle *handle, u32 new_tqps_num, 2926 bool rxfh_configured) 2927 { 2928 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2929 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 2930 u16 cur_rss_size = kinfo->rss_size; 2931 u16 cur_tqps = kinfo->num_tqps; 2932 u32 *rss_indir; 2933 unsigned int i; 2934 int ret; 2935 2936 hclgevf_update_rss_size(handle, new_tqps_num); 2937 2938 ret = hclgevf_set_rss_tc_mode(hdev, kinfo->rss_size); 2939 if (ret) 2940 return ret; 2941 2942 /* RSS indirection table has been configuared by user */ 2943 if (rxfh_configured) 2944 goto out; 2945 2946 /* Reinitializes the rss indirect table according to the new RSS size */ 2947 rss_indir = kcalloc(HCLGEVF_RSS_IND_TBL_SIZE, sizeof(u32), GFP_KERNEL); 2948 if (!rss_indir) 2949 return -ENOMEM; 2950 2951 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 2952 rss_indir[i] = i % kinfo->rss_size; 2953 2954 ret = hclgevf_set_rss(handle, rss_indir, NULL, 0); 2955 if (ret) 2956 dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n", 2957 ret); 2958 2959 kfree(rss_indir); 2960 2961 out: 2962 if (!ret) 2963 dev_info(&hdev->pdev->dev, 2964 "Channels changed, rss_size from %u to %u, tqps from %u to %u", 2965 cur_rss_size, kinfo->rss_size, 2966 cur_tqps, kinfo->rss_size * kinfo->num_tc); 2967 2968 return ret; 2969 } 2970 2971 static int hclgevf_get_status(struct hnae3_handle *handle) 2972 { 2973 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2974 2975 return hdev->hw.mac.link; 2976 } 2977 2978 static void hclgevf_get_ksettings_an_result(struct hnae3_handle *handle, 2979 u8 *auto_neg, u32 *speed, 2980 u8 *duplex) 2981 { 2982 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2983 2984 if (speed) 2985 *speed = hdev->hw.mac.speed; 2986 if (duplex) 2987 *duplex = hdev->hw.mac.duplex; 2988 if (auto_neg) 2989 *auto_neg = AUTONEG_DISABLE; 2990 } 2991 2992 void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed, 2993 u8 duplex) 2994 { 2995 hdev->hw.mac.speed = speed; 2996 hdev->hw.mac.duplex = duplex; 2997 } 2998 2999 static int hclgevf_gro_en(struct hnae3_handle *handle, bool enable) 3000 { 3001 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3002 3003 return hclgevf_config_gro(hdev, enable); 3004 } 3005 3006 static void hclgevf_get_media_type(struct hnae3_handle *handle, u8 *media_type, 3007 u8 *module_type) 3008 { 3009 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3010 3011 if (media_type) 3012 *media_type = hdev->hw.mac.media_type; 3013 3014 if (module_type) 3015 *module_type = hdev->hw.mac.module_type; 3016 } 3017 3018 static bool hclgevf_get_hw_reset_stat(struct hnae3_handle *handle) 3019 { 3020 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3021 3022 return !!hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 3023 } 3024 3025 static bool hclgevf_ae_dev_resetting(struct hnae3_handle *handle) 3026 { 3027 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3028 3029 return test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 3030 } 3031 3032 static unsigned long hclgevf_ae_dev_reset_cnt(struct hnae3_handle *handle) 3033 { 3034 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3035 3036 return hdev->rst_stats.hw_rst_done_cnt; 3037 } 3038 3039 static void hclgevf_get_link_mode(struct hnae3_handle *handle, 3040 unsigned long *supported, 3041 unsigned long *advertising) 3042 { 3043 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3044 3045 *supported = hdev->hw.mac.supported; 3046 *advertising = hdev->hw.mac.advertising; 3047 } 3048 3049 #define MAX_SEPARATE_NUM 4 3050 #define SEPARATOR_VALUE 0xFFFFFFFF 3051 #define REG_NUM_PER_LINE 4 3052 #define REG_LEN_PER_LINE (REG_NUM_PER_LINE * sizeof(u32)) 3053 3054 static int hclgevf_get_regs_len(struct hnae3_handle *handle) 3055 { 3056 int cmdq_lines, common_lines, ring_lines, tqp_intr_lines; 3057 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3058 3059 cmdq_lines = sizeof(cmdq_reg_addr_list) / REG_LEN_PER_LINE + 1; 3060 common_lines = sizeof(common_reg_addr_list) / REG_LEN_PER_LINE + 1; 3061 ring_lines = sizeof(ring_reg_addr_list) / REG_LEN_PER_LINE + 1; 3062 tqp_intr_lines = sizeof(tqp_intr_reg_addr_list) / REG_LEN_PER_LINE + 1; 3063 3064 return (cmdq_lines + common_lines + ring_lines * hdev->num_tqps + 3065 tqp_intr_lines * (hdev->num_msi_used - 1)) * REG_LEN_PER_LINE; 3066 } 3067 3068 static void hclgevf_get_regs(struct hnae3_handle *handle, u32 *version, 3069 void *data) 3070 { 3071 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3072 int i, j, reg_um, separator_num; 3073 u32 *reg = data; 3074 3075 *version = hdev->fw_version; 3076 3077 /* fetching per-VF registers values from VF PCIe register space */ 3078 reg_um = sizeof(cmdq_reg_addr_list) / sizeof(u32); 3079 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 3080 for (i = 0; i < reg_um; i++) 3081 *reg++ = hclgevf_read_dev(&hdev->hw, cmdq_reg_addr_list[i]); 3082 for (i = 0; i < separator_num; i++) 3083 *reg++ = SEPARATOR_VALUE; 3084 3085 reg_um = sizeof(common_reg_addr_list) / sizeof(u32); 3086 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 3087 for (i = 0; i < reg_um; i++) 3088 *reg++ = hclgevf_read_dev(&hdev->hw, common_reg_addr_list[i]); 3089 for (i = 0; i < separator_num; i++) 3090 *reg++ = SEPARATOR_VALUE; 3091 3092 reg_um = sizeof(ring_reg_addr_list) / sizeof(u32); 3093 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 3094 for (j = 0; j < hdev->num_tqps; j++) { 3095 for (i = 0; i < reg_um; i++) 3096 *reg++ = hclgevf_read_dev(&hdev->hw, 3097 ring_reg_addr_list[i] + 3098 0x200 * j); 3099 for (i = 0; i < separator_num; i++) 3100 *reg++ = SEPARATOR_VALUE; 3101 } 3102 3103 reg_um = sizeof(tqp_intr_reg_addr_list) / sizeof(u32); 3104 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 3105 for (j = 0; j < hdev->num_msi_used - 1; j++) { 3106 for (i = 0; i < reg_um; i++) 3107 *reg++ = hclgevf_read_dev(&hdev->hw, 3108 tqp_intr_reg_addr_list[i] + 3109 4 * j); 3110 for (i = 0; i < separator_num; i++) 3111 *reg++ = SEPARATOR_VALUE; 3112 } 3113 } 3114 3115 void hclgevf_update_port_base_vlan_info(struct hclgevf_dev *hdev, u16 state, 3116 u8 *port_base_vlan_info, u8 data_size) 3117 { 3118 struct hnae3_handle *nic = &hdev->nic; 3119 3120 rtnl_lock(); 3121 hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 3122 rtnl_unlock(); 3123 3124 /* send msg to PF and wait update port based vlan info */ 3125 hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 3126 HCLGE_MBX_PORT_BASE_VLAN_CFG, 3127 port_base_vlan_info, data_size, 3128 false, NULL, 0); 3129 3130 if (state == HNAE3_PORT_BASE_VLAN_DISABLE) 3131 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_DISABLE; 3132 else 3133 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_ENABLE; 3134 3135 rtnl_lock(); 3136 hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 3137 rtnl_unlock(); 3138 } 3139 3140 static const struct hnae3_ae_ops hclgevf_ops = { 3141 .init_ae_dev = hclgevf_init_ae_dev, 3142 .uninit_ae_dev = hclgevf_uninit_ae_dev, 3143 .flr_prepare = hclgevf_flr_prepare, 3144 .flr_done = hclgevf_flr_done, 3145 .init_client_instance = hclgevf_init_client_instance, 3146 .uninit_client_instance = hclgevf_uninit_client_instance, 3147 .start = hclgevf_ae_start, 3148 .stop = hclgevf_ae_stop, 3149 .client_start = hclgevf_client_start, 3150 .client_stop = hclgevf_client_stop, 3151 .map_ring_to_vector = hclgevf_map_ring_to_vector, 3152 .unmap_ring_from_vector = hclgevf_unmap_ring_from_vector, 3153 .get_vector = hclgevf_get_vector, 3154 .put_vector = hclgevf_put_vector, 3155 .reset_queue = hclgevf_reset_tqp, 3156 .get_mac_addr = hclgevf_get_mac_addr, 3157 .set_mac_addr = hclgevf_set_mac_addr, 3158 .add_uc_addr = hclgevf_add_uc_addr, 3159 .rm_uc_addr = hclgevf_rm_uc_addr, 3160 .add_mc_addr = hclgevf_add_mc_addr, 3161 .rm_mc_addr = hclgevf_rm_mc_addr, 3162 .get_stats = hclgevf_get_stats, 3163 .update_stats = hclgevf_update_stats, 3164 .get_strings = hclgevf_get_strings, 3165 .get_sset_count = hclgevf_get_sset_count, 3166 .get_rss_key_size = hclgevf_get_rss_key_size, 3167 .get_rss_indir_size = hclgevf_get_rss_indir_size, 3168 .get_rss = hclgevf_get_rss, 3169 .set_rss = hclgevf_set_rss, 3170 .get_rss_tuple = hclgevf_get_rss_tuple, 3171 .set_rss_tuple = hclgevf_set_rss_tuple, 3172 .get_tc_size = hclgevf_get_tc_size, 3173 .get_fw_version = hclgevf_get_fw_version, 3174 .set_vlan_filter = hclgevf_set_vlan_filter, 3175 .enable_hw_strip_rxvtag = hclgevf_en_hw_strip_rxvtag, 3176 .reset_event = hclgevf_reset_event, 3177 .set_default_reset_request = hclgevf_set_def_reset_request, 3178 .set_channels = hclgevf_set_channels, 3179 .get_channels = hclgevf_get_channels, 3180 .get_tqps_and_rss_info = hclgevf_get_tqps_and_rss_info, 3181 .get_regs_len = hclgevf_get_regs_len, 3182 .get_regs = hclgevf_get_regs, 3183 .get_status = hclgevf_get_status, 3184 .get_ksettings_an_result = hclgevf_get_ksettings_an_result, 3185 .get_media_type = hclgevf_get_media_type, 3186 .get_hw_reset_stat = hclgevf_get_hw_reset_stat, 3187 .ae_dev_resetting = hclgevf_ae_dev_resetting, 3188 .ae_dev_reset_cnt = hclgevf_ae_dev_reset_cnt, 3189 .set_gro_en = hclgevf_gro_en, 3190 .set_mtu = hclgevf_set_mtu, 3191 .get_global_queue_id = hclgevf_get_qid_global, 3192 .set_timer_task = hclgevf_set_timer_task, 3193 .get_link_mode = hclgevf_get_link_mode, 3194 .set_promisc_mode = hclgevf_set_promisc_mode, 3195 }; 3196 3197 static struct hnae3_ae_algo ae_algovf = { 3198 .ops = &hclgevf_ops, 3199 .pdev_id_table = ae_algovf_pci_tbl, 3200 }; 3201 3202 static int hclgevf_init(void) 3203 { 3204 pr_info("%s is initializing\n", HCLGEVF_NAME); 3205 3206 hclgevf_wq = alloc_workqueue("%s", WQ_MEM_RECLAIM, 0, HCLGEVF_NAME); 3207 if (!hclgevf_wq) { 3208 pr_err("%s: failed to create workqueue\n", HCLGEVF_NAME); 3209 return -ENOMEM; 3210 } 3211 3212 hnae3_register_ae_algo(&ae_algovf); 3213 3214 return 0; 3215 } 3216 3217 static void hclgevf_exit(void) 3218 { 3219 hnae3_unregister_ae_algo(&ae_algovf); 3220 destroy_workqueue(hclgevf_wq); 3221 } 3222 module_init(hclgevf_init); 3223 module_exit(hclgevf_exit); 3224 3225 MODULE_LICENSE("GPL"); 3226 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 3227 MODULE_DESCRIPTION("HCLGEVF Driver"); 3228 MODULE_VERSION(HCLGEVF_MOD_VERSION); 3229