1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/etherdevice.h> 5 #include <linux/iopoll.h> 6 #include <net/rtnetlink.h> 7 #include "hclgevf_cmd.h" 8 #include "hclgevf_main.h" 9 #include "hclge_mbx.h" 10 #include "hnae3.h" 11 12 #define HCLGEVF_NAME "hclgevf" 13 14 static int hclgevf_reset_hdev(struct hclgevf_dev *hdev); 15 static struct hnae3_ae_algo ae_algovf; 16 17 static const struct pci_device_id ae_algovf_pci_tbl[] = { 18 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0}, 19 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF), 0}, 20 /* required last entry */ 21 {0, } 22 }; 23 24 static const u8 hclgevf_hash_key[] = { 25 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2, 26 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0, 27 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4, 28 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C, 29 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA 30 }; 31 32 MODULE_DEVICE_TABLE(pci, ae_algovf_pci_tbl); 33 34 static const u32 cmdq_reg_addr_list[] = {HCLGEVF_CMDQ_TX_ADDR_L_REG, 35 HCLGEVF_CMDQ_TX_ADDR_H_REG, 36 HCLGEVF_CMDQ_TX_DEPTH_REG, 37 HCLGEVF_CMDQ_TX_TAIL_REG, 38 HCLGEVF_CMDQ_TX_HEAD_REG, 39 HCLGEVF_CMDQ_RX_ADDR_L_REG, 40 HCLGEVF_CMDQ_RX_ADDR_H_REG, 41 HCLGEVF_CMDQ_RX_DEPTH_REG, 42 HCLGEVF_CMDQ_RX_TAIL_REG, 43 HCLGEVF_CMDQ_RX_HEAD_REG, 44 HCLGEVF_VECTOR0_CMDQ_SRC_REG, 45 HCLGEVF_CMDQ_INTR_STS_REG, 46 HCLGEVF_CMDQ_INTR_EN_REG, 47 HCLGEVF_CMDQ_INTR_GEN_REG}; 48 49 static const u32 common_reg_addr_list[] = {HCLGEVF_MISC_VECTOR_REG_BASE, 50 HCLGEVF_RST_ING, 51 HCLGEVF_GRO_EN_REG}; 52 53 static const u32 ring_reg_addr_list[] = {HCLGEVF_RING_RX_ADDR_L_REG, 54 HCLGEVF_RING_RX_ADDR_H_REG, 55 HCLGEVF_RING_RX_BD_NUM_REG, 56 HCLGEVF_RING_RX_BD_LENGTH_REG, 57 HCLGEVF_RING_RX_MERGE_EN_REG, 58 HCLGEVF_RING_RX_TAIL_REG, 59 HCLGEVF_RING_RX_HEAD_REG, 60 HCLGEVF_RING_RX_FBD_NUM_REG, 61 HCLGEVF_RING_RX_OFFSET_REG, 62 HCLGEVF_RING_RX_FBD_OFFSET_REG, 63 HCLGEVF_RING_RX_STASH_REG, 64 HCLGEVF_RING_RX_BD_ERR_REG, 65 HCLGEVF_RING_TX_ADDR_L_REG, 66 HCLGEVF_RING_TX_ADDR_H_REG, 67 HCLGEVF_RING_TX_BD_NUM_REG, 68 HCLGEVF_RING_TX_PRIORITY_REG, 69 HCLGEVF_RING_TX_TC_REG, 70 HCLGEVF_RING_TX_MERGE_EN_REG, 71 HCLGEVF_RING_TX_TAIL_REG, 72 HCLGEVF_RING_TX_HEAD_REG, 73 HCLGEVF_RING_TX_FBD_NUM_REG, 74 HCLGEVF_RING_TX_OFFSET_REG, 75 HCLGEVF_RING_TX_EBD_NUM_REG, 76 HCLGEVF_RING_TX_EBD_OFFSET_REG, 77 HCLGEVF_RING_TX_BD_ERR_REG, 78 HCLGEVF_RING_EN_REG}; 79 80 static const u32 tqp_intr_reg_addr_list[] = {HCLGEVF_TQP_INTR_CTRL_REG, 81 HCLGEVF_TQP_INTR_GL0_REG, 82 HCLGEVF_TQP_INTR_GL1_REG, 83 HCLGEVF_TQP_INTR_GL2_REG, 84 HCLGEVF_TQP_INTR_RL_REG}; 85 86 static inline struct hclgevf_dev *hclgevf_ae_get_hdev( 87 struct hnae3_handle *handle) 88 { 89 if (!handle->client) 90 return container_of(handle, struct hclgevf_dev, nic); 91 else if (handle->client->type == HNAE3_CLIENT_ROCE) 92 return container_of(handle, struct hclgevf_dev, roce); 93 else 94 return container_of(handle, struct hclgevf_dev, nic); 95 } 96 97 static int hclgevf_tqps_update_stats(struct hnae3_handle *handle) 98 { 99 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 100 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 101 struct hclgevf_desc desc; 102 struct hclgevf_tqp *tqp; 103 int status; 104 int i; 105 106 for (i = 0; i < kinfo->num_tqps; i++) { 107 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 108 hclgevf_cmd_setup_basic_desc(&desc, 109 HCLGEVF_OPC_QUERY_RX_STATUS, 110 true); 111 112 desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 113 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 114 if (status) { 115 dev_err(&hdev->pdev->dev, 116 "Query tqp stat fail, status = %d,queue = %d\n", 117 status, i); 118 return status; 119 } 120 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd += 121 le32_to_cpu(desc.data[1]); 122 123 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_TX_STATUS, 124 true); 125 126 desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 127 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 128 if (status) { 129 dev_err(&hdev->pdev->dev, 130 "Query tqp stat fail, status = %d,queue = %d\n", 131 status, i); 132 return status; 133 } 134 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd += 135 le32_to_cpu(desc.data[1]); 136 } 137 138 return 0; 139 } 140 141 static u64 *hclgevf_tqps_get_stats(struct hnae3_handle *handle, u64 *data) 142 { 143 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 144 struct hclgevf_tqp *tqp; 145 u64 *buff = data; 146 int i; 147 148 for (i = 0; i < kinfo->num_tqps; i++) { 149 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 150 *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd; 151 } 152 for (i = 0; i < kinfo->num_tqps; i++) { 153 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 154 *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd; 155 } 156 157 return buff; 158 } 159 160 static int hclgevf_tqps_get_sset_count(struct hnae3_handle *handle, int strset) 161 { 162 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 163 164 return kinfo->num_tqps * 2; 165 } 166 167 static u8 *hclgevf_tqps_get_strings(struct hnae3_handle *handle, u8 *data) 168 { 169 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 170 u8 *buff = data; 171 int i = 0; 172 173 for (i = 0; i < kinfo->num_tqps; i++) { 174 struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 175 struct hclgevf_tqp, q); 176 snprintf(buff, ETH_GSTRING_LEN, "txq%d_pktnum_rcd", 177 tqp->index); 178 buff += ETH_GSTRING_LEN; 179 } 180 181 for (i = 0; i < kinfo->num_tqps; i++) { 182 struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 183 struct hclgevf_tqp, q); 184 snprintf(buff, ETH_GSTRING_LEN, "rxq%d_pktnum_rcd", 185 tqp->index); 186 buff += ETH_GSTRING_LEN; 187 } 188 189 return buff; 190 } 191 192 static void hclgevf_update_stats(struct hnae3_handle *handle, 193 struct net_device_stats *net_stats) 194 { 195 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 196 int status; 197 198 status = hclgevf_tqps_update_stats(handle); 199 if (status) 200 dev_err(&hdev->pdev->dev, 201 "VF update of TQPS stats fail, status = %d.\n", 202 status); 203 } 204 205 static int hclgevf_get_sset_count(struct hnae3_handle *handle, int strset) 206 { 207 if (strset == ETH_SS_TEST) 208 return -EOPNOTSUPP; 209 else if (strset == ETH_SS_STATS) 210 return hclgevf_tqps_get_sset_count(handle, strset); 211 212 return 0; 213 } 214 215 static void hclgevf_get_strings(struct hnae3_handle *handle, u32 strset, 216 u8 *data) 217 { 218 u8 *p = (char *)data; 219 220 if (strset == ETH_SS_STATS) 221 p = hclgevf_tqps_get_strings(handle, p); 222 } 223 224 static void hclgevf_get_stats(struct hnae3_handle *handle, u64 *data) 225 { 226 hclgevf_tqps_get_stats(handle, data); 227 } 228 229 static int hclgevf_get_tc_info(struct hclgevf_dev *hdev) 230 { 231 u8 resp_msg; 232 int status; 233 234 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_TCINFO, 0, NULL, 0, 235 true, &resp_msg, sizeof(u8)); 236 if (status) { 237 dev_err(&hdev->pdev->dev, 238 "VF request to get TC info from PF failed %d", 239 status); 240 return status; 241 } 242 243 hdev->hw_tc_map = resp_msg; 244 245 return 0; 246 } 247 248 static int hclgevf_get_queue_info(struct hclgevf_dev *hdev) 249 { 250 #define HCLGEVF_TQPS_RSS_INFO_LEN 6 251 u8 resp_msg[HCLGEVF_TQPS_RSS_INFO_LEN]; 252 int status; 253 254 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QINFO, 0, NULL, 0, 255 true, resp_msg, 256 HCLGEVF_TQPS_RSS_INFO_LEN); 257 if (status) { 258 dev_err(&hdev->pdev->dev, 259 "VF request to get tqp info from PF failed %d", 260 status); 261 return status; 262 } 263 264 memcpy(&hdev->num_tqps, &resp_msg[0], sizeof(u16)); 265 memcpy(&hdev->rss_size_max, &resp_msg[2], sizeof(u16)); 266 memcpy(&hdev->rx_buf_len, &resp_msg[4], sizeof(u16)); 267 268 return 0; 269 } 270 271 static int hclgevf_get_queue_depth(struct hclgevf_dev *hdev) 272 { 273 #define HCLGEVF_TQPS_DEPTH_INFO_LEN 4 274 u8 resp_msg[HCLGEVF_TQPS_DEPTH_INFO_LEN]; 275 int ret; 276 277 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QDEPTH, 0, NULL, 0, 278 true, resp_msg, 279 HCLGEVF_TQPS_DEPTH_INFO_LEN); 280 if (ret) { 281 dev_err(&hdev->pdev->dev, 282 "VF request to get tqp depth info from PF failed %d", 283 ret); 284 return ret; 285 } 286 287 memcpy(&hdev->num_tx_desc, &resp_msg[0], sizeof(u16)); 288 memcpy(&hdev->num_rx_desc, &resp_msg[2], sizeof(u16)); 289 290 return 0; 291 } 292 293 static u16 hclgevf_get_qid_global(struct hnae3_handle *handle, u16 queue_id) 294 { 295 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 296 u8 msg_data[2], resp_data[2]; 297 u16 qid_in_pf = 0; 298 int ret; 299 300 memcpy(&msg_data[0], &queue_id, sizeof(queue_id)); 301 302 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QID_IN_PF, 0, msg_data, 303 2, true, resp_data, 2); 304 if (!ret) 305 qid_in_pf = *(u16 *)resp_data; 306 307 return qid_in_pf; 308 } 309 310 static int hclgevf_get_pf_media_type(struct hclgevf_dev *hdev) 311 { 312 u8 resp_msg; 313 int ret; 314 315 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_MEDIA_TYPE, 0, NULL, 0, 316 true, &resp_msg, sizeof(resp_msg)); 317 if (ret) { 318 dev_err(&hdev->pdev->dev, 319 "VF request to get the pf port media type failed %d", 320 ret); 321 return ret; 322 } 323 324 hdev->hw.mac.media_type = resp_msg; 325 326 return 0; 327 } 328 329 static int hclgevf_alloc_tqps(struct hclgevf_dev *hdev) 330 { 331 struct hclgevf_tqp *tqp; 332 int i; 333 334 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 335 sizeof(struct hclgevf_tqp), GFP_KERNEL); 336 if (!hdev->htqp) 337 return -ENOMEM; 338 339 tqp = hdev->htqp; 340 341 for (i = 0; i < hdev->num_tqps; i++) { 342 tqp->dev = &hdev->pdev->dev; 343 tqp->index = i; 344 345 tqp->q.ae_algo = &ae_algovf; 346 tqp->q.buf_size = hdev->rx_buf_len; 347 tqp->q.tx_desc_num = hdev->num_tx_desc; 348 tqp->q.rx_desc_num = hdev->num_rx_desc; 349 tqp->q.io_base = hdev->hw.io_base + HCLGEVF_TQP_REG_OFFSET + 350 i * HCLGEVF_TQP_REG_SIZE; 351 352 tqp++; 353 } 354 355 return 0; 356 } 357 358 static int hclgevf_knic_setup(struct hclgevf_dev *hdev) 359 { 360 struct hnae3_handle *nic = &hdev->nic; 361 struct hnae3_knic_private_info *kinfo; 362 u16 new_tqps = hdev->num_tqps; 363 int i; 364 365 kinfo = &nic->kinfo; 366 kinfo->num_tc = 0; 367 kinfo->num_tx_desc = hdev->num_tx_desc; 368 kinfo->num_rx_desc = hdev->num_rx_desc; 369 kinfo->rx_buf_len = hdev->rx_buf_len; 370 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) 371 if (hdev->hw_tc_map & BIT(i)) 372 kinfo->num_tc++; 373 374 kinfo->rss_size 375 = min_t(u16, hdev->rss_size_max, new_tqps / kinfo->num_tc); 376 new_tqps = kinfo->rss_size * kinfo->num_tc; 377 kinfo->num_tqps = min(new_tqps, hdev->num_tqps); 378 379 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps, 380 sizeof(struct hnae3_queue *), GFP_KERNEL); 381 if (!kinfo->tqp) 382 return -ENOMEM; 383 384 for (i = 0; i < kinfo->num_tqps; i++) { 385 hdev->htqp[i].q.handle = &hdev->nic; 386 hdev->htqp[i].q.tqp_index = i; 387 kinfo->tqp[i] = &hdev->htqp[i].q; 388 } 389 390 return 0; 391 } 392 393 static void hclgevf_request_link_info(struct hclgevf_dev *hdev) 394 { 395 int status; 396 u8 resp_msg; 397 398 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_STATUS, 0, NULL, 399 0, false, &resp_msg, sizeof(u8)); 400 if (status) 401 dev_err(&hdev->pdev->dev, 402 "VF failed to fetch link status(%d) from PF", status); 403 } 404 405 void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state) 406 { 407 struct hnae3_handle *rhandle = &hdev->roce; 408 struct hnae3_handle *handle = &hdev->nic; 409 struct hnae3_client *rclient; 410 struct hnae3_client *client; 411 412 client = handle->client; 413 rclient = hdev->roce_client; 414 415 link_state = 416 test_bit(HCLGEVF_STATE_DOWN, &hdev->state) ? 0 : link_state; 417 418 if (link_state != hdev->hw.mac.link) { 419 client->ops->link_status_change(handle, !!link_state); 420 if (rclient && rclient->ops->link_status_change) 421 rclient->ops->link_status_change(rhandle, !!link_state); 422 hdev->hw.mac.link = link_state; 423 } 424 } 425 426 static void hclgevf_update_link_mode(struct hclgevf_dev *hdev) 427 { 428 #define HCLGEVF_ADVERTISING 0 429 #define HCLGEVF_SUPPORTED 1 430 u8 send_msg; 431 u8 resp_msg; 432 433 send_msg = HCLGEVF_ADVERTISING; 434 hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_MODE, 0, &send_msg, 435 sizeof(u8), false, &resp_msg, sizeof(u8)); 436 send_msg = HCLGEVF_SUPPORTED; 437 hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_MODE, 0, &send_msg, 438 sizeof(u8), false, &resp_msg, sizeof(u8)); 439 } 440 441 static int hclgevf_set_handle_info(struct hclgevf_dev *hdev) 442 { 443 struct hnae3_handle *nic = &hdev->nic; 444 int ret; 445 446 nic->ae_algo = &ae_algovf; 447 nic->pdev = hdev->pdev; 448 nic->numa_node_mask = hdev->numa_node_mask; 449 nic->flags |= HNAE3_SUPPORT_VF; 450 451 if (hdev->ae_dev->dev_type != HNAE3_DEV_KNIC) { 452 dev_err(&hdev->pdev->dev, "unsupported device type %d\n", 453 hdev->ae_dev->dev_type); 454 return -EINVAL; 455 } 456 457 ret = hclgevf_knic_setup(hdev); 458 if (ret) 459 dev_err(&hdev->pdev->dev, "VF knic setup failed %d\n", 460 ret); 461 return ret; 462 } 463 464 static void hclgevf_free_vector(struct hclgevf_dev *hdev, int vector_id) 465 { 466 if (hdev->vector_status[vector_id] == HCLGEVF_INVALID_VPORT) { 467 dev_warn(&hdev->pdev->dev, 468 "vector(vector_id %d) has been freed.\n", vector_id); 469 return; 470 } 471 472 hdev->vector_status[vector_id] = HCLGEVF_INVALID_VPORT; 473 hdev->num_msi_left += 1; 474 hdev->num_msi_used -= 1; 475 } 476 477 static int hclgevf_get_vector(struct hnae3_handle *handle, u16 vector_num, 478 struct hnae3_vector_info *vector_info) 479 { 480 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 481 struct hnae3_vector_info *vector = vector_info; 482 int alloc = 0; 483 int i, j; 484 485 vector_num = min(hdev->num_msi_left, vector_num); 486 487 for (j = 0; j < vector_num; j++) { 488 for (i = HCLGEVF_MISC_VECTOR_NUM + 1; i < hdev->num_msi; i++) { 489 if (hdev->vector_status[i] == HCLGEVF_INVALID_VPORT) { 490 vector->vector = pci_irq_vector(hdev->pdev, i); 491 vector->io_addr = hdev->hw.io_base + 492 HCLGEVF_VECTOR_REG_BASE + 493 (i - 1) * HCLGEVF_VECTOR_REG_OFFSET; 494 hdev->vector_status[i] = 0; 495 hdev->vector_irq[i] = vector->vector; 496 497 vector++; 498 alloc++; 499 500 break; 501 } 502 } 503 } 504 hdev->num_msi_left -= alloc; 505 hdev->num_msi_used += alloc; 506 507 return alloc; 508 } 509 510 static int hclgevf_get_vector_index(struct hclgevf_dev *hdev, int vector) 511 { 512 int i; 513 514 for (i = 0; i < hdev->num_msi; i++) 515 if (vector == hdev->vector_irq[i]) 516 return i; 517 518 return -EINVAL; 519 } 520 521 static int hclgevf_set_rss_algo_key(struct hclgevf_dev *hdev, 522 const u8 hfunc, const u8 *key) 523 { 524 struct hclgevf_rss_config_cmd *req; 525 struct hclgevf_desc desc; 526 int key_offset; 527 int key_size; 528 int ret; 529 530 req = (struct hclgevf_rss_config_cmd *)desc.data; 531 532 for (key_offset = 0; key_offset < 3; key_offset++) { 533 hclgevf_cmd_setup_basic_desc(&desc, 534 HCLGEVF_OPC_RSS_GENERIC_CONFIG, 535 false); 536 537 req->hash_config |= (hfunc & HCLGEVF_RSS_HASH_ALGO_MASK); 538 req->hash_config |= 539 (key_offset << HCLGEVF_RSS_HASH_KEY_OFFSET_B); 540 541 if (key_offset == 2) 542 key_size = 543 HCLGEVF_RSS_KEY_SIZE - HCLGEVF_RSS_HASH_KEY_NUM * 2; 544 else 545 key_size = HCLGEVF_RSS_HASH_KEY_NUM; 546 547 memcpy(req->hash_key, 548 key + key_offset * HCLGEVF_RSS_HASH_KEY_NUM, key_size); 549 550 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 551 if (ret) { 552 dev_err(&hdev->pdev->dev, 553 "Configure RSS config fail, status = %d\n", 554 ret); 555 return ret; 556 } 557 } 558 559 return 0; 560 } 561 562 static u32 hclgevf_get_rss_key_size(struct hnae3_handle *handle) 563 { 564 return HCLGEVF_RSS_KEY_SIZE; 565 } 566 567 static u32 hclgevf_get_rss_indir_size(struct hnae3_handle *handle) 568 { 569 return HCLGEVF_RSS_IND_TBL_SIZE; 570 } 571 572 static int hclgevf_set_rss_indir_table(struct hclgevf_dev *hdev) 573 { 574 const u8 *indir = hdev->rss_cfg.rss_indirection_tbl; 575 struct hclgevf_rss_indirection_table_cmd *req; 576 struct hclgevf_desc desc; 577 int status; 578 int i, j; 579 580 req = (struct hclgevf_rss_indirection_table_cmd *)desc.data; 581 582 for (i = 0; i < HCLGEVF_RSS_CFG_TBL_NUM; i++) { 583 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INDIR_TABLE, 584 false); 585 req->start_table_index = i * HCLGEVF_RSS_CFG_TBL_SIZE; 586 req->rss_set_bitmap = HCLGEVF_RSS_SET_BITMAP_MSK; 587 for (j = 0; j < HCLGEVF_RSS_CFG_TBL_SIZE; j++) 588 req->rss_result[j] = 589 indir[i * HCLGEVF_RSS_CFG_TBL_SIZE + j]; 590 591 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 592 if (status) { 593 dev_err(&hdev->pdev->dev, 594 "VF failed(=%d) to set RSS indirection table\n", 595 status); 596 return status; 597 } 598 } 599 600 return 0; 601 } 602 603 static int hclgevf_set_rss_tc_mode(struct hclgevf_dev *hdev, u16 rss_size) 604 { 605 struct hclgevf_rss_tc_mode_cmd *req; 606 u16 tc_offset[HCLGEVF_MAX_TC_NUM]; 607 u16 tc_valid[HCLGEVF_MAX_TC_NUM]; 608 u16 tc_size[HCLGEVF_MAX_TC_NUM]; 609 struct hclgevf_desc desc; 610 u16 roundup_size; 611 int status; 612 int i; 613 614 req = (struct hclgevf_rss_tc_mode_cmd *)desc.data; 615 616 roundup_size = roundup_pow_of_two(rss_size); 617 roundup_size = ilog2(roundup_size); 618 619 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 620 tc_valid[i] = !!(hdev->hw_tc_map & BIT(i)); 621 tc_size[i] = roundup_size; 622 tc_offset[i] = rss_size * i; 623 } 624 625 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_TC_MODE, false); 626 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 627 hnae3_set_bit(req->rss_tc_mode[i], HCLGEVF_RSS_TC_VALID_B, 628 (tc_valid[i] & 0x1)); 629 hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_SIZE_M, 630 HCLGEVF_RSS_TC_SIZE_S, tc_size[i]); 631 hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_OFFSET_M, 632 HCLGEVF_RSS_TC_OFFSET_S, tc_offset[i]); 633 } 634 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 635 if (status) 636 dev_err(&hdev->pdev->dev, 637 "VF failed(=%d) to set rss tc mode\n", status); 638 639 return status; 640 } 641 642 /* for revision 0x20, vf shared the same rss config with pf */ 643 static int hclgevf_get_rss_hash_key(struct hclgevf_dev *hdev) 644 { 645 #define HCLGEVF_RSS_MBX_RESP_LEN 8 646 647 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 648 u8 resp_msg[HCLGEVF_RSS_MBX_RESP_LEN]; 649 u16 msg_num, hash_key_index; 650 u8 index; 651 int ret; 652 653 msg_num = (HCLGEVF_RSS_KEY_SIZE + HCLGEVF_RSS_MBX_RESP_LEN - 1) / 654 HCLGEVF_RSS_MBX_RESP_LEN; 655 for (index = 0; index < msg_num; index++) { 656 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_RSS_KEY, 0, 657 &index, sizeof(index), 658 true, resp_msg, 659 HCLGEVF_RSS_MBX_RESP_LEN); 660 if (ret) { 661 dev_err(&hdev->pdev->dev, 662 "VF get rss hash key from PF failed, ret=%d", 663 ret); 664 return ret; 665 } 666 667 hash_key_index = HCLGEVF_RSS_MBX_RESP_LEN * index; 668 if (index == msg_num - 1) 669 memcpy(&rss_cfg->rss_hash_key[hash_key_index], 670 &resp_msg[0], 671 HCLGEVF_RSS_KEY_SIZE - hash_key_index); 672 else 673 memcpy(&rss_cfg->rss_hash_key[hash_key_index], 674 &resp_msg[0], HCLGEVF_RSS_MBX_RESP_LEN); 675 } 676 677 return 0; 678 } 679 680 static int hclgevf_get_rss(struct hnae3_handle *handle, u32 *indir, u8 *key, 681 u8 *hfunc) 682 { 683 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 684 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 685 int i, ret; 686 687 if (handle->pdev->revision >= 0x21) { 688 /* Get hash algorithm */ 689 if (hfunc) { 690 switch (rss_cfg->hash_algo) { 691 case HCLGEVF_RSS_HASH_ALGO_TOEPLITZ: 692 *hfunc = ETH_RSS_HASH_TOP; 693 break; 694 case HCLGEVF_RSS_HASH_ALGO_SIMPLE: 695 *hfunc = ETH_RSS_HASH_XOR; 696 break; 697 default: 698 *hfunc = ETH_RSS_HASH_UNKNOWN; 699 break; 700 } 701 } 702 703 /* Get the RSS Key required by the user */ 704 if (key) 705 memcpy(key, rss_cfg->rss_hash_key, 706 HCLGEVF_RSS_KEY_SIZE); 707 } else { 708 if (hfunc) 709 *hfunc = ETH_RSS_HASH_TOP; 710 if (key) { 711 ret = hclgevf_get_rss_hash_key(hdev); 712 if (ret) 713 return ret; 714 memcpy(key, rss_cfg->rss_hash_key, 715 HCLGEVF_RSS_KEY_SIZE); 716 } 717 } 718 719 if (indir) 720 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 721 indir[i] = rss_cfg->rss_indirection_tbl[i]; 722 723 return 0; 724 } 725 726 static int hclgevf_set_rss(struct hnae3_handle *handle, const u32 *indir, 727 const u8 *key, const u8 hfunc) 728 { 729 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 730 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 731 int ret, i; 732 733 if (handle->pdev->revision >= 0x21) { 734 /* Set the RSS Hash Key if specififed by the user */ 735 if (key) { 736 switch (hfunc) { 737 case ETH_RSS_HASH_TOP: 738 rss_cfg->hash_algo = 739 HCLGEVF_RSS_HASH_ALGO_TOEPLITZ; 740 break; 741 case ETH_RSS_HASH_XOR: 742 rss_cfg->hash_algo = 743 HCLGEVF_RSS_HASH_ALGO_SIMPLE; 744 break; 745 case ETH_RSS_HASH_NO_CHANGE: 746 break; 747 default: 748 return -EINVAL; 749 } 750 751 ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 752 key); 753 if (ret) 754 return ret; 755 756 /* Update the shadow RSS key with user specified qids */ 757 memcpy(rss_cfg->rss_hash_key, key, 758 HCLGEVF_RSS_KEY_SIZE); 759 } 760 } 761 762 /* update the shadow RSS table with user specified qids */ 763 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 764 rss_cfg->rss_indirection_tbl[i] = indir[i]; 765 766 /* update the hardware */ 767 return hclgevf_set_rss_indir_table(hdev); 768 } 769 770 static u8 hclgevf_get_rss_hash_bits(struct ethtool_rxnfc *nfc) 771 { 772 u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGEVF_S_PORT_BIT : 0; 773 774 if (nfc->data & RXH_L4_B_2_3) 775 hash_sets |= HCLGEVF_D_PORT_BIT; 776 else 777 hash_sets &= ~HCLGEVF_D_PORT_BIT; 778 779 if (nfc->data & RXH_IP_SRC) 780 hash_sets |= HCLGEVF_S_IP_BIT; 781 else 782 hash_sets &= ~HCLGEVF_S_IP_BIT; 783 784 if (nfc->data & RXH_IP_DST) 785 hash_sets |= HCLGEVF_D_IP_BIT; 786 else 787 hash_sets &= ~HCLGEVF_D_IP_BIT; 788 789 if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW) 790 hash_sets |= HCLGEVF_V_TAG_BIT; 791 792 return hash_sets; 793 } 794 795 static int hclgevf_set_rss_tuple(struct hnae3_handle *handle, 796 struct ethtool_rxnfc *nfc) 797 { 798 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 799 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 800 struct hclgevf_rss_input_tuple_cmd *req; 801 struct hclgevf_desc desc; 802 u8 tuple_sets; 803 int ret; 804 805 if (handle->pdev->revision == 0x20) 806 return -EOPNOTSUPP; 807 808 if (nfc->data & 809 ~(RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3)) 810 return -EINVAL; 811 812 req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 813 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 814 815 req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 816 req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 817 req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 818 req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 819 req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 820 req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 821 req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 822 req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 823 824 tuple_sets = hclgevf_get_rss_hash_bits(nfc); 825 switch (nfc->flow_type) { 826 case TCP_V4_FLOW: 827 req->ipv4_tcp_en = tuple_sets; 828 break; 829 case TCP_V6_FLOW: 830 req->ipv6_tcp_en = tuple_sets; 831 break; 832 case UDP_V4_FLOW: 833 req->ipv4_udp_en = tuple_sets; 834 break; 835 case UDP_V6_FLOW: 836 req->ipv6_udp_en = tuple_sets; 837 break; 838 case SCTP_V4_FLOW: 839 req->ipv4_sctp_en = tuple_sets; 840 break; 841 case SCTP_V6_FLOW: 842 if ((nfc->data & RXH_L4_B_0_1) || 843 (nfc->data & RXH_L4_B_2_3)) 844 return -EINVAL; 845 846 req->ipv6_sctp_en = tuple_sets; 847 break; 848 case IPV4_FLOW: 849 req->ipv4_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 850 break; 851 case IPV6_FLOW: 852 req->ipv6_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 853 break; 854 default: 855 return -EINVAL; 856 } 857 858 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 859 if (ret) { 860 dev_err(&hdev->pdev->dev, 861 "Set rss tuple fail, status = %d\n", ret); 862 return ret; 863 } 864 865 rss_cfg->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en; 866 rss_cfg->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en; 867 rss_cfg->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en; 868 rss_cfg->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en; 869 rss_cfg->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en; 870 rss_cfg->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en; 871 rss_cfg->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en; 872 rss_cfg->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en; 873 return 0; 874 } 875 876 static int hclgevf_get_rss_tuple(struct hnae3_handle *handle, 877 struct ethtool_rxnfc *nfc) 878 { 879 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 880 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 881 u8 tuple_sets; 882 883 if (handle->pdev->revision == 0x20) 884 return -EOPNOTSUPP; 885 886 nfc->data = 0; 887 888 switch (nfc->flow_type) { 889 case TCP_V4_FLOW: 890 tuple_sets = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 891 break; 892 case UDP_V4_FLOW: 893 tuple_sets = rss_cfg->rss_tuple_sets.ipv4_udp_en; 894 break; 895 case TCP_V6_FLOW: 896 tuple_sets = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 897 break; 898 case UDP_V6_FLOW: 899 tuple_sets = rss_cfg->rss_tuple_sets.ipv6_udp_en; 900 break; 901 case SCTP_V4_FLOW: 902 tuple_sets = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 903 break; 904 case SCTP_V6_FLOW: 905 tuple_sets = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 906 break; 907 case IPV4_FLOW: 908 case IPV6_FLOW: 909 tuple_sets = HCLGEVF_S_IP_BIT | HCLGEVF_D_IP_BIT; 910 break; 911 default: 912 return -EINVAL; 913 } 914 915 if (!tuple_sets) 916 return 0; 917 918 if (tuple_sets & HCLGEVF_D_PORT_BIT) 919 nfc->data |= RXH_L4_B_2_3; 920 if (tuple_sets & HCLGEVF_S_PORT_BIT) 921 nfc->data |= RXH_L4_B_0_1; 922 if (tuple_sets & HCLGEVF_D_IP_BIT) 923 nfc->data |= RXH_IP_DST; 924 if (tuple_sets & HCLGEVF_S_IP_BIT) 925 nfc->data |= RXH_IP_SRC; 926 927 return 0; 928 } 929 930 static int hclgevf_set_rss_input_tuple(struct hclgevf_dev *hdev, 931 struct hclgevf_rss_cfg *rss_cfg) 932 { 933 struct hclgevf_rss_input_tuple_cmd *req; 934 struct hclgevf_desc desc; 935 int ret; 936 937 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 938 939 req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 940 941 req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 942 req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 943 req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 944 req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 945 req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 946 req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 947 req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 948 req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 949 950 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 951 if (ret) 952 dev_err(&hdev->pdev->dev, 953 "Configure rss input fail, status = %d\n", ret); 954 return ret; 955 } 956 957 static int hclgevf_get_tc_size(struct hnae3_handle *handle) 958 { 959 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 960 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 961 962 return rss_cfg->rss_size; 963 } 964 965 static int hclgevf_bind_ring_to_vector(struct hnae3_handle *handle, bool en, 966 int vector_id, 967 struct hnae3_ring_chain_node *ring_chain) 968 { 969 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 970 struct hnae3_ring_chain_node *node; 971 struct hclge_mbx_vf_to_pf_cmd *req; 972 struct hclgevf_desc desc; 973 int i = 0; 974 int status; 975 u8 type; 976 977 req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data; 978 979 for (node = ring_chain; node; node = node->next) { 980 int idx_offset = HCLGE_MBX_RING_MAP_BASIC_MSG_NUM + 981 HCLGE_MBX_RING_NODE_VARIABLE_NUM * i; 982 983 if (i == 0) { 984 hclgevf_cmd_setup_basic_desc(&desc, 985 HCLGEVF_OPC_MBX_VF_TO_PF, 986 false); 987 type = en ? 988 HCLGE_MBX_MAP_RING_TO_VECTOR : 989 HCLGE_MBX_UNMAP_RING_TO_VECTOR; 990 req->msg[0] = type; 991 req->msg[1] = vector_id; 992 } 993 994 req->msg[idx_offset] = 995 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B); 996 req->msg[idx_offset + 1] = node->tqp_index; 997 req->msg[idx_offset + 2] = hnae3_get_field(node->int_gl_idx, 998 HNAE3_RING_GL_IDX_M, 999 HNAE3_RING_GL_IDX_S); 1000 1001 i++; 1002 if ((i == (HCLGE_MBX_VF_MSG_DATA_NUM - 1003 HCLGE_MBX_RING_MAP_BASIC_MSG_NUM) / 1004 HCLGE_MBX_RING_NODE_VARIABLE_NUM) || 1005 !node->next) { 1006 req->msg[2] = i; 1007 1008 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1009 if (status) { 1010 dev_err(&hdev->pdev->dev, 1011 "Map TQP fail, status is %d.\n", 1012 status); 1013 return status; 1014 } 1015 i = 0; 1016 hclgevf_cmd_setup_basic_desc(&desc, 1017 HCLGEVF_OPC_MBX_VF_TO_PF, 1018 false); 1019 req->msg[0] = type; 1020 req->msg[1] = vector_id; 1021 } 1022 } 1023 1024 return 0; 1025 } 1026 1027 static int hclgevf_map_ring_to_vector(struct hnae3_handle *handle, int vector, 1028 struct hnae3_ring_chain_node *ring_chain) 1029 { 1030 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1031 int vector_id; 1032 1033 vector_id = hclgevf_get_vector_index(hdev, vector); 1034 if (vector_id < 0) { 1035 dev_err(&handle->pdev->dev, 1036 "Get vector index fail. ret =%d\n", vector_id); 1037 return vector_id; 1038 } 1039 1040 return hclgevf_bind_ring_to_vector(handle, true, vector_id, ring_chain); 1041 } 1042 1043 static int hclgevf_unmap_ring_from_vector( 1044 struct hnae3_handle *handle, 1045 int vector, 1046 struct hnae3_ring_chain_node *ring_chain) 1047 { 1048 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1049 int ret, vector_id; 1050 1051 if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 1052 return 0; 1053 1054 vector_id = hclgevf_get_vector_index(hdev, vector); 1055 if (vector_id < 0) { 1056 dev_err(&handle->pdev->dev, 1057 "Get vector index fail. ret =%d\n", vector_id); 1058 return vector_id; 1059 } 1060 1061 ret = hclgevf_bind_ring_to_vector(handle, false, vector_id, ring_chain); 1062 if (ret) 1063 dev_err(&handle->pdev->dev, 1064 "Unmap ring from vector fail. vector=%d, ret =%d\n", 1065 vector_id, 1066 ret); 1067 1068 return ret; 1069 } 1070 1071 static int hclgevf_put_vector(struct hnae3_handle *handle, int vector) 1072 { 1073 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1074 int vector_id; 1075 1076 vector_id = hclgevf_get_vector_index(hdev, vector); 1077 if (vector_id < 0) { 1078 dev_err(&handle->pdev->dev, 1079 "hclgevf_put_vector get vector index fail. ret =%d\n", 1080 vector_id); 1081 return vector_id; 1082 } 1083 1084 hclgevf_free_vector(hdev, vector_id); 1085 1086 return 0; 1087 } 1088 1089 static int hclgevf_cmd_set_promisc_mode(struct hclgevf_dev *hdev, 1090 bool en_bc_pmc) 1091 { 1092 struct hclge_mbx_vf_to_pf_cmd *req; 1093 struct hclgevf_desc desc; 1094 int ret; 1095 1096 req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data; 1097 1098 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_MBX_VF_TO_PF, false); 1099 req->msg[0] = HCLGE_MBX_SET_PROMISC_MODE; 1100 req->msg[1] = en_bc_pmc ? 1 : 0; 1101 1102 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1103 if (ret) 1104 dev_err(&hdev->pdev->dev, 1105 "Set promisc mode fail, status is %d.\n", ret); 1106 1107 return ret; 1108 } 1109 1110 static int hclgevf_set_promisc_mode(struct hclgevf_dev *hdev, bool en_bc_pmc) 1111 { 1112 return hclgevf_cmd_set_promisc_mode(hdev, en_bc_pmc); 1113 } 1114 1115 static int hclgevf_tqp_enable(struct hclgevf_dev *hdev, int tqp_id, 1116 int stream_id, bool enable) 1117 { 1118 struct hclgevf_cfg_com_tqp_queue_cmd *req; 1119 struct hclgevf_desc desc; 1120 int status; 1121 1122 req = (struct hclgevf_cfg_com_tqp_queue_cmd *)desc.data; 1123 1124 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_CFG_COM_TQP_QUEUE, 1125 false); 1126 req->tqp_id = cpu_to_le16(tqp_id & HCLGEVF_RING_ID_MASK); 1127 req->stream_id = cpu_to_le16(stream_id); 1128 req->enable |= enable << HCLGEVF_TQP_ENABLE_B; 1129 1130 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1131 if (status) 1132 dev_err(&hdev->pdev->dev, 1133 "TQP enable fail, status =%d.\n", status); 1134 1135 return status; 1136 } 1137 1138 static void hclgevf_reset_tqp_stats(struct hnae3_handle *handle) 1139 { 1140 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 1141 struct hclgevf_tqp *tqp; 1142 int i; 1143 1144 for (i = 0; i < kinfo->num_tqps; i++) { 1145 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 1146 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats)); 1147 } 1148 } 1149 1150 static void hclgevf_get_mac_addr(struct hnae3_handle *handle, u8 *p) 1151 { 1152 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1153 1154 ether_addr_copy(p, hdev->hw.mac.mac_addr); 1155 } 1156 1157 static int hclgevf_set_mac_addr(struct hnae3_handle *handle, void *p, 1158 bool is_first) 1159 { 1160 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1161 u8 *old_mac_addr = (u8 *)hdev->hw.mac.mac_addr; 1162 u8 *new_mac_addr = (u8 *)p; 1163 u8 msg_data[ETH_ALEN * 2]; 1164 u16 subcode; 1165 int status; 1166 1167 ether_addr_copy(msg_data, new_mac_addr); 1168 ether_addr_copy(&msg_data[ETH_ALEN], old_mac_addr); 1169 1170 subcode = is_first ? HCLGE_MBX_MAC_VLAN_UC_ADD : 1171 HCLGE_MBX_MAC_VLAN_UC_MODIFY; 1172 1173 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 1174 subcode, msg_data, ETH_ALEN * 2, 1175 true, NULL, 0); 1176 if (!status) 1177 ether_addr_copy(hdev->hw.mac.mac_addr, new_mac_addr); 1178 1179 return status; 1180 } 1181 1182 static int hclgevf_add_uc_addr(struct hnae3_handle *handle, 1183 const unsigned char *addr) 1184 { 1185 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1186 1187 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 1188 HCLGE_MBX_MAC_VLAN_UC_ADD, 1189 addr, ETH_ALEN, false, NULL, 0); 1190 } 1191 1192 static int hclgevf_rm_uc_addr(struct hnae3_handle *handle, 1193 const unsigned char *addr) 1194 { 1195 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1196 1197 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 1198 HCLGE_MBX_MAC_VLAN_UC_REMOVE, 1199 addr, ETH_ALEN, false, NULL, 0); 1200 } 1201 1202 static int hclgevf_add_mc_addr(struct hnae3_handle *handle, 1203 const unsigned char *addr) 1204 { 1205 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1206 1207 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 1208 HCLGE_MBX_MAC_VLAN_MC_ADD, 1209 addr, ETH_ALEN, false, NULL, 0); 1210 } 1211 1212 static int hclgevf_rm_mc_addr(struct hnae3_handle *handle, 1213 const unsigned char *addr) 1214 { 1215 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1216 1217 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 1218 HCLGE_MBX_MAC_VLAN_MC_REMOVE, 1219 addr, ETH_ALEN, false, NULL, 0); 1220 } 1221 1222 static int hclgevf_set_vlan_filter(struct hnae3_handle *handle, 1223 __be16 proto, u16 vlan_id, 1224 bool is_kill) 1225 { 1226 #define HCLGEVF_VLAN_MBX_MSG_LEN 5 1227 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1228 u8 msg_data[HCLGEVF_VLAN_MBX_MSG_LEN]; 1229 1230 if (vlan_id > 4095) 1231 return -EINVAL; 1232 1233 if (proto != htons(ETH_P_8021Q)) 1234 return -EPROTONOSUPPORT; 1235 1236 msg_data[0] = is_kill; 1237 memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id)); 1238 memcpy(&msg_data[3], &proto, sizeof(proto)); 1239 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 1240 HCLGE_MBX_VLAN_FILTER, msg_data, 1241 HCLGEVF_VLAN_MBX_MSG_LEN, false, NULL, 0); 1242 } 1243 1244 static int hclgevf_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) 1245 { 1246 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1247 u8 msg_data; 1248 1249 msg_data = enable ? 1 : 0; 1250 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 1251 HCLGE_MBX_VLAN_RX_OFF_CFG, &msg_data, 1252 1, false, NULL, 0); 1253 } 1254 1255 static int hclgevf_reset_tqp(struct hnae3_handle *handle, u16 queue_id) 1256 { 1257 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1258 u8 msg_data[2]; 1259 int ret; 1260 1261 memcpy(&msg_data[0], &queue_id, sizeof(queue_id)); 1262 1263 /* disable vf queue before send queue reset msg to PF */ 1264 ret = hclgevf_tqp_enable(hdev, queue_id, 0, false); 1265 if (ret) 1266 return ret; 1267 1268 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_QUEUE_RESET, 0, msg_data, 1269 2, true, NULL, 0); 1270 } 1271 1272 static int hclgevf_set_mtu(struct hnae3_handle *handle, int new_mtu) 1273 { 1274 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1275 1276 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MTU, 0, (u8 *)&new_mtu, 1277 sizeof(new_mtu), true, NULL, 0); 1278 } 1279 1280 static int hclgevf_notify_client(struct hclgevf_dev *hdev, 1281 enum hnae3_reset_notify_type type) 1282 { 1283 struct hnae3_client *client = hdev->nic_client; 1284 struct hnae3_handle *handle = &hdev->nic; 1285 int ret; 1286 1287 if (!client->ops->reset_notify) 1288 return -EOPNOTSUPP; 1289 1290 ret = client->ops->reset_notify(handle, type); 1291 if (ret) 1292 dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n", 1293 type, ret); 1294 1295 return ret; 1296 } 1297 1298 static void hclgevf_flr_done(struct hnae3_ae_dev *ae_dev) 1299 { 1300 struct hclgevf_dev *hdev = ae_dev->priv; 1301 1302 set_bit(HNAE3_FLR_DONE, &hdev->flr_state); 1303 } 1304 1305 static int hclgevf_flr_poll_timeout(struct hclgevf_dev *hdev, 1306 unsigned long delay_us, 1307 unsigned long wait_cnt) 1308 { 1309 unsigned long cnt = 0; 1310 1311 while (!test_bit(HNAE3_FLR_DONE, &hdev->flr_state) && 1312 cnt++ < wait_cnt) 1313 usleep_range(delay_us, delay_us * 2); 1314 1315 if (!test_bit(HNAE3_FLR_DONE, &hdev->flr_state)) { 1316 dev_err(&hdev->pdev->dev, 1317 "flr wait timeout\n"); 1318 return -ETIMEDOUT; 1319 } 1320 1321 return 0; 1322 } 1323 1324 static int hclgevf_reset_wait(struct hclgevf_dev *hdev) 1325 { 1326 #define HCLGEVF_RESET_WAIT_US 20000 1327 #define HCLGEVF_RESET_WAIT_CNT 2000 1328 #define HCLGEVF_RESET_WAIT_TIMEOUT_US \ 1329 (HCLGEVF_RESET_WAIT_US * HCLGEVF_RESET_WAIT_CNT) 1330 1331 u32 val; 1332 int ret; 1333 1334 /* wait to check the hardware reset completion status */ 1335 val = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 1336 dev_info(&hdev->pdev->dev, "checking vf resetting status: %x\n", val); 1337 1338 if (hdev->reset_type == HNAE3_FLR_RESET) 1339 return hclgevf_flr_poll_timeout(hdev, 1340 HCLGEVF_RESET_WAIT_US, 1341 HCLGEVF_RESET_WAIT_CNT); 1342 1343 ret = readl_poll_timeout(hdev->hw.io_base + HCLGEVF_RST_ING, val, 1344 !(val & HCLGEVF_RST_ING_BITS), 1345 HCLGEVF_RESET_WAIT_US, 1346 HCLGEVF_RESET_WAIT_TIMEOUT_US); 1347 1348 /* hardware completion status should be available by this time */ 1349 if (ret) { 1350 dev_err(&hdev->pdev->dev, 1351 "could'nt get reset done status from h/w, timeout!\n"); 1352 return ret; 1353 } 1354 1355 /* we will wait a bit more to let reset of the stack to complete. This 1356 * might happen in case reset assertion was made by PF. Yes, this also 1357 * means we might end up waiting bit more even for VF reset. 1358 */ 1359 msleep(5000); 1360 1361 return 0; 1362 } 1363 1364 static int hclgevf_reset_stack(struct hclgevf_dev *hdev) 1365 { 1366 int ret; 1367 1368 /* uninitialize the nic client */ 1369 ret = hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT); 1370 if (ret) 1371 return ret; 1372 1373 /* re-initialize the hclge device */ 1374 ret = hclgevf_reset_hdev(hdev); 1375 if (ret) { 1376 dev_err(&hdev->pdev->dev, 1377 "hclge device re-init failed, VF is disabled!\n"); 1378 return ret; 1379 } 1380 1381 /* bring up the nic client again */ 1382 ret = hclgevf_notify_client(hdev, HNAE3_INIT_CLIENT); 1383 if (ret) 1384 return ret; 1385 1386 return hclgevf_notify_client(hdev, HNAE3_RESTORE_CLIENT); 1387 } 1388 1389 static int hclgevf_reset_prepare_wait(struct hclgevf_dev *hdev) 1390 { 1391 int ret = 0; 1392 1393 switch (hdev->reset_type) { 1394 case HNAE3_VF_FUNC_RESET: 1395 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_RESET, 0, NULL, 1396 0, true, NULL, sizeof(u8)); 1397 break; 1398 case HNAE3_FLR_RESET: 1399 set_bit(HNAE3_FLR_DOWN, &hdev->flr_state); 1400 break; 1401 default: 1402 break; 1403 } 1404 1405 set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 1406 1407 dev_info(&hdev->pdev->dev, "prepare reset(%d) wait done, ret:%d\n", 1408 hdev->reset_type, ret); 1409 1410 return ret; 1411 } 1412 1413 static int hclgevf_reset(struct hclgevf_dev *hdev) 1414 { 1415 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1416 int ret; 1417 1418 /* Initialize ae_dev reset status as well, in case enet layer wants to 1419 * know if device is undergoing reset 1420 */ 1421 ae_dev->reset_type = hdev->reset_type; 1422 hdev->reset_count++; 1423 rtnl_lock(); 1424 1425 /* bring down the nic to stop any ongoing TX/RX */ 1426 ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 1427 if (ret) 1428 goto err_reset_lock; 1429 1430 rtnl_unlock(); 1431 1432 ret = hclgevf_reset_prepare_wait(hdev); 1433 if (ret) 1434 goto err_reset; 1435 1436 /* check if VF could successfully fetch the hardware reset completion 1437 * status from the hardware 1438 */ 1439 ret = hclgevf_reset_wait(hdev); 1440 if (ret) { 1441 /* can't do much in this situation, will disable VF */ 1442 dev_err(&hdev->pdev->dev, 1443 "VF failed(=%d) to fetch H/W reset completion status\n", 1444 ret); 1445 goto err_reset; 1446 } 1447 1448 rtnl_lock(); 1449 1450 /* now, re-initialize the nic client and ae device*/ 1451 ret = hclgevf_reset_stack(hdev); 1452 if (ret) { 1453 dev_err(&hdev->pdev->dev, "failed to reset VF stack\n"); 1454 goto err_reset_lock; 1455 } 1456 1457 /* bring up the nic to enable TX/RX again */ 1458 ret = hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 1459 if (ret) 1460 goto err_reset_lock; 1461 1462 rtnl_unlock(); 1463 1464 hdev->last_reset_time = jiffies; 1465 ae_dev->reset_type = HNAE3_NONE_RESET; 1466 1467 return ret; 1468 err_reset_lock: 1469 rtnl_unlock(); 1470 err_reset: 1471 /* When VF reset failed, only the higher level reset asserted by PF 1472 * can restore it, so re-initialize the command queue to receive 1473 * this higher reset event. 1474 */ 1475 hclgevf_cmd_init(hdev); 1476 dev_err(&hdev->pdev->dev, "failed to reset VF\n"); 1477 if (hclgevf_is_reset_pending(hdev)) 1478 hclgevf_reset_task_schedule(hdev); 1479 1480 return ret; 1481 } 1482 1483 static enum hnae3_reset_type hclgevf_get_reset_level(struct hclgevf_dev *hdev, 1484 unsigned long *addr) 1485 { 1486 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; 1487 1488 /* return the highest priority reset level amongst all */ 1489 if (test_bit(HNAE3_VF_RESET, addr)) { 1490 rst_level = HNAE3_VF_RESET; 1491 clear_bit(HNAE3_VF_RESET, addr); 1492 clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1493 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1494 } else if (test_bit(HNAE3_VF_FULL_RESET, addr)) { 1495 rst_level = HNAE3_VF_FULL_RESET; 1496 clear_bit(HNAE3_VF_FULL_RESET, addr); 1497 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1498 } else if (test_bit(HNAE3_VF_PF_FUNC_RESET, addr)) { 1499 rst_level = HNAE3_VF_PF_FUNC_RESET; 1500 clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1501 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1502 } else if (test_bit(HNAE3_VF_FUNC_RESET, addr)) { 1503 rst_level = HNAE3_VF_FUNC_RESET; 1504 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1505 } else if (test_bit(HNAE3_FLR_RESET, addr)) { 1506 rst_level = HNAE3_FLR_RESET; 1507 clear_bit(HNAE3_FLR_RESET, addr); 1508 } 1509 1510 return rst_level; 1511 } 1512 1513 static void hclgevf_reset_event(struct pci_dev *pdev, 1514 struct hnae3_handle *handle) 1515 { 1516 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 1517 struct hclgevf_dev *hdev = ae_dev->priv; 1518 1519 dev_info(&hdev->pdev->dev, "received reset request from VF enet\n"); 1520 1521 if (hdev->default_reset_request) 1522 hdev->reset_level = 1523 hclgevf_get_reset_level(hdev, 1524 &hdev->default_reset_request); 1525 else 1526 hdev->reset_level = HNAE3_VF_FUNC_RESET; 1527 1528 /* reset of this VF requested */ 1529 set_bit(HCLGEVF_RESET_REQUESTED, &hdev->reset_state); 1530 hclgevf_reset_task_schedule(hdev); 1531 1532 hdev->last_reset_time = jiffies; 1533 } 1534 1535 static void hclgevf_set_def_reset_request(struct hnae3_ae_dev *ae_dev, 1536 enum hnae3_reset_type rst_type) 1537 { 1538 struct hclgevf_dev *hdev = ae_dev->priv; 1539 1540 set_bit(rst_type, &hdev->default_reset_request); 1541 } 1542 1543 static void hclgevf_flr_prepare(struct hnae3_ae_dev *ae_dev) 1544 { 1545 #define HCLGEVF_FLR_WAIT_MS 100 1546 #define HCLGEVF_FLR_WAIT_CNT 50 1547 struct hclgevf_dev *hdev = ae_dev->priv; 1548 int cnt = 0; 1549 1550 clear_bit(HNAE3_FLR_DOWN, &hdev->flr_state); 1551 clear_bit(HNAE3_FLR_DONE, &hdev->flr_state); 1552 set_bit(HNAE3_FLR_RESET, &hdev->default_reset_request); 1553 hclgevf_reset_event(hdev->pdev, NULL); 1554 1555 while (!test_bit(HNAE3_FLR_DOWN, &hdev->flr_state) && 1556 cnt++ < HCLGEVF_FLR_WAIT_CNT) 1557 msleep(HCLGEVF_FLR_WAIT_MS); 1558 1559 if (!test_bit(HNAE3_FLR_DOWN, &hdev->flr_state)) 1560 dev_err(&hdev->pdev->dev, 1561 "flr wait down timeout: %d\n", cnt); 1562 } 1563 1564 static u32 hclgevf_get_fw_version(struct hnae3_handle *handle) 1565 { 1566 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1567 1568 return hdev->fw_version; 1569 } 1570 1571 static void hclgevf_get_misc_vector(struct hclgevf_dev *hdev) 1572 { 1573 struct hclgevf_misc_vector *vector = &hdev->misc_vector; 1574 1575 vector->vector_irq = pci_irq_vector(hdev->pdev, 1576 HCLGEVF_MISC_VECTOR_NUM); 1577 vector->addr = hdev->hw.io_base + HCLGEVF_MISC_VECTOR_REG_BASE; 1578 /* vector status always valid for Vector 0 */ 1579 hdev->vector_status[HCLGEVF_MISC_VECTOR_NUM] = 0; 1580 hdev->vector_irq[HCLGEVF_MISC_VECTOR_NUM] = vector->vector_irq; 1581 1582 hdev->num_msi_left -= 1; 1583 hdev->num_msi_used += 1; 1584 } 1585 1586 void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev) 1587 { 1588 if (!test_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state) && 1589 !test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) { 1590 set_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state); 1591 schedule_work(&hdev->rst_service_task); 1592 } 1593 } 1594 1595 void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev) 1596 { 1597 if (!test_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state) && 1598 !test_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) { 1599 set_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 1600 schedule_work(&hdev->mbx_service_task); 1601 } 1602 } 1603 1604 static void hclgevf_task_schedule(struct hclgevf_dev *hdev) 1605 { 1606 if (!test_bit(HCLGEVF_STATE_DOWN, &hdev->state) && 1607 !test_and_set_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state)) 1608 schedule_work(&hdev->service_task); 1609 } 1610 1611 static void hclgevf_deferred_task_schedule(struct hclgevf_dev *hdev) 1612 { 1613 /* if we have any pending mailbox event then schedule the mbx task */ 1614 if (hdev->mbx_event_pending) 1615 hclgevf_mbx_task_schedule(hdev); 1616 1617 if (test_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state)) 1618 hclgevf_reset_task_schedule(hdev); 1619 } 1620 1621 static void hclgevf_service_timer(struct timer_list *t) 1622 { 1623 struct hclgevf_dev *hdev = from_timer(hdev, t, service_timer); 1624 1625 mod_timer(&hdev->service_timer, jiffies + 5 * HZ); 1626 1627 hclgevf_task_schedule(hdev); 1628 } 1629 1630 static void hclgevf_reset_service_task(struct work_struct *work) 1631 { 1632 struct hclgevf_dev *hdev = 1633 container_of(work, struct hclgevf_dev, rst_service_task); 1634 int ret; 1635 1636 if (test_and_set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 1637 return; 1638 1639 clear_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state); 1640 1641 if (test_and_clear_bit(HCLGEVF_RESET_PENDING, 1642 &hdev->reset_state)) { 1643 /* PF has initmated that it is about to reset the hardware. 1644 * We now have to poll & check if harware has actually completed 1645 * the reset sequence. On hardware reset completion, VF needs to 1646 * reset the client and ae device. 1647 */ 1648 hdev->reset_attempts = 0; 1649 1650 hdev->last_reset_time = jiffies; 1651 while ((hdev->reset_type = 1652 hclgevf_get_reset_level(hdev, &hdev->reset_pending)) 1653 != HNAE3_NONE_RESET) { 1654 ret = hclgevf_reset(hdev); 1655 if (ret) 1656 dev_err(&hdev->pdev->dev, 1657 "VF stack reset failed %d.\n", ret); 1658 } 1659 } else if (test_and_clear_bit(HCLGEVF_RESET_REQUESTED, 1660 &hdev->reset_state)) { 1661 /* we could be here when either of below happens: 1662 * 1. reset was initiated due to watchdog timeout due to 1663 * a. IMP was earlier reset and our TX got choked down and 1664 * which resulted in watchdog reacting and inducing VF 1665 * reset. This also means our cmdq would be unreliable. 1666 * b. problem in TX due to other lower layer(example link 1667 * layer not functioning properly etc.) 1668 * 2. VF reset might have been initiated due to some config 1669 * change. 1670 * 1671 * NOTE: Theres no clear way to detect above cases than to react 1672 * to the response of PF for this reset request. PF will ack the 1673 * 1b and 2. cases but we will not get any intimation about 1a 1674 * from PF as cmdq would be in unreliable state i.e. mailbox 1675 * communication between PF and VF would be broken. 1676 */ 1677 1678 /* if we are never geting into pending state it means either: 1679 * 1. PF is not receiving our request which could be due to IMP 1680 * reset 1681 * 2. PF is screwed 1682 * We cannot do much for 2. but to check first we can try reset 1683 * our PCIe + stack and see if it alleviates the problem. 1684 */ 1685 if (hdev->reset_attempts > 3) { 1686 /* prepare for full reset of stack + pcie interface */ 1687 set_bit(HNAE3_VF_FULL_RESET, &hdev->reset_pending); 1688 1689 /* "defer" schedule the reset task again */ 1690 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1691 } else { 1692 hdev->reset_attempts++; 1693 1694 set_bit(hdev->reset_level, &hdev->reset_pending); 1695 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1696 } 1697 hclgevf_reset_task_schedule(hdev); 1698 } 1699 1700 clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 1701 } 1702 1703 static void hclgevf_mailbox_service_task(struct work_struct *work) 1704 { 1705 struct hclgevf_dev *hdev; 1706 1707 hdev = container_of(work, struct hclgevf_dev, mbx_service_task); 1708 1709 if (test_and_set_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) 1710 return; 1711 1712 clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 1713 1714 hclgevf_mbx_async_handler(hdev); 1715 1716 clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 1717 } 1718 1719 static void hclgevf_keep_alive_timer(struct timer_list *t) 1720 { 1721 struct hclgevf_dev *hdev = from_timer(hdev, t, keep_alive_timer); 1722 1723 schedule_work(&hdev->keep_alive_task); 1724 mod_timer(&hdev->keep_alive_timer, jiffies + 2 * HZ); 1725 } 1726 1727 static void hclgevf_keep_alive_task(struct work_struct *work) 1728 { 1729 struct hclgevf_dev *hdev; 1730 u8 respmsg; 1731 int ret; 1732 1733 hdev = container_of(work, struct hclgevf_dev, keep_alive_task); 1734 1735 if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 1736 return; 1737 1738 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_KEEP_ALIVE, 0, NULL, 1739 0, false, &respmsg, sizeof(u8)); 1740 if (ret) 1741 dev_err(&hdev->pdev->dev, 1742 "VF sends keep alive cmd failed(=%d)\n", ret); 1743 } 1744 1745 static void hclgevf_service_task(struct work_struct *work) 1746 { 1747 struct hclgevf_dev *hdev; 1748 1749 hdev = container_of(work, struct hclgevf_dev, service_task); 1750 1751 /* request the link status from the PF. PF would be able to tell VF 1752 * about such updates in future so we might remove this later 1753 */ 1754 hclgevf_request_link_info(hdev); 1755 1756 hclgevf_update_link_mode(hdev); 1757 1758 hclgevf_deferred_task_schedule(hdev); 1759 1760 clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 1761 } 1762 1763 static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regclr) 1764 { 1765 hclgevf_write_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_SRC_REG, regclr); 1766 } 1767 1768 static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev, 1769 u32 *clearval) 1770 { 1771 u32 cmdq_src_reg, rst_ing_reg; 1772 1773 /* fetch the events from their corresponding regs */ 1774 cmdq_src_reg = hclgevf_read_dev(&hdev->hw, 1775 HCLGEVF_VECTOR0_CMDQ_SRC_REG); 1776 1777 if (BIT(HCLGEVF_VECTOR0_RST_INT_B) & cmdq_src_reg) { 1778 rst_ing_reg = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 1779 dev_info(&hdev->pdev->dev, 1780 "receive reset interrupt 0x%x!\n", rst_ing_reg); 1781 set_bit(HNAE3_VF_RESET, &hdev->reset_pending); 1782 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1783 set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 1784 cmdq_src_reg &= ~BIT(HCLGEVF_VECTOR0_RST_INT_B); 1785 *clearval = cmdq_src_reg; 1786 return HCLGEVF_VECTOR0_EVENT_RST; 1787 } 1788 1789 /* check for vector0 mailbox(=CMDQ RX) event source */ 1790 if (BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) { 1791 cmdq_src_reg &= ~BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 1792 *clearval = cmdq_src_reg; 1793 return HCLGEVF_VECTOR0_EVENT_MBX; 1794 } 1795 1796 dev_dbg(&hdev->pdev->dev, "vector 0 interrupt from unknown source\n"); 1797 1798 return HCLGEVF_VECTOR0_EVENT_OTHER; 1799 } 1800 1801 static void hclgevf_enable_vector(struct hclgevf_misc_vector *vector, bool en) 1802 { 1803 writel(en ? 1 : 0, vector->addr); 1804 } 1805 1806 static irqreturn_t hclgevf_misc_irq_handle(int irq, void *data) 1807 { 1808 enum hclgevf_evt_cause event_cause; 1809 struct hclgevf_dev *hdev = data; 1810 u32 clearval; 1811 1812 hclgevf_enable_vector(&hdev->misc_vector, false); 1813 event_cause = hclgevf_check_evt_cause(hdev, &clearval); 1814 1815 switch (event_cause) { 1816 case HCLGEVF_VECTOR0_EVENT_RST: 1817 hclgevf_reset_task_schedule(hdev); 1818 break; 1819 case HCLGEVF_VECTOR0_EVENT_MBX: 1820 hclgevf_mbx_handler(hdev); 1821 break; 1822 default: 1823 break; 1824 } 1825 1826 if (event_cause != HCLGEVF_VECTOR0_EVENT_OTHER) { 1827 hclgevf_clear_event_cause(hdev, clearval); 1828 hclgevf_enable_vector(&hdev->misc_vector, true); 1829 } 1830 1831 return IRQ_HANDLED; 1832 } 1833 1834 static int hclgevf_configure(struct hclgevf_dev *hdev) 1835 { 1836 int ret; 1837 1838 /* get queue configuration from PF */ 1839 ret = hclgevf_get_queue_info(hdev); 1840 if (ret) 1841 return ret; 1842 1843 /* get queue depth info from PF */ 1844 ret = hclgevf_get_queue_depth(hdev); 1845 if (ret) 1846 return ret; 1847 1848 ret = hclgevf_get_pf_media_type(hdev); 1849 if (ret) 1850 return ret; 1851 1852 /* get tc configuration from PF */ 1853 return hclgevf_get_tc_info(hdev); 1854 } 1855 1856 static int hclgevf_alloc_hdev(struct hnae3_ae_dev *ae_dev) 1857 { 1858 struct pci_dev *pdev = ae_dev->pdev; 1859 struct hclgevf_dev *hdev; 1860 1861 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 1862 if (!hdev) 1863 return -ENOMEM; 1864 1865 hdev->pdev = pdev; 1866 hdev->ae_dev = ae_dev; 1867 ae_dev->priv = hdev; 1868 1869 return 0; 1870 } 1871 1872 static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev) 1873 { 1874 struct hnae3_handle *roce = &hdev->roce; 1875 struct hnae3_handle *nic = &hdev->nic; 1876 1877 roce->rinfo.num_vectors = hdev->num_roce_msix; 1878 1879 if (hdev->num_msi_left < roce->rinfo.num_vectors || 1880 hdev->num_msi_left == 0) 1881 return -EINVAL; 1882 1883 roce->rinfo.base_vector = hdev->roce_base_vector; 1884 1885 roce->rinfo.netdev = nic->kinfo.netdev; 1886 roce->rinfo.roce_io_base = hdev->hw.io_base; 1887 1888 roce->pdev = nic->pdev; 1889 roce->ae_algo = nic->ae_algo; 1890 roce->numa_node_mask = nic->numa_node_mask; 1891 1892 return 0; 1893 } 1894 1895 static int hclgevf_config_gro(struct hclgevf_dev *hdev, bool en) 1896 { 1897 struct hclgevf_cfg_gro_status_cmd *req; 1898 struct hclgevf_desc desc; 1899 int ret; 1900 1901 if (!hnae3_dev_gro_supported(hdev)) 1902 return 0; 1903 1904 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_GRO_GENERIC_CONFIG, 1905 false); 1906 req = (struct hclgevf_cfg_gro_status_cmd *)desc.data; 1907 1908 req->gro_en = cpu_to_le16(en ? 1 : 0); 1909 1910 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1911 if (ret) 1912 dev_err(&hdev->pdev->dev, 1913 "VF GRO hardware config cmd failed, ret = %d.\n", ret); 1914 1915 return ret; 1916 } 1917 1918 static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev) 1919 { 1920 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 1921 int i, ret; 1922 1923 rss_cfg->rss_size = hdev->rss_size_max; 1924 1925 if (hdev->pdev->revision >= 0x21) { 1926 rss_cfg->hash_algo = HCLGEVF_RSS_HASH_ALGO_SIMPLE; 1927 memcpy(rss_cfg->rss_hash_key, hclgevf_hash_key, 1928 HCLGEVF_RSS_KEY_SIZE); 1929 1930 ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 1931 rss_cfg->rss_hash_key); 1932 if (ret) 1933 return ret; 1934 1935 rss_cfg->rss_tuple_sets.ipv4_tcp_en = 1936 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1937 rss_cfg->rss_tuple_sets.ipv4_udp_en = 1938 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1939 rss_cfg->rss_tuple_sets.ipv4_sctp_en = 1940 HCLGEVF_RSS_INPUT_TUPLE_SCTP; 1941 rss_cfg->rss_tuple_sets.ipv4_fragment_en = 1942 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1943 rss_cfg->rss_tuple_sets.ipv6_tcp_en = 1944 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1945 rss_cfg->rss_tuple_sets.ipv6_udp_en = 1946 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1947 rss_cfg->rss_tuple_sets.ipv6_sctp_en = 1948 HCLGEVF_RSS_INPUT_TUPLE_SCTP; 1949 rss_cfg->rss_tuple_sets.ipv6_fragment_en = 1950 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1951 1952 ret = hclgevf_set_rss_input_tuple(hdev, rss_cfg); 1953 if (ret) 1954 return ret; 1955 1956 } 1957 1958 /* Initialize RSS indirect table for each vport */ 1959 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 1960 rss_cfg->rss_indirection_tbl[i] = i % hdev->rss_size_max; 1961 1962 ret = hclgevf_set_rss_indir_table(hdev); 1963 if (ret) 1964 return ret; 1965 1966 return hclgevf_set_rss_tc_mode(hdev, hdev->rss_size_max); 1967 } 1968 1969 static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev) 1970 { 1971 /* other vlan config(like, VLAN TX/RX offload) would also be added 1972 * here later 1973 */ 1974 return hclgevf_set_vlan_filter(&hdev->nic, htons(ETH_P_8021Q), 0, 1975 false); 1976 } 1977 1978 static void hclgevf_set_timer_task(struct hnae3_handle *handle, bool enable) 1979 { 1980 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1981 1982 if (enable) { 1983 mod_timer(&hdev->service_timer, jiffies + HZ); 1984 } else { 1985 del_timer_sync(&hdev->service_timer); 1986 cancel_work_sync(&hdev->service_task); 1987 clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 1988 } 1989 } 1990 1991 static int hclgevf_ae_start(struct hnae3_handle *handle) 1992 { 1993 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1994 1995 /* reset tqp stats */ 1996 hclgevf_reset_tqp_stats(handle); 1997 1998 hclgevf_request_link_info(hdev); 1999 2000 hclgevf_update_link_mode(hdev); 2001 2002 clear_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2003 2004 return 0; 2005 } 2006 2007 static void hclgevf_ae_stop(struct hnae3_handle *handle) 2008 { 2009 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2010 int i; 2011 2012 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2013 2014 for (i = 0; i < handle->kinfo.num_tqps; i++) 2015 hclgevf_reset_tqp(handle, i); 2016 2017 /* reset tqp stats */ 2018 hclgevf_reset_tqp_stats(handle); 2019 hclgevf_update_link_status(hdev, 0); 2020 } 2021 2022 static int hclgevf_set_alive(struct hnae3_handle *handle, bool alive) 2023 { 2024 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2025 u8 msg_data; 2026 2027 msg_data = alive ? 1 : 0; 2028 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_ALIVE, 2029 0, &msg_data, 1, false, NULL, 0); 2030 } 2031 2032 static int hclgevf_client_start(struct hnae3_handle *handle) 2033 { 2034 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2035 2036 mod_timer(&hdev->keep_alive_timer, jiffies + 2 * HZ); 2037 return hclgevf_set_alive(handle, true); 2038 } 2039 2040 static void hclgevf_client_stop(struct hnae3_handle *handle) 2041 { 2042 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2043 int ret; 2044 2045 ret = hclgevf_set_alive(handle, false); 2046 if (ret) 2047 dev_warn(&hdev->pdev->dev, 2048 "%s failed %d\n", __func__, ret); 2049 2050 del_timer_sync(&hdev->keep_alive_timer); 2051 cancel_work_sync(&hdev->keep_alive_task); 2052 } 2053 2054 static void hclgevf_state_init(struct hclgevf_dev *hdev) 2055 { 2056 /* setup tasks for the MBX */ 2057 INIT_WORK(&hdev->mbx_service_task, hclgevf_mailbox_service_task); 2058 clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 2059 clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 2060 2061 /* setup tasks for service timer */ 2062 timer_setup(&hdev->service_timer, hclgevf_service_timer, 0); 2063 2064 INIT_WORK(&hdev->service_task, hclgevf_service_task); 2065 clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 2066 2067 INIT_WORK(&hdev->rst_service_task, hclgevf_reset_service_task); 2068 2069 mutex_init(&hdev->mbx_resp.mbx_mutex); 2070 2071 /* bring the device down */ 2072 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2073 } 2074 2075 static void hclgevf_state_uninit(struct hclgevf_dev *hdev) 2076 { 2077 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2078 2079 if (hdev->service_timer.function) 2080 del_timer_sync(&hdev->service_timer); 2081 if (hdev->service_task.func) 2082 cancel_work_sync(&hdev->service_task); 2083 if (hdev->mbx_service_task.func) 2084 cancel_work_sync(&hdev->mbx_service_task); 2085 if (hdev->rst_service_task.func) 2086 cancel_work_sync(&hdev->rst_service_task); 2087 2088 mutex_destroy(&hdev->mbx_resp.mbx_mutex); 2089 } 2090 2091 static int hclgevf_init_msi(struct hclgevf_dev *hdev) 2092 { 2093 struct pci_dev *pdev = hdev->pdev; 2094 int vectors; 2095 int i; 2096 2097 if (hnae3_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B)) 2098 vectors = pci_alloc_irq_vectors(pdev, 2099 hdev->roce_base_msix_offset + 1, 2100 hdev->num_msi, 2101 PCI_IRQ_MSIX); 2102 else 2103 vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi, 2104 PCI_IRQ_MSI | PCI_IRQ_MSIX); 2105 2106 if (vectors < 0) { 2107 dev_err(&pdev->dev, 2108 "failed(%d) to allocate MSI/MSI-X vectors\n", 2109 vectors); 2110 return vectors; 2111 } 2112 if (vectors < hdev->num_msi) 2113 dev_warn(&hdev->pdev->dev, 2114 "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n", 2115 hdev->num_msi, vectors); 2116 2117 hdev->num_msi = vectors; 2118 hdev->num_msi_left = vectors; 2119 hdev->base_msi_vector = pdev->irq; 2120 hdev->roce_base_vector = pdev->irq + hdev->roce_base_msix_offset; 2121 2122 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 2123 sizeof(u16), GFP_KERNEL); 2124 if (!hdev->vector_status) { 2125 pci_free_irq_vectors(pdev); 2126 return -ENOMEM; 2127 } 2128 2129 for (i = 0; i < hdev->num_msi; i++) 2130 hdev->vector_status[i] = HCLGEVF_INVALID_VPORT; 2131 2132 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 2133 sizeof(int), GFP_KERNEL); 2134 if (!hdev->vector_irq) { 2135 devm_kfree(&pdev->dev, hdev->vector_status); 2136 pci_free_irq_vectors(pdev); 2137 return -ENOMEM; 2138 } 2139 2140 return 0; 2141 } 2142 2143 static void hclgevf_uninit_msi(struct hclgevf_dev *hdev) 2144 { 2145 struct pci_dev *pdev = hdev->pdev; 2146 2147 devm_kfree(&pdev->dev, hdev->vector_status); 2148 devm_kfree(&pdev->dev, hdev->vector_irq); 2149 pci_free_irq_vectors(pdev); 2150 } 2151 2152 static int hclgevf_misc_irq_init(struct hclgevf_dev *hdev) 2153 { 2154 int ret = 0; 2155 2156 hclgevf_get_misc_vector(hdev); 2157 2158 ret = request_irq(hdev->misc_vector.vector_irq, hclgevf_misc_irq_handle, 2159 0, "hclgevf_cmd", hdev); 2160 if (ret) { 2161 dev_err(&hdev->pdev->dev, "VF failed to request misc irq(%d)\n", 2162 hdev->misc_vector.vector_irq); 2163 return ret; 2164 } 2165 2166 hclgevf_clear_event_cause(hdev, 0); 2167 2168 /* enable misc. vector(vector 0) */ 2169 hclgevf_enable_vector(&hdev->misc_vector, true); 2170 2171 return ret; 2172 } 2173 2174 static void hclgevf_misc_irq_uninit(struct hclgevf_dev *hdev) 2175 { 2176 /* disable misc vector(vector 0) */ 2177 hclgevf_enable_vector(&hdev->misc_vector, false); 2178 synchronize_irq(hdev->misc_vector.vector_irq); 2179 free_irq(hdev->misc_vector.vector_irq, hdev); 2180 hclgevf_free_vector(hdev, 0); 2181 } 2182 2183 static int hclgevf_init_client_instance(struct hnae3_client *client, 2184 struct hnae3_ae_dev *ae_dev) 2185 { 2186 struct hclgevf_dev *hdev = ae_dev->priv; 2187 int ret; 2188 2189 switch (client->type) { 2190 case HNAE3_CLIENT_KNIC: 2191 hdev->nic_client = client; 2192 hdev->nic.client = client; 2193 2194 ret = client->ops->init_instance(&hdev->nic); 2195 if (ret) 2196 goto clear_nic; 2197 2198 hnae3_set_client_init_flag(client, ae_dev, 1); 2199 2200 if (hdev->roce_client && hnae3_dev_roce_supported(hdev)) { 2201 struct hnae3_client *rc = hdev->roce_client; 2202 2203 ret = hclgevf_init_roce_base_info(hdev); 2204 if (ret) 2205 goto clear_roce; 2206 ret = rc->ops->init_instance(&hdev->roce); 2207 if (ret) 2208 goto clear_roce; 2209 2210 hnae3_set_client_init_flag(hdev->roce_client, ae_dev, 2211 1); 2212 } 2213 break; 2214 case HNAE3_CLIENT_UNIC: 2215 hdev->nic_client = client; 2216 hdev->nic.client = client; 2217 2218 ret = client->ops->init_instance(&hdev->nic); 2219 if (ret) 2220 goto clear_nic; 2221 2222 hnae3_set_client_init_flag(client, ae_dev, 1); 2223 break; 2224 case HNAE3_CLIENT_ROCE: 2225 if (hnae3_dev_roce_supported(hdev)) { 2226 hdev->roce_client = client; 2227 hdev->roce.client = client; 2228 } 2229 2230 if (hdev->roce_client && hdev->nic_client) { 2231 ret = hclgevf_init_roce_base_info(hdev); 2232 if (ret) 2233 goto clear_roce; 2234 2235 ret = client->ops->init_instance(&hdev->roce); 2236 if (ret) 2237 goto clear_roce; 2238 } 2239 2240 hnae3_set_client_init_flag(client, ae_dev, 1); 2241 break; 2242 default: 2243 return -EINVAL; 2244 } 2245 2246 return 0; 2247 2248 clear_nic: 2249 hdev->nic_client = NULL; 2250 hdev->nic.client = NULL; 2251 return ret; 2252 clear_roce: 2253 hdev->roce_client = NULL; 2254 hdev->roce.client = NULL; 2255 return ret; 2256 } 2257 2258 static void hclgevf_uninit_client_instance(struct hnae3_client *client, 2259 struct hnae3_ae_dev *ae_dev) 2260 { 2261 struct hclgevf_dev *hdev = ae_dev->priv; 2262 2263 /* un-init roce, if it exists */ 2264 if (hdev->roce_client) { 2265 hdev->roce_client->ops->uninit_instance(&hdev->roce, 0); 2266 hdev->roce_client = NULL; 2267 hdev->roce.client = NULL; 2268 } 2269 2270 /* un-init nic/unic, if this was not called by roce client */ 2271 if (client->ops->uninit_instance && hdev->nic_client && 2272 client->type != HNAE3_CLIENT_ROCE) { 2273 client->ops->uninit_instance(&hdev->nic, 0); 2274 hdev->nic_client = NULL; 2275 hdev->nic.client = NULL; 2276 } 2277 } 2278 2279 static int hclgevf_pci_init(struct hclgevf_dev *hdev) 2280 { 2281 struct pci_dev *pdev = hdev->pdev; 2282 struct hclgevf_hw *hw; 2283 int ret; 2284 2285 ret = pci_enable_device(pdev); 2286 if (ret) { 2287 dev_err(&pdev->dev, "failed to enable PCI device\n"); 2288 return ret; 2289 } 2290 2291 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 2292 if (ret) { 2293 dev_err(&pdev->dev, "can't set consistent PCI DMA, exiting"); 2294 goto err_disable_device; 2295 } 2296 2297 ret = pci_request_regions(pdev, HCLGEVF_DRIVER_NAME); 2298 if (ret) { 2299 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 2300 goto err_disable_device; 2301 } 2302 2303 pci_set_master(pdev); 2304 hw = &hdev->hw; 2305 hw->hdev = hdev; 2306 hw->io_base = pci_iomap(pdev, 2, 0); 2307 if (!hw->io_base) { 2308 dev_err(&pdev->dev, "can't map configuration register space\n"); 2309 ret = -ENOMEM; 2310 goto err_clr_master; 2311 } 2312 2313 return 0; 2314 2315 err_clr_master: 2316 pci_clear_master(pdev); 2317 pci_release_regions(pdev); 2318 err_disable_device: 2319 pci_disable_device(pdev); 2320 2321 return ret; 2322 } 2323 2324 static void hclgevf_pci_uninit(struct hclgevf_dev *hdev) 2325 { 2326 struct pci_dev *pdev = hdev->pdev; 2327 2328 pci_iounmap(pdev, hdev->hw.io_base); 2329 pci_clear_master(pdev); 2330 pci_release_regions(pdev); 2331 pci_disable_device(pdev); 2332 } 2333 2334 static int hclgevf_query_vf_resource(struct hclgevf_dev *hdev) 2335 { 2336 struct hclgevf_query_res_cmd *req; 2337 struct hclgevf_desc desc; 2338 int ret; 2339 2340 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_VF_RSRC, true); 2341 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 2342 if (ret) { 2343 dev_err(&hdev->pdev->dev, 2344 "query vf resource failed, ret = %d.\n", ret); 2345 return ret; 2346 } 2347 2348 req = (struct hclgevf_query_res_cmd *)desc.data; 2349 2350 if (hnae3_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B)) { 2351 hdev->roce_base_msix_offset = 2352 hnae3_get_field(__le16_to_cpu(req->msixcap_localid_ba_rocee), 2353 HCLGEVF_MSIX_OFT_ROCEE_M, 2354 HCLGEVF_MSIX_OFT_ROCEE_S); 2355 hdev->num_roce_msix = 2356 hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number), 2357 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 2358 2359 /* VF should have NIC vectors and Roce vectors, NIC vectors 2360 * are queued before Roce vectors. The offset is fixed to 64. 2361 */ 2362 hdev->num_msi = hdev->num_roce_msix + 2363 hdev->roce_base_msix_offset; 2364 } else { 2365 hdev->num_msi = 2366 hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number), 2367 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 2368 } 2369 2370 return 0; 2371 } 2372 2373 static int hclgevf_pci_reset(struct hclgevf_dev *hdev) 2374 { 2375 struct pci_dev *pdev = hdev->pdev; 2376 int ret = 0; 2377 2378 if (hdev->reset_type == HNAE3_VF_FULL_RESET && 2379 test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2380 hclgevf_misc_irq_uninit(hdev); 2381 hclgevf_uninit_msi(hdev); 2382 clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2383 } 2384 2385 if (!test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2386 pci_set_master(pdev); 2387 ret = hclgevf_init_msi(hdev); 2388 if (ret) { 2389 dev_err(&pdev->dev, 2390 "failed(%d) to init MSI/MSI-X\n", ret); 2391 return ret; 2392 } 2393 2394 ret = hclgevf_misc_irq_init(hdev); 2395 if (ret) { 2396 hclgevf_uninit_msi(hdev); 2397 dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 2398 ret); 2399 return ret; 2400 } 2401 2402 set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2403 } 2404 2405 return ret; 2406 } 2407 2408 static int hclgevf_reset_hdev(struct hclgevf_dev *hdev) 2409 { 2410 struct pci_dev *pdev = hdev->pdev; 2411 int ret; 2412 2413 ret = hclgevf_pci_reset(hdev); 2414 if (ret) { 2415 dev_err(&pdev->dev, "pci reset failed %d\n", ret); 2416 return ret; 2417 } 2418 2419 ret = hclgevf_cmd_init(hdev); 2420 if (ret) { 2421 dev_err(&pdev->dev, "cmd failed %d\n", ret); 2422 return ret; 2423 } 2424 2425 ret = hclgevf_rss_init_hw(hdev); 2426 if (ret) { 2427 dev_err(&hdev->pdev->dev, 2428 "failed(%d) to initialize RSS\n", ret); 2429 return ret; 2430 } 2431 2432 ret = hclgevf_config_gro(hdev, true); 2433 if (ret) 2434 return ret; 2435 2436 ret = hclgevf_init_vlan_config(hdev); 2437 if (ret) { 2438 dev_err(&hdev->pdev->dev, 2439 "failed(%d) to initialize VLAN config\n", ret); 2440 return ret; 2441 } 2442 2443 dev_info(&hdev->pdev->dev, "Reset done\n"); 2444 2445 return 0; 2446 } 2447 2448 static int hclgevf_init_hdev(struct hclgevf_dev *hdev) 2449 { 2450 struct pci_dev *pdev = hdev->pdev; 2451 int ret; 2452 2453 ret = hclgevf_pci_init(hdev); 2454 if (ret) { 2455 dev_err(&pdev->dev, "PCI initialization failed\n"); 2456 return ret; 2457 } 2458 2459 ret = hclgevf_cmd_queue_init(hdev); 2460 if (ret) { 2461 dev_err(&pdev->dev, "Cmd queue init failed: %d\n", ret); 2462 goto err_cmd_queue_init; 2463 } 2464 2465 ret = hclgevf_cmd_init(hdev); 2466 if (ret) 2467 goto err_cmd_init; 2468 2469 /* Get vf resource */ 2470 ret = hclgevf_query_vf_resource(hdev); 2471 if (ret) { 2472 dev_err(&hdev->pdev->dev, 2473 "Query vf status error, ret = %d.\n", ret); 2474 goto err_cmd_init; 2475 } 2476 2477 ret = hclgevf_init_msi(hdev); 2478 if (ret) { 2479 dev_err(&pdev->dev, "failed(%d) to init MSI/MSI-X\n", ret); 2480 goto err_cmd_init; 2481 } 2482 2483 hclgevf_state_init(hdev); 2484 hdev->reset_level = HNAE3_VF_FUNC_RESET; 2485 2486 ret = hclgevf_misc_irq_init(hdev); 2487 if (ret) { 2488 dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 2489 ret); 2490 goto err_misc_irq_init; 2491 } 2492 2493 set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2494 2495 ret = hclgevf_configure(hdev); 2496 if (ret) { 2497 dev_err(&pdev->dev, "failed(%d) to fetch configuration\n", ret); 2498 goto err_config; 2499 } 2500 2501 ret = hclgevf_alloc_tqps(hdev); 2502 if (ret) { 2503 dev_err(&pdev->dev, "failed(%d) to allocate TQPs\n", ret); 2504 goto err_config; 2505 } 2506 2507 ret = hclgevf_set_handle_info(hdev); 2508 if (ret) { 2509 dev_err(&pdev->dev, "failed(%d) to set handle info\n", ret); 2510 goto err_config; 2511 } 2512 2513 ret = hclgevf_config_gro(hdev, true); 2514 if (ret) 2515 goto err_config; 2516 2517 /* vf is not allowed to enable unicast/multicast promisc mode. 2518 * For revision 0x20, default to disable broadcast promisc mode, 2519 * firmware makes sure broadcast packets can be accepted. 2520 * For revision 0x21, default to enable broadcast promisc mode. 2521 */ 2522 ret = hclgevf_set_promisc_mode(hdev, true); 2523 if (ret) 2524 goto err_config; 2525 2526 /* Initialize RSS for this VF */ 2527 ret = hclgevf_rss_init_hw(hdev); 2528 if (ret) { 2529 dev_err(&hdev->pdev->dev, 2530 "failed(%d) to initialize RSS\n", ret); 2531 goto err_config; 2532 } 2533 2534 ret = hclgevf_init_vlan_config(hdev); 2535 if (ret) { 2536 dev_err(&hdev->pdev->dev, 2537 "failed(%d) to initialize VLAN config\n", ret); 2538 goto err_config; 2539 } 2540 2541 hdev->last_reset_time = jiffies; 2542 pr_info("finished initializing %s driver\n", HCLGEVF_DRIVER_NAME); 2543 2544 return 0; 2545 2546 err_config: 2547 hclgevf_misc_irq_uninit(hdev); 2548 err_misc_irq_init: 2549 hclgevf_state_uninit(hdev); 2550 hclgevf_uninit_msi(hdev); 2551 err_cmd_init: 2552 hclgevf_cmd_uninit(hdev); 2553 err_cmd_queue_init: 2554 hclgevf_pci_uninit(hdev); 2555 clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2556 return ret; 2557 } 2558 2559 static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev) 2560 { 2561 hclgevf_state_uninit(hdev); 2562 2563 if (test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2564 hclgevf_misc_irq_uninit(hdev); 2565 hclgevf_uninit_msi(hdev); 2566 } 2567 2568 hclgevf_pci_uninit(hdev); 2569 hclgevf_cmd_uninit(hdev); 2570 } 2571 2572 static int hclgevf_init_ae_dev(struct hnae3_ae_dev *ae_dev) 2573 { 2574 struct pci_dev *pdev = ae_dev->pdev; 2575 struct hclgevf_dev *hdev; 2576 int ret; 2577 2578 ret = hclgevf_alloc_hdev(ae_dev); 2579 if (ret) { 2580 dev_err(&pdev->dev, "hclge device allocation failed\n"); 2581 return ret; 2582 } 2583 2584 ret = hclgevf_init_hdev(ae_dev->priv); 2585 if (ret) { 2586 dev_err(&pdev->dev, "hclge device initialization failed\n"); 2587 return ret; 2588 } 2589 2590 hdev = ae_dev->priv; 2591 timer_setup(&hdev->keep_alive_timer, hclgevf_keep_alive_timer, 0); 2592 INIT_WORK(&hdev->keep_alive_task, hclgevf_keep_alive_task); 2593 2594 return 0; 2595 } 2596 2597 static void hclgevf_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 2598 { 2599 struct hclgevf_dev *hdev = ae_dev->priv; 2600 2601 hclgevf_uninit_hdev(hdev); 2602 ae_dev->priv = NULL; 2603 } 2604 2605 static u32 hclgevf_get_max_channels(struct hclgevf_dev *hdev) 2606 { 2607 struct hnae3_handle *nic = &hdev->nic; 2608 struct hnae3_knic_private_info *kinfo = &nic->kinfo; 2609 2610 return min_t(u32, hdev->rss_size_max, 2611 hdev->num_tqps / kinfo->num_tc); 2612 } 2613 2614 /** 2615 * hclgevf_get_channels - Get the current channels enabled and max supported. 2616 * @handle: hardware information for network interface 2617 * @ch: ethtool channels structure 2618 * 2619 * We don't support separate tx and rx queues as channels. The other count 2620 * represents how many queues are being used for control. max_combined counts 2621 * how many queue pairs we can support. They may not be mapped 1 to 1 with 2622 * q_vectors since we support a lot more queue pairs than q_vectors. 2623 **/ 2624 static void hclgevf_get_channels(struct hnae3_handle *handle, 2625 struct ethtool_channels *ch) 2626 { 2627 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2628 2629 ch->max_combined = hclgevf_get_max_channels(hdev); 2630 ch->other_count = 0; 2631 ch->max_other = 0; 2632 ch->combined_count = handle->kinfo.rss_size; 2633 } 2634 2635 static void hclgevf_get_tqps_and_rss_info(struct hnae3_handle *handle, 2636 u16 *alloc_tqps, u16 *max_rss_size) 2637 { 2638 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2639 2640 *alloc_tqps = hdev->num_tqps; 2641 *max_rss_size = hdev->rss_size_max; 2642 } 2643 2644 static int hclgevf_get_status(struct hnae3_handle *handle) 2645 { 2646 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2647 2648 return hdev->hw.mac.link; 2649 } 2650 2651 static void hclgevf_get_ksettings_an_result(struct hnae3_handle *handle, 2652 u8 *auto_neg, u32 *speed, 2653 u8 *duplex) 2654 { 2655 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2656 2657 if (speed) 2658 *speed = hdev->hw.mac.speed; 2659 if (duplex) 2660 *duplex = hdev->hw.mac.duplex; 2661 if (auto_neg) 2662 *auto_neg = AUTONEG_DISABLE; 2663 } 2664 2665 void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed, 2666 u8 duplex) 2667 { 2668 hdev->hw.mac.speed = speed; 2669 hdev->hw.mac.duplex = duplex; 2670 } 2671 2672 static int hclgevf_gro_en(struct hnae3_handle *handle, bool enable) 2673 { 2674 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2675 2676 return hclgevf_config_gro(hdev, enable); 2677 } 2678 2679 static void hclgevf_get_media_type(struct hnae3_handle *handle, 2680 u8 *media_type) 2681 { 2682 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2683 if (media_type) 2684 *media_type = hdev->hw.mac.media_type; 2685 } 2686 2687 static bool hclgevf_get_hw_reset_stat(struct hnae3_handle *handle) 2688 { 2689 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2690 2691 return !!hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 2692 } 2693 2694 static bool hclgevf_ae_dev_resetting(struct hnae3_handle *handle) 2695 { 2696 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2697 2698 return test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 2699 } 2700 2701 static unsigned long hclgevf_ae_dev_reset_cnt(struct hnae3_handle *handle) 2702 { 2703 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2704 2705 return hdev->reset_count; 2706 } 2707 2708 static void hclgevf_get_link_mode(struct hnae3_handle *handle, 2709 unsigned long *supported, 2710 unsigned long *advertising) 2711 { 2712 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2713 2714 *supported = hdev->hw.mac.supported; 2715 *advertising = hdev->hw.mac.advertising; 2716 } 2717 2718 #define MAX_SEPARATE_NUM 4 2719 #define SEPARATOR_VALUE 0xFFFFFFFF 2720 #define REG_NUM_PER_LINE 4 2721 #define REG_LEN_PER_LINE (REG_NUM_PER_LINE * sizeof(u32)) 2722 2723 static int hclgevf_get_regs_len(struct hnae3_handle *handle) 2724 { 2725 int cmdq_lines, common_lines, ring_lines, tqp_intr_lines; 2726 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2727 2728 cmdq_lines = sizeof(cmdq_reg_addr_list) / REG_LEN_PER_LINE + 1; 2729 common_lines = sizeof(common_reg_addr_list) / REG_LEN_PER_LINE + 1; 2730 ring_lines = sizeof(ring_reg_addr_list) / REG_LEN_PER_LINE + 1; 2731 tqp_intr_lines = sizeof(tqp_intr_reg_addr_list) / REG_LEN_PER_LINE + 1; 2732 2733 return (cmdq_lines + common_lines + ring_lines * hdev->num_tqps + 2734 tqp_intr_lines * (hdev->num_msi_used - 1)) * REG_LEN_PER_LINE; 2735 } 2736 2737 static void hclgevf_get_regs(struct hnae3_handle *handle, u32 *version, 2738 void *data) 2739 { 2740 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2741 int i, j, reg_um, separator_num; 2742 u32 *reg = data; 2743 2744 *version = hdev->fw_version; 2745 2746 /* fetching per-VF registers values from VF PCIe register space */ 2747 reg_um = sizeof(cmdq_reg_addr_list) / sizeof(u32); 2748 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 2749 for (i = 0; i < reg_um; i++) 2750 *reg++ = hclgevf_read_dev(&hdev->hw, cmdq_reg_addr_list[i]); 2751 for (i = 0; i < separator_num; i++) 2752 *reg++ = SEPARATOR_VALUE; 2753 2754 reg_um = sizeof(common_reg_addr_list) / sizeof(u32); 2755 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 2756 for (i = 0; i < reg_um; i++) 2757 *reg++ = hclgevf_read_dev(&hdev->hw, common_reg_addr_list[i]); 2758 for (i = 0; i < separator_num; i++) 2759 *reg++ = SEPARATOR_VALUE; 2760 2761 reg_um = sizeof(ring_reg_addr_list) / sizeof(u32); 2762 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 2763 for (j = 0; j < hdev->num_tqps; j++) { 2764 for (i = 0; i < reg_um; i++) 2765 *reg++ = hclgevf_read_dev(&hdev->hw, 2766 ring_reg_addr_list[i] + 2767 0x200 * j); 2768 for (i = 0; i < separator_num; i++) 2769 *reg++ = SEPARATOR_VALUE; 2770 } 2771 2772 reg_um = sizeof(tqp_intr_reg_addr_list) / sizeof(u32); 2773 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 2774 for (j = 0; j < hdev->num_msi_used - 1; j++) { 2775 for (i = 0; i < reg_um; i++) 2776 *reg++ = hclgevf_read_dev(&hdev->hw, 2777 tqp_intr_reg_addr_list[i] + 2778 4 * j); 2779 for (i = 0; i < separator_num; i++) 2780 *reg++ = SEPARATOR_VALUE; 2781 } 2782 } 2783 2784 static const struct hnae3_ae_ops hclgevf_ops = { 2785 .init_ae_dev = hclgevf_init_ae_dev, 2786 .uninit_ae_dev = hclgevf_uninit_ae_dev, 2787 .flr_prepare = hclgevf_flr_prepare, 2788 .flr_done = hclgevf_flr_done, 2789 .init_client_instance = hclgevf_init_client_instance, 2790 .uninit_client_instance = hclgevf_uninit_client_instance, 2791 .start = hclgevf_ae_start, 2792 .stop = hclgevf_ae_stop, 2793 .client_start = hclgevf_client_start, 2794 .client_stop = hclgevf_client_stop, 2795 .map_ring_to_vector = hclgevf_map_ring_to_vector, 2796 .unmap_ring_from_vector = hclgevf_unmap_ring_from_vector, 2797 .get_vector = hclgevf_get_vector, 2798 .put_vector = hclgevf_put_vector, 2799 .reset_queue = hclgevf_reset_tqp, 2800 .get_mac_addr = hclgevf_get_mac_addr, 2801 .set_mac_addr = hclgevf_set_mac_addr, 2802 .add_uc_addr = hclgevf_add_uc_addr, 2803 .rm_uc_addr = hclgevf_rm_uc_addr, 2804 .add_mc_addr = hclgevf_add_mc_addr, 2805 .rm_mc_addr = hclgevf_rm_mc_addr, 2806 .get_stats = hclgevf_get_stats, 2807 .update_stats = hclgevf_update_stats, 2808 .get_strings = hclgevf_get_strings, 2809 .get_sset_count = hclgevf_get_sset_count, 2810 .get_rss_key_size = hclgevf_get_rss_key_size, 2811 .get_rss_indir_size = hclgevf_get_rss_indir_size, 2812 .get_rss = hclgevf_get_rss, 2813 .set_rss = hclgevf_set_rss, 2814 .get_rss_tuple = hclgevf_get_rss_tuple, 2815 .set_rss_tuple = hclgevf_set_rss_tuple, 2816 .get_tc_size = hclgevf_get_tc_size, 2817 .get_fw_version = hclgevf_get_fw_version, 2818 .set_vlan_filter = hclgevf_set_vlan_filter, 2819 .enable_hw_strip_rxvtag = hclgevf_en_hw_strip_rxvtag, 2820 .reset_event = hclgevf_reset_event, 2821 .set_default_reset_request = hclgevf_set_def_reset_request, 2822 .get_channels = hclgevf_get_channels, 2823 .get_tqps_and_rss_info = hclgevf_get_tqps_and_rss_info, 2824 .get_regs_len = hclgevf_get_regs_len, 2825 .get_regs = hclgevf_get_regs, 2826 .get_status = hclgevf_get_status, 2827 .get_ksettings_an_result = hclgevf_get_ksettings_an_result, 2828 .get_media_type = hclgevf_get_media_type, 2829 .get_hw_reset_stat = hclgevf_get_hw_reset_stat, 2830 .ae_dev_resetting = hclgevf_ae_dev_resetting, 2831 .ae_dev_reset_cnt = hclgevf_ae_dev_reset_cnt, 2832 .set_gro_en = hclgevf_gro_en, 2833 .set_mtu = hclgevf_set_mtu, 2834 .get_global_queue_id = hclgevf_get_qid_global, 2835 .set_timer_task = hclgevf_set_timer_task, 2836 .get_link_mode = hclgevf_get_link_mode, 2837 }; 2838 2839 static struct hnae3_ae_algo ae_algovf = { 2840 .ops = &hclgevf_ops, 2841 .pdev_id_table = ae_algovf_pci_tbl, 2842 }; 2843 2844 static int hclgevf_init(void) 2845 { 2846 pr_info("%s is initializing\n", HCLGEVF_NAME); 2847 2848 hnae3_register_ae_algo(&ae_algovf); 2849 2850 return 0; 2851 } 2852 2853 static void hclgevf_exit(void) 2854 { 2855 hnae3_unregister_ae_algo(&ae_algovf); 2856 } 2857 module_init(hclgevf_init); 2858 module_exit(hclgevf_exit); 2859 2860 MODULE_LICENSE("GPL"); 2861 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 2862 MODULE_DESCRIPTION("HCLGEVF Driver"); 2863 MODULE_VERSION(HCLGEVF_MOD_VERSION); 2864