1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/etherdevice.h> 5 #include <linux/iopoll.h> 6 #include <net/rtnetlink.h> 7 #include "hclgevf_cmd.h" 8 #include "hclgevf_main.h" 9 #include "hclge_mbx.h" 10 #include "hnae3.h" 11 12 #define HCLGEVF_NAME "hclgevf" 13 14 #define HCLGEVF_RESET_MAX_FAIL_CNT 5 15 16 static int hclgevf_reset_hdev(struct hclgevf_dev *hdev); 17 static void hclgevf_task_schedule(struct hclgevf_dev *hdev, 18 unsigned long delay); 19 20 static struct hnae3_ae_algo ae_algovf; 21 22 static struct workqueue_struct *hclgevf_wq; 23 24 static const struct pci_device_id ae_algovf_pci_tbl[] = { 25 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_VF), 0}, 26 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF), 27 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 28 /* required last entry */ 29 {0, } 30 }; 31 32 static const u8 hclgevf_hash_key[] = { 33 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2, 34 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0, 35 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4, 36 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C, 37 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA 38 }; 39 40 MODULE_DEVICE_TABLE(pci, ae_algovf_pci_tbl); 41 42 static const u32 cmdq_reg_addr_list[] = {HCLGEVF_CMDQ_TX_ADDR_L_REG, 43 HCLGEVF_CMDQ_TX_ADDR_H_REG, 44 HCLGEVF_CMDQ_TX_DEPTH_REG, 45 HCLGEVF_CMDQ_TX_TAIL_REG, 46 HCLGEVF_CMDQ_TX_HEAD_REG, 47 HCLGEVF_CMDQ_RX_ADDR_L_REG, 48 HCLGEVF_CMDQ_RX_ADDR_H_REG, 49 HCLGEVF_CMDQ_RX_DEPTH_REG, 50 HCLGEVF_CMDQ_RX_TAIL_REG, 51 HCLGEVF_CMDQ_RX_HEAD_REG, 52 HCLGEVF_VECTOR0_CMDQ_SRC_REG, 53 HCLGEVF_VECTOR0_CMDQ_STATE_REG, 54 HCLGEVF_CMDQ_INTR_EN_REG, 55 HCLGEVF_CMDQ_INTR_GEN_REG}; 56 57 static const u32 common_reg_addr_list[] = {HCLGEVF_MISC_VECTOR_REG_BASE, 58 HCLGEVF_RST_ING, 59 HCLGEVF_GRO_EN_REG}; 60 61 static const u32 ring_reg_addr_list[] = {HCLGEVF_RING_RX_ADDR_L_REG, 62 HCLGEVF_RING_RX_ADDR_H_REG, 63 HCLGEVF_RING_RX_BD_NUM_REG, 64 HCLGEVF_RING_RX_BD_LENGTH_REG, 65 HCLGEVF_RING_RX_MERGE_EN_REG, 66 HCLGEVF_RING_RX_TAIL_REG, 67 HCLGEVF_RING_RX_HEAD_REG, 68 HCLGEVF_RING_RX_FBD_NUM_REG, 69 HCLGEVF_RING_RX_OFFSET_REG, 70 HCLGEVF_RING_RX_FBD_OFFSET_REG, 71 HCLGEVF_RING_RX_STASH_REG, 72 HCLGEVF_RING_RX_BD_ERR_REG, 73 HCLGEVF_RING_TX_ADDR_L_REG, 74 HCLGEVF_RING_TX_ADDR_H_REG, 75 HCLGEVF_RING_TX_BD_NUM_REG, 76 HCLGEVF_RING_TX_PRIORITY_REG, 77 HCLGEVF_RING_TX_TC_REG, 78 HCLGEVF_RING_TX_MERGE_EN_REG, 79 HCLGEVF_RING_TX_TAIL_REG, 80 HCLGEVF_RING_TX_HEAD_REG, 81 HCLGEVF_RING_TX_FBD_NUM_REG, 82 HCLGEVF_RING_TX_OFFSET_REG, 83 HCLGEVF_RING_TX_EBD_NUM_REG, 84 HCLGEVF_RING_TX_EBD_OFFSET_REG, 85 HCLGEVF_RING_TX_BD_ERR_REG, 86 HCLGEVF_RING_EN_REG}; 87 88 static const u32 tqp_intr_reg_addr_list[] = {HCLGEVF_TQP_INTR_CTRL_REG, 89 HCLGEVF_TQP_INTR_GL0_REG, 90 HCLGEVF_TQP_INTR_GL1_REG, 91 HCLGEVF_TQP_INTR_GL2_REG, 92 HCLGEVF_TQP_INTR_RL_REG}; 93 94 static struct hclgevf_dev *hclgevf_ae_get_hdev(struct hnae3_handle *handle) 95 { 96 if (!handle->client) 97 return container_of(handle, struct hclgevf_dev, nic); 98 else if (handle->client->type == HNAE3_CLIENT_ROCE) 99 return container_of(handle, struct hclgevf_dev, roce); 100 else 101 return container_of(handle, struct hclgevf_dev, nic); 102 } 103 104 static int hclgevf_tqps_update_stats(struct hnae3_handle *handle) 105 { 106 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 107 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 108 struct hclgevf_desc desc; 109 struct hclgevf_tqp *tqp; 110 int status; 111 int i; 112 113 for (i = 0; i < kinfo->num_tqps; i++) { 114 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 115 hclgevf_cmd_setup_basic_desc(&desc, 116 HCLGEVF_OPC_QUERY_RX_STATUS, 117 true); 118 119 desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 120 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 121 if (status) { 122 dev_err(&hdev->pdev->dev, 123 "Query tqp stat fail, status = %d,queue = %d\n", 124 status, i); 125 return status; 126 } 127 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd += 128 le32_to_cpu(desc.data[1]); 129 130 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_TX_STATUS, 131 true); 132 133 desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 134 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 135 if (status) { 136 dev_err(&hdev->pdev->dev, 137 "Query tqp stat fail, status = %d,queue = %d\n", 138 status, i); 139 return status; 140 } 141 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd += 142 le32_to_cpu(desc.data[1]); 143 } 144 145 return 0; 146 } 147 148 static u64 *hclgevf_tqps_get_stats(struct hnae3_handle *handle, u64 *data) 149 { 150 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 151 struct hclgevf_tqp *tqp; 152 u64 *buff = data; 153 int i; 154 155 for (i = 0; i < kinfo->num_tqps; i++) { 156 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 157 *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd; 158 } 159 for (i = 0; i < kinfo->num_tqps; i++) { 160 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 161 *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd; 162 } 163 164 return buff; 165 } 166 167 static int hclgevf_tqps_get_sset_count(struct hnae3_handle *handle, int strset) 168 { 169 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 170 171 return kinfo->num_tqps * 2; 172 } 173 174 static u8 *hclgevf_tqps_get_strings(struct hnae3_handle *handle, u8 *data) 175 { 176 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 177 u8 *buff = data; 178 int i; 179 180 for (i = 0; i < kinfo->num_tqps; i++) { 181 struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 182 struct hclgevf_tqp, q); 183 snprintf(buff, ETH_GSTRING_LEN, "txq%u_pktnum_rcd", 184 tqp->index); 185 buff += ETH_GSTRING_LEN; 186 } 187 188 for (i = 0; i < kinfo->num_tqps; i++) { 189 struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 190 struct hclgevf_tqp, q); 191 snprintf(buff, ETH_GSTRING_LEN, "rxq%u_pktnum_rcd", 192 tqp->index); 193 buff += ETH_GSTRING_LEN; 194 } 195 196 return buff; 197 } 198 199 static void hclgevf_update_stats(struct hnae3_handle *handle, 200 struct net_device_stats *net_stats) 201 { 202 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 203 int status; 204 205 status = hclgevf_tqps_update_stats(handle); 206 if (status) 207 dev_err(&hdev->pdev->dev, 208 "VF update of TQPS stats fail, status = %d.\n", 209 status); 210 } 211 212 static int hclgevf_get_sset_count(struct hnae3_handle *handle, int strset) 213 { 214 if (strset == ETH_SS_TEST) 215 return -EOPNOTSUPP; 216 else if (strset == ETH_SS_STATS) 217 return hclgevf_tqps_get_sset_count(handle, strset); 218 219 return 0; 220 } 221 222 static void hclgevf_get_strings(struct hnae3_handle *handle, u32 strset, 223 u8 *data) 224 { 225 u8 *p = (char *)data; 226 227 if (strset == ETH_SS_STATS) 228 p = hclgevf_tqps_get_strings(handle, p); 229 } 230 231 static void hclgevf_get_stats(struct hnae3_handle *handle, u64 *data) 232 { 233 hclgevf_tqps_get_stats(handle, data); 234 } 235 236 static void hclgevf_build_send_msg(struct hclge_vf_to_pf_msg *msg, u8 code, 237 u8 subcode) 238 { 239 if (msg) { 240 memset(msg, 0, sizeof(struct hclge_vf_to_pf_msg)); 241 msg->code = code; 242 msg->subcode = subcode; 243 } 244 } 245 246 static int hclgevf_get_tc_info(struct hclgevf_dev *hdev) 247 { 248 struct hclge_vf_to_pf_msg send_msg; 249 u8 resp_msg; 250 int status; 251 252 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_TCINFO, 0); 253 status = hclgevf_send_mbx_msg(hdev, &send_msg, true, &resp_msg, 254 sizeof(resp_msg)); 255 if (status) { 256 dev_err(&hdev->pdev->dev, 257 "VF request to get TC info from PF failed %d", 258 status); 259 return status; 260 } 261 262 hdev->hw_tc_map = resp_msg; 263 264 return 0; 265 } 266 267 static int hclgevf_get_port_base_vlan_filter_state(struct hclgevf_dev *hdev) 268 { 269 struct hnae3_handle *nic = &hdev->nic; 270 struct hclge_vf_to_pf_msg send_msg; 271 u8 resp_msg; 272 int ret; 273 274 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 275 HCLGE_MBX_GET_PORT_BASE_VLAN_STATE); 276 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, &resp_msg, 277 sizeof(u8)); 278 if (ret) { 279 dev_err(&hdev->pdev->dev, 280 "VF request to get port based vlan state failed %d", 281 ret); 282 return ret; 283 } 284 285 nic->port_base_vlan_state = resp_msg; 286 287 return 0; 288 } 289 290 static int hclgevf_get_queue_info(struct hclgevf_dev *hdev) 291 { 292 #define HCLGEVF_TQPS_RSS_INFO_LEN 6 293 #define HCLGEVF_TQPS_ALLOC_OFFSET 0 294 #define HCLGEVF_TQPS_RSS_SIZE_OFFSET 2 295 #define HCLGEVF_TQPS_RX_BUFFER_LEN_OFFSET 4 296 297 u8 resp_msg[HCLGEVF_TQPS_RSS_INFO_LEN]; 298 struct hclge_vf_to_pf_msg send_msg; 299 int status; 300 301 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QINFO, 0); 302 status = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 303 HCLGEVF_TQPS_RSS_INFO_LEN); 304 if (status) { 305 dev_err(&hdev->pdev->dev, 306 "VF request to get tqp info from PF failed %d", 307 status); 308 return status; 309 } 310 311 memcpy(&hdev->num_tqps, &resp_msg[HCLGEVF_TQPS_ALLOC_OFFSET], 312 sizeof(u16)); 313 memcpy(&hdev->rss_size_max, &resp_msg[HCLGEVF_TQPS_RSS_SIZE_OFFSET], 314 sizeof(u16)); 315 memcpy(&hdev->rx_buf_len, &resp_msg[HCLGEVF_TQPS_RX_BUFFER_LEN_OFFSET], 316 sizeof(u16)); 317 318 return 0; 319 } 320 321 static int hclgevf_get_queue_depth(struct hclgevf_dev *hdev) 322 { 323 #define HCLGEVF_TQPS_DEPTH_INFO_LEN 4 324 #define HCLGEVF_TQPS_NUM_TX_DESC_OFFSET 0 325 #define HCLGEVF_TQPS_NUM_RX_DESC_OFFSET 2 326 327 u8 resp_msg[HCLGEVF_TQPS_DEPTH_INFO_LEN]; 328 struct hclge_vf_to_pf_msg send_msg; 329 int ret; 330 331 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QDEPTH, 0); 332 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 333 HCLGEVF_TQPS_DEPTH_INFO_LEN); 334 if (ret) { 335 dev_err(&hdev->pdev->dev, 336 "VF request to get tqp depth info from PF failed %d", 337 ret); 338 return ret; 339 } 340 341 memcpy(&hdev->num_tx_desc, &resp_msg[HCLGEVF_TQPS_NUM_TX_DESC_OFFSET], 342 sizeof(u16)); 343 memcpy(&hdev->num_rx_desc, &resp_msg[HCLGEVF_TQPS_NUM_RX_DESC_OFFSET], 344 sizeof(u16)); 345 346 return 0; 347 } 348 349 static u16 hclgevf_get_qid_global(struct hnae3_handle *handle, u16 queue_id) 350 { 351 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 352 struct hclge_vf_to_pf_msg send_msg; 353 u16 qid_in_pf = 0; 354 u8 resp_data[2]; 355 int ret; 356 357 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QID_IN_PF, 0); 358 memcpy(send_msg.data, &queue_id, sizeof(queue_id)); 359 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_data, 360 sizeof(resp_data)); 361 if (!ret) 362 qid_in_pf = *(u16 *)resp_data; 363 364 return qid_in_pf; 365 } 366 367 static int hclgevf_get_pf_media_type(struct hclgevf_dev *hdev) 368 { 369 struct hclge_vf_to_pf_msg send_msg; 370 u8 resp_msg[2]; 371 int ret; 372 373 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_MEDIA_TYPE, 0); 374 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 375 sizeof(resp_msg)); 376 if (ret) { 377 dev_err(&hdev->pdev->dev, 378 "VF request to get the pf port media type failed %d", 379 ret); 380 return ret; 381 } 382 383 hdev->hw.mac.media_type = resp_msg[0]; 384 hdev->hw.mac.module_type = resp_msg[1]; 385 386 return 0; 387 } 388 389 static int hclgevf_alloc_tqps(struct hclgevf_dev *hdev) 390 { 391 struct hclgevf_tqp *tqp; 392 int i; 393 394 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 395 sizeof(struct hclgevf_tqp), GFP_KERNEL); 396 if (!hdev->htqp) 397 return -ENOMEM; 398 399 tqp = hdev->htqp; 400 401 for (i = 0; i < hdev->num_tqps; i++) { 402 tqp->dev = &hdev->pdev->dev; 403 tqp->index = i; 404 405 tqp->q.ae_algo = &ae_algovf; 406 tqp->q.buf_size = hdev->rx_buf_len; 407 tqp->q.tx_desc_num = hdev->num_tx_desc; 408 tqp->q.rx_desc_num = hdev->num_rx_desc; 409 410 /* need an extended offset to configure queues >= 411 * HCLGEVF_TQP_MAX_SIZE_DEV_V2. 412 */ 413 if (i < HCLGEVF_TQP_MAX_SIZE_DEV_V2) 414 tqp->q.io_base = hdev->hw.io_base + 415 HCLGEVF_TQP_REG_OFFSET + 416 i * HCLGEVF_TQP_REG_SIZE; 417 else 418 tqp->q.io_base = hdev->hw.io_base + 419 HCLGEVF_TQP_REG_OFFSET + 420 HCLGEVF_TQP_EXT_REG_OFFSET + 421 (i - HCLGEVF_TQP_MAX_SIZE_DEV_V2) * 422 HCLGEVF_TQP_REG_SIZE; 423 424 tqp++; 425 } 426 427 return 0; 428 } 429 430 static int hclgevf_knic_setup(struct hclgevf_dev *hdev) 431 { 432 struct hnae3_handle *nic = &hdev->nic; 433 struct hnae3_knic_private_info *kinfo; 434 u16 new_tqps = hdev->num_tqps; 435 unsigned int i; 436 u8 num_tc = 0; 437 438 kinfo = &nic->kinfo; 439 kinfo->num_tx_desc = hdev->num_tx_desc; 440 kinfo->num_rx_desc = hdev->num_rx_desc; 441 kinfo->rx_buf_len = hdev->rx_buf_len; 442 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) 443 if (hdev->hw_tc_map & BIT(i)) 444 num_tc++; 445 446 num_tc = num_tc ? num_tc : 1; 447 kinfo->tc_info.num_tc = num_tc; 448 kinfo->rss_size = min_t(u16, hdev->rss_size_max, new_tqps / num_tc); 449 new_tqps = kinfo->rss_size * num_tc; 450 kinfo->num_tqps = min(new_tqps, hdev->num_tqps); 451 452 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps, 453 sizeof(struct hnae3_queue *), GFP_KERNEL); 454 if (!kinfo->tqp) 455 return -ENOMEM; 456 457 for (i = 0; i < kinfo->num_tqps; i++) { 458 hdev->htqp[i].q.handle = &hdev->nic; 459 hdev->htqp[i].q.tqp_index = i; 460 kinfo->tqp[i] = &hdev->htqp[i].q; 461 } 462 463 /* after init the max rss_size and tqps, adjust the default tqp numbers 464 * and rss size with the actual vector numbers 465 */ 466 kinfo->num_tqps = min_t(u16, hdev->num_nic_msix - 1, kinfo->num_tqps); 467 kinfo->rss_size = min_t(u16, kinfo->num_tqps / num_tc, 468 kinfo->rss_size); 469 470 return 0; 471 } 472 473 static void hclgevf_request_link_info(struct hclgevf_dev *hdev) 474 { 475 struct hclge_vf_to_pf_msg send_msg; 476 int status; 477 478 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_LINK_STATUS, 0); 479 status = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 480 if (status) 481 dev_err(&hdev->pdev->dev, 482 "VF failed to fetch link status(%d) from PF", status); 483 } 484 485 void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state) 486 { 487 struct hnae3_handle *rhandle = &hdev->roce; 488 struct hnae3_handle *handle = &hdev->nic; 489 struct hnae3_client *rclient; 490 struct hnae3_client *client; 491 492 if (test_and_set_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state)) 493 return; 494 495 client = handle->client; 496 rclient = hdev->roce_client; 497 498 link_state = 499 test_bit(HCLGEVF_STATE_DOWN, &hdev->state) ? 0 : link_state; 500 if (link_state != hdev->hw.mac.link) { 501 client->ops->link_status_change(handle, !!link_state); 502 if (rclient && rclient->ops->link_status_change) 503 rclient->ops->link_status_change(rhandle, !!link_state); 504 hdev->hw.mac.link = link_state; 505 } 506 507 clear_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state); 508 } 509 510 static void hclgevf_update_link_mode(struct hclgevf_dev *hdev) 511 { 512 #define HCLGEVF_ADVERTISING 0 513 #define HCLGEVF_SUPPORTED 1 514 515 struct hclge_vf_to_pf_msg send_msg; 516 517 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_LINK_MODE, 0); 518 send_msg.data[0] = HCLGEVF_ADVERTISING; 519 hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 520 send_msg.data[0] = HCLGEVF_SUPPORTED; 521 hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 522 } 523 524 static int hclgevf_set_handle_info(struct hclgevf_dev *hdev) 525 { 526 struct hnae3_handle *nic = &hdev->nic; 527 int ret; 528 529 nic->ae_algo = &ae_algovf; 530 nic->pdev = hdev->pdev; 531 nic->numa_node_mask = hdev->numa_node_mask; 532 nic->flags |= HNAE3_SUPPORT_VF; 533 534 ret = hclgevf_knic_setup(hdev); 535 if (ret) 536 dev_err(&hdev->pdev->dev, "VF knic setup failed %d\n", 537 ret); 538 return ret; 539 } 540 541 static void hclgevf_free_vector(struct hclgevf_dev *hdev, int vector_id) 542 { 543 if (hdev->vector_status[vector_id] == HCLGEVF_INVALID_VPORT) { 544 dev_warn(&hdev->pdev->dev, 545 "vector(vector_id %d) has been freed.\n", vector_id); 546 return; 547 } 548 549 hdev->vector_status[vector_id] = HCLGEVF_INVALID_VPORT; 550 hdev->num_msi_left += 1; 551 hdev->num_msi_used -= 1; 552 } 553 554 static int hclgevf_get_vector(struct hnae3_handle *handle, u16 vector_num, 555 struct hnae3_vector_info *vector_info) 556 { 557 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 558 struct hnae3_vector_info *vector = vector_info; 559 int alloc = 0; 560 int i, j; 561 562 vector_num = min_t(u16, hdev->num_nic_msix - 1, vector_num); 563 vector_num = min(hdev->num_msi_left, vector_num); 564 565 for (j = 0; j < vector_num; j++) { 566 for (i = HCLGEVF_MISC_VECTOR_NUM + 1; i < hdev->num_msi; i++) { 567 if (hdev->vector_status[i] == HCLGEVF_INVALID_VPORT) { 568 vector->vector = pci_irq_vector(hdev->pdev, i); 569 vector->io_addr = hdev->hw.io_base + 570 HCLGEVF_VECTOR_REG_BASE + 571 (i - 1) * HCLGEVF_VECTOR_REG_OFFSET; 572 hdev->vector_status[i] = 0; 573 hdev->vector_irq[i] = vector->vector; 574 575 vector++; 576 alloc++; 577 578 break; 579 } 580 } 581 } 582 hdev->num_msi_left -= alloc; 583 hdev->num_msi_used += alloc; 584 585 return alloc; 586 } 587 588 static int hclgevf_get_vector_index(struct hclgevf_dev *hdev, int vector) 589 { 590 int i; 591 592 for (i = 0; i < hdev->num_msi; i++) 593 if (vector == hdev->vector_irq[i]) 594 return i; 595 596 return -EINVAL; 597 } 598 599 static int hclgevf_set_rss_algo_key(struct hclgevf_dev *hdev, 600 const u8 hfunc, const u8 *key) 601 { 602 struct hclgevf_rss_config_cmd *req; 603 unsigned int key_offset = 0; 604 struct hclgevf_desc desc; 605 int key_counts; 606 int key_size; 607 int ret; 608 609 key_counts = HCLGEVF_RSS_KEY_SIZE; 610 req = (struct hclgevf_rss_config_cmd *)desc.data; 611 612 while (key_counts) { 613 hclgevf_cmd_setup_basic_desc(&desc, 614 HCLGEVF_OPC_RSS_GENERIC_CONFIG, 615 false); 616 617 req->hash_config |= (hfunc & HCLGEVF_RSS_HASH_ALGO_MASK); 618 req->hash_config |= 619 (key_offset << HCLGEVF_RSS_HASH_KEY_OFFSET_B); 620 621 key_size = min(HCLGEVF_RSS_HASH_KEY_NUM, key_counts); 622 memcpy(req->hash_key, 623 key + key_offset * HCLGEVF_RSS_HASH_KEY_NUM, key_size); 624 625 key_counts -= key_size; 626 key_offset++; 627 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 628 if (ret) { 629 dev_err(&hdev->pdev->dev, 630 "Configure RSS config fail, status = %d\n", 631 ret); 632 return ret; 633 } 634 } 635 636 return 0; 637 } 638 639 static u32 hclgevf_get_rss_key_size(struct hnae3_handle *handle) 640 { 641 return HCLGEVF_RSS_KEY_SIZE; 642 } 643 644 static int hclgevf_set_rss_indir_table(struct hclgevf_dev *hdev) 645 { 646 const u8 *indir = hdev->rss_cfg.rss_indirection_tbl; 647 struct hclgevf_rss_indirection_table_cmd *req; 648 struct hclgevf_desc desc; 649 int rss_cfg_tbl_num; 650 int status; 651 int i, j; 652 653 req = (struct hclgevf_rss_indirection_table_cmd *)desc.data; 654 rss_cfg_tbl_num = hdev->ae_dev->dev_specs.rss_ind_tbl_size / 655 HCLGEVF_RSS_CFG_TBL_SIZE; 656 657 for (i = 0; i < rss_cfg_tbl_num; i++) { 658 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INDIR_TABLE, 659 false); 660 req->start_table_index = 661 cpu_to_le16(i * HCLGEVF_RSS_CFG_TBL_SIZE); 662 req->rss_set_bitmap = cpu_to_le16(HCLGEVF_RSS_SET_BITMAP_MSK); 663 for (j = 0; j < HCLGEVF_RSS_CFG_TBL_SIZE; j++) 664 req->rss_result[j] = 665 indir[i * HCLGEVF_RSS_CFG_TBL_SIZE + j]; 666 667 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 668 if (status) { 669 dev_err(&hdev->pdev->dev, 670 "VF failed(=%d) to set RSS indirection table\n", 671 status); 672 return status; 673 } 674 } 675 676 return 0; 677 } 678 679 static int hclgevf_set_rss_tc_mode(struct hclgevf_dev *hdev, u16 rss_size) 680 { 681 struct hclgevf_rss_tc_mode_cmd *req; 682 u16 tc_offset[HCLGEVF_MAX_TC_NUM]; 683 u16 tc_valid[HCLGEVF_MAX_TC_NUM]; 684 u16 tc_size[HCLGEVF_MAX_TC_NUM]; 685 struct hclgevf_desc desc; 686 u16 roundup_size; 687 unsigned int i; 688 int status; 689 690 req = (struct hclgevf_rss_tc_mode_cmd *)desc.data; 691 692 roundup_size = roundup_pow_of_two(rss_size); 693 roundup_size = ilog2(roundup_size); 694 695 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 696 tc_valid[i] = !!(hdev->hw_tc_map & BIT(i)); 697 tc_size[i] = roundup_size; 698 tc_offset[i] = rss_size * i; 699 } 700 701 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_TC_MODE, false); 702 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 703 u16 mode = 0; 704 705 hnae3_set_bit(mode, HCLGEVF_RSS_TC_VALID_B, 706 (tc_valid[i] & 0x1)); 707 hnae3_set_field(mode, HCLGEVF_RSS_TC_SIZE_M, 708 HCLGEVF_RSS_TC_SIZE_S, tc_size[i]); 709 hnae3_set_field(mode, HCLGEVF_RSS_TC_OFFSET_M, 710 HCLGEVF_RSS_TC_OFFSET_S, tc_offset[i]); 711 712 req->rss_tc_mode[i] = cpu_to_le16(mode); 713 } 714 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 715 if (status) 716 dev_err(&hdev->pdev->dev, 717 "VF failed(=%d) to set rss tc mode\n", status); 718 719 return status; 720 } 721 722 /* for revision 0x20, vf shared the same rss config with pf */ 723 static int hclgevf_get_rss_hash_key(struct hclgevf_dev *hdev) 724 { 725 #define HCLGEVF_RSS_MBX_RESP_LEN 8 726 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 727 u8 resp_msg[HCLGEVF_RSS_MBX_RESP_LEN]; 728 struct hclge_vf_to_pf_msg send_msg; 729 u16 msg_num, hash_key_index; 730 u8 index; 731 int ret; 732 733 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_RSS_KEY, 0); 734 msg_num = (HCLGEVF_RSS_KEY_SIZE + HCLGEVF_RSS_MBX_RESP_LEN - 1) / 735 HCLGEVF_RSS_MBX_RESP_LEN; 736 for (index = 0; index < msg_num; index++) { 737 send_msg.data[0] = index; 738 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 739 HCLGEVF_RSS_MBX_RESP_LEN); 740 if (ret) { 741 dev_err(&hdev->pdev->dev, 742 "VF get rss hash key from PF failed, ret=%d", 743 ret); 744 return ret; 745 } 746 747 hash_key_index = HCLGEVF_RSS_MBX_RESP_LEN * index; 748 if (index == msg_num - 1) 749 memcpy(&rss_cfg->rss_hash_key[hash_key_index], 750 &resp_msg[0], 751 HCLGEVF_RSS_KEY_SIZE - hash_key_index); 752 else 753 memcpy(&rss_cfg->rss_hash_key[hash_key_index], 754 &resp_msg[0], HCLGEVF_RSS_MBX_RESP_LEN); 755 } 756 757 return 0; 758 } 759 760 static int hclgevf_get_rss(struct hnae3_handle *handle, u32 *indir, u8 *key, 761 u8 *hfunc) 762 { 763 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 764 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 765 int i, ret; 766 767 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 768 /* Get hash algorithm */ 769 if (hfunc) { 770 switch (rss_cfg->hash_algo) { 771 case HCLGEVF_RSS_HASH_ALGO_TOEPLITZ: 772 *hfunc = ETH_RSS_HASH_TOP; 773 break; 774 case HCLGEVF_RSS_HASH_ALGO_SIMPLE: 775 *hfunc = ETH_RSS_HASH_XOR; 776 break; 777 default: 778 *hfunc = ETH_RSS_HASH_UNKNOWN; 779 break; 780 } 781 } 782 783 /* Get the RSS Key required by the user */ 784 if (key) 785 memcpy(key, rss_cfg->rss_hash_key, 786 HCLGEVF_RSS_KEY_SIZE); 787 } else { 788 if (hfunc) 789 *hfunc = ETH_RSS_HASH_TOP; 790 if (key) { 791 ret = hclgevf_get_rss_hash_key(hdev); 792 if (ret) 793 return ret; 794 memcpy(key, rss_cfg->rss_hash_key, 795 HCLGEVF_RSS_KEY_SIZE); 796 } 797 } 798 799 if (indir) 800 for (i = 0; i < hdev->ae_dev->dev_specs.rss_ind_tbl_size; i++) 801 indir[i] = rss_cfg->rss_indirection_tbl[i]; 802 803 return 0; 804 } 805 806 static int hclgevf_set_rss(struct hnae3_handle *handle, const u32 *indir, 807 const u8 *key, const u8 hfunc) 808 { 809 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 810 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 811 int ret, i; 812 813 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 814 /* Set the RSS Hash Key if specififed by the user */ 815 if (key) { 816 switch (hfunc) { 817 case ETH_RSS_HASH_TOP: 818 rss_cfg->hash_algo = 819 HCLGEVF_RSS_HASH_ALGO_TOEPLITZ; 820 break; 821 case ETH_RSS_HASH_XOR: 822 rss_cfg->hash_algo = 823 HCLGEVF_RSS_HASH_ALGO_SIMPLE; 824 break; 825 case ETH_RSS_HASH_NO_CHANGE: 826 break; 827 default: 828 return -EINVAL; 829 } 830 831 ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 832 key); 833 if (ret) 834 return ret; 835 836 /* Update the shadow RSS key with user specified qids */ 837 memcpy(rss_cfg->rss_hash_key, key, 838 HCLGEVF_RSS_KEY_SIZE); 839 } 840 } 841 842 /* update the shadow RSS table with user specified qids */ 843 for (i = 0; i < hdev->ae_dev->dev_specs.rss_ind_tbl_size; i++) 844 rss_cfg->rss_indirection_tbl[i] = indir[i]; 845 846 /* update the hardware */ 847 return hclgevf_set_rss_indir_table(hdev); 848 } 849 850 static u8 hclgevf_get_rss_hash_bits(struct ethtool_rxnfc *nfc) 851 { 852 u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGEVF_S_PORT_BIT : 0; 853 854 if (nfc->data & RXH_L4_B_2_3) 855 hash_sets |= HCLGEVF_D_PORT_BIT; 856 else 857 hash_sets &= ~HCLGEVF_D_PORT_BIT; 858 859 if (nfc->data & RXH_IP_SRC) 860 hash_sets |= HCLGEVF_S_IP_BIT; 861 else 862 hash_sets &= ~HCLGEVF_S_IP_BIT; 863 864 if (nfc->data & RXH_IP_DST) 865 hash_sets |= HCLGEVF_D_IP_BIT; 866 else 867 hash_sets &= ~HCLGEVF_D_IP_BIT; 868 869 if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW) 870 hash_sets |= HCLGEVF_V_TAG_BIT; 871 872 return hash_sets; 873 } 874 875 static int hclgevf_init_rss_tuple_cmd(struct hnae3_handle *handle, 876 struct ethtool_rxnfc *nfc, 877 struct hclgevf_rss_input_tuple_cmd *req) 878 { 879 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 880 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 881 u8 tuple_sets; 882 883 req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 884 req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 885 req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 886 req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 887 req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 888 req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 889 req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 890 req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 891 892 tuple_sets = hclgevf_get_rss_hash_bits(nfc); 893 switch (nfc->flow_type) { 894 case TCP_V4_FLOW: 895 req->ipv4_tcp_en = tuple_sets; 896 break; 897 case TCP_V6_FLOW: 898 req->ipv6_tcp_en = tuple_sets; 899 break; 900 case UDP_V4_FLOW: 901 req->ipv4_udp_en = tuple_sets; 902 break; 903 case UDP_V6_FLOW: 904 req->ipv6_udp_en = tuple_sets; 905 break; 906 case SCTP_V4_FLOW: 907 req->ipv4_sctp_en = tuple_sets; 908 break; 909 case SCTP_V6_FLOW: 910 if (hdev->ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2 && 911 (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3))) 912 return -EINVAL; 913 914 req->ipv6_sctp_en = tuple_sets; 915 break; 916 case IPV4_FLOW: 917 req->ipv4_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 918 break; 919 case IPV6_FLOW: 920 req->ipv6_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 921 break; 922 default: 923 return -EINVAL; 924 } 925 926 return 0; 927 } 928 929 static int hclgevf_set_rss_tuple(struct hnae3_handle *handle, 930 struct ethtool_rxnfc *nfc) 931 { 932 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 933 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 934 struct hclgevf_rss_input_tuple_cmd *req; 935 struct hclgevf_desc desc; 936 int ret; 937 938 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 939 return -EOPNOTSUPP; 940 941 if (nfc->data & 942 ~(RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3)) 943 return -EINVAL; 944 945 req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 946 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 947 948 ret = hclgevf_init_rss_tuple_cmd(handle, nfc, req); 949 if (ret) { 950 dev_err(&hdev->pdev->dev, 951 "failed to init rss tuple cmd, ret = %d\n", ret); 952 return ret; 953 } 954 955 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 956 if (ret) { 957 dev_err(&hdev->pdev->dev, 958 "Set rss tuple fail, status = %d\n", ret); 959 return ret; 960 } 961 962 rss_cfg->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en; 963 rss_cfg->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en; 964 rss_cfg->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en; 965 rss_cfg->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en; 966 rss_cfg->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en; 967 rss_cfg->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en; 968 rss_cfg->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en; 969 rss_cfg->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en; 970 return 0; 971 } 972 973 static int hclgevf_get_rss_tuple_by_flow_type(struct hclgevf_dev *hdev, 974 int flow_type, u8 *tuple_sets) 975 { 976 switch (flow_type) { 977 case TCP_V4_FLOW: 978 *tuple_sets = hdev->rss_cfg.rss_tuple_sets.ipv4_tcp_en; 979 break; 980 case UDP_V4_FLOW: 981 *tuple_sets = hdev->rss_cfg.rss_tuple_sets.ipv4_udp_en; 982 break; 983 case TCP_V6_FLOW: 984 *tuple_sets = hdev->rss_cfg.rss_tuple_sets.ipv6_tcp_en; 985 break; 986 case UDP_V6_FLOW: 987 *tuple_sets = hdev->rss_cfg.rss_tuple_sets.ipv6_udp_en; 988 break; 989 case SCTP_V4_FLOW: 990 *tuple_sets = hdev->rss_cfg.rss_tuple_sets.ipv4_sctp_en; 991 break; 992 case SCTP_V6_FLOW: 993 *tuple_sets = hdev->rss_cfg.rss_tuple_sets.ipv6_sctp_en; 994 break; 995 case IPV4_FLOW: 996 case IPV6_FLOW: 997 *tuple_sets = HCLGEVF_S_IP_BIT | HCLGEVF_D_IP_BIT; 998 break; 999 default: 1000 return -EINVAL; 1001 } 1002 1003 return 0; 1004 } 1005 1006 static u64 hclgevf_convert_rss_tuple(u8 tuple_sets) 1007 { 1008 u64 tuple_data = 0; 1009 1010 if (tuple_sets & HCLGEVF_D_PORT_BIT) 1011 tuple_data |= RXH_L4_B_2_3; 1012 if (tuple_sets & HCLGEVF_S_PORT_BIT) 1013 tuple_data |= RXH_L4_B_0_1; 1014 if (tuple_sets & HCLGEVF_D_IP_BIT) 1015 tuple_data |= RXH_IP_DST; 1016 if (tuple_sets & HCLGEVF_S_IP_BIT) 1017 tuple_data |= RXH_IP_SRC; 1018 1019 return tuple_data; 1020 } 1021 1022 static int hclgevf_get_rss_tuple(struct hnae3_handle *handle, 1023 struct ethtool_rxnfc *nfc) 1024 { 1025 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1026 u8 tuple_sets; 1027 int ret; 1028 1029 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 1030 return -EOPNOTSUPP; 1031 1032 nfc->data = 0; 1033 1034 ret = hclgevf_get_rss_tuple_by_flow_type(hdev, nfc->flow_type, 1035 &tuple_sets); 1036 if (ret || !tuple_sets) 1037 return ret; 1038 1039 nfc->data = hclgevf_convert_rss_tuple(tuple_sets); 1040 1041 return 0; 1042 } 1043 1044 static int hclgevf_set_rss_input_tuple(struct hclgevf_dev *hdev, 1045 struct hclgevf_rss_cfg *rss_cfg) 1046 { 1047 struct hclgevf_rss_input_tuple_cmd *req; 1048 struct hclgevf_desc desc; 1049 int ret; 1050 1051 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 1052 1053 req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 1054 1055 req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 1056 req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 1057 req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 1058 req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 1059 req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 1060 req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 1061 req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 1062 req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 1063 1064 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1065 if (ret) 1066 dev_err(&hdev->pdev->dev, 1067 "Configure rss input fail, status = %d\n", ret); 1068 return ret; 1069 } 1070 1071 static int hclgevf_get_tc_size(struct hnae3_handle *handle) 1072 { 1073 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1074 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 1075 1076 return rss_cfg->rss_size; 1077 } 1078 1079 static int hclgevf_bind_ring_to_vector(struct hnae3_handle *handle, bool en, 1080 int vector_id, 1081 struct hnae3_ring_chain_node *ring_chain) 1082 { 1083 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1084 struct hclge_vf_to_pf_msg send_msg; 1085 struct hnae3_ring_chain_node *node; 1086 int status; 1087 int i = 0; 1088 1089 memset(&send_msg, 0, sizeof(send_msg)); 1090 send_msg.code = en ? HCLGE_MBX_MAP_RING_TO_VECTOR : 1091 HCLGE_MBX_UNMAP_RING_TO_VECTOR; 1092 send_msg.vector_id = vector_id; 1093 1094 for (node = ring_chain; node; node = node->next) { 1095 send_msg.param[i].ring_type = 1096 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B); 1097 1098 send_msg.param[i].tqp_index = node->tqp_index; 1099 send_msg.param[i].int_gl_index = 1100 hnae3_get_field(node->int_gl_idx, 1101 HNAE3_RING_GL_IDX_M, 1102 HNAE3_RING_GL_IDX_S); 1103 1104 i++; 1105 if (i == HCLGE_MBX_MAX_RING_CHAIN_PARAM_NUM || !node->next) { 1106 send_msg.ring_num = i; 1107 1108 status = hclgevf_send_mbx_msg(hdev, &send_msg, false, 1109 NULL, 0); 1110 if (status) { 1111 dev_err(&hdev->pdev->dev, 1112 "Map TQP fail, status is %d.\n", 1113 status); 1114 return status; 1115 } 1116 i = 0; 1117 } 1118 } 1119 1120 return 0; 1121 } 1122 1123 static int hclgevf_map_ring_to_vector(struct hnae3_handle *handle, int vector, 1124 struct hnae3_ring_chain_node *ring_chain) 1125 { 1126 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1127 int vector_id; 1128 1129 vector_id = hclgevf_get_vector_index(hdev, vector); 1130 if (vector_id < 0) { 1131 dev_err(&handle->pdev->dev, 1132 "Get vector index fail. ret =%d\n", vector_id); 1133 return vector_id; 1134 } 1135 1136 return hclgevf_bind_ring_to_vector(handle, true, vector_id, ring_chain); 1137 } 1138 1139 static int hclgevf_unmap_ring_from_vector( 1140 struct hnae3_handle *handle, 1141 int vector, 1142 struct hnae3_ring_chain_node *ring_chain) 1143 { 1144 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1145 int ret, vector_id; 1146 1147 if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 1148 return 0; 1149 1150 vector_id = hclgevf_get_vector_index(hdev, vector); 1151 if (vector_id < 0) { 1152 dev_err(&handle->pdev->dev, 1153 "Get vector index fail. ret =%d\n", vector_id); 1154 return vector_id; 1155 } 1156 1157 ret = hclgevf_bind_ring_to_vector(handle, false, vector_id, ring_chain); 1158 if (ret) 1159 dev_err(&handle->pdev->dev, 1160 "Unmap ring from vector fail. vector=%d, ret =%d\n", 1161 vector_id, 1162 ret); 1163 1164 return ret; 1165 } 1166 1167 static int hclgevf_put_vector(struct hnae3_handle *handle, int vector) 1168 { 1169 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1170 int vector_id; 1171 1172 vector_id = hclgevf_get_vector_index(hdev, vector); 1173 if (vector_id < 0) { 1174 dev_err(&handle->pdev->dev, 1175 "hclgevf_put_vector get vector index fail. ret =%d\n", 1176 vector_id); 1177 return vector_id; 1178 } 1179 1180 hclgevf_free_vector(hdev, vector_id); 1181 1182 return 0; 1183 } 1184 1185 static int hclgevf_cmd_set_promisc_mode(struct hclgevf_dev *hdev, 1186 bool en_uc_pmc, bool en_mc_pmc, 1187 bool en_bc_pmc) 1188 { 1189 struct hnae3_handle *handle = &hdev->nic; 1190 struct hclge_vf_to_pf_msg send_msg; 1191 int ret; 1192 1193 memset(&send_msg, 0, sizeof(send_msg)); 1194 send_msg.code = HCLGE_MBX_SET_PROMISC_MODE; 1195 send_msg.en_bc = en_bc_pmc ? 1 : 0; 1196 send_msg.en_uc = en_uc_pmc ? 1 : 0; 1197 send_msg.en_mc = en_mc_pmc ? 1 : 0; 1198 send_msg.en_limit_promisc = test_bit(HNAE3_PFLAG_LIMIT_PROMISC, 1199 &handle->priv_flags) ? 1 : 0; 1200 1201 ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 1202 if (ret) 1203 dev_err(&hdev->pdev->dev, 1204 "Set promisc mode fail, status is %d.\n", ret); 1205 1206 return ret; 1207 } 1208 1209 static int hclgevf_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc, 1210 bool en_mc_pmc) 1211 { 1212 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1213 bool en_bc_pmc; 1214 1215 en_bc_pmc = hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2; 1216 1217 return hclgevf_cmd_set_promisc_mode(hdev, en_uc_pmc, en_mc_pmc, 1218 en_bc_pmc); 1219 } 1220 1221 static void hclgevf_request_update_promisc_mode(struct hnae3_handle *handle) 1222 { 1223 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1224 1225 set_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state); 1226 hclgevf_task_schedule(hdev, 0); 1227 } 1228 1229 static void hclgevf_sync_promisc_mode(struct hclgevf_dev *hdev) 1230 { 1231 struct hnae3_handle *handle = &hdev->nic; 1232 bool en_uc_pmc = handle->netdev_flags & HNAE3_UPE; 1233 bool en_mc_pmc = handle->netdev_flags & HNAE3_MPE; 1234 int ret; 1235 1236 if (test_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state)) { 1237 ret = hclgevf_set_promisc_mode(handle, en_uc_pmc, en_mc_pmc); 1238 if (!ret) 1239 clear_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state); 1240 } 1241 } 1242 1243 static int hclgevf_tqp_enable(struct hclgevf_dev *hdev, unsigned int tqp_id, 1244 int stream_id, bool enable) 1245 { 1246 struct hclgevf_cfg_com_tqp_queue_cmd *req; 1247 struct hclgevf_desc desc; 1248 int status; 1249 1250 req = (struct hclgevf_cfg_com_tqp_queue_cmd *)desc.data; 1251 1252 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_CFG_COM_TQP_QUEUE, 1253 false); 1254 req->tqp_id = cpu_to_le16(tqp_id & HCLGEVF_RING_ID_MASK); 1255 req->stream_id = cpu_to_le16(stream_id); 1256 if (enable) 1257 req->enable |= 1U << HCLGEVF_TQP_ENABLE_B; 1258 1259 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1260 if (status) 1261 dev_err(&hdev->pdev->dev, 1262 "TQP enable fail, status =%d.\n", status); 1263 1264 return status; 1265 } 1266 1267 static void hclgevf_reset_tqp_stats(struct hnae3_handle *handle) 1268 { 1269 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 1270 struct hclgevf_tqp *tqp; 1271 int i; 1272 1273 for (i = 0; i < kinfo->num_tqps; i++) { 1274 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 1275 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats)); 1276 } 1277 } 1278 1279 static int hclgevf_get_host_mac_addr(struct hclgevf_dev *hdev, u8 *p) 1280 { 1281 struct hclge_vf_to_pf_msg send_msg; 1282 u8 host_mac[ETH_ALEN]; 1283 int status; 1284 1285 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_MAC_ADDR, 0); 1286 status = hclgevf_send_mbx_msg(hdev, &send_msg, true, host_mac, 1287 ETH_ALEN); 1288 if (status) { 1289 dev_err(&hdev->pdev->dev, 1290 "fail to get VF MAC from host %d", status); 1291 return status; 1292 } 1293 1294 ether_addr_copy(p, host_mac); 1295 1296 return 0; 1297 } 1298 1299 static void hclgevf_get_mac_addr(struct hnae3_handle *handle, u8 *p) 1300 { 1301 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1302 u8 host_mac_addr[ETH_ALEN]; 1303 1304 if (hclgevf_get_host_mac_addr(hdev, host_mac_addr)) 1305 return; 1306 1307 hdev->has_pf_mac = !is_zero_ether_addr(host_mac_addr); 1308 if (hdev->has_pf_mac) 1309 ether_addr_copy(p, host_mac_addr); 1310 else 1311 ether_addr_copy(p, hdev->hw.mac.mac_addr); 1312 } 1313 1314 static int hclgevf_set_mac_addr(struct hnae3_handle *handle, void *p, 1315 bool is_first) 1316 { 1317 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1318 u8 *old_mac_addr = (u8 *)hdev->hw.mac.mac_addr; 1319 struct hclge_vf_to_pf_msg send_msg; 1320 u8 *new_mac_addr = (u8 *)p; 1321 int status; 1322 1323 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_UNICAST, 0); 1324 send_msg.subcode = HCLGE_MBX_MAC_VLAN_UC_MODIFY; 1325 ether_addr_copy(send_msg.data, new_mac_addr); 1326 if (is_first && !hdev->has_pf_mac) 1327 eth_zero_addr(&send_msg.data[ETH_ALEN]); 1328 else 1329 ether_addr_copy(&send_msg.data[ETH_ALEN], old_mac_addr); 1330 status = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1331 if (!status) 1332 ether_addr_copy(hdev->hw.mac.mac_addr, new_mac_addr); 1333 1334 return status; 1335 } 1336 1337 static struct hclgevf_mac_addr_node * 1338 hclgevf_find_mac_node(struct list_head *list, const u8 *mac_addr) 1339 { 1340 struct hclgevf_mac_addr_node *mac_node, *tmp; 1341 1342 list_for_each_entry_safe(mac_node, tmp, list, node) 1343 if (ether_addr_equal(mac_addr, mac_node->mac_addr)) 1344 return mac_node; 1345 1346 return NULL; 1347 } 1348 1349 static void hclgevf_update_mac_node(struct hclgevf_mac_addr_node *mac_node, 1350 enum HCLGEVF_MAC_NODE_STATE state) 1351 { 1352 switch (state) { 1353 /* from set_rx_mode or tmp_add_list */ 1354 case HCLGEVF_MAC_TO_ADD: 1355 if (mac_node->state == HCLGEVF_MAC_TO_DEL) 1356 mac_node->state = HCLGEVF_MAC_ACTIVE; 1357 break; 1358 /* only from set_rx_mode */ 1359 case HCLGEVF_MAC_TO_DEL: 1360 if (mac_node->state == HCLGEVF_MAC_TO_ADD) { 1361 list_del(&mac_node->node); 1362 kfree(mac_node); 1363 } else { 1364 mac_node->state = HCLGEVF_MAC_TO_DEL; 1365 } 1366 break; 1367 /* only from tmp_add_list, the mac_node->state won't be 1368 * HCLGEVF_MAC_ACTIVE 1369 */ 1370 case HCLGEVF_MAC_ACTIVE: 1371 if (mac_node->state == HCLGEVF_MAC_TO_ADD) 1372 mac_node->state = HCLGEVF_MAC_ACTIVE; 1373 break; 1374 } 1375 } 1376 1377 static int hclgevf_update_mac_list(struct hnae3_handle *handle, 1378 enum HCLGEVF_MAC_NODE_STATE state, 1379 enum HCLGEVF_MAC_ADDR_TYPE mac_type, 1380 const unsigned char *addr) 1381 { 1382 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1383 struct hclgevf_mac_addr_node *mac_node; 1384 struct list_head *list; 1385 1386 list = (mac_type == HCLGEVF_MAC_ADDR_UC) ? 1387 &hdev->mac_table.uc_mac_list : &hdev->mac_table.mc_mac_list; 1388 1389 spin_lock_bh(&hdev->mac_table.mac_list_lock); 1390 1391 /* if the mac addr is already in the mac list, no need to add a new 1392 * one into it, just check the mac addr state, convert it to a new 1393 * new state, or just remove it, or do nothing. 1394 */ 1395 mac_node = hclgevf_find_mac_node(list, addr); 1396 if (mac_node) { 1397 hclgevf_update_mac_node(mac_node, state); 1398 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1399 return 0; 1400 } 1401 /* if this address is never added, unnecessary to delete */ 1402 if (state == HCLGEVF_MAC_TO_DEL) { 1403 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1404 return -ENOENT; 1405 } 1406 1407 mac_node = kzalloc(sizeof(*mac_node), GFP_ATOMIC); 1408 if (!mac_node) { 1409 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1410 return -ENOMEM; 1411 } 1412 1413 mac_node->state = state; 1414 ether_addr_copy(mac_node->mac_addr, addr); 1415 list_add_tail(&mac_node->node, list); 1416 1417 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1418 return 0; 1419 } 1420 1421 static int hclgevf_add_uc_addr(struct hnae3_handle *handle, 1422 const unsigned char *addr) 1423 { 1424 return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_ADD, 1425 HCLGEVF_MAC_ADDR_UC, addr); 1426 } 1427 1428 static int hclgevf_rm_uc_addr(struct hnae3_handle *handle, 1429 const unsigned char *addr) 1430 { 1431 return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_DEL, 1432 HCLGEVF_MAC_ADDR_UC, addr); 1433 } 1434 1435 static int hclgevf_add_mc_addr(struct hnae3_handle *handle, 1436 const unsigned char *addr) 1437 { 1438 return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_ADD, 1439 HCLGEVF_MAC_ADDR_MC, addr); 1440 } 1441 1442 static int hclgevf_rm_mc_addr(struct hnae3_handle *handle, 1443 const unsigned char *addr) 1444 { 1445 return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_DEL, 1446 HCLGEVF_MAC_ADDR_MC, addr); 1447 } 1448 1449 static int hclgevf_add_del_mac_addr(struct hclgevf_dev *hdev, 1450 struct hclgevf_mac_addr_node *mac_node, 1451 enum HCLGEVF_MAC_ADDR_TYPE mac_type) 1452 { 1453 struct hclge_vf_to_pf_msg send_msg; 1454 u8 code, subcode; 1455 1456 if (mac_type == HCLGEVF_MAC_ADDR_UC) { 1457 code = HCLGE_MBX_SET_UNICAST; 1458 if (mac_node->state == HCLGEVF_MAC_TO_ADD) 1459 subcode = HCLGE_MBX_MAC_VLAN_UC_ADD; 1460 else 1461 subcode = HCLGE_MBX_MAC_VLAN_UC_REMOVE; 1462 } else { 1463 code = HCLGE_MBX_SET_MULTICAST; 1464 if (mac_node->state == HCLGEVF_MAC_TO_ADD) 1465 subcode = HCLGE_MBX_MAC_VLAN_MC_ADD; 1466 else 1467 subcode = HCLGE_MBX_MAC_VLAN_MC_REMOVE; 1468 } 1469 1470 hclgevf_build_send_msg(&send_msg, code, subcode); 1471 ether_addr_copy(send_msg.data, mac_node->mac_addr); 1472 return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 1473 } 1474 1475 static void hclgevf_config_mac_list(struct hclgevf_dev *hdev, 1476 struct list_head *list, 1477 enum HCLGEVF_MAC_ADDR_TYPE mac_type) 1478 { 1479 struct hclgevf_mac_addr_node *mac_node, *tmp; 1480 int ret; 1481 1482 list_for_each_entry_safe(mac_node, tmp, list, node) { 1483 ret = hclgevf_add_del_mac_addr(hdev, mac_node, mac_type); 1484 if (ret) { 1485 dev_err(&hdev->pdev->dev, 1486 "failed to configure mac %pM, state = %d, ret = %d\n", 1487 mac_node->mac_addr, mac_node->state, ret); 1488 return; 1489 } 1490 if (mac_node->state == HCLGEVF_MAC_TO_ADD) { 1491 mac_node->state = HCLGEVF_MAC_ACTIVE; 1492 } else { 1493 list_del(&mac_node->node); 1494 kfree(mac_node); 1495 } 1496 } 1497 } 1498 1499 static void hclgevf_sync_from_add_list(struct list_head *add_list, 1500 struct list_head *mac_list) 1501 { 1502 struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node; 1503 1504 list_for_each_entry_safe(mac_node, tmp, add_list, node) { 1505 /* if the mac address from tmp_add_list is not in the 1506 * uc/mc_mac_list, it means have received a TO_DEL request 1507 * during the time window of sending mac config request to PF 1508 * If mac_node state is ACTIVE, then change its state to TO_DEL, 1509 * then it will be removed at next time. If is TO_ADD, it means 1510 * send TO_ADD request failed, so just remove the mac node. 1511 */ 1512 new_node = hclgevf_find_mac_node(mac_list, mac_node->mac_addr); 1513 if (new_node) { 1514 hclgevf_update_mac_node(new_node, mac_node->state); 1515 list_del(&mac_node->node); 1516 kfree(mac_node); 1517 } else if (mac_node->state == HCLGEVF_MAC_ACTIVE) { 1518 mac_node->state = HCLGEVF_MAC_TO_DEL; 1519 list_del(&mac_node->node); 1520 list_add_tail(&mac_node->node, mac_list); 1521 } else { 1522 list_del(&mac_node->node); 1523 kfree(mac_node); 1524 } 1525 } 1526 } 1527 1528 static void hclgevf_sync_from_del_list(struct list_head *del_list, 1529 struct list_head *mac_list) 1530 { 1531 struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node; 1532 1533 list_for_each_entry_safe(mac_node, tmp, del_list, node) { 1534 new_node = hclgevf_find_mac_node(mac_list, mac_node->mac_addr); 1535 if (new_node) { 1536 /* If the mac addr is exist in the mac list, it means 1537 * received a new request TO_ADD during the time window 1538 * of sending mac addr configurrequest to PF, so just 1539 * change the mac state to ACTIVE. 1540 */ 1541 new_node->state = HCLGEVF_MAC_ACTIVE; 1542 list_del(&mac_node->node); 1543 kfree(mac_node); 1544 } else { 1545 list_del(&mac_node->node); 1546 list_add_tail(&mac_node->node, mac_list); 1547 } 1548 } 1549 } 1550 1551 static void hclgevf_clear_list(struct list_head *list) 1552 { 1553 struct hclgevf_mac_addr_node *mac_node, *tmp; 1554 1555 list_for_each_entry_safe(mac_node, tmp, list, node) { 1556 list_del(&mac_node->node); 1557 kfree(mac_node); 1558 } 1559 } 1560 1561 static void hclgevf_sync_mac_list(struct hclgevf_dev *hdev, 1562 enum HCLGEVF_MAC_ADDR_TYPE mac_type) 1563 { 1564 struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node; 1565 struct list_head tmp_add_list, tmp_del_list; 1566 struct list_head *list; 1567 1568 INIT_LIST_HEAD(&tmp_add_list); 1569 INIT_LIST_HEAD(&tmp_del_list); 1570 1571 /* move the mac addr to the tmp_add_list and tmp_del_list, then 1572 * we can add/delete these mac addr outside the spin lock 1573 */ 1574 list = (mac_type == HCLGEVF_MAC_ADDR_UC) ? 1575 &hdev->mac_table.uc_mac_list : &hdev->mac_table.mc_mac_list; 1576 1577 spin_lock_bh(&hdev->mac_table.mac_list_lock); 1578 1579 list_for_each_entry_safe(mac_node, tmp, list, node) { 1580 switch (mac_node->state) { 1581 case HCLGEVF_MAC_TO_DEL: 1582 list_del(&mac_node->node); 1583 list_add_tail(&mac_node->node, &tmp_del_list); 1584 break; 1585 case HCLGEVF_MAC_TO_ADD: 1586 new_node = kzalloc(sizeof(*new_node), GFP_ATOMIC); 1587 if (!new_node) 1588 goto stop_traverse; 1589 1590 ether_addr_copy(new_node->mac_addr, mac_node->mac_addr); 1591 new_node->state = mac_node->state; 1592 list_add_tail(&new_node->node, &tmp_add_list); 1593 break; 1594 default: 1595 break; 1596 } 1597 } 1598 1599 stop_traverse: 1600 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1601 1602 /* delete first, in order to get max mac table space for adding */ 1603 hclgevf_config_mac_list(hdev, &tmp_del_list, mac_type); 1604 hclgevf_config_mac_list(hdev, &tmp_add_list, mac_type); 1605 1606 /* if some mac addresses were added/deleted fail, move back to the 1607 * mac_list, and retry at next time. 1608 */ 1609 spin_lock_bh(&hdev->mac_table.mac_list_lock); 1610 1611 hclgevf_sync_from_del_list(&tmp_del_list, list); 1612 hclgevf_sync_from_add_list(&tmp_add_list, list); 1613 1614 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1615 } 1616 1617 static void hclgevf_sync_mac_table(struct hclgevf_dev *hdev) 1618 { 1619 hclgevf_sync_mac_list(hdev, HCLGEVF_MAC_ADDR_UC); 1620 hclgevf_sync_mac_list(hdev, HCLGEVF_MAC_ADDR_MC); 1621 } 1622 1623 static void hclgevf_uninit_mac_list(struct hclgevf_dev *hdev) 1624 { 1625 spin_lock_bh(&hdev->mac_table.mac_list_lock); 1626 1627 hclgevf_clear_list(&hdev->mac_table.uc_mac_list); 1628 hclgevf_clear_list(&hdev->mac_table.mc_mac_list); 1629 1630 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1631 } 1632 1633 static int hclgevf_set_vlan_filter(struct hnae3_handle *handle, 1634 __be16 proto, u16 vlan_id, 1635 bool is_kill) 1636 { 1637 #define HCLGEVF_VLAN_MBX_IS_KILL_OFFSET 0 1638 #define HCLGEVF_VLAN_MBX_VLAN_ID_OFFSET 1 1639 #define HCLGEVF_VLAN_MBX_PROTO_OFFSET 3 1640 1641 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1642 struct hclge_vf_to_pf_msg send_msg; 1643 int ret; 1644 1645 if (vlan_id > HCLGEVF_MAX_VLAN_ID) 1646 return -EINVAL; 1647 1648 if (proto != htons(ETH_P_8021Q)) 1649 return -EPROTONOSUPPORT; 1650 1651 /* When device is resetting or reset failed, firmware is unable to 1652 * handle mailbox. Just record the vlan id, and remove it after 1653 * reset finished. 1654 */ 1655 if ((test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) || 1656 test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) && is_kill) { 1657 set_bit(vlan_id, hdev->vlan_del_fail_bmap); 1658 return -EBUSY; 1659 } 1660 1661 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 1662 HCLGE_MBX_VLAN_FILTER); 1663 send_msg.data[HCLGEVF_VLAN_MBX_IS_KILL_OFFSET] = is_kill; 1664 memcpy(&send_msg.data[HCLGEVF_VLAN_MBX_VLAN_ID_OFFSET], &vlan_id, 1665 sizeof(vlan_id)); 1666 memcpy(&send_msg.data[HCLGEVF_VLAN_MBX_PROTO_OFFSET], &proto, 1667 sizeof(proto)); 1668 /* when remove hw vlan filter failed, record the vlan id, 1669 * and try to remove it from hw later, to be consistence 1670 * with stack. 1671 */ 1672 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1673 if (is_kill && ret) 1674 set_bit(vlan_id, hdev->vlan_del_fail_bmap); 1675 1676 return ret; 1677 } 1678 1679 static void hclgevf_sync_vlan_filter(struct hclgevf_dev *hdev) 1680 { 1681 #define HCLGEVF_MAX_SYNC_COUNT 60 1682 struct hnae3_handle *handle = &hdev->nic; 1683 int ret, sync_cnt = 0; 1684 u16 vlan_id; 1685 1686 vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID); 1687 while (vlan_id != VLAN_N_VID) { 1688 ret = hclgevf_set_vlan_filter(handle, htons(ETH_P_8021Q), 1689 vlan_id, true); 1690 if (ret) 1691 return; 1692 1693 clear_bit(vlan_id, hdev->vlan_del_fail_bmap); 1694 sync_cnt++; 1695 if (sync_cnt >= HCLGEVF_MAX_SYNC_COUNT) 1696 return; 1697 1698 vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID); 1699 } 1700 } 1701 1702 static int hclgevf_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) 1703 { 1704 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1705 struct hclge_vf_to_pf_msg send_msg; 1706 1707 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 1708 HCLGE_MBX_VLAN_RX_OFF_CFG); 1709 send_msg.data[0] = enable ? 1 : 0; 1710 return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 1711 } 1712 1713 static int hclgevf_reset_tqp(struct hnae3_handle *handle, u16 queue_id) 1714 { 1715 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1716 struct hclge_vf_to_pf_msg send_msg; 1717 int ret; 1718 1719 /* disable vf queue before send queue reset msg to PF */ 1720 ret = hclgevf_tqp_enable(hdev, queue_id, 0, false); 1721 if (ret) 1722 return ret; 1723 1724 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_QUEUE_RESET, 0); 1725 memcpy(send_msg.data, &queue_id, sizeof(queue_id)); 1726 return hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1727 } 1728 1729 static int hclgevf_set_mtu(struct hnae3_handle *handle, int new_mtu) 1730 { 1731 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1732 struct hclge_vf_to_pf_msg send_msg; 1733 1734 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_MTU, 0); 1735 memcpy(send_msg.data, &new_mtu, sizeof(new_mtu)); 1736 return hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1737 } 1738 1739 static int hclgevf_notify_client(struct hclgevf_dev *hdev, 1740 enum hnae3_reset_notify_type type) 1741 { 1742 struct hnae3_client *client = hdev->nic_client; 1743 struct hnae3_handle *handle = &hdev->nic; 1744 int ret; 1745 1746 if (!test_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state) || 1747 !client) 1748 return 0; 1749 1750 if (!client->ops->reset_notify) 1751 return -EOPNOTSUPP; 1752 1753 ret = client->ops->reset_notify(handle, type); 1754 if (ret) 1755 dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n", 1756 type, ret); 1757 1758 return ret; 1759 } 1760 1761 static int hclgevf_notify_roce_client(struct hclgevf_dev *hdev, 1762 enum hnae3_reset_notify_type type) 1763 { 1764 struct hnae3_client *client = hdev->roce_client; 1765 struct hnae3_handle *handle = &hdev->roce; 1766 int ret; 1767 1768 if (!test_bit(HCLGEVF_STATE_ROCE_REGISTERED, &hdev->state) || !client) 1769 return 0; 1770 1771 if (!client->ops->reset_notify) 1772 return -EOPNOTSUPP; 1773 1774 ret = client->ops->reset_notify(handle, type); 1775 if (ret) 1776 dev_err(&hdev->pdev->dev, "notify roce client failed %d(%d)", 1777 type, ret); 1778 return ret; 1779 } 1780 1781 static int hclgevf_reset_wait(struct hclgevf_dev *hdev) 1782 { 1783 #define HCLGEVF_RESET_WAIT_US 20000 1784 #define HCLGEVF_RESET_WAIT_CNT 2000 1785 #define HCLGEVF_RESET_WAIT_TIMEOUT_US \ 1786 (HCLGEVF_RESET_WAIT_US * HCLGEVF_RESET_WAIT_CNT) 1787 1788 u32 val; 1789 int ret; 1790 1791 if (hdev->reset_type == HNAE3_VF_RESET) 1792 ret = readl_poll_timeout(hdev->hw.io_base + 1793 HCLGEVF_VF_RST_ING, val, 1794 !(val & HCLGEVF_VF_RST_ING_BIT), 1795 HCLGEVF_RESET_WAIT_US, 1796 HCLGEVF_RESET_WAIT_TIMEOUT_US); 1797 else 1798 ret = readl_poll_timeout(hdev->hw.io_base + 1799 HCLGEVF_RST_ING, val, 1800 !(val & HCLGEVF_RST_ING_BITS), 1801 HCLGEVF_RESET_WAIT_US, 1802 HCLGEVF_RESET_WAIT_TIMEOUT_US); 1803 1804 /* hardware completion status should be available by this time */ 1805 if (ret) { 1806 dev_err(&hdev->pdev->dev, 1807 "couldn't get reset done status from h/w, timeout!\n"); 1808 return ret; 1809 } 1810 1811 /* we will wait a bit more to let reset of the stack to complete. This 1812 * might happen in case reset assertion was made by PF. Yes, this also 1813 * means we might end up waiting bit more even for VF reset. 1814 */ 1815 msleep(5000); 1816 1817 return 0; 1818 } 1819 1820 static void hclgevf_reset_handshake(struct hclgevf_dev *hdev, bool enable) 1821 { 1822 u32 reg_val; 1823 1824 reg_val = hclgevf_read_dev(&hdev->hw, HCLGEVF_NIC_CSQ_DEPTH_REG); 1825 if (enable) 1826 reg_val |= HCLGEVF_NIC_SW_RST_RDY; 1827 else 1828 reg_val &= ~HCLGEVF_NIC_SW_RST_RDY; 1829 1830 hclgevf_write_dev(&hdev->hw, HCLGEVF_NIC_CSQ_DEPTH_REG, 1831 reg_val); 1832 } 1833 1834 static int hclgevf_reset_stack(struct hclgevf_dev *hdev) 1835 { 1836 int ret; 1837 1838 /* uninitialize the nic client */ 1839 ret = hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT); 1840 if (ret) 1841 return ret; 1842 1843 /* re-initialize the hclge device */ 1844 ret = hclgevf_reset_hdev(hdev); 1845 if (ret) { 1846 dev_err(&hdev->pdev->dev, 1847 "hclge device re-init failed, VF is disabled!\n"); 1848 return ret; 1849 } 1850 1851 /* bring up the nic client again */ 1852 ret = hclgevf_notify_client(hdev, HNAE3_INIT_CLIENT); 1853 if (ret) 1854 return ret; 1855 1856 /* clear handshake status with IMP */ 1857 hclgevf_reset_handshake(hdev, false); 1858 1859 /* bring up the nic to enable TX/RX again */ 1860 return hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 1861 } 1862 1863 static int hclgevf_reset_prepare_wait(struct hclgevf_dev *hdev) 1864 { 1865 #define HCLGEVF_RESET_SYNC_TIME 100 1866 1867 if (hdev->reset_type == HNAE3_VF_FUNC_RESET) { 1868 struct hclge_vf_to_pf_msg send_msg; 1869 int ret; 1870 1871 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_RESET, 0); 1872 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1873 if (ret) { 1874 dev_err(&hdev->pdev->dev, 1875 "failed to assert VF reset, ret = %d\n", ret); 1876 return ret; 1877 } 1878 hdev->rst_stats.vf_func_rst_cnt++; 1879 } 1880 1881 set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 1882 /* inform hardware that preparatory work is done */ 1883 msleep(HCLGEVF_RESET_SYNC_TIME); 1884 hclgevf_reset_handshake(hdev, true); 1885 dev_info(&hdev->pdev->dev, "prepare reset(%d) wait done\n", 1886 hdev->reset_type); 1887 1888 return 0; 1889 } 1890 1891 static void hclgevf_dump_rst_info(struct hclgevf_dev *hdev) 1892 { 1893 dev_info(&hdev->pdev->dev, "VF function reset count: %u\n", 1894 hdev->rst_stats.vf_func_rst_cnt); 1895 dev_info(&hdev->pdev->dev, "FLR reset count: %u\n", 1896 hdev->rst_stats.flr_rst_cnt); 1897 dev_info(&hdev->pdev->dev, "VF reset count: %u\n", 1898 hdev->rst_stats.vf_rst_cnt); 1899 dev_info(&hdev->pdev->dev, "reset done count: %u\n", 1900 hdev->rst_stats.rst_done_cnt); 1901 dev_info(&hdev->pdev->dev, "HW reset done count: %u\n", 1902 hdev->rst_stats.hw_rst_done_cnt); 1903 dev_info(&hdev->pdev->dev, "reset count: %u\n", 1904 hdev->rst_stats.rst_cnt); 1905 dev_info(&hdev->pdev->dev, "reset fail count: %u\n", 1906 hdev->rst_stats.rst_fail_cnt); 1907 dev_info(&hdev->pdev->dev, "vector0 interrupt enable status: 0x%x\n", 1908 hclgevf_read_dev(&hdev->hw, HCLGEVF_MISC_VECTOR_REG_BASE)); 1909 dev_info(&hdev->pdev->dev, "vector0 interrupt status: 0x%x\n", 1910 hclgevf_read_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_STATE_REG)); 1911 dev_info(&hdev->pdev->dev, "handshake status: 0x%x\n", 1912 hclgevf_read_dev(&hdev->hw, HCLGEVF_CMDQ_TX_DEPTH_REG)); 1913 dev_info(&hdev->pdev->dev, "function reset status: 0x%x\n", 1914 hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING)); 1915 dev_info(&hdev->pdev->dev, "hdev state: 0x%lx\n", hdev->state); 1916 } 1917 1918 static void hclgevf_reset_err_handle(struct hclgevf_dev *hdev) 1919 { 1920 /* recover handshake status with IMP when reset fail */ 1921 hclgevf_reset_handshake(hdev, true); 1922 hdev->rst_stats.rst_fail_cnt++; 1923 dev_err(&hdev->pdev->dev, "failed to reset VF(%u)\n", 1924 hdev->rst_stats.rst_fail_cnt); 1925 1926 if (hdev->rst_stats.rst_fail_cnt < HCLGEVF_RESET_MAX_FAIL_CNT) 1927 set_bit(hdev->reset_type, &hdev->reset_pending); 1928 1929 if (hclgevf_is_reset_pending(hdev)) { 1930 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1931 hclgevf_reset_task_schedule(hdev); 1932 } else { 1933 set_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state); 1934 hclgevf_dump_rst_info(hdev); 1935 } 1936 } 1937 1938 static int hclgevf_reset_prepare(struct hclgevf_dev *hdev) 1939 { 1940 int ret; 1941 1942 hdev->rst_stats.rst_cnt++; 1943 1944 /* perform reset of the stack & ae device for a client */ 1945 ret = hclgevf_notify_roce_client(hdev, HNAE3_DOWN_CLIENT); 1946 if (ret) 1947 return ret; 1948 1949 rtnl_lock(); 1950 /* bring down the nic to stop any ongoing TX/RX */ 1951 ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 1952 rtnl_unlock(); 1953 if (ret) 1954 return ret; 1955 1956 return hclgevf_reset_prepare_wait(hdev); 1957 } 1958 1959 static int hclgevf_reset_rebuild(struct hclgevf_dev *hdev) 1960 { 1961 int ret; 1962 1963 hdev->rst_stats.hw_rst_done_cnt++; 1964 ret = hclgevf_notify_roce_client(hdev, HNAE3_UNINIT_CLIENT); 1965 if (ret) 1966 return ret; 1967 1968 rtnl_lock(); 1969 /* now, re-initialize the nic client and ae device */ 1970 ret = hclgevf_reset_stack(hdev); 1971 rtnl_unlock(); 1972 if (ret) { 1973 dev_err(&hdev->pdev->dev, "failed to reset VF stack\n"); 1974 return ret; 1975 } 1976 1977 ret = hclgevf_notify_roce_client(hdev, HNAE3_INIT_CLIENT); 1978 /* ignore RoCE notify error if it fails HCLGEVF_RESET_MAX_FAIL_CNT - 1 1979 * times 1980 */ 1981 if (ret && 1982 hdev->rst_stats.rst_fail_cnt < HCLGEVF_RESET_MAX_FAIL_CNT - 1) 1983 return ret; 1984 1985 ret = hclgevf_notify_roce_client(hdev, HNAE3_UP_CLIENT); 1986 if (ret) 1987 return ret; 1988 1989 hdev->last_reset_time = jiffies; 1990 hdev->rst_stats.rst_done_cnt++; 1991 hdev->rst_stats.rst_fail_cnt = 0; 1992 clear_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state); 1993 1994 return 0; 1995 } 1996 1997 static void hclgevf_reset(struct hclgevf_dev *hdev) 1998 { 1999 if (hclgevf_reset_prepare(hdev)) 2000 goto err_reset; 2001 2002 /* check if VF could successfully fetch the hardware reset completion 2003 * status from the hardware 2004 */ 2005 if (hclgevf_reset_wait(hdev)) { 2006 /* can't do much in this situation, will disable VF */ 2007 dev_err(&hdev->pdev->dev, 2008 "failed to fetch H/W reset completion status\n"); 2009 goto err_reset; 2010 } 2011 2012 if (hclgevf_reset_rebuild(hdev)) 2013 goto err_reset; 2014 2015 return; 2016 2017 err_reset: 2018 hclgevf_reset_err_handle(hdev); 2019 } 2020 2021 static enum hnae3_reset_type hclgevf_get_reset_level(struct hclgevf_dev *hdev, 2022 unsigned long *addr) 2023 { 2024 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; 2025 2026 /* return the highest priority reset level amongst all */ 2027 if (test_bit(HNAE3_VF_RESET, addr)) { 2028 rst_level = HNAE3_VF_RESET; 2029 clear_bit(HNAE3_VF_RESET, addr); 2030 clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 2031 clear_bit(HNAE3_VF_FUNC_RESET, addr); 2032 } else if (test_bit(HNAE3_VF_FULL_RESET, addr)) { 2033 rst_level = HNAE3_VF_FULL_RESET; 2034 clear_bit(HNAE3_VF_FULL_RESET, addr); 2035 clear_bit(HNAE3_VF_FUNC_RESET, addr); 2036 } else if (test_bit(HNAE3_VF_PF_FUNC_RESET, addr)) { 2037 rst_level = HNAE3_VF_PF_FUNC_RESET; 2038 clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 2039 clear_bit(HNAE3_VF_FUNC_RESET, addr); 2040 } else if (test_bit(HNAE3_VF_FUNC_RESET, addr)) { 2041 rst_level = HNAE3_VF_FUNC_RESET; 2042 clear_bit(HNAE3_VF_FUNC_RESET, addr); 2043 } else if (test_bit(HNAE3_FLR_RESET, addr)) { 2044 rst_level = HNAE3_FLR_RESET; 2045 clear_bit(HNAE3_FLR_RESET, addr); 2046 } 2047 2048 return rst_level; 2049 } 2050 2051 static void hclgevf_reset_event(struct pci_dev *pdev, 2052 struct hnae3_handle *handle) 2053 { 2054 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2055 struct hclgevf_dev *hdev = ae_dev->priv; 2056 2057 dev_info(&hdev->pdev->dev, "received reset request from VF enet\n"); 2058 2059 if (hdev->default_reset_request) 2060 hdev->reset_level = 2061 hclgevf_get_reset_level(hdev, 2062 &hdev->default_reset_request); 2063 else 2064 hdev->reset_level = HNAE3_VF_FUNC_RESET; 2065 2066 /* reset of this VF requested */ 2067 set_bit(HCLGEVF_RESET_REQUESTED, &hdev->reset_state); 2068 hclgevf_reset_task_schedule(hdev); 2069 2070 hdev->last_reset_time = jiffies; 2071 } 2072 2073 static void hclgevf_set_def_reset_request(struct hnae3_ae_dev *ae_dev, 2074 enum hnae3_reset_type rst_type) 2075 { 2076 struct hclgevf_dev *hdev = ae_dev->priv; 2077 2078 set_bit(rst_type, &hdev->default_reset_request); 2079 } 2080 2081 static void hclgevf_enable_vector(struct hclgevf_misc_vector *vector, bool en) 2082 { 2083 writel(en ? 1 : 0, vector->addr); 2084 } 2085 2086 static void hclgevf_flr_prepare(struct hnae3_ae_dev *ae_dev) 2087 { 2088 #define HCLGEVF_FLR_RETRY_WAIT_MS 500 2089 #define HCLGEVF_FLR_RETRY_CNT 5 2090 2091 struct hclgevf_dev *hdev = ae_dev->priv; 2092 int retry_cnt = 0; 2093 int ret; 2094 2095 retry: 2096 down(&hdev->reset_sem); 2097 set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 2098 hdev->reset_type = HNAE3_FLR_RESET; 2099 ret = hclgevf_reset_prepare(hdev); 2100 if (ret) { 2101 dev_err(&hdev->pdev->dev, "fail to prepare FLR, ret=%d\n", 2102 ret); 2103 if (hdev->reset_pending || 2104 retry_cnt++ < HCLGEVF_FLR_RETRY_CNT) { 2105 dev_err(&hdev->pdev->dev, 2106 "reset_pending:0x%lx, retry_cnt:%d\n", 2107 hdev->reset_pending, retry_cnt); 2108 clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 2109 up(&hdev->reset_sem); 2110 msleep(HCLGEVF_FLR_RETRY_WAIT_MS); 2111 goto retry; 2112 } 2113 } 2114 2115 /* disable misc vector before FLR done */ 2116 hclgevf_enable_vector(&hdev->misc_vector, false); 2117 hdev->rst_stats.flr_rst_cnt++; 2118 } 2119 2120 static void hclgevf_flr_done(struct hnae3_ae_dev *ae_dev) 2121 { 2122 struct hclgevf_dev *hdev = ae_dev->priv; 2123 int ret; 2124 2125 hclgevf_enable_vector(&hdev->misc_vector, true); 2126 2127 ret = hclgevf_reset_rebuild(hdev); 2128 if (ret) 2129 dev_warn(&hdev->pdev->dev, "fail to rebuild, ret=%d\n", 2130 ret); 2131 2132 hdev->reset_type = HNAE3_NONE_RESET; 2133 clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 2134 up(&hdev->reset_sem); 2135 } 2136 2137 static u32 hclgevf_get_fw_version(struct hnae3_handle *handle) 2138 { 2139 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2140 2141 return hdev->fw_version; 2142 } 2143 2144 static void hclgevf_get_misc_vector(struct hclgevf_dev *hdev) 2145 { 2146 struct hclgevf_misc_vector *vector = &hdev->misc_vector; 2147 2148 vector->vector_irq = pci_irq_vector(hdev->pdev, 2149 HCLGEVF_MISC_VECTOR_NUM); 2150 vector->addr = hdev->hw.io_base + HCLGEVF_MISC_VECTOR_REG_BASE; 2151 /* vector status always valid for Vector 0 */ 2152 hdev->vector_status[HCLGEVF_MISC_VECTOR_NUM] = 0; 2153 hdev->vector_irq[HCLGEVF_MISC_VECTOR_NUM] = vector->vector_irq; 2154 2155 hdev->num_msi_left -= 1; 2156 hdev->num_msi_used += 1; 2157 } 2158 2159 void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev) 2160 { 2161 if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) && 2162 !test_and_set_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, 2163 &hdev->state)) 2164 mod_delayed_work(hclgevf_wq, &hdev->service_task, 0); 2165 } 2166 2167 void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev) 2168 { 2169 if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) && 2170 !test_and_set_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, 2171 &hdev->state)) 2172 mod_delayed_work(hclgevf_wq, &hdev->service_task, 0); 2173 } 2174 2175 static void hclgevf_task_schedule(struct hclgevf_dev *hdev, 2176 unsigned long delay) 2177 { 2178 if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) && 2179 !test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) 2180 mod_delayed_work(hclgevf_wq, &hdev->service_task, delay); 2181 } 2182 2183 static void hclgevf_reset_service_task(struct hclgevf_dev *hdev) 2184 { 2185 #define HCLGEVF_MAX_RESET_ATTEMPTS_CNT 3 2186 2187 if (!test_and_clear_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state)) 2188 return; 2189 2190 down(&hdev->reset_sem); 2191 set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 2192 2193 if (test_and_clear_bit(HCLGEVF_RESET_PENDING, 2194 &hdev->reset_state)) { 2195 /* PF has initmated that it is about to reset the hardware. 2196 * We now have to poll & check if hardware has actually 2197 * completed the reset sequence. On hardware reset completion, 2198 * VF needs to reset the client and ae device. 2199 */ 2200 hdev->reset_attempts = 0; 2201 2202 hdev->last_reset_time = jiffies; 2203 while ((hdev->reset_type = 2204 hclgevf_get_reset_level(hdev, &hdev->reset_pending)) 2205 != HNAE3_NONE_RESET) 2206 hclgevf_reset(hdev); 2207 } else if (test_and_clear_bit(HCLGEVF_RESET_REQUESTED, 2208 &hdev->reset_state)) { 2209 /* we could be here when either of below happens: 2210 * 1. reset was initiated due to watchdog timeout caused by 2211 * a. IMP was earlier reset and our TX got choked down and 2212 * which resulted in watchdog reacting and inducing VF 2213 * reset. This also means our cmdq would be unreliable. 2214 * b. problem in TX due to other lower layer(example link 2215 * layer not functioning properly etc.) 2216 * 2. VF reset might have been initiated due to some config 2217 * change. 2218 * 2219 * NOTE: Theres no clear way to detect above cases than to react 2220 * to the response of PF for this reset request. PF will ack the 2221 * 1b and 2. cases but we will not get any intimation about 1a 2222 * from PF as cmdq would be in unreliable state i.e. mailbox 2223 * communication between PF and VF would be broken. 2224 * 2225 * if we are never geting into pending state it means either: 2226 * 1. PF is not receiving our request which could be due to IMP 2227 * reset 2228 * 2. PF is screwed 2229 * We cannot do much for 2. but to check first we can try reset 2230 * our PCIe + stack and see if it alleviates the problem. 2231 */ 2232 if (hdev->reset_attempts > HCLGEVF_MAX_RESET_ATTEMPTS_CNT) { 2233 /* prepare for full reset of stack + pcie interface */ 2234 set_bit(HNAE3_VF_FULL_RESET, &hdev->reset_pending); 2235 2236 /* "defer" schedule the reset task again */ 2237 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 2238 } else { 2239 hdev->reset_attempts++; 2240 2241 set_bit(hdev->reset_level, &hdev->reset_pending); 2242 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 2243 } 2244 hclgevf_reset_task_schedule(hdev); 2245 } 2246 2247 hdev->reset_type = HNAE3_NONE_RESET; 2248 clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 2249 up(&hdev->reset_sem); 2250 } 2251 2252 static void hclgevf_mailbox_service_task(struct hclgevf_dev *hdev) 2253 { 2254 if (!test_and_clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state)) 2255 return; 2256 2257 if (test_and_set_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) 2258 return; 2259 2260 hclgevf_mbx_async_handler(hdev); 2261 2262 clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 2263 } 2264 2265 static void hclgevf_keep_alive(struct hclgevf_dev *hdev) 2266 { 2267 struct hclge_vf_to_pf_msg send_msg; 2268 int ret; 2269 2270 if (test_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state)) 2271 return; 2272 2273 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_KEEP_ALIVE, 0); 2274 ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 2275 if (ret) 2276 dev_err(&hdev->pdev->dev, 2277 "VF sends keep alive cmd failed(=%d)\n", ret); 2278 } 2279 2280 static void hclgevf_periodic_service_task(struct hclgevf_dev *hdev) 2281 { 2282 unsigned long delta = round_jiffies_relative(HZ); 2283 struct hnae3_handle *handle = &hdev->nic; 2284 2285 if (test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) 2286 return; 2287 2288 if (time_is_after_jiffies(hdev->last_serv_processed + HZ)) { 2289 delta = jiffies - hdev->last_serv_processed; 2290 2291 if (delta < round_jiffies_relative(HZ)) { 2292 delta = round_jiffies_relative(HZ) - delta; 2293 goto out; 2294 } 2295 } 2296 2297 hdev->serv_processed_cnt++; 2298 if (!(hdev->serv_processed_cnt % HCLGEVF_KEEP_ALIVE_TASK_INTERVAL)) 2299 hclgevf_keep_alive(hdev); 2300 2301 if (test_bit(HCLGEVF_STATE_DOWN, &hdev->state)) { 2302 hdev->last_serv_processed = jiffies; 2303 goto out; 2304 } 2305 2306 if (!(hdev->serv_processed_cnt % HCLGEVF_STATS_TIMER_INTERVAL)) 2307 hclgevf_tqps_update_stats(handle); 2308 2309 /* request the link status from the PF. PF would be able to tell VF 2310 * about such updates in future so we might remove this later 2311 */ 2312 hclgevf_request_link_info(hdev); 2313 2314 hclgevf_update_link_mode(hdev); 2315 2316 hclgevf_sync_vlan_filter(hdev); 2317 2318 hclgevf_sync_mac_table(hdev); 2319 2320 hclgevf_sync_promisc_mode(hdev); 2321 2322 hdev->last_serv_processed = jiffies; 2323 2324 out: 2325 hclgevf_task_schedule(hdev, delta); 2326 } 2327 2328 static void hclgevf_service_task(struct work_struct *work) 2329 { 2330 struct hclgevf_dev *hdev = container_of(work, struct hclgevf_dev, 2331 service_task.work); 2332 2333 hclgevf_reset_service_task(hdev); 2334 hclgevf_mailbox_service_task(hdev); 2335 hclgevf_periodic_service_task(hdev); 2336 2337 /* Handle reset and mbx again in case periodical task delays the 2338 * handling by calling hclgevf_task_schedule() in 2339 * hclgevf_periodic_service_task() 2340 */ 2341 hclgevf_reset_service_task(hdev); 2342 hclgevf_mailbox_service_task(hdev); 2343 } 2344 2345 static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regclr) 2346 { 2347 hclgevf_write_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_SRC_REG, regclr); 2348 } 2349 2350 static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev, 2351 u32 *clearval) 2352 { 2353 u32 val, cmdq_stat_reg, rst_ing_reg; 2354 2355 /* fetch the events from their corresponding regs */ 2356 cmdq_stat_reg = hclgevf_read_dev(&hdev->hw, 2357 HCLGEVF_VECTOR0_CMDQ_STATE_REG); 2358 if (BIT(HCLGEVF_VECTOR0_RST_INT_B) & cmdq_stat_reg) { 2359 rst_ing_reg = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 2360 dev_info(&hdev->pdev->dev, 2361 "receive reset interrupt 0x%x!\n", rst_ing_reg); 2362 set_bit(HNAE3_VF_RESET, &hdev->reset_pending); 2363 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 2364 set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 2365 *clearval = ~(1U << HCLGEVF_VECTOR0_RST_INT_B); 2366 hdev->rst_stats.vf_rst_cnt++; 2367 /* set up VF hardware reset status, its PF will clear 2368 * this status when PF has initialized done. 2369 */ 2370 val = hclgevf_read_dev(&hdev->hw, HCLGEVF_VF_RST_ING); 2371 hclgevf_write_dev(&hdev->hw, HCLGEVF_VF_RST_ING, 2372 val | HCLGEVF_VF_RST_ING_BIT); 2373 return HCLGEVF_VECTOR0_EVENT_RST; 2374 } 2375 2376 /* check for vector0 mailbox(=CMDQ RX) event source */ 2377 if (BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) { 2378 /* for revision 0x21, clearing interrupt is writing bit 0 2379 * to the clear register, writing bit 1 means to keep the 2380 * old value. 2381 * for revision 0x20, the clear register is a read & write 2382 * register, so we should just write 0 to the bit we are 2383 * handling, and keep other bits as cmdq_stat_reg. 2384 */ 2385 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) 2386 *clearval = ~(1U << HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 2387 else 2388 *clearval = cmdq_stat_reg & 2389 ~BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 2390 2391 return HCLGEVF_VECTOR0_EVENT_MBX; 2392 } 2393 2394 /* print other vector0 event source */ 2395 dev_info(&hdev->pdev->dev, 2396 "vector 0 interrupt from unknown source, cmdq_src = %#x\n", 2397 cmdq_stat_reg); 2398 2399 return HCLGEVF_VECTOR0_EVENT_OTHER; 2400 } 2401 2402 static irqreturn_t hclgevf_misc_irq_handle(int irq, void *data) 2403 { 2404 enum hclgevf_evt_cause event_cause; 2405 struct hclgevf_dev *hdev = data; 2406 u32 clearval; 2407 2408 hclgevf_enable_vector(&hdev->misc_vector, false); 2409 event_cause = hclgevf_check_evt_cause(hdev, &clearval); 2410 2411 switch (event_cause) { 2412 case HCLGEVF_VECTOR0_EVENT_RST: 2413 hclgevf_reset_task_schedule(hdev); 2414 break; 2415 case HCLGEVF_VECTOR0_EVENT_MBX: 2416 hclgevf_mbx_handler(hdev); 2417 break; 2418 default: 2419 break; 2420 } 2421 2422 if (event_cause != HCLGEVF_VECTOR0_EVENT_OTHER) { 2423 hclgevf_clear_event_cause(hdev, clearval); 2424 hclgevf_enable_vector(&hdev->misc_vector, true); 2425 } 2426 2427 return IRQ_HANDLED; 2428 } 2429 2430 static int hclgevf_configure(struct hclgevf_dev *hdev) 2431 { 2432 int ret; 2433 2434 /* get current port based vlan state from PF */ 2435 ret = hclgevf_get_port_base_vlan_filter_state(hdev); 2436 if (ret) 2437 return ret; 2438 2439 /* get queue configuration from PF */ 2440 ret = hclgevf_get_queue_info(hdev); 2441 if (ret) 2442 return ret; 2443 2444 /* get queue depth info from PF */ 2445 ret = hclgevf_get_queue_depth(hdev); 2446 if (ret) 2447 return ret; 2448 2449 ret = hclgevf_get_pf_media_type(hdev); 2450 if (ret) 2451 return ret; 2452 2453 /* get tc configuration from PF */ 2454 return hclgevf_get_tc_info(hdev); 2455 } 2456 2457 static int hclgevf_alloc_hdev(struct hnae3_ae_dev *ae_dev) 2458 { 2459 struct pci_dev *pdev = ae_dev->pdev; 2460 struct hclgevf_dev *hdev; 2461 2462 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 2463 if (!hdev) 2464 return -ENOMEM; 2465 2466 hdev->pdev = pdev; 2467 hdev->ae_dev = ae_dev; 2468 ae_dev->priv = hdev; 2469 2470 return 0; 2471 } 2472 2473 static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev) 2474 { 2475 struct hnae3_handle *roce = &hdev->roce; 2476 struct hnae3_handle *nic = &hdev->nic; 2477 2478 roce->rinfo.num_vectors = hdev->num_roce_msix; 2479 2480 if (hdev->num_msi_left < roce->rinfo.num_vectors || 2481 hdev->num_msi_left == 0) 2482 return -EINVAL; 2483 2484 roce->rinfo.base_vector = hdev->roce_base_vector; 2485 2486 roce->rinfo.netdev = nic->kinfo.netdev; 2487 roce->rinfo.roce_io_base = hdev->hw.io_base; 2488 roce->rinfo.roce_mem_base = hdev->hw.mem_base; 2489 2490 roce->pdev = nic->pdev; 2491 roce->ae_algo = nic->ae_algo; 2492 roce->numa_node_mask = nic->numa_node_mask; 2493 2494 return 0; 2495 } 2496 2497 static int hclgevf_config_gro(struct hclgevf_dev *hdev, bool en) 2498 { 2499 struct hclgevf_cfg_gro_status_cmd *req; 2500 struct hclgevf_desc desc; 2501 int ret; 2502 2503 if (!hnae3_dev_gro_supported(hdev)) 2504 return 0; 2505 2506 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_GRO_GENERIC_CONFIG, 2507 false); 2508 req = (struct hclgevf_cfg_gro_status_cmd *)desc.data; 2509 2510 req->gro_en = en ? 1 : 0; 2511 2512 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 2513 if (ret) 2514 dev_err(&hdev->pdev->dev, 2515 "VF GRO hardware config cmd failed, ret = %d.\n", ret); 2516 2517 return ret; 2518 } 2519 2520 static int hclgevf_rss_init_cfg(struct hclgevf_dev *hdev) 2521 { 2522 u16 rss_ind_tbl_size = hdev->ae_dev->dev_specs.rss_ind_tbl_size; 2523 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 2524 struct hclgevf_rss_tuple_cfg *tuple_sets; 2525 u32 i; 2526 2527 rss_cfg->hash_algo = HCLGEVF_RSS_HASH_ALGO_TOEPLITZ; 2528 rss_cfg->rss_size = hdev->nic.kinfo.rss_size; 2529 tuple_sets = &rss_cfg->rss_tuple_sets; 2530 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 2531 u8 *rss_ind_tbl; 2532 2533 rss_cfg->hash_algo = HCLGEVF_RSS_HASH_ALGO_SIMPLE; 2534 2535 rss_ind_tbl = devm_kcalloc(&hdev->pdev->dev, rss_ind_tbl_size, 2536 sizeof(*rss_ind_tbl), GFP_KERNEL); 2537 if (!rss_ind_tbl) 2538 return -ENOMEM; 2539 2540 rss_cfg->rss_indirection_tbl = rss_ind_tbl; 2541 memcpy(rss_cfg->rss_hash_key, hclgevf_hash_key, 2542 HCLGEVF_RSS_KEY_SIZE); 2543 2544 tuple_sets->ipv4_tcp_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2545 tuple_sets->ipv4_udp_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2546 tuple_sets->ipv4_sctp_en = HCLGEVF_RSS_INPUT_TUPLE_SCTP; 2547 tuple_sets->ipv4_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2548 tuple_sets->ipv6_tcp_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2549 tuple_sets->ipv6_udp_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2550 tuple_sets->ipv6_sctp_en = 2551 hdev->ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2 ? 2552 HCLGEVF_RSS_INPUT_TUPLE_SCTP_NO_PORT : 2553 HCLGEVF_RSS_INPUT_TUPLE_SCTP; 2554 tuple_sets->ipv6_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2555 } 2556 2557 /* Initialize RSS indirect table */ 2558 for (i = 0; i < rss_ind_tbl_size; i++) 2559 rss_cfg->rss_indirection_tbl[i] = i % rss_cfg->rss_size; 2560 2561 return 0; 2562 } 2563 2564 static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev) 2565 { 2566 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 2567 int ret; 2568 2569 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 2570 ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 2571 rss_cfg->rss_hash_key); 2572 if (ret) 2573 return ret; 2574 2575 ret = hclgevf_set_rss_input_tuple(hdev, rss_cfg); 2576 if (ret) 2577 return ret; 2578 } 2579 2580 ret = hclgevf_set_rss_indir_table(hdev); 2581 if (ret) 2582 return ret; 2583 2584 return hclgevf_set_rss_tc_mode(hdev, rss_cfg->rss_size); 2585 } 2586 2587 static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev) 2588 { 2589 return hclgevf_set_vlan_filter(&hdev->nic, htons(ETH_P_8021Q), 0, 2590 false); 2591 } 2592 2593 static void hclgevf_flush_link_update(struct hclgevf_dev *hdev) 2594 { 2595 #define HCLGEVF_FLUSH_LINK_TIMEOUT 100000 2596 2597 unsigned long last = hdev->serv_processed_cnt; 2598 int i = 0; 2599 2600 while (test_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state) && 2601 i++ < HCLGEVF_FLUSH_LINK_TIMEOUT && 2602 last == hdev->serv_processed_cnt) 2603 usleep_range(1, 1); 2604 } 2605 2606 static void hclgevf_set_timer_task(struct hnae3_handle *handle, bool enable) 2607 { 2608 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2609 2610 if (enable) { 2611 hclgevf_task_schedule(hdev, 0); 2612 } else { 2613 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2614 2615 /* flush memory to make sure DOWN is seen by service task */ 2616 smp_mb__before_atomic(); 2617 hclgevf_flush_link_update(hdev); 2618 } 2619 } 2620 2621 static int hclgevf_ae_start(struct hnae3_handle *handle) 2622 { 2623 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2624 2625 hclgevf_reset_tqp_stats(handle); 2626 2627 hclgevf_request_link_info(hdev); 2628 2629 hclgevf_update_link_mode(hdev); 2630 2631 clear_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2632 2633 return 0; 2634 } 2635 2636 static void hclgevf_ae_stop(struct hnae3_handle *handle) 2637 { 2638 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2639 int i; 2640 2641 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2642 2643 if (hdev->reset_type != HNAE3_VF_RESET) 2644 for (i = 0; i < handle->kinfo.num_tqps; i++) 2645 if (hclgevf_reset_tqp(handle, i)) 2646 break; 2647 2648 hclgevf_reset_tqp_stats(handle); 2649 hclgevf_update_link_status(hdev, 0); 2650 } 2651 2652 static int hclgevf_set_alive(struct hnae3_handle *handle, bool alive) 2653 { 2654 #define HCLGEVF_STATE_ALIVE 1 2655 #define HCLGEVF_STATE_NOT_ALIVE 0 2656 2657 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2658 struct hclge_vf_to_pf_msg send_msg; 2659 2660 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_ALIVE, 0); 2661 send_msg.data[0] = alive ? HCLGEVF_STATE_ALIVE : 2662 HCLGEVF_STATE_NOT_ALIVE; 2663 return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 2664 } 2665 2666 static int hclgevf_client_start(struct hnae3_handle *handle) 2667 { 2668 return hclgevf_set_alive(handle, true); 2669 } 2670 2671 static void hclgevf_client_stop(struct hnae3_handle *handle) 2672 { 2673 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2674 int ret; 2675 2676 ret = hclgevf_set_alive(handle, false); 2677 if (ret) 2678 dev_warn(&hdev->pdev->dev, 2679 "%s failed %d\n", __func__, ret); 2680 } 2681 2682 static void hclgevf_state_init(struct hclgevf_dev *hdev) 2683 { 2684 clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 2685 clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 2686 clear_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state); 2687 2688 INIT_DELAYED_WORK(&hdev->service_task, hclgevf_service_task); 2689 2690 mutex_init(&hdev->mbx_resp.mbx_mutex); 2691 sema_init(&hdev->reset_sem, 1); 2692 2693 spin_lock_init(&hdev->mac_table.mac_list_lock); 2694 INIT_LIST_HEAD(&hdev->mac_table.uc_mac_list); 2695 INIT_LIST_HEAD(&hdev->mac_table.mc_mac_list); 2696 2697 /* bring the device down */ 2698 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2699 } 2700 2701 static void hclgevf_state_uninit(struct hclgevf_dev *hdev) 2702 { 2703 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2704 set_bit(HCLGEVF_STATE_REMOVING, &hdev->state); 2705 2706 if (hdev->service_task.work.func) 2707 cancel_delayed_work_sync(&hdev->service_task); 2708 2709 mutex_destroy(&hdev->mbx_resp.mbx_mutex); 2710 } 2711 2712 static int hclgevf_init_msi(struct hclgevf_dev *hdev) 2713 { 2714 struct pci_dev *pdev = hdev->pdev; 2715 int vectors; 2716 int i; 2717 2718 if (hnae3_dev_roce_supported(hdev)) 2719 vectors = pci_alloc_irq_vectors(pdev, 2720 hdev->roce_base_msix_offset + 1, 2721 hdev->num_msi, 2722 PCI_IRQ_MSIX); 2723 else 2724 vectors = pci_alloc_irq_vectors(pdev, HNAE3_MIN_VECTOR_NUM, 2725 hdev->num_msi, 2726 PCI_IRQ_MSI | PCI_IRQ_MSIX); 2727 2728 if (vectors < 0) { 2729 dev_err(&pdev->dev, 2730 "failed(%d) to allocate MSI/MSI-X vectors\n", 2731 vectors); 2732 return vectors; 2733 } 2734 if (vectors < hdev->num_msi) 2735 dev_warn(&hdev->pdev->dev, 2736 "requested %u MSI/MSI-X, but allocated %d MSI/MSI-X\n", 2737 hdev->num_msi, vectors); 2738 2739 hdev->num_msi = vectors; 2740 hdev->num_msi_left = vectors; 2741 2742 hdev->base_msi_vector = pdev->irq; 2743 hdev->roce_base_vector = pdev->irq + hdev->roce_base_msix_offset; 2744 2745 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 2746 sizeof(u16), GFP_KERNEL); 2747 if (!hdev->vector_status) { 2748 pci_free_irq_vectors(pdev); 2749 return -ENOMEM; 2750 } 2751 2752 for (i = 0; i < hdev->num_msi; i++) 2753 hdev->vector_status[i] = HCLGEVF_INVALID_VPORT; 2754 2755 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 2756 sizeof(int), GFP_KERNEL); 2757 if (!hdev->vector_irq) { 2758 devm_kfree(&pdev->dev, hdev->vector_status); 2759 pci_free_irq_vectors(pdev); 2760 return -ENOMEM; 2761 } 2762 2763 return 0; 2764 } 2765 2766 static void hclgevf_uninit_msi(struct hclgevf_dev *hdev) 2767 { 2768 struct pci_dev *pdev = hdev->pdev; 2769 2770 devm_kfree(&pdev->dev, hdev->vector_status); 2771 devm_kfree(&pdev->dev, hdev->vector_irq); 2772 pci_free_irq_vectors(pdev); 2773 } 2774 2775 static int hclgevf_misc_irq_init(struct hclgevf_dev *hdev) 2776 { 2777 int ret; 2778 2779 hclgevf_get_misc_vector(hdev); 2780 2781 snprintf(hdev->misc_vector.name, HNAE3_INT_NAME_LEN, "%s-misc-%s", 2782 HCLGEVF_NAME, pci_name(hdev->pdev)); 2783 ret = request_irq(hdev->misc_vector.vector_irq, hclgevf_misc_irq_handle, 2784 0, hdev->misc_vector.name, hdev); 2785 if (ret) { 2786 dev_err(&hdev->pdev->dev, "VF failed to request misc irq(%d)\n", 2787 hdev->misc_vector.vector_irq); 2788 return ret; 2789 } 2790 2791 hclgevf_clear_event_cause(hdev, 0); 2792 2793 /* enable misc. vector(vector 0) */ 2794 hclgevf_enable_vector(&hdev->misc_vector, true); 2795 2796 return ret; 2797 } 2798 2799 static void hclgevf_misc_irq_uninit(struct hclgevf_dev *hdev) 2800 { 2801 /* disable misc vector(vector 0) */ 2802 hclgevf_enable_vector(&hdev->misc_vector, false); 2803 synchronize_irq(hdev->misc_vector.vector_irq); 2804 free_irq(hdev->misc_vector.vector_irq, hdev); 2805 hclgevf_free_vector(hdev, 0); 2806 } 2807 2808 static void hclgevf_info_show(struct hclgevf_dev *hdev) 2809 { 2810 struct device *dev = &hdev->pdev->dev; 2811 2812 dev_info(dev, "VF info begin:\n"); 2813 2814 dev_info(dev, "Task queue pairs numbers: %u\n", hdev->num_tqps); 2815 dev_info(dev, "Desc num per TX queue: %u\n", hdev->num_tx_desc); 2816 dev_info(dev, "Desc num per RX queue: %u\n", hdev->num_rx_desc); 2817 dev_info(dev, "Numbers of vports: %u\n", hdev->num_alloc_vport); 2818 dev_info(dev, "HW tc map: 0x%x\n", hdev->hw_tc_map); 2819 dev_info(dev, "PF media type of this VF: %u\n", 2820 hdev->hw.mac.media_type); 2821 2822 dev_info(dev, "VF info end.\n"); 2823 } 2824 2825 static int hclgevf_init_nic_client_instance(struct hnae3_ae_dev *ae_dev, 2826 struct hnae3_client *client) 2827 { 2828 struct hclgevf_dev *hdev = ae_dev->priv; 2829 int rst_cnt = hdev->rst_stats.rst_cnt; 2830 int ret; 2831 2832 ret = client->ops->init_instance(&hdev->nic); 2833 if (ret) 2834 return ret; 2835 2836 set_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 2837 if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) || 2838 rst_cnt != hdev->rst_stats.rst_cnt) { 2839 clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 2840 2841 client->ops->uninit_instance(&hdev->nic, 0); 2842 return -EBUSY; 2843 } 2844 2845 hnae3_set_client_init_flag(client, ae_dev, 1); 2846 2847 if (netif_msg_drv(&hdev->nic)) 2848 hclgevf_info_show(hdev); 2849 2850 return 0; 2851 } 2852 2853 static int hclgevf_init_roce_client_instance(struct hnae3_ae_dev *ae_dev, 2854 struct hnae3_client *client) 2855 { 2856 struct hclgevf_dev *hdev = ae_dev->priv; 2857 int ret; 2858 2859 if (!hnae3_dev_roce_supported(hdev) || !hdev->roce_client || 2860 !hdev->nic_client) 2861 return 0; 2862 2863 ret = hclgevf_init_roce_base_info(hdev); 2864 if (ret) 2865 return ret; 2866 2867 ret = client->ops->init_instance(&hdev->roce); 2868 if (ret) 2869 return ret; 2870 2871 set_bit(HCLGEVF_STATE_ROCE_REGISTERED, &hdev->state); 2872 hnae3_set_client_init_flag(client, ae_dev, 1); 2873 2874 return 0; 2875 } 2876 2877 static int hclgevf_init_client_instance(struct hnae3_client *client, 2878 struct hnae3_ae_dev *ae_dev) 2879 { 2880 struct hclgevf_dev *hdev = ae_dev->priv; 2881 int ret; 2882 2883 switch (client->type) { 2884 case HNAE3_CLIENT_KNIC: 2885 hdev->nic_client = client; 2886 hdev->nic.client = client; 2887 2888 ret = hclgevf_init_nic_client_instance(ae_dev, client); 2889 if (ret) 2890 goto clear_nic; 2891 2892 ret = hclgevf_init_roce_client_instance(ae_dev, 2893 hdev->roce_client); 2894 if (ret) 2895 goto clear_roce; 2896 2897 break; 2898 case HNAE3_CLIENT_ROCE: 2899 if (hnae3_dev_roce_supported(hdev)) { 2900 hdev->roce_client = client; 2901 hdev->roce.client = client; 2902 } 2903 2904 ret = hclgevf_init_roce_client_instance(ae_dev, client); 2905 if (ret) 2906 goto clear_roce; 2907 2908 break; 2909 default: 2910 return -EINVAL; 2911 } 2912 2913 return 0; 2914 2915 clear_nic: 2916 hdev->nic_client = NULL; 2917 hdev->nic.client = NULL; 2918 return ret; 2919 clear_roce: 2920 hdev->roce_client = NULL; 2921 hdev->roce.client = NULL; 2922 return ret; 2923 } 2924 2925 static void hclgevf_uninit_client_instance(struct hnae3_client *client, 2926 struct hnae3_ae_dev *ae_dev) 2927 { 2928 struct hclgevf_dev *hdev = ae_dev->priv; 2929 2930 /* un-init roce, if it exists */ 2931 if (hdev->roce_client) { 2932 clear_bit(HCLGEVF_STATE_ROCE_REGISTERED, &hdev->state); 2933 hdev->roce_client->ops->uninit_instance(&hdev->roce, 0); 2934 hdev->roce_client = NULL; 2935 hdev->roce.client = NULL; 2936 } 2937 2938 /* un-init nic/unic, if this was not called by roce client */ 2939 if (client->ops->uninit_instance && hdev->nic_client && 2940 client->type != HNAE3_CLIENT_ROCE) { 2941 clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 2942 2943 client->ops->uninit_instance(&hdev->nic, 0); 2944 hdev->nic_client = NULL; 2945 hdev->nic.client = NULL; 2946 } 2947 } 2948 2949 static int hclgevf_dev_mem_map(struct hclgevf_dev *hdev) 2950 { 2951 #define HCLGEVF_MEM_BAR 4 2952 2953 struct pci_dev *pdev = hdev->pdev; 2954 struct hclgevf_hw *hw = &hdev->hw; 2955 2956 /* for device does not have device memory, return directly */ 2957 if (!(pci_select_bars(pdev, IORESOURCE_MEM) & BIT(HCLGEVF_MEM_BAR))) 2958 return 0; 2959 2960 hw->mem_base = devm_ioremap_wc(&pdev->dev, 2961 pci_resource_start(pdev, 2962 HCLGEVF_MEM_BAR), 2963 pci_resource_len(pdev, HCLGEVF_MEM_BAR)); 2964 if (!hw->mem_base) { 2965 dev_err(&pdev->dev, "failed to map device memory\n"); 2966 return -EFAULT; 2967 } 2968 2969 return 0; 2970 } 2971 2972 static int hclgevf_pci_init(struct hclgevf_dev *hdev) 2973 { 2974 struct pci_dev *pdev = hdev->pdev; 2975 struct hclgevf_hw *hw; 2976 int ret; 2977 2978 ret = pci_enable_device(pdev); 2979 if (ret) { 2980 dev_err(&pdev->dev, "failed to enable PCI device\n"); 2981 return ret; 2982 } 2983 2984 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 2985 if (ret) { 2986 dev_err(&pdev->dev, "can't set consistent PCI DMA, exiting"); 2987 goto err_disable_device; 2988 } 2989 2990 ret = pci_request_regions(pdev, HCLGEVF_DRIVER_NAME); 2991 if (ret) { 2992 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 2993 goto err_disable_device; 2994 } 2995 2996 pci_set_master(pdev); 2997 hw = &hdev->hw; 2998 hw->hdev = hdev; 2999 hw->io_base = pci_iomap(pdev, 2, 0); 3000 if (!hw->io_base) { 3001 dev_err(&pdev->dev, "can't map configuration register space\n"); 3002 ret = -ENOMEM; 3003 goto err_clr_master; 3004 } 3005 3006 ret = hclgevf_dev_mem_map(hdev); 3007 if (ret) 3008 goto err_unmap_io_base; 3009 3010 return 0; 3011 3012 err_unmap_io_base: 3013 pci_iounmap(pdev, hdev->hw.io_base); 3014 err_clr_master: 3015 pci_clear_master(pdev); 3016 pci_release_regions(pdev); 3017 err_disable_device: 3018 pci_disable_device(pdev); 3019 3020 return ret; 3021 } 3022 3023 static void hclgevf_pci_uninit(struct hclgevf_dev *hdev) 3024 { 3025 struct pci_dev *pdev = hdev->pdev; 3026 3027 if (hdev->hw.mem_base) 3028 devm_iounmap(&pdev->dev, hdev->hw.mem_base); 3029 3030 pci_iounmap(pdev, hdev->hw.io_base); 3031 pci_clear_master(pdev); 3032 pci_release_regions(pdev); 3033 pci_disable_device(pdev); 3034 } 3035 3036 static int hclgevf_query_vf_resource(struct hclgevf_dev *hdev) 3037 { 3038 struct hclgevf_query_res_cmd *req; 3039 struct hclgevf_desc desc; 3040 int ret; 3041 3042 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_VF_RSRC, true); 3043 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 3044 if (ret) { 3045 dev_err(&hdev->pdev->dev, 3046 "query vf resource failed, ret = %d.\n", ret); 3047 return ret; 3048 } 3049 3050 req = (struct hclgevf_query_res_cmd *)desc.data; 3051 3052 if (hnae3_dev_roce_supported(hdev)) { 3053 hdev->roce_base_msix_offset = 3054 hnae3_get_field(le16_to_cpu(req->msixcap_localid_ba_rocee), 3055 HCLGEVF_MSIX_OFT_ROCEE_M, 3056 HCLGEVF_MSIX_OFT_ROCEE_S); 3057 hdev->num_roce_msix = 3058 hnae3_get_field(le16_to_cpu(req->vf_intr_vector_number), 3059 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 3060 3061 /* nic's msix numbers is always equals to the roce's. */ 3062 hdev->num_nic_msix = hdev->num_roce_msix; 3063 3064 /* VF should have NIC vectors and Roce vectors, NIC vectors 3065 * are queued before Roce vectors. The offset is fixed to 64. 3066 */ 3067 hdev->num_msi = hdev->num_roce_msix + 3068 hdev->roce_base_msix_offset; 3069 } else { 3070 hdev->num_msi = 3071 hnae3_get_field(le16_to_cpu(req->vf_intr_vector_number), 3072 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 3073 3074 hdev->num_nic_msix = hdev->num_msi; 3075 } 3076 3077 if (hdev->num_nic_msix < HNAE3_MIN_VECTOR_NUM) { 3078 dev_err(&hdev->pdev->dev, 3079 "Just %u msi resources, not enough for vf(min:2).\n", 3080 hdev->num_nic_msix); 3081 return -EINVAL; 3082 } 3083 3084 return 0; 3085 } 3086 3087 static void hclgevf_set_default_dev_specs(struct hclgevf_dev *hdev) 3088 { 3089 #define HCLGEVF_MAX_NON_TSO_BD_NUM 8U 3090 3091 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 3092 3093 ae_dev->dev_specs.max_non_tso_bd_num = 3094 HCLGEVF_MAX_NON_TSO_BD_NUM; 3095 ae_dev->dev_specs.rss_ind_tbl_size = HCLGEVF_RSS_IND_TBL_SIZE; 3096 ae_dev->dev_specs.rss_key_size = HCLGEVF_RSS_KEY_SIZE; 3097 ae_dev->dev_specs.max_int_gl = HCLGEVF_DEF_MAX_INT_GL; 3098 ae_dev->dev_specs.max_frm_size = HCLGEVF_MAC_MAX_FRAME; 3099 } 3100 3101 static void hclgevf_parse_dev_specs(struct hclgevf_dev *hdev, 3102 struct hclgevf_desc *desc) 3103 { 3104 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 3105 struct hclgevf_dev_specs_0_cmd *req0; 3106 struct hclgevf_dev_specs_1_cmd *req1; 3107 3108 req0 = (struct hclgevf_dev_specs_0_cmd *)desc[0].data; 3109 req1 = (struct hclgevf_dev_specs_1_cmd *)desc[1].data; 3110 3111 ae_dev->dev_specs.max_non_tso_bd_num = req0->max_non_tso_bd_num; 3112 ae_dev->dev_specs.rss_ind_tbl_size = 3113 le16_to_cpu(req0->rss_ind_tbl_size); 3114 ae_dev->dev_specs.int_ql_max = le16_to_cpu(req0->int_ql_max); 3115 ae_dev->dev_specs.rss_key_size = le16_to_cpu(req0->rss_key_size); 3116 ae_dev->dev_specs.max_int_gl = le16_to_cpu(req1->max_int_gl); 3117 ae_dev->dev_specs.max_frm_size = le16_to_cpu(req1->max_frm_size); 3118 } 3119 3120 static void hclgevf_check_dev_specs(struct hclgevf_dev *hdev) 3121 { 3122 struct hnae3_dev_specs *dev_specs = &hdev->ae_dev->dev_specs; 3123 3124 if (!dev_specs->max_non_tso_bd_num) 3125 dev_specs->max_non_tso_bd_num = HCLGEVF_MAX_NON_TSO_BD_NUM; 3126 if (!dev_specs->rss_ind_tbl_size) 3127 dev_specs->rss_ind_tbl_size = HCLGEVF_RSS_IND_TBL_SIZE; 3128 if (!dev_specs->rss_key_size) 3129 dev_specs->rss_key_size = HCLGEVF_RSS_KEY_SIZE; 3130 if (!dev_specs->max_int_gl) 3131 dev_specs->max_int_gl = HCLGEVF_DEF_MAX_INT_GL; 3132 if (!dev_specs->max_frm_size) 3133 dev_specs->max_frm_size = HCLGEVF_MAC_MAX_FRAME; 3134 } 3135 3136 static int hclgevf_query_dev_specs(struct hclgevf_dev *hdev) 3137 { 3138 struct hclgevf_desc desc[HCLGEVF_QUERY_DEV_SPECS_BD_NUM]; 3139 int ret; 3140 int i; 3141 3142 /* set default specifications as devices lower than version V3 do not 3143 * support querying specifications from firmware. 3144 */ 3145 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3) { 3146 hclgevf_set_default_dev_specs(hdev); 3147 return 0; 3148 } 3149 3150 for (i = 0; i < HCLGEVF_QUERY_DEV_SPECS_BD_NUM - 1; i++) { 3151 hclgevf_cmd_setup_basic_desc(&desc[i], 3152 HCLGEVF_OPC_QUERY_DEV_SPECS, true); 3153 desc[i].flag |= cpu_to_le16(HCLGEVF_CMD_FLAG_NEXT); 3154 } 3155 hclgevf_cmd_setup_basic_desc(&desc[i], HCLGEVF_OPC_QUERY_DEV_SPECS, 3156 true); 3157 3158 ret = hclgevf_cmd_send(&hdev->hw, desc, HCLGEVF_QUERY_DEV_SPECS_BD_NUM); 3159 if (ret) 3160 return ret; 3161 3162 hclgevf_parse_dev_specs(hdev, desc); 3163 hclgevf_check_dev_specs(hdev); 3164 3165 return 0; 3166 } 3167 3168 static int hclgevf_pci_reset(struct hclgevf_dev *hdev) 3169 { 3170 struct pci_dev *pdev = hdev->pdev; 3171 int ret = 0; 3172 3173 if (hdev->reset_type == HNAE3_VF_FULL_RESET && 3174 test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 3175 hclgevf_misc_irq_uninit(hdev); 3176 hclgevf_uninit_msi(hdev); 3177 clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 3178 } 3179 3180 if (!test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 3181 pci_set_master(pdev); 3182 ret = hclgevf_init_msi(hdev); 3183 if (ret) { 3184 dev_err(&pdev->dev, 3185 "failed(%d) to init MSI/MSI-X\n", ret); 3186 return ret; 3187 } 3188 3189 ret = hclgevf_misc_irq_init(hdev); 3190 if (ret) { 3191 hclgevf_uninit_msi(hdev); 3192 dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 3193 ret); 3194 return ret; 3195 } 3196 3197 set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 3198 } 3199 3200 return ret; 3201 } 3202 3203 static int hclgevf_clear_vport_list(struct hclgevf_dev *hdev) 3204 { 3205 struct hclge_vf_to_pf_msg send_msg; 3206 3207 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_HANDLE_VF_TBL, 3208 HCLGE_MBX_VPORT_LIST_CLEAR); 3209 return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 3210 } 3211 3212 static int hclgevf_reset_hdev(struct hclgevf_dev *hdev) 3213 { 3214 struct pci_dev *pdev = hdev->pdev; 3215 int ret; 3216 3217 ret = hclgevf_pci_reset(hdev); 3218 if (ret) { 3219 dev_err(&pdev->dev, "pci reset failed %d\n", ret); 3220 return ret; 3221 } 3222 3223 ret = hclgevf_cmd_init(hdev); 3224 if (ret) { 3225 dev_err(&pdev->dev, "cmd failed %d\n", ret); 3226 return ret; 3227 } 3228 3229 ret = hclgevf_rss_init_hw(hdev); 3230 if (ret) { 3231 dev_err(&hdev->pdev->dev, 3232 "failed(%d) to initialize RSS\n", ret); 3233 return ret; 3234 } 3235 3236 ret = hclgevf_config_gro(hdev, true); 3237 if (ret) 3238 return ret; 3239 3240 ret = hclgevf_init_vlan_config(hdev); 3241 if (ret) { 3242 dev_err(&hdev->pdev->dev, 3243 "failed(%d) to initialize VLAN config\n", ret); 3244 return ret; 3245 } 3246 3247 set_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state); 3248 3249 dev_info(&hdev->pdev->dev, "Reset done\n"); 3250 3251 return 0; 3252 } 3253 3254 static int hclgevf_init_hdev(struct hclgevf_dev *hdev) 3255 { 3256 struct pci_dev *pdev = hdev->pdev; 3257 int ret; 3258 3259 ret = hclgevf_pci_init(hdev); 3260 if (ret) 3261 return ret; 3262 3263 ret = hclgevf_cmd_queue_init(hdev); 3264 if (ret) 3265 goto err_cmd_queue_init; 3266 3267 ret = hclgevf_cmd_init(hdev); 3268 if (ret) 3269 goto err_cmd_init; 3270 3271 /* Get vf resource */ 3272 ret = hclgevf_query_vf_resource(hdev); 3273 if (ret) 3274 goto err_cmd_init; 3275 3276 ret = hclgevf_query_dev_specs(hdev); 3277 if (ret) { 3278 dev_err(&pdev->dev, 3279 "failed to query dev specifications, ret = %d\n", ret); 3280 goto err_cmd_init; 3281 } 3282 3283 ret = hclgevf_init_msi(hdev); 3284 if (ret) { 3285 dev_err(&pdev->dev, "failed(%d) to init MSI/MSI-X\n", ret); 3286 goto err_cmd_init; 3287 } 3288 3289 hclgevf_state_init(hdev); 3290 hdev->reset_level = HNAE3_VF_FUNC_RESET; 3291 hdev->reset_type = HNAE3_NONE_RESET; 3292 3293 ret = hclgevf_misc_irq_init(hdev); 3294 if (ret) 3295 goto err_misc_irq_init; 3296 3297 set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 3298 3299 ret = hclgevf_configure(hdev); 3300 if (ret) { 3301 dev_err(&pdev->dev, "failed(%d) to fetch configuration\n", ret); 3302 goto err_config; 3303 } 3304 3305 ret = hclgevf_alloc_tqps(hdev); 3306 if (ret) { 3307 dev_err(&pdev->dev, "failed(%d) to allocate TQPs\n", ret); 3308 goto err_config; 3309 } 3310 3311 ret = hclgevf_set_handle_info(hdev); 3312 if (ret) 3313 goto err_config; 3314 3315 ret = hclgevf_config_gro(hdev, true); 3316 if (ret) 3317 goto err_config; 3318 3319 /* Initialize RSS for this VF */ 3320 ret = hclgevf_rss_init_cfg(hdev); 3321 if (ret) { 3322 dev_err(&pdev->dev, "failed to init rss cfg, ret = %d\n", ret); 3323 goto err_config; 3324 } 3325 3326 ret = hclgevf_rss_init_hw(hdev); 3327 if (ret) { 3328 dev_err(&hdev->pdev->dev, 3329 "failed(%d) to initialize RSS\n", ret); 3330 goto err_config; 3331 } 3332 3333 /* ensure vf tbl list as empty before init*/ 3334 ret = hclgevf_clear_vport_list(hdev); 3335 if (ret) { 3336 dev_err(&pdev->dev, 3337 "failed to clear tbl list configuration, ret = %d.\n", 3338 ret); 3339 goto err_config; 3340 } 3341 3342 ret = hclgevf_init_vlan_config(hdev); 3343 if (ret) { 3344 dev_err(&hdev->pdev->dev, 3345 "failed(%d) to initialize VLAN config\n", ret); 3346 goto err_config; 3347 } 3348 3349 hdev->last_reset_time = jiffies; 3350 dev_info(&hdev->pdev->dev, "finished initializing %s driver\n", 3351 HCLGEVF_DRIVER_NAME); 3352 3353 hclgevf_task_schedule(hdev, round_jiffies_relative(HZ)); 3354 3355 return 0; 3356 3357 err_config: 3358 hclgevf_misc_irq_uninit(hdev); 3359 err_misc_irq_init: 3360 hclgevf_state_uninit(hdev); 3361 hclgevf_uninit_msi(hdev); 3362 err_cmd_init: 3363 hclgevf_cmd_uninit(hdev); 3364 err_cmd_queue_init: 3365 hclgevf_pci_uninit(hdev); 3366 clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 3367 return ret; 3368 } 3369 3370 static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev) 3371 { 3372 struct hclge_vf_to_pf_msg send_msg; 3373 3374 hclgevf_state_uninit(hdev); 3375 3376 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_VF_UNINIT, 0); 3377 hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 3378 3379 if (test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 3380 hclgevf_misc_irq_uninit(hdev); 3381 hclgevf_uninit_msi(hdev); 3382 } 3383 3384 hclgevf_cmd_uninit(hdev); 3385 hclgevf_pci_uninit(hdev); 3386 hclgevf_uninit_mac_list(hdev); 3387 } 3388 3389 static int hclgevf_init_ae_dev(struct hnae3_ae_dev *ae_dev) 3390 { 3391 struct pci_dev *pdev = ae_dev->pdev; 3392 int ret; 3393 3394 ret = hclgevf_alloc_hdev(ae_dev); 3395 if (ret) { 3396 dev_err(&pdev->dev, "hclge device allocation failed\n"); 3397 return ret; 3398 } 3399 3400 ret = hclgevf_init_hdev(ae_dev->priv); 3401 if (ret) { 3402 dev_err(&pdev->dev, "hclge device initialization failed\n"); 3403 return ret; 3404 } 3405 3406 return 0; 3407 } 3408 3409 static void hclgevf_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 3410 { 3411 struct hclgevf_dev *hdev = ae_dev->priv; 3412 3413 hclgevf_uninit_hdev(hdev); 3414 ae_dev->priv = NULL; 3415 } 3416 3417 static u32 hclgevf_get_max_channels(struct hclgevf_dev *hdev) 3418 { 3419 struct hnae3_handle *nic = &hdev->nic; 3420 struct hnae3_knic_private_info *kinfo = &nic->kinfo; 3421 3422 return min_t(u32, hdev->rss_size_max, 3423 hdev->num_tqps / kinfo->tc_info.num_tc); 3424 } 3425 3426 /** 3427 * hclgevf_get_channels - Get the current channels enabled and max supported. 3428 * @handle: hardware information for network interface 3429 * @ch: ethtool channels structure 3430 * 3431 * We don't support separate tx and rx queues as channels. The other count 3432 * represents how many queues are being used for control. max_combined counts 3433 * how many queue pairs we can support. They may not be mapped 1 to 1 with 3434 * q_vectors since we support a lot more queue pairs than q_vectors. 3435 **/ 3436 static void hclgevf_get_channels(struct hnae3_handle *handle, 3437 struct ethtool_channels *ch) 3438 { 3439 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3440 3441 ch->max_combined = hclgevf_get_max_channels(hdev); 3442 ch->other_count = 0; 3443 ch->max_other = 0; 3444 ch->combined_count = handle->kinfo.rss_size; 3445 } 3446 3447 static void hclgevf_get_tqps_and_rss_info(struct hnae3_handle *handle, 3448 u16 *alloc_tqps, u16 *max_rss_size) 3449 { 3450 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3451 3452 *alloc_tqps = hdev->num_tqps; 3453 *max_rss_size = hdev->rss_size_max; 3454 } 3455 3456 static void hclgevf_update_rss_size(struct hnae3_handle *handle, 3457 u32 new_tqps_num) 3458 { 3459 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 3460 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3461 u16 max_rss_size; 3462 3463 kinfo->req_rss_size = new_tqps_num; 3464 3465 max_rss_size = min_t(u16, hdev->rss_size_max, 3466 hdev->num_tqps / kinfo->tc_info.num_tc); 3467 3468 /* Use the user's configuration when it is not larger than 3469 * max_rss_size, otherwise, use the maximum specification value. 3470 */ 3471 if (kinfo->req_rss_size != kinfo->rss_size && kinfo->req_rss_size && 3472 kinfo->req_rss_size <= max_rss_size) 3473 kinfo->rss_size = kinfo->req_rss_size; 3474 else if (kinfo->rss_size > max_rss_size || 3475 (!kinfo->req_rss_size && kinfo->rss_size < max_rss_size)) 3476 kinfo->rss_size = max_rss_size; 3477 3478 kinfo->num_tqps = kinfo->tc_info.num_tc * kinfo->rss_size; 3479 } 3480 3481 static int hclgevf_set_channels(struct hnae3_handle *handle, u32 new_tqps_num, 3482 bool rxfh_configured) 3483 { 3484 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3485 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 3486 u16 cur_rss_size = kinfo->rss_size; 3487 u16 cur_tqps = kinfo->num_tqps; 3488 u32 *rss_indir; 3489 unsigned int i; 3490 int ret; 3491 3492 hclgevf_update_rss_size(handle, new_tqps_num); 3493 3494 ret = hclgevf_set_rss_tc_mode(hdev, kinfo->rss_size); 3495 if (ret) 3496 return ret; 3497 3498 /* RSS indirection table has been configuared by user */ 3499 if (rxfh_configured) 3500 goto out; 3501 3502 /* Reinitializes the rss indirect table according to the new RSS size */ 3503 rss_indir = kcalloc(hdev->ae_dev->dev_specs.rss_ind_tbl_size, 3504 sizeof(u32), GFP_KERNEL); 3505 if (!rss_indir) 3506 return -ENOMEM; 3507 3508 for (i = 0; i < hdev->ae_dev->dev_specs.rss_ind_tbl_size; i++) 3509 rss_indir[i] = i % kinfo->rss_size; 3510 3511 hdev->rss_cfg.rss_size = kinfo->rss_size; 3512 3513 ret = hclgevf_set_rss(handle, rss_indir, NULL, 0); 3514 if (ret) 3515 dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n", 3516 ret); 3517 3518 kfree(rss_indir); 3519 3520 out: 3521 if (!ret) 3522 dev_info(&hdev->pdev->dev, 3523 "Channels changed, rss_size from %u to %u, tqps from %u to %u", 3524 cur_rss_size, kinfo->rss_size, 3525 cur_tqps, kinfo->rss_size * kinfo->tc_info.num_tc); 3526 3527 return ret; 3528 } 3529 3530 static int hclgevf_get_status(struct hnae3_handle *handle) 3531 { 3532 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3533 3534 return hdev->hw.mac.link; 3535 } 3536 3537 static void hclgevf_get_ksettings_an_result(struct hnae3_handle *handle, 3538 u8 *auto_neg, u32 *speed, 3539 u8 *duplex) 3540 { 3541 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3542 3543 if (speed) 3544 *speed = hdev->hw.mac.speed; 3545 if (duplex) 3546 *duplex = hdev->hw.mac.duplex; 3547 if (auto_neg) 3548 *auto_neg = AUTONEG_DISABLE; 3549 } 3550 3551 void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed, 3552 u8 duplex) 3553 { 3554 hdev->hw.mac.speed = speed; 3555 hdev->hw.mac.duplex = duplex; 3556 } 3557 3558 static int hclgevf_gro_en(struct hnae3_handle *handle, bool enable) 3559 { 3560 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3561 3562 return hclgevf_config_gro(hdev, enable); 3563 } 3564 3565 static void hclgevf_get_media_type(struct hnae3_handle *handle, u8 *media_type, 3566 u8 *module_type) 3567 { 3568 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3569 3570 if (media_type) 3571 *media_type = hdev->hw.mac.media_type; 3572 3573 if (module_type) 3574 *module_type = hdev->hw.mac.module_type; 3575 } 3576 3577 static bool hclgevf_get_hw_reset_stat(struct hnae3_handle *handle) 3578 { 3579 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3580 3581 return !!hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 3582 } 3583 3584 static bool hclgevf_get_cmdq_stat(struct hnae3_handle *handle) 3585 { 3586 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3587 3588 return test_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 3589 } 3590 3591 static bool hclgevf_ae_dev_resetting(struct hnae3_handle *handle) 3592 { 3593 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3594 3595 return test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 3596 } 3597 3598 static unsigned long hclgevf_ae_dev_reset_cnt(struct hnae3_handle *handle) 3599 { 3600 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3601 3602 return hdev->rst_stats.hw_rst_done_cnt; 3603 } 3604 3605 static void hclgevf_get_link_mode(struct hnae3_handle *handle, 3606 unsigned long *supported, 3607 unsigned long *advertising) 3608 { 3609 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3610 3611 *supported = hdev->hw.mac.supported; 3612 *advertising = hdev->hw.mac.advertising; 3613 } 3614 3615 #define MAX_SEPARATE_NUM 4 3616 #define SEPARATOR_VALUE 0xFFFFFFFF 3617 #define REG_NUM_PER_LINE 4 3618 #define REG_LEN_PER_LINE (REG_NUM_PER_LINE * sizeof(u32)) 3619 3620 static int hclgevf_get_regs_len(struct hnae3_handle *handle) 3621 { 3622 int cmdq_lines, common_lines, ring_lines, tqp_intr_lines; 3623 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3624 3625 cmdq_lines = sizeof(cmdq_reg_addr_list) / REG_LEN_PER_LINE + 1; 3626 common_lines = sizeof(common_reg_addr_list) / REG_LEN_PER_LINE + 1; 3627 ring_lines = sizeof(ring_reg_addr_list) / REG_LEN_PER_LINE + 1; 3628 tqp_intr_lines = sizeof(tqp_intr_reg_addr_list) / REG_LEN_PER_LINE + 1; 3629 3630 return (cmdq_lines + common_lines + ring_lines * hdev->num_tqps + 3631 tqp_intr_lines * (hdev->num_msi_used - 1)) * REG_LEN_PER_LINE; 3632 } 3633 3634 static void hclgevf_get_regs(struct hnae3_handle *handle, u32 *version, 3635 void *data) 3636 { 3637 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3638 int i, j, reg_um, separator_num; 3639 u32 *reg = data; 3640 3641 *version = hdev->fw_version; 3642 3643 /* fetching per-VF registers values from VF PCIe register space */ 3644 reg_um = sizeof(cmdq_reg_addr_list) / sizeof(u32); 3645 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 3646 for (i = 0; i < reg_um; i++) 3647 *reg++ = hclgevf_read_dev(&hdev->hw, cmdq_reg_addr_list[i]); 3648 for (i = 0; i < separator_num; i++) 3649 *reg++ = SEPARATOR_VALUE; 3650 3651 reg_um = sizeof(common_reg_addr_list) / sizeof(u32); 3652 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 3653 for (i = 0; i < reg_um; i++) 3654 *reg++ = hclgevf_read_dev(&hdev->hw, common_reg_addr_list[i]); 3655 for (i = 0; i < separator_num; i++) 3656 *reg++ = SEPARATOR_VALUE; 3657 3658 reg_um = sizeof(ring_reg_addr_list) / sizeof(u32); 3659 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 3660 for (j = 0; j < hdev->num_tqps; j++) { 3661 for (i = 0; i < reg_um; i++) 3662 *reg++ = hclgevf_read_dev(&hdev->hw, 3663 ring_reg_addr_list[i] + 3664 0x200 * j); 3665 for (i = 0; i < separator_num; i++) 3666 *reg++ = SEPARATOR_VALUE; 3667 } 3668 3669 reg_um = sizeof(tqp_intr_reg_addr_list) / sizeof(u32); 3670 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 3671 for (j = 0; j < hdev->num_msi_used - 1; j++) { 3672 for (i = 0; i < reg_um; i++) 3673 *reg++ = hclgevf_read_dev(&hdev->hw, 3674 tqp_intr_reg_addr_list[i] + 3675 4 * j); 3676 for (i = 0; i < separator_num; i++) 3677 *reg++ = SEPARATOR_VALUE; 3678 } 3679 } 3680 3681 void hclgevf_update_port_base_vlan_info(struct hclgevf_dev *hdev, u16 state, 3682 u8 *port_base_vlan_info, u8 data_size) 3683 { 3684 struct hnae3_handle *nic = &hdev->nic; 3685 struct hclge_vf_to_pf_msg send_msg; 3686 int ret; 3687 3688 rtnl_lock(); 3689 3690 if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) || 3691 test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) { 3692 dev_warn(&hdev->pdev->dev, 3693 "is resetting when updating port based vlan info\n"); 3694 rtnl_unlock(); 3695 return; 3696 } 3697 3698 ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 3699 if (ret) { 3700 rtnl_unlock(); 3701 return; 3702 } 3703 3704 /* send msg to PF and wait update port based vlan info */ 3705 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 3706 HCLGE_MBX_PORT_BASE_VLAN_CFG); 3707 memcpy(send_msg.data, port_base_vlan_info, data_size); 3708 ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 3709 if (!ret) { 3710 if (state == HNAE3_PORT_BASE_VLAN_DISABLE) 3711 nic->port_base_vlan_state = state; 3712 else 3713 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_ENABLE; 3714 } 3715 3716 hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 3717 rtnl_unlock(); 3718 } 3719 3720 static const struct hnae3_ae_ops hclgevf_ops = { 3721 .init_ae_dev = hclgevf_init_ae_dev, 3722 .uninit_ae_dev = hclgevf_uninit_ae_dev, 3723 .flr_prepare = hclgevf_flr_prepare, 3724 .flr_done = hclgevf_flr_done, 3725 .init_client_instance = hclgevf_init_client_instance, 3726 .uninit_client_instance = hclgevf_uninit_client_instance, 3727 .start = hclgevf_ae_start, 3728 .stop = hclgevf_ae_stop, 3729 .client_start = hclgevf_client_start, 3730 .client_stop = hclgevf_client_stop, 3731 .map_ring_to_vector = hclgevf_map_ring_to_vector, 3732 .unmap_ring_from_vector = hclgevf_unmap_ring_from_vector, 3733 .get_vector = hclgevf_get_vector, 3734 .put_vector = hclgevf_put_vector, 3735 .reset_queue = hclgevf_reset_tqp, 3736 .get_mac_addr = hclgevf_get_mac_addr, 3737 .set_mac_addr = hclgevf_set_mac_addr, 3738 .add_uc_addr = hclgevf_add_uc_addr, 3739 .rm_uc_addr = hclgevf_rm_uc_addr, 3740 .add_mc_addr = hclgevf_add_mc_addr, 3741 .rm_mc_addr = hclgevf_rm_mc_addr, 3742 .get_stats = hclgevf_get_stats, 3743 .update_stats = hclgevf_update_stats, 3744 .get_strings = hclgevf_get_strings, 3745 .get_sset_count = hclgevf_get_sset_count, 3746 .get_rss_key_size = hclgevf_get_rss_key_size, 3747 .get_rss = hclgevf_get_rss, 3748 .set_rss = hclgevf_set_rss, 3749 .get_rss_tuple = hclgevf_get_rss_tuple, 3750 .set_rss_tuple = hclgevf_set_rss_tuple, 3751 .get_tc_size = hclgevf_get_tc_size, 3752 .get_fw_version = hclgevf_get_fw_version, 3753 .set_vlan_filter = hclgevf_set_vlan_filter, 3754 .enable_hw_strip_rxvtag = hclgevf_en_hw_strip_rxvtag, 3755 .reset_event = hclgevf_reset_event, 3756 .set_default_reset_request = hclgevf_set_def_reset_request, 3757 .set_channels = hclgevf_set_channels, 3758 .get_channels = hclgevf_get_channels, 3759 .get_tqps_and_rss_info = hclgevf_get_tqps_and_rss_info, 3760 .get_regs_len = hclgevf_get_regs_len, 3761 .get_regs = hclgevf_get_regs, 3762 .get_status = hclgevf_get_status, 3763 .get_ksettings_an_result = hclgevf_get_ksettings_an_result, 3764 .get_media_type = hclgevf_get_media_type, 3765 .get_hw_reset_stat = hclgevf_get_hw_reset_stat, 3766 .ae_dev_resetting = hclgevf_ae_dev_resetting, 3767 .ae_dev_reset_cnt = hclgevf_ae_dev_reset_cnt, 3768 .set_gro_en = hclgevf_gro_en, 3769 .set_mtu = hclgevf_set_mtu, 3770 .get_global_queue_id = hclgevf_get_qid_global, 3771 .set_timer_task = hclgevf_set_timer_task, 3772 .get_link_mode = hclgevf_get_link_mode, 3773 .set_promisc_mode = hclgevf_set_promisc_mode, 3774 .request_update_promisc_mode = hclgevf_request_update_promisc_mode, 3775 .get_cmdq_stat = hclgevf_get_cmdq_stat, 3776 }; 3777 3778 static struct hnae3_ae_algo ae_algovf = { 3779 .ops = &hclgevf_ops, 3780 .pdev_id_table = ae_algovf_pci_tbl, 3781 }; 3782 3783 static int hclgevf_init(void) 3784 { 3785 pr_info("%s is initializing\n", HCLGEVF_NAME); 3786 3787 hclgevf_wq = alloc_workqueue("%s", 0, 0, HCLGEVF_NAME); 3788 if (!hclgevf_wq) { 3789 pr_err("%s: failed to create workqueue\n", HCLGEVF_NAME); 3790 return -ENOMEM; 3791 } 3792 3793 hnae3_register_ae_algo(&ae_algovf); 3794 3795 return 0; 3796 } 3797 3798 static void hclgevf_exit(void) 3799 { 3800 hnae3_unregister_ae_algo(&ae_algovf); 3801 destroy_workqueue(hclgevf_wq); 3802 } 3803 module_init(hclgevf_init); 3804 module_exit(hclgevf_exit); 3805 3806 MODULE_LICENSE("GPL"); 3807 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 3808 MODULE_DESCRIPTION("HCLGEVF Driver"); 3809 MODULE_VERSION(HCLGEVF_MOD_VERSION); 3810