1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/etherdevice.h> 5 #include <linux/iopoll.h> 6 #include <net/rtnetlink.h> 7 #include "hclgevf_cmd.h" 8 #include "hclgevf_main.h" 9 #include "hclge_mbx.h" 10 #include "hnae3.h" 11 12 #define HCLGEVF_NAME "hclgevf" 13 14 #define HCLGEVF_RESET_MAX_FAIL_CNT 5 15 16 static int hclgevf_reset_hdev(struct hclgevf_dev *hdev); 17 static struct hnae3_ae_algo ae_algovf; 18 19 static const struct pci_device_id ae_algovf_pci_tbl[] = { 20 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0}, 21 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF), 0}, 22 /* required last entry */ 23 {0, } 24 }; 25 26 static const u8 hclgevf_hash_key[] = { 27 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2, 28 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0, 29 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4, 30 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C, 31 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA 32 }; 33 34 MODULE_DEVICE_TABLE(pci, ae_algovf_pci_tbl); 35 36 static const u32 cmdq_reg_addr_list[] = {HCLGEVF_CMDQ_TX_ADDR_L_REG, 37 HCLGEVF_CMDQ_TX_ADDR_H_REG, 38 HCLGEVF_CMDQ_TX_DEPTH_REG, 39 HCLGEVF_CMDQ_TX_TAIL_REG, 40 HCLGEVF_CMDQ_TX_HEAD_REG, 41 HCLGEVF_CMDQ_RX_ADDR_L_REG, 42 HCLGEVF_CMDQ_RX_ADDR_H_REG, 43 HCLGEVF_CMDQ_RX_DEPTH_REG, 44 HCLGEVF_CMDQ_RX_TAIL_REG, 45 HCLGEVF_CMDQ_RX_HEAD_REG, 46 HCLGEVF_VECTOR0_CMDQ_SRC_REG, 47 HCLGEVF_CMDQ_INTR_STS_REG, 48 HCLGEVF_CMDQ_INTR_EN_REG, 49 HCLGEVF_CMDQ_INTR_GEN_REG}; 50 51 static const u32 common_reg_addr_list[] = {HCLGEVF_MISC_VECTOR_REG_BASE, 52 HCLGEVF_RST_ING, 53 HCLGEVF_GRO_EN_REG}; 54 55 static const u32 ring_reg_addr_list[] = {HCLGEVF_RING_RX_ADDR_L_REG, 56 HCLGEVF_RING_RX_ADDR_H_REG, 57 HCLGEVF_RING_RX_BD_NUM_REG, 58 HCLGEVF_RING_RX_BD_LENGTH_REG, 59 HCLGEVF_RING_RX_MERGE_EN_REG, 60 HCLGEVF_RING_RX_TAIL_REG, 61 HCLGEVF_RING_RX_HEAD_REG, 62 HCLGEVF_RING_RX_FBD_NUM_REG, 63 HCLGEVF_RING_RX_OFFSET_REG, 64 HCLGEVF_RING_RX_FBD_OFFSET_REG, 65 HCLGEVF_RING_RX_STASH_REG, 66 HCLGEVF_RING_RX_BD_ERR_REG, 67 HCLGEVF_RING_TX_ADDR_L_REG, 68 HCLGEVF_RING_TX_ADDR_H_REG, 69 HCLGEVF_RING_TX_BD_NUM_REG, 70 HCLGEVF_RING_TX_PRIORITY_REG, 71 HCLGEVF_RING_TX_TC_REG, 72 HCLGEVF_RING_TX_MERGE_EN_REG, 73 HCLGEVF_RING_TX_TAIL_REG, 74 HCLGEVF_RING_TX_HEAD_REG, 75 HCLGEVF_RING_TX_FBD_NUM_REG, 76 HCLGEVF_RING_TX_OFFSET_REG, 77 HCLGEVF_RING_TX_EBD_NUM_REG, 78 HCLGEVF_RING_TX_EBD_OFFSET_REG, 79 HCLGEVF_RING_TX_BD_ERR_REG, 80 HCLGEVF_RING_EN_REG}; 81 82 static const u32 tqp_intr_reg_addr_list[] = {HCLGEVF_TQP_INTR_CTRL_REG, 83 HCLGEVF_TQP_INTR_GL0_REG, 84 HCLGEVF_TQP_INTR_GL1_REG, 85 HCLGEVF_TQP_INTR_GL2_REG, 86 HCLGEVF_TQP_INTR_RL_REG}; 87 88 static struct hclgevf_dev *hclgevf_ae_get_hdev(struct hnae3_handle *handle) 89 { 90 if (!handle->client) 91 return container_of(handle, struct hclgevf_dev, nic); 92 else if (handle->client->type == HNAE3_CLIENT_ROCE) 93 return container_of(handle, struct hclgevf_dev, roce); 94 else 95 return container_of(handle, struct hclgevf_dev, nic); 96 } 97 98 static int hclgevf_tqps_update_stats(struct hnae3_handle *handle) 99 { 100 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 101 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 102 struct hclgevf_desc desc; 103 struct hclgevf_tqp *tqp; 104 int status; 105 int i; 106 107 for (i = 0; i < kinfo->num_tqps; i++) { 108 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 109 hclgevf_cmd_setup_basic_desc(&desc, 110 HCLGEVF_OPC_QUERY_RX_STATUS, 111 true); 112 113 desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 114 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 115 if (status) { 116 dev_err(&hdev->pdev->dev, 117 "Query tqp stat fail, status = %d,queue = %d\n", 118 status, i); 119 return status; 120 } 121 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd += 122 le32_to_cpu(desc.data[1]); 123 124 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_TX_STATUS, 125 true); 126 127 desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 128 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 129 if (status) { 130 dev_err(&hdev->pdev->dev, 131 "Query tqp stat fail, status = %d,queue = %d\n", 132 status, i); 133 return status; 134 } 135 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd += 136 le32_to_cpu(desc.data[1]); 137 } 138 139 return 0; 140 } 141 142 static u64 *hclgevf_tqps_get_stats(struct hnae3_handle *handle, u64 *data) 143 { 144 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 145 struct hclgevf_tqp *tqp; 146 u64 *buff = data; 147 int i; 148 149 for (i = 0; i < kinfo->num_tqps; i++) { 150 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 151 *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd; 152 } 153 for (i = 0; i < kinfo->num_tqps; i++) { 154 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 155 *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd; 156 } 157 158 return buff; 159 } 160 161 static int hclgevf_tqps_get_sset_count(struct hnae3_handle *handle, int strset) 162 { 163 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 164 165 return kinfo->num_tqps * 2; 166 } 167 168 static u8 *hclgevf_tqps_get_strings(struct hnae3_handle *handle, u8 *data) 169 { 170 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 171 u8 *buff = data; 172 int i = 0; 173 174 for (i = 0; i < kinfo->num_tqps; i++) { 175 struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 176 struct hclgevf_tqp, q); 177 snprintf(buff, ETH_GSTRING_LEN, "txq%d_pktnum_rcd", 178 tqp->index); 179 buff += ETH_GSTRING_LEN; 180 } 181 182 for (i = 0; i < kinfo->num_tqps; i++) { 183 struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 184 struct hclgevf_tqp, q); 185 snprintf(buff, ETH_GSTRING_LEN, "rxq%d_pktnum_rcd", 186 tqp->index); 187 buff += ETH_GSTRING_LEN; 188 } 189 190 return buff; 191 } 192 193 static void hclgevf_update_stats(struct hnae3_handle *handle, 194 struct net_device_stats *net_stats) 195 { 196 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 197 int status; 198 199 status = hclgevf_tqps_update_stats(handle); 200 if (status) 201 dev_err(&hdev->pdev->dev, 202 "VF update of TQPS stats fail, status = %d.\n", 203 status); 204 } 205 206 static int hclgevf_get_sset_count(struct hnae3_handle *handle, int strset) 207 { 208 if (strset == ETH_SS_TEST) 209 return -EOPNOTSUPP; 210 else if (strset == ETH_SS_STATS) 211 return hclgevf_tqps_get_sset_count(handle, strset); 212 213 return 0; 214 } 215 216 static void hclgevf_get_strings(struct hnae3_handle *handle, u32 strset, 217 u8 *data) 218 { 219 u8 *p = (char *)data; 220 221 if (strset == ETH_SS_STATS) 222 p = hclgevf_tqps_get_strings(handle, p); 223 } 224 225 static void hclgevf_get_stats(struct hnae3_handle *handle, u64 *data) 226 { 227 hclgevf_tqps_get_stats(handle, data); 228 } 229 230 static int hclgevf_get_tc_info(struct hclgevf_dev *hdev) 231 { 232 u8 resp_msg; 233 int status; 234 235 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_TCINFO, 0, NULL, 0, 236 true, &resp_msg, sizeof(resp_msg)); 237 if (status) { 238 dev_err(&hdev->pdev->dev, 239 "VF request to get TC info from PF failed %d", 240 status); 241 return status; 242 } 243 244 hdev->hw_tc_map = resp_msg; 245 246 return 0; 247 } 248 249 static int hclgevf_get_port_base_vlan_filter_state(struct hclgevf_dev *hdev) 250 { 251 struct hnae3_handle *nic = &hdev->nic; 252 u8 resp_msg; 253 int ret; 254 255 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 256 HCLGE_MBX_GET_PORT_BASE_VLAN_STATE, 257 NULL, 0, true, &resp_msg, sizeof(u8)); 258 if (ret) { 259 dev_err(&hdev->pdev->dev, 260 "VF request to get port based vlan state failed %d", 261 ret); 262 return ret; 263 } 264 265 nic->port_base_vlan_state = resp_msg; 266 267 return 0; 268 } 269 270 static int hclgevf_get_queue_info(struct hclgevf_dev *hdev) 271 { 272 #define HCLGEVF_TQPS_RSS_INFO_LEN 6 273 u8 resp_msg[HCLGEVF_TQPS_RSS_INFO_LEN]; 274 int status; 275 276 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QINFO, 0, NULL, 0, 277 true, resp_msg, 278 HCLGEVF_TQPS_RSS_INFO_LEN); 279 if (status) { 280 dev_err(&hdev->pdev->dev, 281 "VF request to get tqp info from PF failed %d", 282 status); 283 return status; 284 } 285 286 memcpy(&hdev->num_tqps, &resp_msg[0], sizeof(u16)); 287 memcpy(&hdev->rss_size_max, &resp_msg[2], sizeof(u16)); 288 memcpy(&hdev->rx_buf_len, &resp_msg[4], sizeof(u16)); 289 290 return 0; 291 } 292 293 static int hclgevf_get_queue_depth(struct hclgevf_dev *hdev) 294 { 295 #define HCLGEVF_TQPS_DEPTH_INFO_LEN 4 296 u8 resp_msg[HCLGEVF_TQPS_DEPTH_INFO_LEN]; 297 int ret; 298 299 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QDEPTH, 0, NULL, 0, 300 true, resp_msg, 301 HCLGEVF_TQPS_DEPTH_INFO_LEN); 302 if (ret) { 303 dev_err(&hdev->pdev->dev, 304 "VF request to get tqp depth info from PF failed %d", 305 ret); 306 return ret; 307 } 308 309 memcpy(&hdev->num_tx_desc, &resp_msg[0], sizeof(u16)); 310 memcpy(&hdev->num_rx_desc, &resp_msg[2], sizeof(u16)); 311 312 return 0; 313 } 314 315 static u16 hclgevf_get_qid_global(struct hnae3_handle *handle, u16 queue_id) 316 { 317 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 318 u8 msg_data[2], resp_data[2]; 319 u16 qid_in_pf = 0; 320 int ret; 321 322 memcpy(&msg_data[0], &queue_id, sizeof(queue_id)); 323 324 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QID_IN_PF, 0, msg_data, 325 sizeof(msg_data), true, resp_data, 326 sizeof(resp_data)); 327 if (!ret) 328 qid_in_pf = *(u16 *)resp_data; 329 330 return qid_in_pf; 331 } 332 333 static int hclgevf_get_pf_media_type(struct hclgevf_dev *hdev) 334 { 335 u8 resp_msg[2]; 336 int ret; 337 338 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_MEDIA_TYPE, 0, NULL, 0, 339 true, resp_msg, sizeof(resp_msg)); 340 if (ret) { 341 dev_err(&hdev->pdev->dev, 342 "VF request to get the pf port media type failed %d", 343 ret); 344 return ret; 345 } 346 347 hdev->hw.mac.media_type = resp_msg[0]; 348 hdev->hw.mac.module_type = resp_msg[1]; 349 350 return 0; 351 } 352 353 static int hclgevf_alloc_tqps(struct hclgevf_dev *hdev) 354 { 355 struct hclgevf_tqp *tqp; 356 int i; 357 358 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 359 sizeof(struct hclgevf_tqp), GFP_KERNEL); 360 if (!hdev->htqp) 361 return -ENOMEM; 362 363 tqp = hdev->htqp; 364 365 for (i = 0; i < hdev->num_tqps; i++) { 366 tqp->dev = &hdev->pdev->dev; 367 tqp->index = i; 368 369 tqp->q.ae_algo = &ae_algovf; 370 tqp->q.buf_size = hdev->rx_buf_len; 371 tqp->q.tx_desc_num = hdev->num_tx_desc; 372 tqp->q.rx_desc_num = hdev->num_rx_desc; 373 tqp->q.io_base = hdev->hw.io_base + HCLGEVF_TQP_REG_OFFSET + 374 i * HCLGEVF_TQP_REG_SIZE; 375 376 tqp++; 377 } 378 379 return 0; 380 } 381 382 static int hclgevf_knic_setup(struct hclgevf_dev *hdev) 383 { 384 struct hnae3_handle *nic = &hdev->nic; 385 struct hnae3_knic_private_info *kinfo; 386 u16 new_tqps = hdev->num_tqps; 387 unsigned int i; 388 389 kinfo = &nic->kinfo; 390 kinfo->num_tc = 0; 391 kinfo->num_tx_desc = hdev->num_tx_desc; 392 kinfo->num_rx_desc = hdev->num_rx_desc; 393 kinfo->rx_buf_len = hdev->rx_buf_len; 394 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) 395 if (hdev->hw_tc_map & BIT(i)) 396 kinfo->num_tc++; 397 398 kinfo->rss_size 399 = min_t(u16, hdev->rss_size_max, new_tqps / kinfo->num_tc); 400 new_tqps = kinfo->rss_size * kinfo->num_tc; 401 kinfo->num_tqps = min(new_tqps, hdev->num_tqps); 402 403 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps, 404 sizeof(struct hnae3_queue *), GFP_KERNEL); 405 if (!kinfo->tqp) 406 return -ENOMEM; 407 408 for (i = 0; i < kinfo->num_tqps; i++) { 409 hdev->htqp[i].q.handle = &hdev->nic; 410 hdev->htqp[i].q.tqp_index = i; 411 kinfo->tqp[i] = &hdev->htqp[i].q; 412 } 413 414 return 0; 415 } 416 417 static void hclgevf_request_link_info(struct hclgevf_dev *hdev) 418 { 419 int status; 420 u8 resp_msg; 421 422 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_STATUS, 0, NULL, 423 0, false, &resp_msg, sizeof(resp_msg)); 424 if (status) 425 dev_err(&hdev->pdev->dev, 426 "VF failed to fetch link status(%d) from PF", status); 427 } 428 429 void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state) 430 { 431 struct hnae3_handle *rhandle = &hdev->roce; 432 struct hnae3_handle *handle = &hdev->nic; 433 struct hnae3_client *rclient; 434 struct hnae3_client *client; 435 436 client = handle->client; 437 rclient = hdev->roce_client; 438 439 link_state = 440 test_bit(HCLGEVF_STATE_DOWN, &hdev->state) ? 0 : link_state; 441 442 if (link_state != hdev->hw.mac.link) { 443 client->ops->link_status_change(handle, !!link_state); 444 if (rclient && rclient->ops->link_status_change) 445 rclient->ops->link_status_change(rhandle, !!link_state); 446 hdev->hw.mac.link = link_state; 447 } 448 } 449 450 static void hclgevf_update_link_mode(struct hclgevf_dev *hdev) 451 { 452 #define HCLGEVF_ADVERTISING 0 453 #define HCLGEVF_SUPPORTED 1 454 u8 send_msg; 455 u8 resp_msg; 456 457 send_msg = HCLGEVF_ADVERTISING; 458 hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_MODE, 0, 459 &send_msg, sizeof(send_msg), false, 460 &resp_msg, sizeof(resp_msg)); 461 send_msg = HCLGEVF_SUPPORTED; 462 hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_MODE, 0, 463 &send_msg, sizeof(send_msg), false, 464 &resp_msg, sizeof(resp_msg)); 465 } 466 467 static int hclgevf_set_handle_info(struct hclgevf_dev *hdev) 468 { 469 struct hnae3_handle *nic = &hdev->nic; 470 int ret; 471 472 nic->ae_algo = &ae_algovf; 473 nic->pdev = hdev->pdev; 474 nic->numa_node_mask = hdev->numa_node_mask; 475 nic->flags |= HNAE3_SUPPORT_VF; 476 477 ret = hclgevf_knic_setup(hdev); 478 if (ret) 479 dev_err(&hdev->pdev->dev, "VF knic setup failed %d\n", 480 ret); 481 return ret; 482 } 483 484 static void hclgevf_free_vector(struct hclgevf_dev *hdev, int vector_id) 485 { 486 if (hdev->vector_status[vector_id] == HCLGEVF_INVALID_VPORT) { 487 dev_warn(&hdev->pdev->dev, 488 "vector(vector_id %d) has been freed.\n", vector_id); 489 return; 490 } 491 492 hdev->vector_status[vector_id] = HCLGEVF_INVALID_VPORT; 493 hdev->num_msi_left += 1; 494 hdev->num_msi_used -= 1; 495 } 496 497 static int hclgevf_get_vector(struct hnae3_handle *handle, u16 vector_num, 498 struct hnae3_vector_info *vector_info) 499 { 500 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 501 struct hnae3_vector_info *vector = vector_info; 502 int alloc = 0; 503 int i, j; 504 505 vector_num = min(hdev->num_msi_left, vector_num); 506 507 for (j = 0; j < vector_num; j++) { 508 for (i = HCLGEVF_MISC_VECTOR_NUM + 1; i < hdev->num_msi; i++) { 509 if (hdev->vector_status[i] == HCLGEVF_INVALID_VPORT) { 510 vector->vector = pci_irq_vector(hdev->pdev, i); 511 vector->io_addr = hdev->hw.io_base + 512 HCLGEVF_VECTOR_REG_BASE + 513 (i - 1) * HCLGEVF_VECTOR_REG_OFFSET; 514 hdev->vector_status[i] = 0; 515 hdev->vector_irq[i] = vector->vector; 516 517 vector++; 518 alloc++; 519 520 break; 521 } 522 } 523 } 524 hdev->num_msi_left -= alloc; 525 hdev->num_msi_used += alloc; 526 527 return alloc; 528 } 529 530 static int hclgevf_get_vector_index(struct hclgevf_dev *hdev, int vector) 531 { 532 int i; 533 534 for (i = 0; i < hdev->num_msi; i++) 535 if (vector == hdev->vector_irq[i]) 536 return i; 537 538 return -EINVAL; 539 } 540 541 static int hclgevf_set_rss_algo_key(struct hclgevf_dev *hdev, 542 const u8 hfunc, const u8 *key) 543 { 544 struct hclgevf_rss_config_cmd *req; 545 unsigned int key_offset = 0; 546 struct hclgevf_desc desc; 547 int key_counts; 548 int key_size; 549 int ret; 550 551 key_counts = HCLGEVF_RSS_KEY_SIZE; 552 req = (struct hclgevf_rss_config_cmd *)desc.data; 553 554 while (key_counts) { 555 hclgevf_cmd_setup_basic_desc(&desc, 556 HCLGEVF_OPC_RSS_GENERIC_CONFIG, 557 false); 558 559 req->hash_config |= (hfunc & HCLGEVF_RSS_HASH_ALGO_MASK); 560 req->hash_config |= 561 (key_offset << HCLGEVF_RSS_HASH_KEY_OFFSET_B); 562 563 key_size = min(HCLGEVF_RSS_HASH_KEY_NUM, key_counts); 564 memcpy(req->hash_key, 565 key + key_offset * HCLGEVF_RSS_HASH_KEY_NUM, key_size); 566 567 key_counts -= key_size; 568 key_offset++; 569 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 570 if (ret) { 571 dev_err(&hdev->pdev->dev, 572 "Configure RSS config fail, status = %d\n", 573 ret); 574 return ret; 575 } 576 } 577 578 return 0; 579 } 580 581 static u32 hclgevf_get_rss_key_size(struct hnae3_handle *handle) 582 { 583 return HCLGEVF_RSS_KEY_SIZE; 584 } 585 586 static u32 hclgevf_get_rss_indir_size(struct hnae3_handle *handle) 587 { 588 return HCLGEVF_RSS_IND_TBL_SIZE; 589 } 590 591 static int hclgevf_set_rss_indir_table(struct hclgevf_dev *hdev) 592 { 593 const u8 *indir = hdev->rss_cfg.rss_indirection_tbl; 594 struct hclgevf_rss_indirection_table_cmd *req; 595 struct hclgevf_desc desc; 596 int status; 597 int i, j; 598 599 req = (struct hclgevf_rss_indirection_table_cmd *)desc.data; 600 601 for (i = 0; i < HCLGEVF_RSS_CFG_TBL_NUM; i++) { 602 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INDIR_TABLE, 603 false); 604 req->start_table_index = i * HCLGEVF_RSS_CFG_TBL_SIZE; 605 req->rss_set_bitmap = HCLGEVF_RSS_SET_BITMAP_MSK; 606 for (j = 0; j < HCLGEVF_RSS_CFG_TBL_SIZE; j++) 607 req->rss_result[j] = 608 indir[i * HCLGEVF_RSS_CFG_TBL_SIZE + j]; 609 610 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 611 if (status) { 612 dev_err(&hdev->pdev->dev, 613 "VF failed(=%d) to set RSS indirection table\n", 614 status); 615 return status; 616 } 617 } 618 619 return 0; 620 } 621 622 static int hclgevf_set_rss_tc_mode(struct hclgevf_dev *hdev, u16 rss_size) 623 { 624 struct hclgevf_rss_tc_mode_cmd *req; 625 u16 tc_offset[HCLGEVF_MAX_TC_NUM]; 626 u16 tc_valid[HCLGEVF_MAX_TC_NUM]; 627 u16 tc_size[HCLGEVF_MAX_TC_NUM]; 628 struct hclgevf_desc desc; 629 u16 roundup_size; 630 int status; 631 unsigned int i; 632 633 req = (struct hclgevf_rss_tc_mode_cmd *)desc.data; 634 635 roundup_size = roundup_pow_of_two(rss_size); 636 roundup_size = ilog2(roundup_size); 637 638 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 639 tc_valid[i] = !!(hdev->hw_tc_map & BIT(i)); 640 tc_size[i] = roundup_size; 641 tc_offset[i] = rss_size * i; 642 } 643 644 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_TC_MODE, false); 645 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 646 hnae3_set_bit(req->rss_tc_mode[i], HCLGEVF_RSS_TC_VALID_B, 647 (tc_valid[i] & 0x1)); 648 hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_SIZE_M, 649 HCLGEVF_RSS_TC_SIZE_S, tc_size[i]); 650 hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_OFFSET_M, 651 HCLGEVF_RSS_TC_OFFSET_S, tc_offset[i]); 652 } 653 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 654 if (status) 655 dev_err(&hdev->pdev->dev, 656 "VF failed(=%d) to set rss tc mode\n", status); 657 658 return status; 659 } 660 661 /* for revision 0x20, vf shared the same rss config with pf */ 662 static int hclgevf_get_rss_hash_key(struct hclgevf_dev *hdev) 663 { 664 #define HCLGEVF_RSS_MBX_RESP_LEN 8 665 666 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 667 u8 resp_msg[HCLGEVF_RSS_MBX_RESP_LEN]; 668 u16 msg_num, hash_key_index; 669 u8 index; 670 int ret; 671 672 msg_num = (HCLGEVF_RSS_KEY_SIZE + HCLGEVF_RSS_MBX_RESP_LEN - 1) / 673 HCLGEVF_RSS_MBX_RESP_LEN; 674 for (index = 0; index < msg_num; index++) { 675 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_RSS_KEY, 0, 676 &index, sizeof(index), 677 true, resp_msg, 678 HCLGEVF_RSS_MBX_RESP_LEN); 679 if (ret) { 680 dev_err(&hdev->pdev->dev, 681 "VF get rss hash key from PF failed, ret=%d", 682 ret); 683 return ret; 684 } 685 686 hash_key_index = HCLGEVF_RSS_MBX_RESP_LEN * index; 687 if (index == msg_num - 1) 688 memcpy(&rss_cfg->rss_hash_key[hash_key_index], 689 &resp_msg[0], 690 HCLGEVF_RSS_KEY_SIZE - hash_key_index); 691 else 692 memcpy(&rss_cfg->rss_hash_key[hash_key_index], 693 &resp_msg[0], HCLGEVF_RSS_MBX_RESP_LEN); 694 } 695 696 return 0; 697 } 698 699 static int hclgevf_get_rss(struct hnae3_handle *handle, u32 *indir, u8 *key, 700 u8 *hfunc) 701 { 702 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 703 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 704 int i, ret; 705 706 if (handle->pdev->revision >= 0x21) { 707 /* Get hash algorithm */ 708 if (hfunc) { 709 switch (rss_cfg->hash_algo) { 710 case HCLGEVF_RSS_HASH_ALGO_TOEPLITZ: 711 *hfunc = ETH_RSS_HASH_TOP; 712 break; 713 case HCLGEVF_RSS_HASH_ALGO_SIMPLE: 714 *hfunc = ETH_RSS_HASH_XOR; 715 break; 716 default: 717 *hfunc = ETH_RSS_HASH_UNKNOWN; 718 break; 719 } 720 } 721 722 /* Get the RSS Key required by the user */ 723 if (key) 724 memcpy(key, rss_cfg->rss_hash_key, 725 HCLGEVF_RSS_KEY_SIZE); 726 } else { 727 if (hfunc) 728 *hfunc = ETH_RSS_HASH_TOP; 729 if (key) { 730 ret = hclgevf_get_rss_hash_key(hdev); 731 if (ret) 732 return ret; 733 memcpy(key, rss_cfg->rss_hash_key, 734 HCLGEVF_RSS_KEY_SIZE); 735 } 736 } 737 738 if (indir) 739 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 740 indir[i] = rss_cfg->rss_indirection_tbl[i]; 741 742 return 0; 743 } 744 745 static int hclgevf_set_rss(struct hnae3_handle *handle, const u32 *indir, 746 const u8 *key, const u8 hfunc) 747 { 748 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 749 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 750 int ret, i; 751 752 if (handle->pdev->revision >= 0x21) { 753 /* Set the RSS Hash Key if specififed by the user */ 754 if (key) { 755 switch (hfunc) { 756 case ETH_RSS_HASH_TOP: 757 rss_cfg->hash_algo = 758 HCLGEVF_RSS_HASH_ALGO_TOEPLITZ; 759 break; 760 case ETH_RSS_HASH_XOR: 761 rss_cfg->hash_algo = 762 HCLGEVF_RSS_HASH_ALGO_SIMPLE; 763 break; 764 case ETH_RSS_HASH_NO_CHANGE: 765 break; 766 default: 767 return -EINVAL; 768 } 769 770 ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 771 key); 772 if (ret) 773 return ret; 774 775 /* Update the shadow RSS key with user specified qids */ 776 memcpy(rss_cfg->rss_hash_key, key, 777 HCLGEVF_RSS_KEY_SIZE); 778 } 779 } 780 781 /* update the shadow RSS table with user specified qids */ 782 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 783 rss_cfg->rss_indirection_tbl[i] = indir[i]; 784 785 /* update the hardware */ 786 return hclgevf_set_rss_indir_table(hdev); 787 } 788 789 static u8 hclgevf_get_rss_hash_bits(struct ethtool_rxnfc *nfc) 790 { 791 u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGEVF_S_PORT_BIT : 0; 792 793 if (nfc->data & RXH_L4_B_2_3) 794 hash_sets |= HCLGEVF_D_PORT_BIT; 795 else 796 hash_sets &= ~HCLGEVF_D_PORT_BIT; 797 798 if (nfc->data & RXH_IP_SRC) 799 hash_sets |= HCLGEVF_S_IP_BIT; 800 else 801 hash_sets &= ~HCLGEVF_S_IP_BIT; 802 803 if (nfc->data & RXH_IP_DST) 804 hash_sets |= HCLGEVF_D_IP_BIT; 805 else 806 hash_sets &= ~HCLGEVF_D_IP_BIT; 807 808 if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW) 809 hash_sets |= HCLGEVF_V_TAG_BIT; 810 811 return hash_sets; 812 } 813 814 static int hclgevf_set_rss_tuple(struct hnae3_handle *handle, 815 struct ethtool_rxnfc *nfc) 816 { 817 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 818 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 819 struct hclgevf_rss_input_tuple_cmd *req; 820 struct hclgevf_desc desc; 821 u8 tuple_sets; 822 int ret; 823 824 if (handle->pdev->revision == 0x20) 825 return -EOPNOTSUPP; 826 827 if (nfc->data & 828 ~(RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3)) 829 return -EINVAL; 830 831 req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 832 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 833 834 req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 835 req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 836 req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 837 req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 838 req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 839 req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 840 req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 841 req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 842 843 tuple_sets = hclgevf_get_rss_hash_bits(nfc); 844 switch (nfc->flow_type) { 845 case TCP_V4_FLOW: 846 req->ipv4_tcp_en = tuple_sets; 847 break; 848 case TCP_V6_FLOW: 849 req->ipv6_tcp_en = tuple_sets; 850 break; 851 case UDP_V4_FLOW: 852 req->ipv4_udp_en = tuple_sets; 853 break; 854 case UDP_V6_FLOW: 855 req->ipv6_udp_en = tuple_sets; 856 break; 857 case SCTP_V4_FLOW: 858 req->ipv4_sctp_en = tuple_sets; 859 break; 860 case SCTP_V6_FLOW: 861 if ((nfc->data & RXH_L4_B_0_1) || 862 (nfc->data & RXH_L4_B_2_3)) 863 return -EINVAL; 864 865 req->ipv6_sctp_en = tuple_sets; 866 break; 867 case IPV4_FLOW: 868 req->ipv4_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 869 break; 870 case IPV6_FLOW: 871 req->ipv6_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 872 break; 873 default: 874 return -EINVAL; 875 } 876 877 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 878 if (ret) { 879 dev_err(&hdev->pdev->dev, 880 "Set rss tuple fail, status = %d\n", ret); 881 return ret; 882 } 883 884 rss_cfg->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en; 885 rss_cfg->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en; 886 rss_cfg->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en; 887 rss_cfg->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en; 888 rss_cfg->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en; 889 rss_cfg->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en; 890 rss_cfg->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en; 891 rss_cfg->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en; 892 return 0; 893 } 894 895 static int hclgevf_get_rss_tuple(struct hnae3_handle *handle, 896 struct ethtool_rxnfc *nfc) 897 { 898 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 899 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 900 u8 tuple_sets; 901 902 if (handle->pdev->revision == 0x20) 903 return -EOPNOTSUPP; 904 905 nfc->data = 0; 906 907 switch (nfc->flow_type) { 908 case TCP_V4_FLOW: 909 tuple_sets = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 910 break; 911 case UDP_V4_FLOW: 912 tuple_sets = rss_cfg->rss_tuple_sets.ipv4_udp_en; 913 break; 914 case TCP_V6_FLOW: 915 tuple_sets = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 916 break; 917 case UDP_V6_FLOW: 918 tuple_sets = rss_cfg->rss_tuple_sets.ipv6_udp_en; 919 break; 920 case SCTP_V4_FLOW: 921 tuple_sets = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 922 break; 923 case SCTP_V6_FLOW: 924 tuple_sets = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 925 break; 926 case IPV4_FLOW: 927 case IPV6_FLOW: 928 tuple_sets = HCLGEVF_S_IP_BIT | HCLGEVF_D_IP_BIT; 929 break; 930 default: 931 return -EINVAL; 932 } 933 934 if (!tuple_sets) 935 return 0; 936 937 if (tuple_sets & HCLGEVF_D_PORT_BIT) 938 nfc->data |= RXH_L4_B_2_3; 939 if (tuple_sets & HCLGEVF_S_PORT_BIT) 940 nfc->data |= RXH_L4_B_0_1; 941 if (tuple_sets & HCLGEVF_D_IP_BIT) 942 nfc->data |= RXH_IP_DST; 943 if (tuple_sets & HCLGEVF_S_IP_BIT) 944 nfc->data |= RXH_IP_SRC; 945 946 return 0; 947 } 948 949 static int hclgevf_set_rss_input_tuple(struct hclgevf_dev *hdev, 950 struct hclgevf_rss_cfg *rss_cfg) 951 { 952 struct hclgevf_rss_input_tuple_cmd *req; 953 struct hclgevf_desc desc; 954 int ret; 955 956 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 957 958 req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 959 960 req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 961 req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 962 req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 963 req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 964 req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 965 req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 966 req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 967 req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 968 969 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 970 if (ret) 971 dev_err(&hdev->pdev->dev, 972 "Configure rss input fail, status = %d\n", ret); 973 return ret; 974 } 975 976 static int hclgevf_get_tc_size(struct hnae3_handle *handle) 977 { 978 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 979 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 980 981 return rss_cfg->rss_size; 982 } 983 984 static int hclgevf_bind_ring_to_vector(struct hnae3_handle *handle, bool en, 985 int vector_id, 986 struct hnae3_ring_chain_node *ring_chain) 987 { 988 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 989 struct hnae3_ring_chain_node *node; 990 struct hclge_mbx_vf_to_pf_cmd *req; 991 struct hclgevf_desc desc; 992 int i = 0; 993 int status; 994 u8 type; 995 996 req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data; 997 998 for (node = ring_chain; node; node = node->next) { 999 int idx_offset = HCLGE_MBX_RING_MAP_BASIC_MSG_NUM + 1000 HCLGE_MBX_RING_NODE_VARIABLE_NUM * i; 1001 1002 if (i == 0) { 1003 hclgevf_cmd_setup_basic_desc(&desc, 1004 HCLGEVF_OPC_MBX_VF_TO_PF, 1005 false); 1006 type = en ? 1007 HCLGE_MBX_MAP_RING_TO_VECTOR : 1008 HCLGE_MBX_UNMAP_RING_TO_VECTOR; 1009 req->msg[0] = type; 1010 req->msg[1] = vector_id; 1011 } 1012 1013 req->msg[idx_offset] = 1014 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B); 1015 req->msg[idx_offset + 1] = node->tqp_index; 1016 req->msg[idx_offset + 2] = hnae3_get_field(node->int_gl_idx, 1017 HNAE3_RING_GL_IDX_M, 1018 HNAE3_RING_GL_IDX_S); 1019 1020 i++; 1021 if ((i == (HCLGE_MBX_VF_MSG_DATA_NUM - 1022 HCLGE_MBX_RING_MAP_BASIC_MSG_NUM) / 1023 HCLGE_MBX_RING_NODE_VARIABLE_NUM) || 1024 !node->next) { 1025 req->msg[2] = i; 1026 1027 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1028 if (status) { 1029 dev_err(&hdev->pdev->dev, 1030 "Map TQP fail, status is %d.\n", 1031 status); 1032 return status; 1033 } 1034 i = 0; 1035 hclgevf_cmd_setup_basic_desc(&desc, 1036 HCLGEVF_OPC_MBX_VF_TO_PF, 1037 false); 1038 req->msg[0] = type; 1039 req->msg[1] = vector_id; 1040 } 1041 } 1042 1043 return 0; 1044 } 1045 1046 static int hclgevf_map_ring_to_vector(struct hnae3_handle *handle, int vector, 1047 struct hnae3_ring_chain_node *ring_chain) 1048 { 1049 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1050 int vector_id; 1051 1052 vector_id = hclgevf_get_vector_index(hdev, vector); 1053 if (vector_id < 0) { 1054 dev_err(&handle->pdev->dev, 1055 "Get vector index fail. ret =%d\n", vector_id); 1056 return vector_id; 1057 } 1058 1059 return hclgevf_bind_ring_to_vector(handle, true, vector_id, ring_chain); 1060 } 1061 1062 static int hclgevf_unmap_ring_from_vector( 1063 struct hnae3_handle *handle, 1064 int vector, 1065 struct hnae3_ring_chain_node *ring_chain) 1066 { 1067 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1068 int ret, vector_id; 1069 1070 if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 1071 return 0; 1072 1073 vector_id = hclgevf_get_vector_index(hdev, vector); 1074 if (vector_id < 0) { 1075 dev_err(&handle->pdev->dev, 1076 "Get vector index fail. ret =%d\n", vector_id); 1077 return vector_id; 1078 } 1079 1080 ret = hclgevf_bind_ring_to_vector(handle, false, vector_id, ring_chain); 1081 if (ret) 1082 dev_err(&handle->pdev->dev, 1083 "Unmap ring from vector fail. vector=%d, ret =%d\n", 1084 vector_id, 1085 ret); 1086 1087 return ret; 1088 } 1089 1090 static int hclgevf_put_vector(struct hnae3_handle *handle, int vector) 1091 { 1092 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1093 int vector_id; 1094 1095 vector_id = hclgevf_get_vector_index(hdev, vector); 1096 if (vector_id < 0) { 1097 dev_err(&handle->pdev->dev, 1098 "hclgevf_put_vector get vector index fail. ret =%d\n", 1099 vector_id); 1100 return vector_id; 1101 } 1102 1103 hclgevf_free_vector(hdev, vector_id); 1104 1105 return 0; 1106 } 1107 1108 static int hclgevf_cmd_set_promisc_mode(struct hclgevf_dev *hdev, 1109 bool en_bc_pmc) 1110 { 1111 struct hclge_mbx_vf_to_pf_cmd *req; 1112 struct hclgevf_desc desc; 1113 int ret; 1114 1115 req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data; 1116 1117 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_MBX_VF_TO_PF, false); 1118 req->msg[0] = HCLGE_MBX_SET_PROMISC_MODE; 1119 req->msg[1] = en_bc_pmc ? 1 : 0; 1120 1121 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1122 if (ret) 1123 dev_err(&hdev->pdev->dev, 1124 "Set promisc mode fail, status is %d.\n", ret); 1125 1126 return ret; 1127 } 1128 1129 static int hclgevf_set_promisc_mode(struct hclgevf_dev *hdev, bool en_bc_pmc) 1130 { 1131 return hclgevf_cmd_set_promisc_mode(hdev, en_bc_pmc); 1132 } 1133 1134 static int hclgevf_tqp_enable(struct hclgevf_dev *hdev, unsigned int tqp_id, 1135 int stream_id, bool enable) 1136 { 1137 struct hclgevf_cfg_com_tqp_queue_cmd *req; 1138 struct hclgevf_desc desc; 1139 int status; 1140 1141 req = (struct hclgevf_cfg_com_tqp_queue_cmd *)desc.data; 1142 1143 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_CFG_COM_TQP_QUEUE, 1144 false); 1145 req->tqp_id = cpu_to_le16(tqp_id & HCLGEVF_RING_ID_MASK); 1146 req->stream_id = cpu_to_le16(stream_id); 1147 if (enable) 1148 req->enable |= 1U << HCLGEVF_TQP_ENABLE_B; 1149 1150 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1151 if (status) 1152 dev_err(&hdev->pdev->dev, 1153 "TQP enable fail, status =%d.\n", status); 1154 1155 return status; 1156 } 1157 1158 static void hclgevf_reset_tqp_stats(struct hnae3_handle *handle) 1159 { 1160 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 1161 struct hclgevf_tqp *tqp; 1162 int i; 1163 1164 for (i = 0; i < kinfo->num_tqps; i++) { 1165 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 1166 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats)); 1167 } 1168 } 1169 1170 static void hclgevf_get_mac_addr(struct hnae3_handle *handle, u8 *p) 1171 { 1172 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1173 1174 ether_addr_copy(p, hdev->hw.mac.mac_addr); 1175 } 1176 1177 static int hclgevf_set_mac_addr(struct hnae3_handle *handle, void *p, 1178 bool is_first) 1179 { 1180 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1181 u8 *old_mac_addr = (u8 *)hdev->hw.mac.mac_addr; 1182 u8 *new_mac_addr = (u8 *)p; 1183 u8 msg_data[ETH_ALEN * 2]; 1184 u16 subcode; 1185 int status; 1186 1187 ether_addr_copy(msg_data, new_mac_addr); 1188 ether_addr_copy(&msg_data[ETH_ALEN], old_mac_addr); 1189 1190 subcode = is_first ? HCLGE_MBX_MAC_VLAN_UC_ADD : 1191 HCLGE_MBX_MAC_VLAN_UC_MODIFY; 1192 1193 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 1194 subcode, msg_data, sizeof(msg_data), 1195 true, NULL, 0); 1196 if (!status) 1197 ether_addr_copy(hdev->hw.mac.mac_addr, new_mac_addr); 1198 1199 return status; 1200 } 1201 1202 static int hclgevf_add_uc_addr(struct hnae3_handle *handle, 1203 const unsigned char *addr) 1204 { 1205 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1206 1207 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 1208 HCLGE_MBX_MAC_VLAN_UC_ADD, 1209 addr, ETH_ALEN, false, NULL, 0); 1210 } 1211 1212 static int hclgevf_rm_uc_addr(struct hnae3_handle *handle, 1213 const unsigned char *addr) 1214 { 1215 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1216 1217 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 1218 HCLGE_MBX_MAC_VLAN_UC_REMOVE, 1219 addr, ETH_ALEN, false, NULL, 0); 1220 } 1221 1222 static int hclgevf_add_mc_addr(struct hnae3_handle *handle, 1223 const unsigned char *addr) 1224 { 1225 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1226 1227 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 1228 HCLGE_MBX_MAC_VLAN_MC_ADD, 1229 addr, ETH_ALEN, false, NULL, 0); 1230 } 1231 1232 static int hclgevf_rm_mc_addr(struct hnae3_handle *handle, 1233 const unsigned char *addr) 1234 { 1235 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1236 1237 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 1238 HCLGE_MBX_MAC_VLAN_MC_REMOVE, 1239 addr, ETH_ALEN, false, NULL, 0); 1240 } 1241 1242 static int hclgevf_set_vlan_filter(struct hnae3_handle *handle, 1243 __be16 proto, u16 vlan_id, 1244 bool is_kill) 1245 { 1246 #define HCLGEVF_VLAN_MBX_MSG_LEN 5 1247 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1248 u8 msg_data[HCLGEVF_VLAN_MBX_MSG_LEN]; 1249 int ret; 1250 1251 if (vlan_id > HCLGEVF_MAX_VLAN_ID) 1252 return -EINVAL; 1253 1254 if (proto != htons(ETH_P_8021Q)) 1255 return -EPROTONOSUPPORT; 1256 1257 /* When device is resetting, firmware is unable to handle 1258 * mailbox. Just record the vlan id, and remove it after 1259 * reset finished. 1260 */ 1261 if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) && is_kill) { 1262 set_bit(vlan_id, hdev->vlan_del_fail_bmap); 1263 return -EBUSY; 1264 } 1265 1266 msg_data[0] = is_kill; 1267 memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id)); 1268 memcpy(&msg_data[3], &proto, sizeof(proto)); 1269 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 1270 HCLGE_MBX_VLAN_FILTER, msg_data, 1271 HCLGEVF_VLAN_MBX_MSG_LEN, false, NULL, 0); 1272 1273 /* When remove hw vlan filter failed, record the vlan id, 1274 * and try to remove it from hw later, to be consistence 1275 * with stack. 1276 */ 1277 if (is_kill && ret) 1278 set_bit(vlan_id, hdev->vlan_del_fail_bmap); 1279 1280 return ret; 1281 } 1282 1283 static void hclgevf_sync_vlan_filter(struct hclgevf_dev *hdev) 1284 { 1285 #define HCLGEVF_MAX_SYNC_COUNT 60 1286 struct hnae3_handle *handle = &hdev->nic; 1287 int ret, sync_cnt = 0; 1288 u16 vlan_id; 1289 1290 vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID); 1291 while (vlan_id != VLAN_N_VID) { 1292 ret = hclgevf_set_vlan_filter(handle, htons(ETH_P_8021Q), 1293 vlan_id, true); 1294 if (ret) 1295 return; 1296 1297 clear_bit(vlan_id, hdev->vlan_del_fail_bmap); 1298 sync_cnt++; 1299 if (sync_cnt >= HCLGEVF_MAX_SYNC_COUNT) 1300 return; 1301 1302 vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID); 1303 } 1304 } 1305 1306 static int hclgevf_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) 1307 { 1308 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1309 u8 msg_data; 1310 1311 msg_data = enable ? 1 : 0; 1312 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 1313 HCLGE_MBX_VLAN_RX_OFF_CFG, &msg_data, 1314 1, false, NULL, 0); 1315 } 1316 1317 static int hclgevf_reset_tqp(struct hnae3_handle *handle, u16 queue_id) 1318 { 1319 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1320 u8 msg_data[2]; 1321 int ret; 1322 1323 memcpy(msg_data, &queue_id, sizeof(queue_id)); 1324 1325 /* disable vf queue before send queue reset msg to PF */ 1326 ret = hclgevf_tqp_enable(hdev, queue_id, 0, false); 1327 if (ret) 1328 return ret; 1329 1330 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_QUEUE_RESET, 0, msg_data, 1331 sizeof(msg_data), true, NULL, 0); 1332 } 1333 1334 static int hclgevf_set_mtu(struct hnae3_handle *handle, int new_mtu) 1335 { 1336 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1337 1338 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MTU, 0, (u8 *)&new_mtu, 1339 sizeof(new_mtu), true, NULL, 0); 1340 } 1341 1342 static int hclgevf_notify_client(struct hclgevf_dev *hdev, 1343 enum hnae3_reset_notify_type type) 1344 { 1345 struct hnae3_client *client = hdev->nic_client; 1346 struct hnae3_handle *handle = &hdev->nic; 1347 int ret; 1348 1349 if (!test_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state) || 1350 !client) 1351 return 0; 1352 1353 if (!client->ops->reset_notify) 1354 return -EOPNOTSUPP; 1355 1356 ret = client->ops->reset_notify(handle, type); 1357 if (ret) 1358 dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n", 1359 type, ret); 1360 1361 return ret; 1362 } 1363 1364 static void hclgevf_flr_done(struct hnae3_ae_dev *ae_dev) 1365 { 1366 struct hclgevf_dev *hdev = ae_dev->priv; 1367 1368 set_bit(HNAE3_FLR_DONE, &hdev->flr_state); 1369 } 1370 1371 static int hclgevf_flr_poll_timeout(struct hclgevf_dev *hdev, 1372 unsigned long delay_us, 1373 unsigned long wait_cnt) 1374 { 1375 unsigned long cnt = 0; 1376 1377 while (!test_bit(HNAE3_FLR_DONE, &hdev->flr_state) && 1378 cnt++ < wait_cnt) 1379 usleep_range(delay_us, delay_us * 2); 1380 1381 if (!test_bit(HNAE3_FLR_DONE, &hdev->flr_state)) { 1382 dev_err(&hdev->pdev->dev, 1383 "flr wait timeout\n"); 1384 return -ETIMEDOUT; 1385 } 1386 1387 return 0; 1388 } 1389 1390 static int hclgevf_reset_wait(struct hclgevf_dev *hdev) 1391 { 1392 #define HCLGEVF_RESET_WAIT_US 20000 1393 #define HCLGEVF_RESET_WAIT_CNT 2000 1394 #define HCLGEVF_RESET_WAIT_TIMEOUT_US \ 1395 (HCLGEVF_RESET_WAIT_US * HCLGEVF_RESET_WAIT_CNT) 1396 1397 u32 val; 1398 int ret; 1399 1400 /* wait to check the hardware reset completion status */ 1401 val = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 1402 dev_info(&hdev->pdev->dev, "checking vf resetting status: %x\n", val); 1403 1404 if (hdev->reset_type == HNAE3_FLR_RESET) 1405 return hclgevf_flr_poll_timeout(hdev, 1406 HCLGEVF_RESET_WAIT_US, 1407 HCLGEVF_RESET_WAIT_CNT); 1408 1409 ret = readl_poll_timeout(hdev->hw.io_base + HCLGEVF_RST_ING, val, 1410 !(val & HCLGEVF_RST_ING_BITS), 1411 HCLGEVF_RESET_WAIT_US, 1412 HCLGEVF_RESET_WAIT_TIMEOUT_US); 1413 1414 /* hardware completion status should be available by this time */ 1415 if (ret) { 1416 dev_err(&hdev->pdev->dev, 1417 "could'nt get reset done status from h/w, timeout!\n"); 1418 return ret; 1419 } 1420 1421 /* we will wait a bit more to let reset of the stack to complete. This 1422 * might happen in case reset assertion was made by PF. Yes, this also 1423 * means we might end up waiting bit more even for VF reset. 1424 */ 1425 msleep(5000); 1426 1427 return 0; 1428 } 1429 1430 static int hclgevf_reset_stack(struct hclgevf_dev *hdev) 1431 { 1432 int ret; 1433 1434 /* uninitialize the nic client */ 1435 ret = hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT); 1436 if (ret) 1437 return ret; 1438 1439 /* re-initialize the hclge device */ 1440 ret = hclgevf_reset_hdev(hdev); 1441 if (ret) { 1442 dev_err(&hdev->pdev->dev, 1443 "hclge device re-init failed, VF is disabled!\n"); 1444 return ret; 1445 } 1446 1447 /* bring up the nic client again */ 1448 ret = hclgevf_notify_client(hdev, HNAE3_INIT_CLIENT); 1449 if (ret) 1450 return ret; 1451 1452 return hclgevf_notify_client(hdev, HNAE3_RESTORE_CLIENT); 1453 } 1454 1455 static int hclgevf_reset_prepare_wait(struct hclgevf_dev *hdev) 1456 { 1457 #define HCLGEVF_RESET_SYNC_TIME 100 1458 1459 int ret = 0; 1460 1461 switch (hdev->reset_type) { 1462 case HNAE3_VF_FUNC_RESET: 1463 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_RESET, 0, NULL, 1464 0, true, NULL, sizeof(u8)); 1465 hdev->rst_stats.vf_func_rst_cnt++; 1466 break; 1467 case HNAE3_FLR_RESET: 1468 set_bit(HNAE3_FLR_DOWN, &hdev->flr_state); 1469 hdev->rst_stats.flr_rst_cnt++; 1470 break; 1471 default: 1472 break; 1473 } 1474 1475 set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 1476 /* inform hardware that preparatory work is done */ 1477 msleep(HCLGEVF_RESET_SYNC_TIME); 1478 hclgevf_write_dev(&hdev->hw, HCLGEVF_NIC_CSQ_DEPTH_REG, 1479 HCLGEVF_NIC_CMQ_ENABLE); 1480 dev_info(&hdev->pdev->dev, "prepare reset(%d) wait done, ret:%d\n", 1481 hdev->reset_type, ret); 1482 1483 return ret; 1484 } 1485 1486 static void hclgevf_reset_err_handle(struct hclgevf_dev *hdev) 1487 { 1488 hdev->rst_stats.rst_fail_cnt++; 1489 dev_err(&hdev->pdev->dev, "failed to reset VF(%d)\n", 1490 hdev->rst_stats.rst_fail_cnt); 1491 1492 if (hdev->rst_stats.rst_fail_cnt < HCLGEVF_RESET_MAX_FAIL_CNT) 1493 set_bit(hdev->reset_type, &hdev->reset_pending); 1494 1495 if (hclgevf_is_reset_pending(hdev)) { 1496 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1497 hclgevf_reset_task_schedule(hdev); 1498 } else { 1499 hclgevf_write_dev(&hdev->hw, HCLGEVF_NIC_CSQ_DEPTH_REG, 1500 HCLGEVF_NIC_CMQ_ENABLE); 1501 } 1502 } 1503 1504 static int hclgevf_reset(struct hclgevf_dev *hdev) 1505 { 1506 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1507 int ret; 1508 1509 /* Initialize ae_dev reset status as well, in case enet layer wants to 1510 * know if device is undergoing reset 1511 */ 1512 ae_dev->reset_type = hdev->reset_type; 1513 hdev->rst_stats.rst_cnt++; 1514 rtnl_lock(); 1515 1516 /* bring down the nic to stop any ongoing TX/RX */ 1517 ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 1518 if (ret) 1519 goto err_reset_lock; 1520 1521 rtnl_unlock(); 1522 1523 ret = hclgevf_reset_prepare_wait(hdev); 1524 if (ret) 1525 goto err_reset; 1526 1527 /* check if VF could successfully fetch the hardware reset completion 1528 * status from the hardware 1529 */ 1530 ret = hclgevf_reset_wait(hdev); 1531 if (ret) { 1532 /* can't do much in this situation, will disable VF */ 1533 dev_err(&hdev->pdev->dev, 1534 "VF failed(=%d) to fetch H/W reset completion status\n", 1535 ret); 1536 goto err_reset; 1537 } 1538 1539 hdev->rst_stats.hw_rst_done_cnt++; 1540 1541 rtnl_lock(); 1542 1543 /* now, re-initialize the nic client and ae device*/ 1544 ret = hclgevf_reset_stack(hdev); 1545 if (ret) { 1546 dev_err(&hdev->pdev->dev, "failed to reset VF stack\n"); 1547 goto err_reset_lock; 1548 } 1549 1550 /* bring up the nic to enable TX/RX again */ 1551 ret = hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 1552 if (ret) 1553 goto err_reset_lock; 1554 1555 rtnl_unlock(); 1556 1557 hdev->last_reset_time = jiffies; 1558 ae_dev->reset_type = HNAE3_NONE_RESET; 1559 hdev->rst_stats.rst_done_cnt++; 1560 hdev->rst_stats.rst_fail_cnt = 0; 1561 1562 return ret; 1563 err_reset_lock: 1564 rtnl_unlock(); 1565 err_reset: 1566 hclgevf_reset_err_handle(hdev); 1567 1568 return ret; 1569 } 1570 1571 static enum hnae3_reset_type hclgevf_get_reset_level(struct hclgevf_dev *hdev, 1572 unsigned long *addr) 1573 { 1574 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; 1575 1576 /* return the highest priority reset level amongst all */ 1577 if (test_bit(HNAE3_VF_RESET, addr)) { 1578 rst_level = HNAE3_VF_RESET; 1579 clear_bit(HNAE3_VF_RESET, addr); 1580 clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1581 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1582 } else if (test_bit(HNAE3_VF_FULL_RESET, addr)) { 1583 rst_level = HNAE3_VF_FULL_RESET; 1584 clear_bit(HNAE3_VF_FULL_RESET, addr); 1585 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1586 } else if (test_bit(HNAE3_VF_PF_FUNC_RESET, addr)) { 1587 rst_level = HNAE3_VF_PF_FUNC_RESET; 1588 clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1589 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1590 } else if (test_bit(HNAE3_VF_FUNC_RESET, addr)) { 1591 rst_level = HNAE3_VF_FUNC_RESET; 1592 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1593 } else if (test_bit(HNAE3_FLR_RESET, addr)) { 1594 rst_level = HNAE3_FLR_RESET; 1595 clear_bit(HNAE3_FLR_RESET, addr); 1596 } 1597 1598 return rst_level; 1599 } 1600 1601 static void hclgevf_reset_event(struct pci_dev *pdev, 1602 struct hnae3_handle *handle) 1603 { 1604 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 1605 struct hclgevf_dev *hdev = ae_dev->priv; 1606 1607 dev_info(&hdev->pdev->dev, "received reset request from VF enet\n"); 1608 1609 if (hdev->default_reset_request) 1610 hdev->reset_level = 1611 hclgevf_get_reset_level(hdev, 1612 &hdev->default_reset_request); 1613 else 1614 hdev->reset_level = HNAE3_VF_FUNC_RESET; 1615 1616 /* reset of this VF requested */ 1617 set_bit(HCLGEVF_RESET_REQUESTED, &hdev->reset_state); 1618 hclgevf_reset_task_schedule(hdev); 1619 1620 hdev->last_reset_time = jiffies; 1621 } 1622 1623 static void hclgevf_set_def_reset_request(struct hnae3_ae_dev *ae_dev, 1624 enum hnae3_reset_type rst_type) 1625 { 1626 struct hclgevf_dev *hdev = ae_dev->priv; 1627 1628 set_bit(rst_type, &hdev->default_reset_request); 1629 } 1630 1631 static void hclgevf_flr_prepare(struct hnae3_ae_dev *ae_dev) 1632 { 1633 #define HCLGEVF_FLR_WAIT_MS 100 1634 #define HCLGEVF_FLR_WAIT_CNT 50 1635 struct hclgevf_dev *hdev = ae_dev->priv; 1636 int cnt = 0; 1637 1638 clear_bit(HNAE3_FLR_DOWN, &hdev->flr_state); 1639 clear_bit(HNAE3_FLR_DONE, &hdev->flr_state); 1640 set_bit(HNAE3_FLR_RESET, &hdev->default_reset_request); 1641 hclgevf_reset_event(hdev->pdev, NULL); 1642 1643 while (!test_bit(HNAE3_FLR_DOWN, &hdev->flr_state) && 1644 cnt++ < HCLGEVF_FLR_WAIT_CNT) 1645 msleep(HCLGEVF_FLR_WAIT_MS); 1646 1647 if (!test_bit(HNAE3_FLR_DOWN, &hdev->flr_state)) 1648 dev_err(&hdev->pdev->dev, 1649 "flr wait down timeout: %d\n", cnt); 1650 } 1651 1652 static u32 hclgevf_get_fw_version(struct hnae3_handle *handle) 1653 { 1654 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1655 1656 return hdev->fw_version; 1657 } 1658 1659 static void hclgevf_get_misc_vector(struct hclgevf_dev *hdev) 1660 { 1661 struct hclgevf_misc_vector *vector = &hdev->misc_vector; 1662 1663 vector->vector_irq = pci_irq_vector(hdev->pdev, 1664 HCLGEVF_MISC_VECTOR_NUM); 1665 vector->addr = hdev->hw.io_base + HCLGEVF_MISC_VECTOR_REG_BASE; 1666 /* vector status always valid for Vector 0 */ 1667 hdev->vector_status[HCLGEVF_MISC_VECTOR_NUM] = 0; 1668 hdev->vector_irq[HCLGEVF_MISC_VECTOR_NUM] = vector->vector_irq; 1669 1670 hdev->num_msi_left -= 1; 1671 hdev->num_msi_used += 1; 1672 } 1673 1674 void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev) 1675 { 1676 if (!test_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state) && 1677 !test_bit(HCLGEVF_STATE_REMOVING, &hdev->state)) { 1678 set_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state); 1679 schedule_work(&hdev->rst_service_task); 1680 } 1681 } 1682 1683 void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev) 1684 { 1685 if (!test_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state) && 1686 !test_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) { 1687 set_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 1688 schedule_work(&hdev->mbx_service_task); 1689 } 1690 } 1691 1692 static void hclgevf_task_schedule(struct hclgevf_dev *hdev) 1693 { 1694 if (!test_bit(HCLGEVF_STATE_DOWN, &hdev->state) && 1695 !test_and_set_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state)) 1696 schedule_work(&hdev->service_task); 1697 } 1698 1699 static void hclgevf_deferred_task_schedule(struct hclgevf_dev *hdev) 1700 { 1701 /* if we have any pending mailbox event then schedule the mbx task */ 1702 if (hdev->mbx_event_pending) 1703 hclgevf_mbx_task_schedule(hdev); 1704 1705 if (test_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state)) 1706 hclgevf_reset_task_schedule(hdev); 1707 } 1708 1709 static void hclgevf_service_timer(struct timer_list *t) 1710 { 1711 struct hclgevf_dev *hdev = from_timer(hdev, t, service_timer); 1712 1713 mod_timer(&hdev->service_timer, jiffies + 1714 HCLGEVF_GENERAL_TASK_INTERVAL * HZ); 1715 1716 hdev->stats_timer++; 1717 hclgevf_task_schedule(hdev); 1718 } 1719 1720 static void hclgevf_reset_service_task(struct work_struct *work) 1721 { 1722 struct hclgevf_dev *hdev = 1723 container_of(work, struct hclgevf_dev, rst_service_task); 1724 int ret; 1725 1726 if (test_and_set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 1727 return; 1728 1729 clear_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state); 1730 1731 if (test_and_clear_bit(HCLGEVF_RESET_PENDING, 1732 &hdev->reset_state)) { 1733 /* PF has initmated that it is about to reset the hardware. 1734 * We now have to poll & check if hardware has actually 1735 * completed the reset sequence. On hardware reset completion, 1736 * VF needs to reset the client and ae device. 1737 */ 1738 hdev->reset_attempts = 0; 1739 1740 hdev->last_reset_time = jiffies; 1741 while ((hdev->reset_type = 1742 hclgevf_get_reset_level(hdev, &hdev->reset_pending)) 1743 != HNAE3_NONE_RESET) { 1744 ret = hclgevf_reset(hdev); 1745 if (ret) 1746 dev_err(&hdev->pdev->dev, 1747 "VF stack reset failed %d.\n", ret); 1748 } 1749 } else if (test_and_clear_bit(HCLGEVF_RESET_REQUESTED, 1750 &hdev->reset_state)) { 1751 /* we could be here when either of below happens: 1752 * 1. reset was initiated due to watchdog timeout caused by 1753 * a. IMP was earlier reset and our TX got choked down and 1754 * which resulted in watchdog reacting and inducing VF 1755 * reset. This also means our cmdq would be unreliable. 1756 * b. problem in TX due to other lower layer(example link 1757 * layer not functioning properly etc.) 1758 * 2. VF reset might have been initiated due to some config 1759 * change. 1760 * 1761 * NOTE: Theres no clear way to detect above cases than to react 1762 * to the response of PF for this reset request. PF will ack the 1763 * 1b and 2. cases but we will not get any intimation about 1a 1764 * from PF as cmdq would be in unreliable state i.e. mailbox 1765 * communication between PF and VF would be broken. 1766 */ 1767 1768 /* if we are never geting into pending state it means either: 1769 * 1. PF is not receiving our request which could be due to IMP 1770 * reset 1771 * 2. PF is screwed 1772 * We cannot do much for 2. but to check first we can try reset 1773 * our PCIe + stack and see if it alleviates the problem. 1774 */ 1775 if (hdev->reset_attempts > 3) { 1776 /* prepare for full reset of stack + pcie interface */ 1777 set_bit(HNAE3_VF_FULL_RESET, &hdev->reset_pending); 1778 1779 /* "defer" schedule the reset task again */ 1780 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1781 } else { 1782 hdev->reset_attempts++; 1783 1784 set_bit(hdev->reset_level, &hdev->reset_pending); 1785 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1786 } 1787 hclgevf_reset_task_schedule(hdev); 1788 } 1789 1790 clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 1791 } 1792 1793 static void hclgevf_mailbox_service_task(struct work_struct *work) 1794 { 1795 struct hclgevf_dev *hdev; 1796 1797 hdev = container_of(work, struct hclgevf_dev, mbx_service_task); 1798 1799 if (test_and_set_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) 1800 return; 1801 1802 clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 1803 1804 hclgevf_mbx_async_handler(hdev); 1805 1806 clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 1807 } 1808 1809 static void hclgevf_keep_alive_timer(struct timer_list *t) 1810 { 1811 struct hclgevf_dev *hdev = from_timer(hdev, t, keep_alive_timer); 1812 1813 schedule_work(&hdev->keep_alive_task); 1814 mod_timer(&hdev->keep_alive_timer, jiffies + 1815 HCLGEVF_KEEP_ALIVE_TASK_INTERVAL * HZ); 1816 } 1817 1818 static void hclgevf_keep_alive_task(struct work_struct *work) 1819 { 1820 struct hclgevf_dev *hdev; 1821 u8 respmsg; 1822 int ret; 1823 1824 hdev = container_of(work, struct hclgevf_dev, keep_alive_task); 1825 1826 if (test_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state)) 1827 return; 1828 1829 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_KEEP_ALIVE, 0, NULL, 1830 0, false, &respmsg, sizeof(respmsg)); 1831 if (ret) 1832 dev_err(&hdev->pdev->dev, 1833 "VF sends keep alive cmd failed(=%d)\n", ret); 1834 } 1835 1836 static void hclgevf_service_task(struct work_struct *work) 1837 { 1838 struct hnae3_handle *handle; 1839 struct hclgevf_dev *hdev; 1840 1841 hdev = container_of(work, struct hclgevf_dev, service_task); 1842 handle = &hdev->nic; 1843 1844 if (hdev->stats_timer >= HCLGEVF_STATS_TIMER_INTERVAL) { 1845 hclgevf_tqps_update_stats(handle); 1846 hdev->stats_timer = 0; 1847 } 1848 1849 /* request the link status from the PF. PF would be able to tell VF 1850 * about such updates in future so we might remove this later 1851 */ 1852 hclgevf_request_link_info(hdev); 1853 1854 hclgevf_update_link_mode(hdev); 1855 1856 hclgevf_sync_vlan_filter(hdev); 1857 1858 hclgevf_deferred_task_schedule(hdev); 1859 1860 clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 1861 } 1862 1863 static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regclr) 1864 { 1865 hclgevf_write_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_SRC_REG, regclr); 1866 } 1867 1868 static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev, 1869 u32 *clearval) 1870 { 1871 u32 cmdq_src_reg, rst_ing_reg; 1872 1873 /* fetch the events from their corresponding regs */ 1874 cmdq_src_reg = hclgevf_read_dev(&hdev->hw, 1875 HCLGEVF_VECTOR0_CMDQ_SRC_REG); 1876 1877 if (BIT(HCLGEVF_VECTOR0_RST_INT_B) & cmdq_src_reg) { 1878 rst_ing_reg = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 1879 dev_info(&hdev->pdev->dev, 1880 "receive reset interrupt 0x%x!\n", rst_ing_reg); 1881 set_bit(HNAE3_VF_RESET, &hdev->reset_pending); 1882 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1883 set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 1884 cmdq_src_reg &= ~BIT(HCLGEVF_VECTOR0_RST_INT_B); 1885 *clearval = cmdq_src_reg; 1886 hdev->rst_stats.vf_rst_cnt++; 1887 return HCLGEVF_VECTOR0_EVENT_RST; 1888 } 1889 1890 /* check for vector0 mailbox(=CMDQ RX) event source */ 1891 if (BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) { 1892 cmdq_src_reg &= ~BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 1893 *clearval = cmdq_src_reg; 1894 return HCLGEVF_VECTOR0_EVENT_MBX; 1895 } 1896 1897 dev_dbg(&hdev->pdev->dev, "vector 0 interrupt from unknown source\n"); 1898 1899 return HCLGEVF_VECTOR0_EVENT_OTHER; 1900 } 1901 1902 static void hclgevf_enable_vector(struct hclgevf_misc_vector *vector, bool en) 1903 { 1904 writel(en ? 1 : 0, vector->addr); 1905 } 1906 1907 static irqreturn_t hclgevf_misc_irq_handle(int irq, void *data) 1908 { 1909 enum hclgevf_evt_cause event_cause; 1910 struct hclgevf_dev *hdev = data; 1911 u32 clearval; 1912 1913 hclgevf_enable_vector(&hdev->misc_vector, false); 1914 event_cause = hclgevf_check_evt_cause(hdev, &clearval); 1915 1916 switch (event_cause) { 1917 case HCLGEVF_VECTOR0_EVENT_RST: 1918 hclgevf_reset_task_schedule(hdev); 1919 break; 1920 case HCLGEVF_VECTOR0_EVENT_MBX: 1921 hclgevf_mbx_handler(hdev); 1922 break; 1923 default: 1924 break; 1925 } 1926 1927 if (event_cause != HCLGEVF_VECTOR0_EVENT_OTHER) { 1928 hclgevf_clear_event_cause(hdev, clearval); 1929 hclgevf_enable_vector(&hdev->misc_vector, true); 1930 } 1931 1932 return IRQ_HANDLED; 1933 } 1934 1935 static int hclgevf_configure(struct hclgevf_dev *hdev) 1936 { 1937 int ret; 1938 1939 /* get current port based vlan state from PF */ 1940 ret = hclgevf_get_port_base_vlan_filter_state(hdev); 1941 if (ret) 1942 return ret; 1943 1944 /* get queue configuration from PF */ 1945 ret = hclgevf_get_queue_info(hdev); 1946 if (ret) 1947 return ret; 1948 1949 /* get queue depth info from PF */ 1950 ret = hclgevf_get_queue_depth(hdev); 1951 if (ret) 1952 return ret; 1953 1954 ret = hclgevf_get_pf_media_type(hdev); 1955 if (ret) 1956 return ret; 1957 1958 /* get tc configuration from PF */ 1959 return hclgevf_get_tc_info(hdev); 1960 } 1961 1962 static int hclgevf_alloc_hdev(struct hnae3_ae_dev *ae_dev) 1963 { 1964 struct pci_dev *pdev = ae_dev->pdev; 1965 struct hclgevf_dev *hdev; 1966 1967 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 1968 if (!hdev) 1969 return -ENOMEM; 1970 1971 hdev->pdev = pdev; 1972 hdev->ae_dev = ae_dev; 1973 ae_dev->priv = hdev; 1974 1975 return 0; 1976 } 1977 1978 static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev) 1979 { 1980 struct hnae3_handle *roce = &hdev->roce; 1981 struct hnae3_handle *nic = &hdev->nic; 1982 1983 roce->rinfo.num_vectors = hdev->num_roce_msix; 1984 1985 if (hdev->num_msi_left < roce->rinfo.num_vectors || 1986 hdev->num_msi_left == 0) 1987 return -EINVAL; 1988 1989 roce->rinfo.base_vector = hdev->roce_base_vector; 1990 1991 roce->rinfo.netdev = nic->kinfo.netdev; 1992 roce->rinfo.roce_io_base = hdev->hw.io_base; 1993 1994 roce->pdev = nic->pdev; 1995 roce->ae_algo = nic->ae_algo; 1996 roce->numa_node_mask = nic->numa_node_mask; 1997 1998 return 0; 1999 } 2000 2001 static int hclgevf_config_gro(struct hclgevf_dev *hdev, bool en) 2002 { 2003 struct hclgevf_cfg_gro_status_cmd *req; 2004 struct hclgevf_desc desc; 2005 int ret; 2006 2007 if (!hnae3_dev_gro_supported(hdev)) 2008 return 0; 2009 2010 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_GRO_GENERIC_CONFIG, 2011 false); 2012 req = (struct hclgevf_cfg_gro_status_cmd *)desc.data; 2013 2014 req->gro_en = cpu_to_le16(en ? 1 : 0); 2015 2016 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 2017 if (ret) 2018 dev_err(&hdev->pdev->dev, 2019 "VF GRO hardware config cmd failed, ret = %d.\n", ret); 2020 2021 return ret; 2022 } 2023 2024 static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev) 2025 { 2026 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 2027 int i, ret; 2028 2029 rss_cfg->rss_size = hdev->rss_size_max; 2030 2031 if (hdev->pdev->revision >= 0x21) { 2032 rss_cfg->hash_algo = HCLGEVF_RSS_HASH_ALGO_SIMPLE; 2033 memcpy(rss_cfg->rss_hash_key, hclgevf_hash_key, 2034 HCLGEVF_RSS_KEY_SIZE); 2035 2036 ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 2037 rss_cfg->rss_hash_key); 2038 if (ret) 2039 return ret; 2040 2041 rss_cfg->rss_tuple_sets.ipv4_tcp_en = 2042 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2043 rss_cfg->rss_tuple_sets.ipv4_udp_en = 2044 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2045 rss_cfg->rss_tuple_sets.ipv4_sctp_en = 2046 HCLGEVF_RSS_INPUT_TUPLE_SCTP; 2047 rss_cfg->rss_tuple_sets.ipv4_fragment_en = 2048 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2049 rss_cfg->rss_tuple_sets.ipv6_tcp_en = 2050 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2051 rss_cfg->rss_tuple_sets.ipv6_udp_en = 2052 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2053 rss_cfg->rss_tuple_sets.ipv6_sctp_en = 2054 HCLGEVF_RSS_INPUT_TUPLE_SCTP; 2055 rss_cfg->rss_tuple_sets.ipv6_fragment_en = 2056 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2057 2058 ret = hclgevf_set_rss_input_tuple(hdev, rss_cfg); 2059 if (ret) 2060 return ret; 2061 2062 } 2063 2064 /* Initialize RSS indirect table */ 2065 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 2066 rss_cfg->rss_indirection_tbl[i] = i % hdev->rss_size_max; 2067 2068 ret = hclgevf_set_rss_indir_table(hdev); 2069 if (ret) 2070 return ret; 2071 2072 return hclgevf_set_rss_tc_mode(hdev, hdev->rss_size_max); 2073 } 2074 2075 static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev) 2076 { 2077 return hclgevf_set_vlan_filter(&hdev->nic, htons(ETH_P_8021Q), 0, 2078 false); 2079 } 2080 2081 static void hclgevf_set_timer_task(struct hnae3_handle *handle, bool enable) 2082 { 2083 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2084 2085 if (enable) { 2086 mod_timer(&hdev->service_timer, jiffies + HZ); 2087 } else { 2088 del_timer_sync(&hdev->service_timer); 2089 cancel_work_sync(&hdev->service_task); 2090 clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 2091 } 2092 } 2093 2094 static int hclgevf_ae_start(struct hnae3_handle *handle) 2095 { 2096 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2097 2098 hclgevf_reset_tqp_stats(handle); 2099 2100 hclgevf_request_link_info(hdev); 2101 2102 hclgevf_update_link_mode(hdev); 2103 2104 clear_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2105 2106 return 0; 2107 } 2108 2109 static void hclgevf_ae_stop(struct hnae3_handle *handle) 2110 { 2111 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2112 int i; 2113 2114 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2115 2116 if (hdev->reset_type != HNAE3_VF_RESET) 2117 for (i = 0; i < handle->kinfo.num_tqps; i++) 2118 if (hclgevf_reset_tqp(handle, i)) 2119 break; 2120 2121 hclgevf_reset_tqp_stats(handle); 2122 hclgevf_update_link_status(hdev, 0); 2123 } 2124 2125 static int hclgevf_set_alive(struct hnae3_handle *handle, bool alive) 2126 { 2127 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2128 u8 msg_data; 2129 2130 msg_data = alive ? 1 : 0; 2131 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_ALIVE, 2132 0, &msg_data, 1, false, NULL, 0); 2133 } 2134 2135 static int hclgevf_client_start(struct hnae3_handle *handle) 2136 { 2137 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2138 int ret; 2139 2140 ret = hclgevf_set_alive(handle, true); 2141 if (ret) 2142 return ret; 2143 2144 mod_timer(&hdev->keep_alive_timer, jiffies + 2145 HCLGEVF_KEEP_ALIVE_TASK_INTERVAL * HZ); 2146 2147 return 0; 2148 } 2149 2150 static void hclgevf_client_stop(struct hnae3_handle *handle) 2151 { 2152 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2153 int ret; 2154 2155 ret = hclgevf_set_alive(handle, false); 2156 if (ret) 2157 dev_warn(&hdev->pdev->dev, 2158 "%s failed %d\n", __func__, ret); 2159 2160 del_timer_sync(&hdev->keep_alive_timer); 2161 cancel_work_sync(&hdev->keep_alive_task); 2162 } 2163 2164 static void hclgevf_state_init(struct hclgevf_dev *hdev) 2165 { 2166 /* setup tasks for the MBX */ 2167 INIT_WORK(&hdev->mbx_service_task, hclgevf_mailbox_service_task); 2168 clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 2169 clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 2170 2171 /* setup tasks for service timer */ 2172 timer_setup(&hdev->service_timer, hclgevf_service_timer, 0); 2173 2174 INIT_WORK(&hdev->service_task, hclgevf_service_task); 2175 clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 2176 2177 INIT_WORK(&hdev->rst_service_task, hclgevf_reset_service_task); 2178 2179 mutex_init(&hdev->mbx_resp.mbx_mutex); 2180 2181 /* bring the device down */ 2182 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2183 } 2184 2185 static void hclgevf_state_uninit(struct hclgevf_dev *hdev) 2186 { 2187 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2188 set_bit(HCLGEVF_STATE_REMOVING, &hdev->state); 2189 2190 if (hdev->keep_alive_timer.function) 2191 del_timer_sync(&hdev->keep_alive_timer); 2192 if (hdev->keep_alive_task.func) 2193 cancel_work_sync(&hdev->keep_alive_task); 2194 if (hdev->service_timer.function) 2195 del_timer_sync(&hdev->service_timer); 2196 if (hdev->service_task.func) 2197 cancel_work_sync(&hdev->service_task); 2198 if (hdev->mbx_service_task.func) 2199 cancel_work_sync(&hdev->mbx_service_task); 2200 if (hdev->rst_service_task.func) 2201 cancel_work_sync(&hdev->rst_service_task); 2202 2203 mutex_destroy(&hdev->mbx_resp.mbx_mutex); 2204 } 2205 2206 static int hclgevf_init_msi(struct hclgevf_dev *hdev) 2207 { 2208 struct pci_dev *pdev = hdev->pdev; 2209 int vectors; 2210 int i; 2211 2212 if (hnae3_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B)) 2213 vectors = pci_alloc_irq_vectors(pdev, 2214 hdev->roce_base_msix_offset + 1, 2215 hdev->num_msi, 2216 PCI_IRQ_MSIX); 2217 else 2218 vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi, 2219 PCI_IRQ_MSI | PCI_IRQ_MSIX); 2220 2221 if (vectors < 0) { 2222 dev_err(&pdev->dev, 2223 "failed(%d) to allocate MSI/MSI-X vectors\n", 2224 vectors); 2225 return vectors; 2226 } 2227 if (vectors < hdev->num_msi) 2228 dev_warn(&hdev->pdev->dev, 2229 "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n", 2230 hdev->num_msi, vectors); 2231 2232 hdev->num_msi = vectors; 2233 hdev->num_msi_left = vectors; 2234 hdev->base_msi_vector = pdev->irq; 2235 hdev->roce_base_vector = pdev->irq + hdev->roce_base_msix_offset; 2236 2237 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 2238 sizeof(u16), GFP_KERNEL); 2239 if (!hdev->vector_status) { 2240 pci_free_irq_vectors(pdev); 2241 return -ENOMEM; 2242 } 2243 2244 for (i = 0; i < hdev->num_msi; i++) 2245 hdev->vector_status[i] = HCLGEVF_INVALID_VPORT; 2246 2247 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 2248 sizeof(int), GFP_KERNEL); 2249 if (!hdev->vector_irq) { 2250 devm_kfree(&pdev->dev, hdev->vector_status); 2251 pci_free_irq_vectors(pdev); 2252 return -ENOMEM; 2253 } 2254 2255 return 0; 2256 } 2257 2258 static void hclgevf_uninit_msi(struct hclgevf_dev *hdev) 2259 { 2260 struct pci_dev *pdev = hdev->pdev; 2261 2262 devm_kfree(&pdev->dev, hdev->vector_status); 2263 devm_kfree(&pdev->dev, hdev->vector_irq); 2264 pci_free_irq_vectors(pdev); 2265 } 2266 2267 static int hclgevf_misc_irq_init(struct hclgevf_dev *hdev) 2268 { 2269 int ret = 0; 2270 2271 hclgevf_get_misc_vector(hdev); 2272 2273 ret = request_irq(hdev->misc_vector.vector_irq, hclgevf_misc_irq_handle, 2274 0, "hclgevf_cmd", hdev); 2275 if (ret) { 2276 dev_err(&hdev->pdev->dev, "VF failed to request misc irq(%d)\n", 2277 hdev->misc_vector.vector_irq); 2278 return ret; 2279 } 2280 2281 hclgevf_clear_event_cause(hdev, 0); 2282 2283 /* enable misc. vector(vector 0) */ 2284 hclgevf_enable_vector(&hdev->misc_vector, true); 2285 2286 return ret; 2287 } 2288 2289 static void hclgevf_misc_irq_uninit(struct hclgevf_dev *hdev) 2290 { 2291 /* disable misc vector(vector 0) */ 2292 hclgevf_enable_vector(&hdev->misc_vector, false); 2293 synchronize_irq(hdev->misc_vector.vector_irq); 2294 free_irq(hdev->misc_vector.vector_irq, hdev); 2295 hclgevf_free_vector(hdev, 0); 2296 } 2297 2298 static void hclgevf_info_show(struct hclgevf_dev *hdev) 2299 { 2300 struct device *dev = &hdev->pdev->dev; 2301 2302 dev_info(dev, "VF info begin:\n"); 2303 2304 dev_info(dev, "Task queue pairs numbers: %d\n", hdev->num_tqps); 2305 dev_info(dev, "Desc num per TX queue: %d\n", hdev->num_tx_desc); 2306 dev_info(dev, "Desc num per RX queue: %d\n", hdev->num_rx_desc); 2307 dev_info(dev, "Numbers of vports: %d\n", hdev->num_alloc_vport); 2308 dev_info(dev, "HW tc map: %d\n", hdev->hw_tc_map); 2309 dev_info(dev, "PF media type of this VF: %d\n", 2310 hdev->hw.mac.media_type); 2311 2312 dev_info(dev, "VF info end.\n"); 2313 } 2314 2315 static int hclgevf_init_nic_client_instance(struct hnae3_ae_dev *ae_dev, 2316 struct hnae3_client *client) 2317 { 2318 struct hclgevf_dev *hdev = ae_dev->priv; 2319 int ret; 2320 2321 ret = client->ops->init_instance(&hdev->nic); 2322 if (ret) 2323 return ret; 2324 2325 set_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 2326 hnae3_set_client_init_flag(client, ae_dev, 1); 2327 2328 if (netif_msg_drv(&hdev->nic)) 2329 hclgevf_info_show(hdev); 2330 2331 return 0; 2332 } 2333 2334 static int hclgevf_init_roce_client_instance(struct hnae3_ae_dev *ae_dev, 2335 struct hnae3_client *client) 2336 { 2337 struct hclgevf_dev *hdev = ae_dev->priv; 2338 int ret; 2339 2340 if (!hnae3_dev_roce_supported(hdev) || !hdev->roce_client || 2341 !hdev->nic_client) 2342 return 0; 2343 2344 ret = hclgevf_init_roce_base_info(hdev); 2345 if (ret) 2346 return ret; 2347 2348 ret = client->ops->init_instance(&hdev->roce); 2349 if (ret) 2350 return ret; 2351 2352 hnae3_set_client_init_flag(client, ae_dev, 1); 2353 2354 return 0; 2355 } 2356 2357 static int hclgevf_init_client_instance(struct hnae3_client *client, 2358 struct hnae3_ae_dev *ae_dev) 2359 { 2360 struct hclgevf_dev *hdev = ae_dev->priv; 2361 int ret; 2362 2363 switch (client->type) { 2364 case HNAE3_CLIENT_KNIC: 2365 hdev->nic_client = client; 2366 hdev->nic.client = client; 2367 2368 ret = hclgevf_init_nic_client_instance(ae_dev, client); 2369 if (ret) 2370 goto clear_nic; 2371 2372 ret = hclgevf_init_roce_client_instance(ae_dev, 2373 hdev->roce_client); 2374 if (ret) 2375 goto clear_roce; 2376 2377 break; 2378 case HNAE3_CLIENT_ROCE: 2379 if (hnae3_dev_roce_supported(hdev)) { 2380 hdev->roce_client = client; 2381 hdev->roce.client = client; 2382 } 2383 2384 ret = hclgevf_init_roce_client_instance(ae_dev, client); 2385 if (ret) 2386 goto clear_roce; 2387 2388 break; 2389 default: 2390 return -EINVAL; 2391 } 2392 2393 return 0; 2394 2395 clear_nic: 2396 hdev->nic_client = NULL; 2397 hdev->nic.client = NULL; 2398 return ret; 2399 clear_roce: 2400 hdev->roce_client = NULL; 2401 hdev->roce.client = NULL; 2402 return ret; 2403 } 2404 2405 static void hclgevf_uninit_client_instance(struct hnae3_client *client, 2406 struct hnae3_ae_dev *ae_dev) 2407 { 2408 struct hclgevf_dev *hdev = ae_dev->priv; 2409 2410 /* un-init roce, if it exists */ 2411 if (hdev->roce_client) { 2412 hdev->roce_client->ops->uninit_instance(&hdev->roce, 0); 2413 hdev->roce_client = NULL; 2414 hdev->roce.client = NULL; 2415 } 2416 2417 /* un-init nic/unic, if this was not called by roce client */ 2418 if (client->ops->uninit_instance && hdev->nic_client && 2419 client->type != HNAE3_CLIENT_ROCE) { 2420 clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 2421 2422 client->ops->uninit_instance(&hdev->nic, 0); 2423 hdev->nic_client = NULL; 2424 hdev->nic.client = NULL; 2425 } 2426 } 2427 2428 static int hclgevf_pci_init(struct hclgevf_dev *hdev) 2429 { 2430 struct pci_dev *pdev = hdev->pdev; 2431 struct hclgevf_hw *hw; 2432 int ret; 2433 2434 ret = pci_enable_device(pdev); 2435 if (ret) { 2436 dev_err(&pdev->dev, "failed to enable PCI device\n"); 2437 return ret; 2438 } 2439 2440 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 2441 if (ret) { 2442 dev_err(&pdev->dev, "can't set consistent PCI DMA, exiting"); 2443 goto err_disable_device; 2444 } 2445 2446 ret = pci_request_regions(pdev, HCLGEVF_DRIVER_NAME); 2447 if (ret) { 2448 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 2449 goto err_disable_device; 2450 } 2451 2452 pci_set_master(pdev); 2453 hw = &hdev->hw; 2454 hw->hdev = hdev; 2455 hw->io_base = pci_iomap(pdev, 2, 0); 2456 if (!hw->io_base) { 2457 dev_err(&pdev->dev, "can't map configuration register space\n"); 2458 ret = -ENOMEM; 2459 goto err_clr_master; 2460 } 2461 2462 return 0; 2463 2464 err_clr_master: 2465 pci_clear_master(pdev); 2466 pci_release_regions(pdev); 2467 err_disable_device: 2468 pci_disable_device(pdev); 2469 2470 return ret; 2471 } 2472 2473 static void hclgevf_pci_uninit(struct hclgevf_dev *hdev) 2474 { 2475 struct pci_dev *pdev = hdev->pdev; 2476 2477 pci_iounmap(pdev, hdev->hw.io_base); 2478 pci_clear_master(pdev); 2479 pci_release_regions(pdev); 2480 pci_disable_device(pdev); 2481 } 2482 2483 static int hclgevf_query_vf_resource(struct hclgevf_dev *hdev) 2484 { 2485 struct hclgevf_query_res_cmd *req; 2486 struct hclgevf_desc desc; 2487 int ret; 2488 2489 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_VF_RSRC, true); 2490 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 2491 if (ret) { 2492 dev_err(&hdev->pdev->dev, 2493 "query vf resource failed, ret = %d.\n", ret); 2494 return ret; 2495 } 2496 2497 req = (struct hclgevf_query_res_cmd *)desc.data; 2498 2499 if (hnae3_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B)) { 2500 hdev->roce_base_msix_offset = 2501 hnae3_get_field(__le16_to_cpu(req->msixcap_localid_ba_rocee), 2502 HCLGEVF_MSIX_OFT_ROCEE_M, 2503 HCLGEVF_MSIX_OFT_ROCEE_S); 2504 hdev->num_roce_msix = 2505 hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number), 2506 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 2507 2508 /* VF should have NIC vectors and Roce vectors, NIC vectors 2509 * are queued before Roce vectors. The offset is fixed to 64. 2510 */ 2511 hdev->num_msi = hdev->num_roce_msix + 2512 hdev->roce_base_msix_offset; 2513 } else { 2514 hdev->num_msi = 2515 hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number), 2516 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 2517 } 2518 2519 return 0; 2520 } 2521 2522 static int hclgevf_pci_reset(struct hclgevf_dev *hdev) 2523 { 2524 struct pci_dev *pdev = hdev->pdev; 2525 int ret = 0; 2526 2527 if (hdev->reset_type == HNAE3_VF_FULL_RESET && 2528 test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2529 hclgevf_misc_irq_uninit(hdev); 2530 hclgevf_uninit_msi(hdev); 2531 clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2532 } 2533 2534 if (!test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2535 pci_set_master(pdev); 2536 ret = hclgevf_init_msi(hdev); 2537 if (ret) { 2538 dev_err(&pdev->dev, 2539 "failed(%d) to init MSI/MSI-X\n", ret); 2540 return ret; 2541 } 2542 2543 ret = hclgevf_misc_irq_init(hdev); 2544 if (ret) { 2545 hclgevf_uninit_msi(hdev); 2546 dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 2547 ret); 2548 return ret; 2549 } 2550 2551 set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2552 } 2553 2554 return ret; 2555 } 2556 2557 static int hclgevf_reset_hdev(struct hclgevf_dev *hdev) 2558 { 2559 struct pci_dev *pdev = hdev->pdev; 2560 int ret; 2561 2562 ret = hclgevf_pci_reset(hdev); 2563 if (ret) { 2564 dev_err(&pdev->dev, "pci reset failed %d\n", ret); 2565 return ret; 2566 } 2567 2568 ret = hclgevf_cmd_init(hdev); 2569 if (ret) { 2570 dev_err(&pdev->dev, "cmd failed %d\n", ret); 2571 return ret; 2572 } 2573 2574 ret = hclgevf_rss_init_hw(hdev); 2575 if (ret) { 2576 dev_err(&hdev->pdev->dev, 2577 "failed(%d) to initialize RSS\n", ret); 2578 return ret; 2579 } 2580 2581 ret = hclgevf_config_gro(hdev, true); 2582 if (ret) 2583 return ret; 2584 2585 ret = hclgevf_init_vlan_config(hdev); 2586 if (ret) { 2587 dev_err(&hdev->pdev->dev, 2588 "failed(%d) to initialize VLAN config\n", ret); 2589 return ret; 2590 } 2591 2592 dev_info(&hdev->pdev->dev, "Reset done\n"); 2593 2594 return 0; 2595 } 2596 2597 static int hclgevf_init_hdev(struct hclgevf_dev *hdev) 2598 { 2599 struct pci_dev *pdev = hdev->pdev; 2600 int ret; 2601 2602 ret = hclgevf_pci_init(hdev); 2603 if (ret) { 2604 dev_err(&pdev->dev, "PCI initialization failed\n"); 2605 return ret; 2606 } 2607 2608 ret = hclgevf_cmd_queue_init(hdev); 2609 if (ret) { 2610 dev_err(&pdev->dev, "Cmd queue init failed: %d\n", ret); 2611 goto err_cmd_queue_init; 2612 } 2613 2614 ret = hclgevf_cmd_init(hdev); 2615 if (ret) 2616 goto err_cmd_init; 2617 2618 /* Get vf resource */ 2619 ret = hclgevf_query_vf_resource(hdev); 2620 if (ret) { 2621 dev_err(&hdev->pdev->dev, 2622 "Query vf status error, ret = %d.\n", ret); 2623 goto err_cmd_init; 2624 } 2625 2626 ret = hclgevf_init_msi(hdev); 2627 if (ret) { 2628 dev_err(&pdev->dev, "failed(%d) to init MSI/MSI-X\n", ret); 2629 goto err_cmd_init; 2630 } 2631 2632 hclgevf_state_init(hdev); 2633 hdev->reset_level = HNAE3_VF_FUNC_RESET; 2634 2635 ret = hclgevf_misc_irq_init(hdev); 2636 if (ret) { 2637 dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 2638 ret); 2639 goto err_misc_irq_init; 2640 } 2641 2642 set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2643 2644 ret = hclgevf_configure(hdev); 2645 if (ret) { 2646 dev_err(&pdev->dev, "failed(%d) to fetch configuration\n", ret); 2647 goto err_config; 2648 } 2649 2650 ret = hclgevf_alloc_tqps(hdev); 2651 if (ret) { 2652 dev_err(&pdev->dev, "failed(%d) to allocate TQPs\n", ret); 2653 goto err_config; 2654 } 2655 2656 ret = hclgevf_set_handle_info(hdev); 2657 if (ret) { 2658 dev_err(&pdev->dev, "failed(%d) to set handle info\n", ret); 2659 goto err_config; 2660 } 2661 2662 ret = hclgevf_config_gro(hdev, true); 2663 if (ret) 2664 goto err_config; 2665 2666 /* vf is not allowed to enable unicast/multicast promisc mode. 2667 * For revision 0x20, default to disable broadcast promisc mode, 2668 * firmware makes sure broadcast packets can be accepted. 2669 * For revision 0x21, default to enable broadcast promisc mode. 2670 */ 2671 ret = hclgevf_set_promisc_mode(hdev, true); 2672 if (ret) 2673 goto err_config; 2674 2675 /* Initialize RSS for this VF */ 2676 ret = hclgevf_rss_init_hw(hdev); 2677 if (ret) { 2678 dev_err(&hdev->pdev->dev, 2679 "failed(%d) to initialize RSS\n", ret); 2680 goto err_config; 2681 } 2682 2683 ret = hclgevf_init_vlan_config(hdev); 2684 if (ret) { 2685 dev_err(&hdev->pdev->dev, 2686 "failed(%d) to initialize VLAN config\n", ret); 2687 goto err_config; 2688 } 2689 2690 hdev->last_reset_time = jiffies; 2691 pr_info("finished initializing %s driver\n", HCLGEVF_DRIVER_NAME); 2692 2693 return 0; 2694 2695 err_config: 2696 hclgevf_misc_irq_uninit(hdev); 2697 err_misc_irq_init: 2698 hclgevf_state_uninit(hdev); 2699 hclgevf_uninit_msi(hdev); 2700 err_cmd_init: 2701 hclgevf_cmd_uninit(hdev); 2702 err_cmd_queue_init: 2703 hclgevf_pci_uninit(hdev); 2704 clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2705 return ret; 2706 } 2707 2708 static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev) 2709 { 2710 hclgevf_state_uninit(hdev); 2711 2712 if (test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2713 hclgevf_misc_irq_uninit(hdev); 2714 hclgevf_uninit_msi(hdev); 2715 } 2716 2717 hclgevf_pci_uninit(hdev); 2718 hclgevf_cmd_uninit(hdev); 2719 } 2720 2721 static int hclgevf_init_ae_dev(struct hnae3_ae_dev *ae_dev) 2722 { 2723 struct pci_dev *pdev = ae_dev->pdev; 2724 struct hclgevf_dev *hdev; 2725 int ret; 2726 2727 ret = hclgevf_alloc_hdev(ae_dev); 2728 if (ret) { 2729 dev_err(&pdev->dev, "hclge device allocation failed\n"); 2730 return ret; 2731 } 2732 2733 ret = hclgevf_init_hdev(ae_dev->priv); 2734 if (ret) { 2735 dev_err(&pdev->dev, "hclge device initialization failed\n"); 2736 return ret; 2737 } 2738 2739 hdev = ae_dev->priv; 2740 timer_setup(&hdev->keep_alive_timer, hclgevf_keep_alive_timer, 0); 2741 INIT_WORK(&hdev->keep_alive_task, hclgevf_keep_alive_task); 2742 2743 return 0; 2744 } 2745 2746 static void hclgevf_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 2747 { 2748 struct hclgevf_dev *hdev = ae_dev->priv; 2749 2750 hclgevf_uninit_hdev(hdev); 2751 ae_dev->priv = NULL; 2752 } 2753 2754 static u32 hclgevf_get_max_channels(struct hclgevf_dev *hdev) 2755 { 2756 struct hnae3_handle *nic = &hdev->nic; 2757 struct hnae3_knic_private_info *kinfo = &nic->kinfo; 2758 2759 return min_t(u32, hdev->rss_size_max, 2760 hdev->num_tqps / kinfo->num_tc); 2761 } 2762 2763 /** 2764 * hclgevf_get_channels - Get the current channels enabled and max supported. 2765 * @handle: hardware information for network interface 2766 * @ch: ethtool channels structure 2767 * 2768 * We don't support separate tx and rx queues as channels. The other count 2769 * represents how many queues are being used for control. max_combined counts 2770 * how many queue pairs we can support. They may not be mapped 1 to 1 with 2771 * q_vectors since we support a lot more queue pairs than q_vectors. 2772 **/ 2773 static void hclgevf_get_channels(struct hnae3_handle *handle, 2774 struct ethtool_channels *ch) 2775 { 2776 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2777 2778 ch->max_combined = hclgevf_get_max_channels(hdev); 2779 ch->other_count = 0; 2780 ch->max_other = 0; 2781 ch->combined_count = handle->kinfo.rss_size; 2782 } 2783 2784 static void hclgevf_get_tqps_and_rss_info(struct hnae3_handle *handle, 2785 u16 *alloc_tqps, u16 *max_rss_size) 2786 { 2787 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2788 2789 *alloc_tqps = hdev->num_tqps; 2790 *max_rss_size = hdev->rss_size_max; 2791 } 2792 2793 static int hclgevf_get_status(struct hnae3_handle *handle) 2794 { 2795 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2796 2797 return hdev->hw.mac.link; 2798 } 2799 2800 static void hclgevf_get_ksettings_an_result(struct hnae3_handle *handle, 2801 u8 *auto_neg, u32 *speed, 2802 u8 *duplex) 2803 { 2804 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2805 2806 if (speed) 2807 *speed = hdev->hw.mac.speed; 2808 if (duplex) 2809 *duplex = hdev->hw.mac.duplex; 2810 if (auto_neg) 2811 *auto_neg = AUTONEG_DISABLE; 2812 } 2813 2814 void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed, 2815 u8 duplex) 2816 { 2817 hdev->hw.mac.speed = speed; 2818 hdev->hw.mac.duplex = duplex; 2819 } 2820 2821 static int hclgevf_gro_en(struct hnae3_handle *handle, bool enable) 2822 { 2823 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2824 2825 return hclgevf_config_gro(hdev, enable); 2826 } 2827 2828 static void hclgevf_get_media_type(struct hnae3_handle *handle, u8 *media_type, 2829 u8 *module_type) 2830 { 2831 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2832 2833 if (media_type) 2834 *media_type = hdev->hw.mac.media_type; 2835 2836 if (module_type) 2837 *module_type = hdev->hw.mac.module_type; 2838 } 2839 2840 static bool hclgevf_get_hw_reset_stat(struct hnae3_handle *handle) 2841 { 2842 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2843 2844 return !!hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 2845 } 2846 2847 static bool hclgevf_ae_dev_resetting(struct hnae3_handle *handle) 2848 { 2849 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2850 2851 return test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 2852 } 2853 2854 static unsigned long hclgevf_ae_dev_reset_cnt(struct hnae3_handle *handle) 2855 { 2856 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2857 2858 return hdev->rst_stats.hw_rst_done_cnt; 2859 } 2860 2861 static void hclgevf_get_link_mode(struct hnae3_handle *handle, 2862 unsigned long *supported, 2863 unsigned long *advertising) 2864 { 2865 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2866 2867 *supported = hdev->hw.mac.supported; 2868 *advertising = hdev->hw.mac.advertising; 2869 } 2870 2871 #define MAX_SEPARATE_NUM 4 2872 #define SEPARATOR_VALUE 0xFFFFFFFF 2873 #define REG_NUM_PER_LINE 4 2874 #define REG_LEN_PER_LINE (REG_NUM_PER_LINE * sizeof(u32)) 2875 2876 static int hclgevf_get_regs_len(struct hnae3_handle *handle) 2877 { 2878 int cmdq_lines, common_lines, ring_lines, tqp_intr_lines; 2879 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2880 2881 cmdq_lines = sizeof(cmdq_reg_addr_list) / REG_LEN_PER_LINE + 1; 2882 common_lines = sizeof(common_reg_addr_list) / REG_LEN_PER_LINE + 1; 2883 ring_lines = sizeof(ring_reg_addr_list) / REG_LEN_PER_LINE + 1; 2884 tqp_intr_lines = sizeof(tqp_intr_reg_addr_list) / REG_LEN_PER_LINE + 1; 2885 2886 return (cmdq_lines + common_lines + ring_lines * hdev->num_tqps + 2887 tqp_intr_lines * (hdev->num_msi_used - 1)) * REG_LEN_PER_LINE; 2888 } 2889 2890 static void hclgevf_get_regs(struct hnae3_handle *handle, u32 *version, 2891 void *data) 2892 { 2893 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2894 int i, j, reg_um, separator_num; 2895 u32 *reg = data; 2896 2897 *version = hdev->fw_version; 2898 2899 /* fetching per-VF registers values from VF PCIe register space */ 2900 reg_um = sizeof(cmdq_reg_addr_list) / sizeof(u32); 2901 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 2902 for (i = 0; i < reg_um; i++) 2903 *reg++ = hclgevf_read_dev(&hdev->hw, cmdq_reg_addr_list[i]); 2904 for (i = 0; i < separator_num; i++) 2905 *reg++ = SEPARATOR_VALUE; 2906 2907 reg_um = sizeof(common_reg_addr_list) / sizeof(u32); 2908 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 2909 for (i = 0; i < reg_um; i++) 2910 *reg++ = hclgevf_read_dev(&hdev->hw, common_reg_addr_list[i]); 2911 for (i = 0; i < separator_num; i++) 2912 *reg++ = SEPARATOR_VALUE; 2913 2914 reg_um = sizeof(ring_reg_addr_list) / sizeof(u32); 2915 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 2916 for (j = 0; j < hdev->num_tqps; j++) { 2917 for (i = 0; i < reg_um; i++) 2918 *reg++ = hclgevf_read_dev(&hdev->hw, 2919 ring_reg_addr_list[i] + 2920 0x200 * j); 2921 for (i = 0; i < separator_num; i++) 2922 *reg++ = SEPARATOR_VALUE; 2923 } 2924 2925 reg_um = sizeof(tqp_intr_reg_addr_list) / sizeof(u32); 2926 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 2927 for (j = 0; j < hdev->num_msi_used - 1; j++) { 2928 for (i = 0; i < reg_um; i++) 2929 *reg++ = hclgevf_read_dev(&hdev->hw, 2930 tqp_intr_reg_addr_list[i] + 2931 4 * j); 2932 for (i = 0; i < separator_num; i++) 2933 *reg++ = SEPARATOR_VALUE; 2934 } 2935 } 2936 2937 void hclgevf_update_port_base_vlan_info(struct hclgevf_dev *hdev, u16 state, 2938 u8 *port_base_vlan_info, u8 data_size) 2939 { 2940 struct hnae3_handle *nic = &hdev->nic; 2941 2942 rtnl_lock(); 2943 hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 2944 rtnl_unlock(); 2945 2946 /* send msg to PF and wait update port based vlan info */ 2947 hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 2948 HCLGE_MBX_PORT_BASE_VLAN_CFG, 2949 port_base_vlan_info, data_size, 2950 false, NULL, 0); 2951 2952 if (state == HNAE3_PORT_BASE_VLAN_DISABLE) 2953 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_DISABLE; 2954 else 2955 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_ENABLE; 2956 2957 rtnl_lock(); 2958 hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 2959 rtnl_unlock(); 2960 } 2961 2962 static const struct hnae3_ae_ops hclgevf_ops = { 2963 .init_ae_dev = hclgevf_init_ae_dev, 2964 .uninit_ae_dev = hclgevf_uninit_ae_dev, 2965 .flr_prepare = hclgevf_flr_prepare, 2966 .flr_done = hclgevf_flr_done, 2967 .init_client_instance = hclgevf_init_client_instance, 2968 .uninit_client_instance = hclgevf_uninit_client_instance, 2969 .start = hclgevf_ae_start, 2970 .stop = hclgevf_ae_stop, 2971 .client_start = hclgevf_client_start, 2972 .client_stop = hclgevf_client_stop, 2973 .map_ring_to_vector = hclgevf_map_ring_to_vector, 2974 .unmap_ring_from_vector = hclgevf_unmap_ring_from_vector, 2975 .get_vector = hclgevf_get_vector, 2976 .put_vector = hclgevf_put_vector, 2977 .reset_queue = hclgevf_reset_tqp, 2978 .get_mac_addr = hclgevf_get_mac_addr, 2979 .set_mac_addr = hclgevf_set_mac_addr, 2980 .add_uc_addr = hclgevf_add_uc_addr, 2981 .rm_uc_addr = hclgevf_rm_uc_addr, 2982 .add_mc_addr = hclgevf_add_mc_addr, 2983 .rm_mc_addr = hclgevf_rm_mc_addr, 2984 .get_stats = hclgevf_get_stats, 2985 .update_stats = hclgevf_update_stats, 2986 .get_strings = hclgevf_get_strings, 2987 .get_sset_count = hclgevf_get_sset_count, 2988 .get_rss_key_size = hclgevf_get_rss_key_size, 2989 .get_rss_indir_size = hclgevf_get_rss_indir_size, 2990 .get_rss = hclgevf_get_rss, 2991 .set_rss = hclgevf_set_rss, 2992 .get_rss_tuple = hclgevf_get_rss_tuple, 2993 .set_rss_tuple = hclgevf_set_rss_tuple, 2994 .get_tc_size = hclgevf_get_tc_size, 2995 .get_fw_version = hclgevf_get_fw_version, 2996 .set_vlan_filter = hclgevf_set_vlan_filter, 2997 .enable_hw_strip_rxvtag = hclgevf_en_hw_strip_rxvtag, 2998 .reset_event = hclgevf_reset_event, 2999 .set_default_reset_request = hclgevf_set_def_reset_request, 3000 .get_channels = hclgevf_get_channels, 3001 .get_tqps_and_rss_info = hclgevf_get_tqps_and_rss_info, 3002 .get_regs_len = hclgevf_get_regs_len, 3003 .get_regs = hclgevf_get_regs, 3004 .get_status = hclgevf_get_status, 3005 .get_ksettings_an_result = hclgevf_get_ksettings_an_result, 3006 .get_media_type = hclgevf_get_media_type, 3007 .get_hw_reset_stat = hclgevf_get_hw_reset_stat, 3008 .ae_dev_resetting = hclgevf_ae_dev_resetting, 3009 .ae_dev_reset_cnt = hclgevf_ae_dev_reset_cnt, 3010 .set_gro_en = hclgevf_gro_en, 3011 .set_mtu = hclgevf_set_mtu, 3012 .get_global_queue_id = hclgevf_get_qid_global, 3013 .set_timer_task = hclgevf_set_timer_task, 3014 .get_link_mode = hclgevf_get_link_mode, 3015 }; 3016 3017 static struct hnae3_ae_algo ae_algovf = { 3018 .ops = &hclgevf_ops, 3019 .pdev_id_table = ae_algovf_pci_tbl, 3020 }; 3021 3022 static int hclgevf_init(void) 3023 { 3024 pr_info("%s is initializing\n", HCLGEVF_NAME); 3025 3026 hnae3_register_ae_algo(&ae_algovf); 3027 3028 return 0; 3029 } 3030 3031 static void hclgevf_exit(void) 3032 { 3033 hnae3_unregister_ae_algo(&ae_algovf); 3034 } 3035 module_init(hclgevf_init); 3036 module_exit(hclgevf_exit); 3037 3038 MODULE_LICENSE("GPL"); 3039 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 3040 MODULE_DESCRIPTION("HCLGEVF Driver"); 3041 MODULE_VERSION(HCLGEVF_MOD_VERSION); 3042