1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/etherdevice.h> 5 #include <linux/iopoll.h> 6 #include <net/rtnetlink.h> 7 #include "hclgevf_cmd.h" 8 #include "hclgevf_main.h" 9 #include "hclge_mbx.h" 10 #include "hnae3.h" 11 12 #define HCLGEVF_NAME "hclgevf" 13 14 static int hclgevf_reset_hdev(struct hclgevf_dev *hdev); 15 static struct hnae3_ae_algo ae_algovf; 16 17 static const struct pci_device_id ae_algovf_pci_tbl[] = { 18 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0}, 19 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF), 0}, 20 /* required last entry */ 21 {0, } 22 }; 23 24 static const u8 hclgevf_hash_key[] = { 25 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2, 26 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0, 27 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4, 28 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C, 29 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA 30 }; 31 32 MODULE_DEVICE_TABLE(pci, ae_algovf_pci_tbl); 33 34 static const u32 cmdq_reg_addr_list[] = {HCLGEVF_CMDQ_TX_ADDR_L_REG, 35 HCLGEVF_CMDQ_TX_ADDR_H_REG, 36 HCLGEVF_CMDQ_TX_DEPTH_REG, 37 HCLGEVF_CMDQ_TX_TAIL_REG, 38 HCLGEVF_CMDQ_TX_HEAD_REG, 39 HCLGEVF_CMDQ_RX_ADDR_L_REG, 40 HCLGEVF_CMDQ_RX_ADDR_H_REG, 41 HCLGEVF_CMDQ_RX_DEPTH_REG, 42 HCLGEVF_CMDQ_RX_TAIL_REG, 43 HCLGEVF_CMDQ_RX_HEAD_REG, 44 HCLGEVF_VECTOR0_CMDQ_SRC_REG, 45 HCLGEVF_CMDQ_INTR_STS_REG, 46 HCLGEVF_CMDQ_INTR_EN_REG, 47 HCLGEVF_CMDQ_INTR_GEN_REG}; 48 49 static const u32 common_reg_addr_list[] = {HCLGEVF_MISC_VECTOR_REG_BASE, 50 HCLGEVF_RST_ING, 51 HCLGEVF_GRO_EN_REG}; 52 53 static const u32 ring_reg_addr_list[] = {HCLGEVF_RING_RX_ADDR_L_REG, 54 HCLGEVF_RING_RX_ADDR_H_REG, 55 HCLGEVF_RING_RX_BD_NUM_REG, 56 HCLGEVF_RING_RX_BD_LENGTH_REG, 57 HCLGEVF_RING_RX_MERGE_EN_REG, 58 HCLGEVF_RING_RX_TAIL_REG, 59 HCLGEVF_RING_RX_HEAD_REG, 60 HCLGEVF_RING_RX_FBD_NUM_REG, 61 HCLGEVF_RING_RX_OFFSET_REG, 62 HCLGEVF_RING_RX_FBD_OFFSET_REG, 63 HCLGEVF_RING_RX_STASH_REG, 64 HCLGEVF_RING_RX_BD_ERR_REG, 65 HCLGEVF_RING_TX_ADDR_L_REG, 66 HCLGEVF_RING_TX_ADDR_H_REG, 67 HCLGEVF_RING_TX_BD_NUM_REG, 68 HCLGEVF_RING_TX_PRIORITY_REG, 69 HCLGEVF_RING_TX_TC_REG, 70 HCLGEVF_RING_TX_MERGE_EN_REG, 71 HCLGEVF_RING_TX_TAIL_REG, 72 HCLGEVF_RING_TX_HEAD_REG, 73 HCLGEVF_RING_TX_FBD_NUM_REG, 74 HCLGEVF_RING_TX_OFFSET_REG, 75 HCLGEVF_RING_TX_EBD_NUM_REG, 76 HCLGEVF_RING_TX_EBD_OFFSET_REG, 77 HCLGEVF_RING_TX_BD_ERR_REG, 78 HCLGEVF_RING_EN_REG}; 79 80 static const u32 tqp_intr_reg_addr_list[] = {HCLGEVF_TQP_INTR_CTRL_REG, 81 HCLGEVF_TQP_INTR_GL0_REG, 82 HCLGEVF_TQP_INTR_GL1_REG, 83 HCLGEVF_TQP_INTR_GL2_REG, 84 HCLGEVF_TQP_INTR_RL_REG}; 85 86 static inline struct hclgevf_dev *hclgevf_ae_get_hdev( 87 struct hnae3_handle *handle) 88 { 89 if (!handle->client) 90 return container_of(handle, struct hclgevf_dev, nic); 91 else if (handle->client->type == HNAE3_CLIENT_ROCE) 92 return container_of(handle, struct hclgevf_dev, roce); 93 else 94 return container_of(handle, struct hclgevf_dev, nic); 95 } 96 97 static int hclgevf_tqps_update_stats(struct hnae3_handle *handle) 98 { 99 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 100 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 101 struct hclgevf_desc desc; 102 struct hclgevf_tqp *tqp; 103 int status; 104 int i; 105 106 for (i = 0; i < kinfo->num_tqps; i++) { 107 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 108 hclgevf_cmd_setup_basic_desc(&desc, 109 HCLGEVF_OPC_QUERY_RX_STATUS, 110 true); 111 112 desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 113 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 114 if (status) { 115 dev_err(&hdev->pdev->dev, 116 "Query tqp stat fail, status = %d,queue = %d\n", 117 status, i); 118 return status; 119 } 120 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd += 121 le32_to_cpu(desc.data[1]); 122 123 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_TX_STATUS, 124 true); 125 126 desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 127 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 128 if (status) { 129 dev_err(&hdev->pdev->dev, 130 "Query tqp stat fail, status = %d,queue = %d\n", 131 status, i); 132 return status; 133 } 134 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd += 135 le32_to_cpu(desc.data[1]); 136 } 137 138 return 0; 139 } 140 141 static u64 *hclgevf_tqps_get_stats(struct hnae3_handle *handle, u64 *data) 142 { 143 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 144 struct hclgevf_tqp *tqp; 145 u64 *buff = data; 146 int i; 147 148 for (i = 0; i < kinfo->num_tqps; i++) { 149 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 150 *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd; 151 } 152 for (i = 0; i < kinfo->num_tqps; i++) { 153 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 154 *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd; 155 } 156 157 return buff; 158 } 159 160 static int hclgevf_tqps_get_sset_count(struct hnae3_handle *handle, int strset) 161 { 162 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 163 164 return kinfo->num_tqps * 2; 165 } 166 167 static u8 *hclgevf_tqps_get_strings(struct hnae3_handle *handle, u8 *data) 168 { 169 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 170 u8 *buff = data; 171 int i = 0; 172 173 for (i = 0; i < kinfo->num_tqps; i++) { 174 struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 175 struct hclgevf_tqp, q); 176 snprintf(buff, ETH_GSTRING_LEN, "txq%d_pktnum_rcd", 177 tqp->index); 178 buff += ETH_GSTRING_LEN; 179 } 180 181 for (i = 0; i < kinfo->num_tqps; i++) { 182 struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 183 struct hclgevf_tqp, q); 184 snprintf(buff, ETH_GSTRING_LEN, "rxq%d_pktnum_rcd", 185 tqp->index); 186 buff += ETH_GSTRING_LEN; 187 } 188 189 return buff; 190 } 191 192 static void hclgevf_update_stats(struct hnae3_handle *handle, 193 struct net_device_stats *net_stats) 194 { 195 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 196 int status; 197 198 status = hclgevf_tqps_update_stats(handle); 199 if (status) 200 dev_err(&hdev->pdev->dev, 201 "VF update of TQPS stats fail, status = %d.\n", 202 status); 203 } 204 205 static int hclgevf_get_sset_count(struct hnae3_handle *handle, int strset) 206 { 207 if (strset == ETH_SS_TEST) 208 return -EOPNOTSUPP; 209 else if (strset == ETH_SS_STATS) 210 return hclgevf_tqps_get_sset_count(handle, strset); 211 212 return 0; 213 } 214 215 static void hclgevf_get_strings(struct hnae3_handle *handle, u32 strset, 216 u8 *data) 217 { 218 u8 *p = (char *)data; 219 220 if (strset == ETH_SS_STATS) 221 p = hclgevf_tqps_get_strings(handle, p); 222 } 223 224 static void hclgevf_get_stats(struct hnae3_handle *handle, u64 *data) 225 { 226 hclgevf_tqps_get_stats(handle, data); 227 } 228 229 static int hclgevf_get_tc_info(struct hclgevf_dev *hdev) 230 { 231 u8 resp_msg; 232 int status; 233 234 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_TCINFO, 0, NULL, 0, 235 true, &resp_msg, sizeof(u8)); 236 if (status) { 237 dev_err(&hdev->pdev->dev, 238 "VF request to get TC info from PF failed %d", 239 status); 240 return status; 241 } 242 243 hdev->hw_tc_map = resp_msg; 244 245 return 0; 246 } 247 248 static int hclgevf_get_port_base_vlan_filter_state(struct hclgevf_dev *hdev) 249 { 250 struct hnae3_handle *nic = &hdev->nic; 251 u8 resp_msg; 252 int ret; 253 254 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 255 HCLGE_MBX_GET_PORT_BASE_VLAN_STATE, 256 NULL, 0, true, &resp_msg, sizeof(u8)); 257 if (ret) { 258 dev_err(&hdev->pdev->dev, 259 "VF request to get port based vlan state failed %d", 260 ret); 261 return ret; 262 } 263 264 nic->port_base_vlan_state = resp_msg; 265 266 return 0; 267 } 268 269 static int hclgevf_get_queue_info(struct hclgevf_dev *hdev) 270 { 271 #define HCLGEVF_TQPS_RSS_INFO_LEN 6 272 u8 resp_msg[HCLGEVF_TQPS_RSS_INFO_LEN]; 273 int status; 274 275 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QINFO, 0, NULL, 0, 276 true, resp_msg, 277 HCLGEVF_TQPS_RSS_INFO_LEN); 278 if (status) { 279 dev_err(&hdev->pdev->dev, 280 "VF request to get tqp info from PF failed %d", 281 status); 282 return status; 283 } 284 285 memcpy(&hdev->num_tqps, &resp_msg[0], sizeof(u16)); 286 memcpy(&hdev->rss_size_max, &resp_msg[2], sizeof(u16)); 287 memcpy(&hdev->rx_buf_len, &resp_msg[4], sizeof(u16)); 288 289 return 0; 290 } 291 292 static int hclgevf_get_queue_depth(struct hclgevf_dev *hdev) 293 { 294 #define HCLGEVF_TQPS_DEPTH_INFO_LEN 4 295 u8 resp_msg[HCLGEVF_TQPS_DEPTH_INFO_LEN]; 296 int ret; 297 298 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QDEPTH, 0, NULL, 0, 299 true, resp_msg, 300 HCLGEVF_TQPS_DEPTH_INFO_LEN); 301 if (ret) { 302 dev_err(&hdev->pdev->dev, 303 "VF request to get tqp depth info from PF failed %d", 304 ret); 305 return ret; 306 } 307 308 memcpy(&hdev->num_tx_desc, &resp_msg[0], sizeof(u16)); 309 memcpy(&hdev->num_rx_desc, &resp_msg[2], sizeof(u16)); 310 311 return 0; 312 } 313 314 static u16 hclgevf_get_qid_global(struct hnae3_handle *handle, u16 queue_id) 315 { 316 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 317 u8 msg_data[2], resp_data[2]; 318 u16 qid_in_pf = 0; 319 int ret; 320 321 memcpy(&msg_data[0], &queue_id, sizeof(queue_id)); 322 323 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QID_IN_PF, 0, msg_data, 324 2, true, resp_data, 2); 325 if (!ret) 326 qid_in_pf = *(u16 *)resp_data; 327 328 return qid_in_pf; 329 } 330 331 static int hclgevf_get_pf_media_type(struct hclgevf_dev *hdev) 332 { 333 u8 resp_msg[2]; 334 int ret; 335 336 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_MEDIA_TYPE, 0, NULL, 0, 337 true, resp_msg, sizeof(resp_msg)); 338 if (ret) { 339 dev_err(&hdev->pdev->dev, 340 "VF request to get the pf port media type failed %d", 341 ret); 342 return ret; 343 } 344 345 hdev->hw.mac.media_type = resp_msg[0]; 346 hdev->hw.mac.module_type = resp_msg[1]; 347 348 return 0; 349 } 350 351 static int hclgevf_alloc_tqps(struct hclgevf_dev *hdev) 352 { 353 struct hclgevf_tqp *tqp; 354 int i; 355 356 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 357 sizeof(struct hclgevf_tqp), GFP_KERNEL); 358 if (!hdev->htqp) 359 return -ENOMEM; 360 361 tqp = hdev->htqp; 362 363 for (i = 0; i < hdev->num_tqps; i++) { 364 tqp->dev = &hdev->pdev->dev; 365 tqp->index = i; 366 367 tqp->q.ae_algo = &ae_algovf; 368 tqp->q.buf_size = hdev->rx_buf_len; 369 tqp->q.tx_desc_num = hdev->num_tx_desc; 370 tqp->q.rx_desc_num = hdev->num_rx_desc; 371 tqp->q.io_base = hdev->hw.io_base + HCLGEVF_TQP_REG_OFFSET + 372 i * HCLGEVF_TQP_REG_SIZE; 373 374 tqp++; 375 } 376 377 return 0; 378 } 379 380 static int hclgevf_knic_setup(struct hclgevf_dev *hdev) 381 { 382 struct hnae3_handle *nic = &hdev->nic; 383 struct hnae3_knic_private_info *kinfo; 384 u16 new_tqps = hdev->num_tqps; 385 int i; 386 387 kinfo = &nic->kinfo; 388 kinfo->num_tc = 0; 389 kinfo->num_tx_desc = hdev->num_tx_desc; 390 kinfo->num_rx_desc = hdev->num_rx_desc; 391 kinfo->rx_buf_len = hdev->rx_buf_len; 392 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) 393 if (hdev->hw_tc_map & BIT(i)) 394 kinfo->num_tc++; 395 396 kinfo->rss_size 397 = min_t(u16, hdev->rss_size_max, new_tqps / kinfo->num_tc); 398 new_tqps = kinfo->rss_size * kinfo->num_tc; 399 kinfo->num_tqps = min(new_tqps, hdev->num_tqps); 400 401 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps, 402 sizeof(struct hnae3_queue *), GFP_KERNEL); 403 if (!kinfo->tqp) 404 return -ENOMEM; 405 406 for (i = 0; i < kinfo->num_tqps; i++) { 407 hdev->htqp[i].q.handle = &hdev->nic; 408 hdev->htqp[i].q.tqp_index = i; 409 kinfo->tqp[i] = &hdev->htqp[i].q; 410 } 411 412 return 0; 413 } 414 415 static void hclgevf_request_link_info(struct hclgevf_dev *hdev) 416 { 417 int status; 418 u8 resp_msg; 419 420 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_STATUS, 0, NULL, 421 0, false, &resp_msg, sizeof(u8)); 422 if (status) 423 dev_err(&hdev->pdev->dev, 424 "VF failed to fetch link status(%d) from PF", status); 425 } 426 427 void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state) 428 { 429 struct hnae3_handle *rhandle = &hdev->roce; 430 struct hnae3_handle *handle = &hdev->nic; 431 struct hnae3_client *rclient; 432 struct hnae3_client *client; 433 434 client = handle->client; 435 rclient = hdev->roce_client; 436 437 link_state = 438 test_bit(HCLGEVF_STATE_DOWN, &hdev->state) ? 0 : link_state; 439 440 if (link_state != hdev->hw.mac.link) { 441 client->ops->link_status_change(handle, !!link_state); 442 if (rclient && rclient->ops->link_status_change) 443 rclient->ops->link_status_change(rhandle, !!link_state); 444 hdev->hw.mac.link = link_state; 445 } 446 } 447 448 static void hclgevf_update_link_mode(struct hclgevf_dev *hdev) 449 { 450 #define HCLGEVF_ADVERTISING 0 451 #define HCLGEVF_SUPPORTED 1 452 u8 send_msg; 453 u8 resp_msg; 454 455 send_msg = HCLGEVF_ADVERTISING; 456 hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_MODE, 0, &send_msg, 457 sizeof(u8), false, &resp_msg, sizeof(u8)); 458 send_msg = HCLGEVF_SUPPORTED; 459 hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_MODE, 0, &send_msg, 460 sizeof(u8), false, &resp_msg, sizeof(u8)); 461 } 462 463 static int hclgevf_set_handle_info(struct hclgevf_dev *hdev) 464 { 465 struct hnae3_handle *nic = &hdev->nic; 466 int ret; 467 468 nic->ae_algo = &ae_algovf; 469 nic->pdev = hdev->pdev; 470 nic->numa_node_mask = hdev->numa_node_mask; 471 nic->flags |= HNAE3_SUPPORT_VF; 472 473 ret = hclgevf_knic_setup(hdev); 474 if (ret) 475 dev_err(&hdev->pdev->dev, "VF knic setup failed %d\n", 476 ret); 477 return ret; 478 } 479 480 static void hclgevf_free_vector(struct hclgevf_dev *hdev, int vector_id) 481 { 482 if (hdev->vector_status[vector_id] == HCLGEVF_INVALID_VPORT) { 483 dev_warn(&hdev->pdev->dev, 484 "vector(vector_id %d) has been freed.\n", vector_id); 485 return; 486 } 487 488 hdev->vector_status[vector_id] = HCLGEVF_INVALID_VPORT; 489 hdev->num_msi_left += 1; 490 hdev->num_msi_used -= 1; 491 } 492 493 static int hclgevf_get_vector(struct hnae3_handle *handle, u16 vector_num, 494 struct hnae3_vector_info *vector_info) 495 { 496 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 497 struct hnae3_vector_info *vector = vector_info; 498 int alloc = 0; 499 int i, j; 500 501 vector_num = min(hdev->num_msi_left, vector_num); 502 503 for (j = 0; j < vector_num; j++) { 504 for (i = HCLGEVF_MISC_VECTOR_NUM + 1; i < hdev->num_msi; i++) { 505 if (hdev->vector_status[i] == HCLGEVF_INVALID_VPORT) { 506 vector->vector = pci_irq_vector(hdev->pdev, i); 507 vector->io_addr = hdev->hw.io_base + 508 HCLGEVF_VECTOR_REG_BASE + 509 (i - 1) * HCLGEVF_VECTOR_REG_OFFSET; 510 hdev->vector_status[i] = 0; 511 hdev->vector_irq[i] = vector->vector; 512 513 vector++; 514 alloc++; 515 516 break; 517 } 518 } 519 } 520 hdev->num_msi_left -= alloc; 521 hdev->num_msi_used += alloc; 522 523 return alloc; 524 } 525 526 static int hclgevf_get_vector_index(struct hclgevf_dev *hdev, int vector) 527 { 528 int i; 529 530 for (i = 0; i < hdev->num_msi; i++) 531 if (vector == hdev->vector_irq[i]) 532 return i; 533 534 return -EINVAL; 535 } 536 537 static int hclgevf_set_rss_algo_key(struct hclgevf_dev *hdev, 538 const u8 hfunc, const u8 *key) 539 { 540 struct hclgevf_rss_config_cmd *req; 541 struct hclgevf_desc desc; 542 int key_offset; 543 int key_size; 544 int ret; 545 546 req = (struct hclgevf_rss_config_cmd *)desc.data; 547 548 for (key_offset = 0; key_offset < 3; key_offset++) { 549 hclgevf_cmd_setup_basic_desc(&desc, 550 HCLGEVF_OPC_RSS_GENERIC_CONFIG, 551 false); 552 553 req->hash_config |= (hfunc & HCLGEVF_RSS_HASH_ALGO_MASK); 554 req->hash_config |= 555 (key_offset << HCLGEVF_RSS_HASH_KEY_OFFSET_B); 556 557 if (key_offset == 2) 558 key_size = 559 HCLGEVF_RSS_KEY_SIZE - HCLGEVF_RSS_HASH_KEY_NUM * 2; 560 else 561 key_size = HCLGEVF_RSS_HASH_KEY_NUM; 562 563 memcpy(req->hash_key, 564 key + key_offset * HCLGEVF_RSS_HASH_KEY_NUM, key_size); 565 566 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 567 if (ret) { 568 dev_err(&hdev->pdev->dev, 569 "Configure RSS config fail, status = %d\n", 570 ret); 571 return ret; 572 } 573 } 574 575 return 0; 576 } 577 578 static u32 hclgevf_get_rss_key_size(struct hnae3_handle *handle) 579 { 580 return HCLGEVF_RSS_KEY_SIZE; 581 } 582 583 static u32 hclgevf_get_rss_indir_size(struct hnae3_handle *handle) 584 { 585 return HCLGEVF_RSS_IND_TBL_SIZE; 586 } 587 588 static int hclgevf_set_rss_indir_table(struct hclgevf_dev *hdev) 589 { 590 const u8 *indir = hdev->rss_cfg.rss_indirection_tbl; 591 struct hclgevf_rss_indirection_table_cmd *req; 592 struct hclgevf_desc desc; 593 int status; 594 int i, j; 595 596 req = (struct hclgevf_rss_indirection_table_cmd *)desc.data; 597 598 for (i = 0; i < HCLGEVF_RSS_CFG_TBL_NUM; i++) { 599 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INDIR_TABLE, 600 false); 601 req->start_table_index = i * HCLGEVF_RSS_CFG_TBL_SIZE; 602 req->rss_set_bitmap = HCLGEVF_RSS_SET_BITMAP_MSK; 603 for (j = 0; j < HCLGEVF_RSS_CFG_TBL_SIZE; j++) 604 req->rss_result[j] = 605 indir[i * HCLGEVF_RSS_CFG_TBL_SIZE + j]; 606 607 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 608 if (status) { 609 dev_err(&hdev->pdev->dev, 610 "VF failed(=%d) to set RSS indirection table\n", 611 status); 612 return status; 613 } 614 } 615 616 return 0; 617 } 618 619 static int hclgevf_set_rss_tc_mode(struct hclgevf_dev *hdev, u16 rss_size) 620 { 621 struct hclgevf_rss_tc_mode_cmd *req; 622 u16 tc_offset[HCLGEVF_MAX_TC_NUM]; 623 u16 tc_valid[HCLGEVF_MAX_TC_NUM]; 624 u16 tc_size[HCLGEVF_MAX_TC_NUM]; 625 struct hclgevf_desc desc; 626 u16 roundup_size; 627 int status; 628 int i; 629 630 req = (struct hclgevf_rss_tc_mode_cmd *)desc.data; 631 632 roundup_size = roundup_pow_of_two(rss_size); 633 roundup_size = ilog2(roundup_size); 634 635 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 636 tc_valid[i] = !!(hdev->hw_tc_map & BIT(i)); 637 tc_size[i] = roundup_size; 638 tc_offset[i] = rss_size * i; 639 } 640 641 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_TC_MODE, false); 642 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 643 hnae3_set_bit(req->rss_tc_mode[i], HCLGEVF_RSS_TC_VALID_B, 644 (tc_valid[i] & 0x1)); 645 hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_SIZE_M, 646 HCLGEVF_RSS_TC_SIZE_S, tc_size[i]); 647 hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_OFFSET_M, 648 HCLGEVF_RSS_TC_OFFSET_S, tc_offset[i]); 649 } 650 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 651 if (status) 652 dev_err(&hdev->pdev->dev, 653 "VF failed(=%d) to set rss tc mode\n", status); 654 655 return status; 656 } 657 658 /* for revision 0x20, vf shared the same rss config with pf */ 659 static int hclgevf_get_rss_hash_key(struct hclgevf_dev *hdev) 660 { 661 #define HCLGEVF_RSS_MBX_RESP_LEN 8 662 663 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 664 u8 resp_msg[HCLGEVF_RSS_MBX_RESP_LEN]; 665 u16 msg_num, hash_key_index; 666 u8 index; 667 int ret; 668 669 msg_num = (HCLGEVF_RSS_KEY_SIZE + HCLGEVF_RSS_MBX_RESP_LEN - 1) / 670 HCLGEVF_RSS_MBX_RESP_LEN; 671 for (index = 0; index < msg_num; index++) { 672 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_RSS_KEY, 0, 673 &index, sizeof(index), 674 true, resp_msg, 675 HCLGEVF_RSS_MBX_RESP_LEN); 676 if (ret) { 677 dev_err(&hdev->pdev->dev, 678 "VF get rss hash key from PF failed, ret=%d", 679 ret); 680 return ret; 681 } 682 683 hash_key_index = HCLGEVF_RSS_MBX_RESP_LEN * index; 684 if (index == msg_num - 1) 685 memcpy(&rss_cfg->rss_hash_key[hash_key_index], 686 &resp_msg[0], 687 HCLGEVF_RSS_KEY_SIZE - hash_key_index); 688 else 689 memcpy(&rss_cfg->rss_hash_key[hash_key_index], 690 &resp_msg[0], HCLGEVF_RSS_MBX_RESP_LEN); 691 } 692 693 return 0; 694 } 695 696 static int hclgevf_get_rss(struct hnae3_handle *handle, u32 *indir, u8 *key, 697 u8 *hfunc) 698 { 699 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 700 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 701 int i, ret; 702 703 if (handle->pdev->revision >= 0x21) { 704 /* Get hash algorithm */ 705 if (hfunc) { 706 switch (rss_cfg->hash_algo) { 707 case HCLGEVF_RSS_HASH_ALGO_TOEPLITZ: 708 *hfunc = ETH_RSS_HASH_TOP; 709 break; 710 case HCLGEVF_RSS_HASH_ALGO_SIMPLE: 711 *hfunc = ETH_RSS_HASH_XOR; 712 break; 713 default: 714 *hfunc = ETH_RSS_HASH_UNKNOWN; 715 break; 716 } 717 } 718 719 /* Get the RSS Key required by the user */ 720 if (key) 721 memcpy(key, rss_cfg->rss_hash_key, 722 HCLGEVF_RSS_KEY_SIZE); 723 } else { 724 if (hfunc) 725 *hfunc = ETH_RSS_HASH_TOP; 726 if (key) { 727 ret = hclgevf_get_rss_hash_key(hdev); 728 if (ret) 729 return ret; 730 memcpy(key, rss_cfg->rss_hash_key, 731 HCLGEVF_RSS_KEY_SIZE); 732 } 733 } 734 735 if (indir) 736 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 737 indir[i] = rss_cfg->rss_indirection_tbl[i]; 738 739 return 0; 740 } 741 742 static int hclgevf_set_rss(struct hnae3_handle *handle, const u32 *indir, 743 const u8 *key, const u8 hfunc) 744 { 745 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 746 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 747 int ret, i; 748 749 if (handle->pdev->revision >= 0x21) { 750 /* Set the RSS Hash Key if specififed by the user */ 751 if (key) { 752 switch (hfunc) { 753 case ETH_RSS_HASH_TOP: 754 rss_cfg->hash_algo = 755 HCLGEVF_RSS_HASH_ALGO_TOEPLITZ; 756 break; 757 case ETH_RSS_HASH_XOR: 758 rss_cfg->hash_algo = 759 HCLGEVF_RSS_HASH_ALGO_SIMPLE; 760 break; 761 case ETH_RSS_HASH_NO_CHANGE: 762 break; 763 default: 764 return -EINVAL; 765 } 766 767 ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 768 key); 769 if (ret) 770 return ret; 771 772 /* Update the shadow RSS key with user specified qids */ 773 memcpy(rss_cfg->rss_hash_key, key, 774 HCLGEVF_RSS_KEY_SIZE); 775 } 776 } 777 778 /* update the shadow RSS table with user specified qids */ 779 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 780 rss_cfg->rss_indirection_tbl[i] = indir[i]; 781 782 /* update the hardware */ 783 return hclgevf_set_rss_indir_table(hdev); 784 } 785 786 static u8 hclgevf_get_rss_hash_bits(struct ethtool_rxnfc *nfc) 787 { 788 u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGEVF_S_PORT_BIT : 0; 789 790 if (nfc->data & RXH_L4_B_2_3) 791 hash_sets |= HCLGEVF_D_PORT_BIT; 792 else 793 hash_sets &= ~HCLGEVF_D_PORT_BIT; 794 795 if (nfc->data & RXH_IP_SRC) 796 hash_sets |= HCLGEVF_S_IP_BIT; 797 else 798 hash_sets &= ~HCLGEVF_S_IP_BIT; 799 800 if (nfc->data & RXH_IP_DST) 801 hash_sets |= HCLGEVF_D_IP_BIT; 802 else 803 hash_sets &= ~HCLGEVF_D_IP_BIT; 804 805 if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW) 806 hash_sets |= HCLGEVF_V_TAG_BIT; 807 808 return hash_sets; 809 } 810 811 static int hclgevf_set_rss_tuple(struct hnae3_handle *handle, 812 struct ethtool_rxnfc *nfc) 813 { 814 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 815 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 816 struct hclgevf_rss_input_tuple_cmd *req; 817 struct hclgevf_desc desc; 818 u8 tuple_sets; 819 int ret; 820 821 if (handle->pdev->revision == 0x20) 822 return -EOPNOTSUPP; 823 824 if (nfc->data & 825 ~(RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3)) 826 return -EINVAL; 827 828 req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 829 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 830 831 req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 832 req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 833 req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 834 req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 835 req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 836 req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 837 req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 838 req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 839 840 tuple_sets = hclgevf_get_rss_hash_bits(nfc); 841 switch (nfc->flow_type) { 842 case TCP_V4_FLOW: 843 req->ipv4_tcp_en = tuple_sets; 844 break; 845 case TCP_V6_FLOW: 846 req->ipv6_tcp_en = tuple_sets; 847 break; 848 case UDP_V4_FLOW: 849 req->ipv4_udp_en = tuple_sets; 850 break; 851 case UDP_V6_FLOW: 852 req->ipv6_udp_en = tuple_sets; 853 break; 854 case SCTP_V4_FLOW: 855 req->ipv4_sctp_en = tuple_sets; 856 break; 857 case SCTP_V6_FLOW: 858 if ((nfc->data & RXH_L4_B_0_1) || 859 (nfc->data & RXH_L4_B_2_3)) 860 return -EINVAL; 861 862 req->ipv6_sctp_en = tuple_sets; 863 break; 864 case IPV4_FLOW: 865 req->ipv4_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 866 break; 867 case IPV6_FLOW: 868 req->ipv6_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 869 break; 870 default: 871 return -EINVAL; 872 } 873 874 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 875 if (ret) { 876 dev_err(&hdev->pdev->dev, 877 "Set rss tuple fail, status = %d\n", ret); 878 return ret; 879 } 880 881 rss_cfg->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en; 882 rss_cfg->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en; 883 rss_cfg->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en; 884 rss_cfg->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en; 885 rss_cfg->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en; 886 rss_cfg->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en; 887 rss_cfg->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en; 888 rss_cfg->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en; 889 return 0; 890 } 891 892 static int hclgevf_get_rss_tuple(struct hnae3_handle *handle, 893 struct ethtool_rxnfc *nfc) 894 { 895 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 896 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 897 u8 tuple_sets; 898 899 if (handle->pdev->revision == 0x20) 900 return -EOPNOTSUPP; 901 902 nfc->data = 0; 903 904 switch (nfc->flow_type) { 905 case TCP_V4_FLOW: 906 tuple_sets = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 907 break; 908 case UDP_V4_FLOW: 909 tuple_sets = rss_cfg->rss_tuple_sets.ipv4_udp_en; 910 break; 911 case TCP_V6_FLOW: 912 tuple_sets = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 913 break; 914 case UDP_V6_FLOW: 915 tuple_sets = rss_cfg->rss_tuple_sets.ipv6_udp_en; 916 break; 917 case SCTP_V4_FLOW: 918 tuple_sets = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 919 break; 920 case SCTP_V6_FLOW: 921 tuple_sets = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 922 break; 923 case IPV4_FLOW: 924 case IPV6_FLOW: 925 tuple_sets = HCLGEVF_S_IP_BIT | HCLGEVF_D_IP_BIT; 926 break; 927 default: 928 return -EINVAL; 929 } 930 931 if (!tuple_sets) 932 return 0; 933 934 if (tuple_sets & HCLGEVF_D_PORT_BIT) 935 nfc->data |= RXH_L4_B_2_3; 936 if (tuple_sets & HCLGEVF_S_PORT_BIT) 937 nfc->data |= RXH_L4_B_0_1; 938 if (tuple_sets & HCLGEVF_D_IP_BIT) 939 nfc->data |= RXH_IP_DST; 940 if (tuple_sets & HCLGEVF_S_IP_BIT) 941 nfc->data |= RXH_IP_SRC; 942 943 return 0; 944 } 945 946 static int hclgevf_set_rss_input_tuple(struct hclgevf_dev *hdev, 947 struct hclgevf_rss_cfg *rss_cfg) 948 { 949 struct hclgevf_rss_input_tuple_cmd *req; 950 struct hclgevf_desc desc; 951 int ret; 952 953 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 954 955 req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 956 957 req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 958 req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 959 req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 960 req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 961 req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 962 req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 963 req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 964 req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 965 966 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 967 if (ret) 968 dev_err(&hdev->pdev->dev, 969 "Configure rss input fail, status = %d\n", ret); 970 return ret; 971 } 972 973 static int hclgevf_get_tc_size(struct hnae3_handle *handle) 974 { 975 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 976 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 977 978 return rss_cfg->rss_size; 979 } 980 981 static int hclgevf_bind_ring_to_vector(struct hnae3_handle *handle, bool en, 982 int vector_id, 983 struct hnae3_ring_chain_node *ring_chain) 984 { 985 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 986 struct hnae3_ring_chain_node *node; 987 struct hclge_mbx_vf_to_pf_cmd *req; 988 struct hclgevf_desc desc; 989 int i = 0; 990 int status; 991 u8 type; 992 993 req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data; 994 995 for (node = ring_chain; node; node = node->next) { 996 int idx_offset = HCLGE_MBX_RING_MAP_BASIC_MSG_NUM + 997 HCLGE_MBX_RING_NODE_VARIABLE_NUM * i; 998 999 if (i == 0) { 1000 hclgevf_cmd_setup_basic_desc(&desc, 1001 HCLGEVF_OPC_MBX_VF_TO_PF, 1002 false); 1003 type = en ? 1004 HCLGE_MBX_MAP_RING_TO_VECTOR : 1005 HCLGE_MBX_UNMAP_RING_TO_VECTOR; 1006 req->msg[0] = type; 1007 req->msg[1] = vector_id; 1008 } 1009 1010 req->msg[idx_offset] = 1011 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B); 1012 req->msg[idx_offset + 1] = node->tqp_index; 1013 req->msg[idx_offset + 2] = hnae3_get_field(node->int_gl_idx, 1014 HNAE3_RING_GL_IDX_M, 1015 HNAE3_RING_GL_IDX_S); 1016 1017 i++; 1018 if ((i == (HCLGE_MBX_VF_MSG_DATA_NUM - 1019 HCLGE_MBX_RING_MAP_BASIC_MSG_NUM) / 1020 HCLGE_MBX_RING_NODE_VARIABLE_NUM) || 1021 !node->next) { 1022 req->msg[2] = i; 1023 1024 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1025 if (status) { 1026 dev_err(&hdev->pdev->dev, 1027 "Map TQP fail, status is %d.\n", 1028 status); 1029 return status; 1030 } 1031 i = 0; 1032 hclgevf_cmd_setup_basic_desc(&desc, 1033 HCLGEVF_OPC_MBX_VF_TO_PF, 1034 false); 1035 req->msg[0] = type; 1036 req->msg[1] = vector_id; 1037 } 1038 } 1039 1040 return 0; 1041 } 1042 1043 static int hclgevf_map_ring_to_vector(struct hnae3_handle *handle, int vector, 1044 struct hnae3_ring_chain_node *ring_chain) 1045 { 1046 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1047 int vector_id; 1048 1049 vector_id = hclgevf_get_vector_index(hdev, vector); 1050 if (vector_id < 0) { 1051 dev_err(&handle->pdev->dev, 1052 "Get vector index fail. ret =%d\n", vector_id); 1053 return vector_id; 1054 } 1055 1056 return hclgevf_bind_ring_to_vector(handle, true, vector_id, ring_chain); 1057 } 1058 1059 static int hclgevf_unmap_ring_from_vector( 1060 struct hnae3_handle *handle, 1061 int vector, 1062 struct hnae3_ring_chain_node *ring_chain) 1063 { 1064 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1065 int ret, vector_id; 1066 1067 if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 1068 return 0; 1069 1070 vector_id = hclgevf_get_vector_index(hdev, vector); 1071 if (vector_id < 0) { 1072 dev_err(&handle->pdev->dev, 1073 "Get vector index fail. ret =%d\n", vector_id); 1074 return vector_id; 1075 } 1076 1077 ret = hclgevf_bind_ring_to_vector(handle, false, vector_id, ring_chain); 1078 if (ret) 1079 dev_err(&handle->pdev->dev, 1080 "Unmap ring from vector fail. vector=%d, ret =%d\n", 1081 vector_id, 1082 ret); 1083 1084 return ret; 1085 } 1086 1087 static int hclgevf_put_vector(struct hnae3_handle *handle, int vector) 1088 { 1089 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1090 int vector_id; 1091 1092 vector_id = hclgevf_get_vector_index(hdev, vector); 1093 if (vector_id < 0) { 1094 dev_err(&handle->pdev->dev, 1095 "hclgevf_put_vector get vector index fail. ret =%d\n", 1096 vector_id); 1097 return vector_id; 1098 } 1099 1100 hclgevf_free_vector(hdev, vector_id); 1101 1102 return 0; 1103 } 1104 1105 static int hclgevf_cmd_set_promisc_mode(struct hclgevf_dev *hdev, 1106 bool en_bc_pmc) 1107 { 1108 struct hclge_mbx_vf_to_pf_cmd *req; 1109 struct hclgevf_desc desc; 1110 int ret; 1111 1112 req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data; 1113 1114 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_MBX_VF_TO_PF, false); 1115 req->msg[0] = HCLGE_MBX_SET_PROMISC_MODE; 1116 req->msg[1] = en_bc_pmc ? 1 : 0; 1117 1118 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1119 if (ret) 1120 dev_err(&hdev->pdev->dev, 1121 "Set promisc mode fail, status is %d.\n", ret); 1122 1123 return ret; 1124 } 1125 1126 static int hclgevf_set_promisc_mode(struct hclgevf_dev *hdev, bool en_bc_pmc) 1127 { 1128 return hclgevf_cmd_set_promisc_mode(hdev, en_bc_pmc); 1129 } 1130 1131 static int hclgevf_tqp_enable(struct hclgevf_dev *hdev, int tqp_id, 1132 int stream_id, bool enable) 1133 { 1134 struct hclgevf_cfg_com_tqp_queue_cmd *req; 1135 struct hclgevf_desc desc; 1136 int status; 1137 1138 req = (struct hclgevf_cfg_com_tqp_queue_cmd *)desc.data; 1139 1140 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_CFG_COM_TQP_QUEUE, 1141 false); 1142 req->tqp_id = cpu_to_le16(tqp_id & HCLGEVF_RING_ID_MASK); 1143 req->stream_id = cpu_to_le16(stream_id); 1144 req->enable |= enable << HCLGEVF_TQP_ENABLE_B; 1145 1146 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1147 if (status) 1148 dev_err(&hdev->pdev->dev, 1149 "TQP enable fail, status =%d.\n", status); 1150 1151 return status; 1152 } 1153 1154 static void hclgevf_reset_tqp_stats(struct hnae3_handle *handle) 1155 { 1156 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 1157 struct hclgevf_tqp *tqp; 1158 int i; 1159 1160 for (i = 0; i < kinfo->num_tqps; i++) { 1161 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 1162 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats)); 1163 } 1164 } 1165 1166 static void hclgevf_get_mac_addr(struct hnae3_handle *handle, u8 *p) 1167 { 1168 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1169 1170 ether_addr_copy(p, hdev->hw.mac.mac_addr); 1171 } 1172 1173 static int hclgevf_set_mac_addr(struct hnae3_handle *handle, void *p, 1174 bool is_first) 1175 { 1176 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1177 u8 *old_mac_addr = (u8 *)hdev->hw.mac.mac_addr; 1178 u8 *new_mac_addr = (u8 *)p; 1179 u8 msg_data[ETH_ALEN * 2]; 1180 u16 subcode; 1181 int status; 1182 1183 ether_addr_copy(msg_data, new_mac_addr); 1184 ether_addr_copy(&msg_data[ETH_ALEN], old_mac_addr); 1185 1186 subcode = is_first ? HCLGE_MBX_MAC_VLAN_UC_ADD : 1187 HCLGE_MBX_MAC_VLAN_UC_MODIFY; 1188 1189 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 1190 subcode, msg_data, ETH_ALEN * 2, 1191 true, NULL, 0); 1192 if (!status) 1193 ether_addr_copy(hdev->hw.mac.mac_addr, new_mac_addr); 1194 1195 return status; 1196 } 1197 1198 static int hclgevf_add_uc_addr(struct hnae3_handle *handle, 1199 const unsigned char *addr) 1200 { 1201 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1202 1203 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 1204 HCLGE_MBX_MAC_VLAN_UC_ADD, 1205 addr, ETH_ALEN, false, NULL, 0); 1206 } 1207 1208 static int hclgevf_rm_uc_addr(struct hnae3_handle *handle, 1209 const unsigned char *addr) 1210 { 1211 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1212 1213 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 1214 HCLGE_MBX_MAC_VLAN_UC_REMOVE, 1215 addr, ETH_ALEN, false, NULL, 0); 1216 } 1217 1218 static int hclgevf_add_mc_addr(struct hnae3_handle *handle, 1219 const unsigned char *addr) 1220 { 1221 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1222 1223 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 1224 HCLGE_MBX_MAC_VLAN_MC_ADD, 1225 addr, ETH_ALEN, false, NULL, 0); 1226 } 1227 1228 static int hclgevf_rm_mc_addr(struct hnae3_handle *handle, 1229 const unsigned char *addr) 1230 { 1231 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1232 1233 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 1234 HCLGE_MBX_MAC_VLAN_MC_REMOVE, 1235 addr, ETH_ALEN, false, NULL, 0); 1236 } 1237 1238 static int hclgevf_set_vlan_filter(struct hnae3_handle *handle, 1239 __be16 proto, u16 vlan_id, 1240 bool is_kill) 1241 { 1242 #define HCLGEVF_VLAN_MBX_MSG_LEN 5 1243 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1244 u8 msg_data[HCLGEVF_VLAN_MBX_MSG_LEN]; 1245 1246 if (vlan_id > 4095) 1247 return -EINVAL; 1248 1249 if (proto != htons(ETH_P_8021Q)) 1250 return -EPROTONOSUPPORT; 1251 1252 msg_data[0] = is_kill; 1253 memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id)); 1254 memcpy(&msg_data[3], &proto, sizeof(proto)); 1255 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 1256 HCLGE_MBX_VLAN_FILTER, msg_data, 1257 HCLGEVF_VLAN_MBX_MSG_LEN, false, NULL, 0); 1258 } 1259 1260 static int hclgevf_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) 1261 { 1262 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1263 u8 msg_data; 1264 1265 msg_data = enable ? 1 : 0; 1266 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 1267 HCLGE_MBX_VLAN_RX_OFF_CFG, &msg_data, 1268 1, false, NULL, 0); 1269 } 1270 1271 static int hclgevf_reset_tqp(struct hnae3_handle *handle, u16 queue_id) 1272 { 1273 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1274 u8 msg_data[2]; 1275 int ret; 1276 1277 memcpy(&msg_data[0], &queue_id, sizeof(queue_id)); 1278 1279 /* disable vf queue before send queue reset msg to PF */ 1280 ret = hclgevf_tqp_enable(hdev, queue_id, 0, false); 1281 if (ret) 1282 return ret; 1283 1284 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_QUEUE_RESET, 0, msg_data, 1285 2, true, NULL, 0); 1286 } 1287 1288 static int hclgevf_set_mtu(struct hnae3_handle *handle, int new_mtu) 1289 { 1290 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1291 1292 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MTU, 0, (u8 *)&new_mtu, 1293 sizeof(new_mtu), true, NULL, 0); 1294 } 1295 1296 static int hclgevf_notify_client(struct hclgevf_dev *hdev, 1297 enum hnae3_reset_notify_type type) 1298 { 1299 struct hnae3_client *client = hdev->nic_client; 1300 struct hnae3_handle *handle = &hdev->nic; 1301 int ret; 1302 1303 if (!test_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state) || 1304 !client) 1305 return 0; 1306 1307 if (!client->ops->reset_notify) 1308 return -EOPNOTSUPP; 1309 1310 ret = client->ops->reset_notify(handle, type); 1311 if (ret) 1312 dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n", 1313 type, ret); 1314 1315 return ret; 1316 } 1317 1318 static void hclgevf_flr_done(struct hnae3_ae_dev *ae_dev) 1319 { 1320 struct hclgevf_dev *hdev = ae_dev->priv; 1321 1322 set_bit(HNAE3_FLR_DONE, &hdev->flr_state); 1323 } 1324 1325 static int hclgevf_flr_poll_timeout(struct hclgevf_dev *hdev, 1326 unsigned long delay_us, 1327 unsigned long wait_cnt) 1328 { 1329 unsigned long cnt = 0; 1330 1331 while (!test_bit(HNAE3_FLR_DONE, &hdev->flr_state) && 1332 cnt++ < wait_cnt) 1333 usleep_range(delay_us, delay_us * 2); 1334 1335 if (!test_bit(HNAE3_FLR_DONE, &hdev->flr_state)) { 1336 dev_err(&hdev->pdev->dev, 1337 "flr wait timeout\n"); 1338 return -ETIMEDOUT; 1339 } 1340 1341 return 0; 1342 } 1343 1344 static int hclgevf_reset_wait(struct hclgevf_dev *hdev) 1345 { 1346 #define HCLGEVF_RESET_WAIT_US 20000 1347 #define HCLGEVF_RESET_WAIT_CNT 2000 1348 #define HCLGEVF_RESET_WAIT_TIMEOUT_US \ 1349 (HCLGEVF_RESET_WAIT_US * HCLGEVF_RESET_WAIT_CNT) 1350 1351 u32 val; 1352 int ret; 1353 1354 /* wait to check the hardware reset completion status */ 1355 val = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 1356 dev_info(&hdev->pdev->dev, "checking vf resetting status: %x\n", val); 1357 1358 if (hdev->reset_type == HNAE3_FLR_RESET) 1359 return hclgevf_flr_poll_timeout(hdev, 1360 HCLGEVF_RESET_WAIT_US, 1361 HCLGEVF_RESET_WAIT_CNT); 1362 1363 ret = readl_poll_timeout(hdev->hw.io_base + HCLGEVF_RST_ING, val, 1364 !(val & HCLGEVF_RST_ING_BITS), 1365 HCLGEVF_RESET_WAIT_US, 1366 HCLGEVF_RESET_WAIT_TIMEOUT_US); 1367 1368 /* hardware completion status should be available by this time */ 1369 if (ret) { 1370 dev_err(&hdev->pdev->dev, 1371 "could'nt get reset done status from h/w, timeout!\n"); 1372 return ret; 1373 } 1374 1375 /* we will wait a bit more to let reset of the stack to complete. This 1376 * might happen in case reset assertion was made by PF. Yes, this also 1377 * means we might end up waiting bit more even for VF reset. 1378 */ 1379 msleep(5000); 1380 1381 return 0; 1382 } 1383 1384 static int hclgevf_reset_stack(struct hclgevf_dev *hdev) 1385 { 1386 int ret; 1387 1388 /* uninitialize the nic client */ 1389 ret = hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT); 1390 if (ret) 1391 return ret; 1392 1393 /* re-initialize the hclge device */ 1394 ret = hclgevf_reset_hdev(hdev); 1395 if (ret) { 1396 dev_err(&hdev->pdev->dev, 1397 "hclge device re-init failed, VF is disabled!\n"); 1398 return ret; 1399 } 1400 1401 /* bring up the nic client again */ 1402 ret = hclgevf_notify_client(hdev, HNAE3_INIT_CLIENT); 1403 if (ret) 1404 return ret; 1405 1406 return hclgevf_notify_client(hdev, HNAE3_RESTORE_CLIENT); 1407 } 1408 1409 static int hclgevf_reset_prepare_wait(struct hclgevf_dev *hdev) 1410 { 1411 #define HCLGEVF_RESET_SYNC_TIME 100 1412 1413 int ret = 0; 1414 1415 switch (hdev->reset_type) { 1416 case HNAE3_VF_FUNC_RESET: 1417 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_RESET, 0, NULL, 1418 0, true, NULL, sizeof(u8)); 1419 hdev->rst_stats.vf_func_rst_cnt++; 1420 break; 1421 case HNAE3_FLR_RESET: 1422 set_bit(HNAE3_FLR_DOWN, &hdev->flr_state); 1423 hdev->rst_stats.flr_rst_cnt++; 1424 break; 1425 default: 1426 break; 1427 } 1428 1429 set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 1430 /* inform hardware that preparatory work is done */ 1431 msleep(HCLGEVF_RESET_SYNC_TIME); 1432 hclgevf_write_dev(&hdev->hw, HCLGEVF_NIC_CSQ_DEPTH_REG, 1433 HCLGEVF_NIC_CMQ_ENABLE); 1434 dev_info(&hdev->pdev->dev, "prepare reset(%d) wait done, ret:%d\n", 1435 hdev->reset_type, ret); 1436 1437 return ret; 1438 } 1439 1440 static int hclgevf_reset(struct hclgevf_dev *hdev) 1441 { 1442 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1443 int ret; 1444 1445 /* Initialize ae_dev reset status as well, in case enet layer wants to 1446 * know if device is undergoing reset 1447 */ 1448 ae_dev->reset_type = hdev->reset_type; 1449 hdev->rst_stats.rst_cnt++; 1450 rtnl_lock(); 1451 1452 /* bring down the nic to stop any ongoing TX/RX */ 1453 ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 1454 if (ret) 1455 goto err_reset_lock; 1456 1457 rtnl_unlock(); 1458 1459 ret = hclgevf_reset_prepare_wait(hdev); 1460 if (ret) 1461 goto err_reset; 1462 1463 /* check if VF could successfully fetch the hardware reset completion 1464 * status from the hardware 1465 */ 1466 ret = hclgevf_reset_wait(hdev); 1467 if (ret) { 1468 /* can't do much in this situation, will disable VF */ 1469 dev_err(&hdev->pdev->dev, 1470 "VF failed(=%d) to fetch H/W reset completion status\n", 1471 ret); 1472 goto err_reset; 1473 } 1474 1475 hdev->rst_stats.hw_rst_done_cnt++; 1476 1477 rtnl_lock(); 1478 1479 /* now, re-initialize the nic client and ae device*/ 1480 ret = hclgevf_reset_stack(hdev); 1481 if (ret) { 1482 dev_err(&hdev->pdev->dev, "failed to reset VF stack\n"); 1483 goto err_reset_lock; 1484 } 1485 1486 /* bring up the nic to enable TX/RX again */ 1487 ret = hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 1488 if (ret) 1489 goto err_reset_lock; 1490 1491 rtnl_unlock(); 1492 1493 hdev->last_reset_time = jiffies; 1494 ae_dev->reset_type = HNAE3_NONE_RESET; 1495 hdev->rst_stats.rst_done_cnt++; 1496 1497 return ret; 1498 err_reset_lock: 1499 rtnl_unlock(); 1500 err_reset: 1501 /* When VF reset failed, only the higher level reset asserted by PF 1502 * can restore it, so re-initialize the command queue to receive 1503 * this higher reset event. 1504 */ 1505 hclgevf_cmd_init(hdev); 1506 dev_err(&hdev->pdev->dev, "failed to reset VF\n"); 1507 if (hclgevf_is_reset_pending(hdev)) 1508 hclgevf_reset_task_schedule(hdev); 1509 1510 return ret; 1511 } 1512 1513 static enum hnae3_reset_type hclgevf_get_reset_level(struct hclgevf_dev *hdev, 1514 unsigned long *addr) 1515 { 1516 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; 1517 1518 /* return the highest priority reset level amongst all */ 1519 if (test_bit(HNAE3_VF_RESET, addr)) { 1520 rst_level = HNAE3_VF_RESET; 1521 clear_bit(HNAE3_VF_RESET, addr); 1522 clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1523 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1524 } else if (test_bit(HNAE3_VF_FULL_RESET, addr)) { 1525 rst_level = HNAE3_VF_FULL_RESET; 1526 clear_bit(HNAE3_VF_FULL_RESET, addr); 1527 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1528 } else if (test_bit(HNAE3_VF_PF_FUNC_RESET, addr)) { 1529 rst_level = HNAE3_VF_PF_FUNC_RESET; 1530 clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1531 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1532 } else if (test_bit(HNAE3_VF_FUNC_RESET, addr)) { 1533 rst_level = HNAE3_VF_FUNC_RESET; 1534 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1535 } else if (test_bit(HNAE3_FLR_RESET, addr)) { 1536 rst_level = HNAE3_FLR_RESET; 1537 clear_bit(HNAE3_FLR_RESET, addr); 1538 } 1539 1540 return rst_level; 1541 } 1542 1543 static void hclgevf_reset_event(struct pci_dev *pdev, 1544 struct hnae3_handle *handle) 1545 { 1546 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 1547 struct hclgevf_dev *hdev = ae_dev->priv; 1548 1549 dev_info(&hdev->pdev->dev, "received reset request from VF enet\n"); 1550 1551 if (hdev->default_reset_request) 1552 hdev->reset_level = 1553 hclgevf_get_reset_level(hdev, 1554 &hdev->default_reset_request); 1555 else 1556 hdev->reset_level = HNAE3_VF_FUNC_RESET; 1557 1558 /* reset of this VF requested */ 1559 set_bit(HCLGEVF_RESET_REQUESTED, &hdev->reset_state); 1560 hclgevf_reset_task_schedule(hdev); 1561 1562 hdev->last_reset_time = jiffies; 1563 } 1564 1565 static void hclgevf_set_def_reset_request(struct hnae3_ae_dev *ae_dev, 1566 enum hnae3_reset_type rst_type) 1567 { 1568 struct hclgevf_dev *hdev = ae_dev->priv; 1569 1570 set_bit(rst_type, &hdev->default_reset_request); 1571 } 1572 1573 static void hclgevf_flr_prepare(struct hnae3_ae_dev *ae_dev) 1574 { 1575 #define HCLGEVF_FLR_WAIT_MS 100 1576 #define HCLGEVF_FLR_WAIT_CNT 50 1577 struct hclgevf_dev *hdev = ae_dev->priv; 1578 int cnt = 0; 1579 1580 clear_bit(HNAE3_FLR_DOWN, &hdev->flr_state); 1581 clear_bit(HNAE3_FLR_DONE, &hdev->flr_state); 1582 set_bit(HNAE3_FLR_RESET, &hdev->default_reset_request); 1583 hclgevf_reset_event(hdev->pdev, NULL); 1584 1585 while (!test_bit(HNAE3_FLR_DOWN, &hdev->flr_state) && 1586 cnt++ < HCLGEVF_FLR_WAIT_CNT) 1587 msleep(HCLGEVF_FLR_WAIT_MS); 1588 1589 if (!test_bit(HNAE3_FLR_DOWN, &hdev->flr_state)) 1590 dev_err(&hdev->pdev->dev, 1591 "flr wait down timeout: %d\n", cnt); 1592 } 1593 1594 static u32 hclgevf_get_fw_version(struct hnae3_handle *handle) 1595 { 1596 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1597 1598 return hdev->fw_version; 1599 } 1600 1601 static void hclgevf_get_misc_vector(struct hclgevf_dev *hdev) 1602 { 1603 struct hclgevf_misc_vector *vector = &hdev->misc_vector; 1604 1605 vector->vector_irq = pci_irq_vector(hdev->pdev, 1606 HCLGEVF_MISC_VECTOR_NUM); 1607 vector->addr = hdev->hw.io_base + HCLGEVF_MISC_VECTOR_REG_BASE; 1608 /* vector status always valid for Vector 0 */ 1609 hdev->vector_status[HCLGEVF_MISC_VECTOR_NUM] = 0; 1610 hdev->vector_irq[HCLGEVF_MISC_VECTOR_NUM] = vector->vector_irq; 1611 1612 hdev->num_msi_left -= 1; 1613 hdev->num_msi_used += 1; 1614 } 1615 1616 void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev) 1617 { 1618 if (!test_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state) && 1619 !test_bit(HCLGEVF_STATE_REMOVING, &hdev->state)) { 1620 set_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state); 1621 schedule_work(&hdev->rst_service_task); 1622 } 1623 } 1624 1625 void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev) 1626 { 1627 if (!test_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state) && 1628 !test_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) { 1629 set_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 1630 schedule_work(&hdev->mbx_service_task); 1631 } 1632 } 1633 1634 static void hclgevf_task_schedule(struct hclgevf_dev *hdev) 1635 { 1636 if (!test_bit(HCLGEVF_STATE_DOWN, &hdev->state) && 1637 !test_and_set_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state)) 1638 schedule_work(&hdev->service_task); 1639 } 1640 1641 static void hclgevf_deferred_task_schedule(struct hclgevf_dev *hdev) 1642 { 1643 /* if we have any pending mailbox event then schedule the mbx task */ 1644 if (hdev->mbx_event_pending) 1645 hclgevf_mbx_task_schedule(hdev); 1646 1647 if (test_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state)) 1648 hclgevf_reset_task_schedule(hdev); 1649 } 1650 1651 static void hclgevf_service_timer(struct timer_list *t) 1652 { 1653 struct hclgevf_dev *hdev = from_timer(hdev, t, service_timer); 1654 1655 mod_timer(&hdev->service_timer, jiffies + 5 * HZ); 1656 1657 hdev->stats_timer++; 1658 hclgevf_task_schedule(hdev); 1659 } 1660 1661 static void hclgevf_reset_service_task(struct work_struct *work) 1662 { 1663 struct hclgevf_dev *hdev = 1664 container_of(work, struct hclgevf_dev, rst_service_task); 1665 int ret; 1666 1667 if (test_and_set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 1668 return; 1669 1670 clear_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state); 1671 1672 if (test_and_clear_bit(HCLGEVF_RESET_PENDING, 1673 &hdev->reset_state)) { 1674 /* PF has initmated that it is about to reset the hardware. 1675 * We now have to poll & check if harware has actually completed 1676 * the reset sequence. On hardware reset completion, VF needs to 1677 * reset the client and ae device. 1678 */ 1679 hdev->reset_attempts = 0; 1680 1681 hdev->last_reset_time = jiffies; 1682 while ((hdev->reset_type = 1683 hclgevf_get_reset_level(hdev, &hdev->reset_pending)) 1684 != HNAE3_NONE_RESET) { 1685 ret = hclgevf_reset(hdev); 1686 if (ret) 1687 dev_err(&hdev->pdev->dev, 1688 "VF stack reset failed %d.\n", ret); 1689 } 1690 } else if (test_and_clear_bit(HCLGEVF_RESET_REQUESTED, 1691 &hdev->reset_state)) { 1692 /* we could be here when either of below happens: 1693 * 1. reset was initiated due to watchdog timeout due to 1694 * a. IMP was earlier reset and our TX got choked down and 1695 * which resulted in watchdog reacting and inducing VF 1696 * reset. This also means our cmdq would be unreliable. 1697 * b. problem in TX due to other lower layer(example link 1698 * layer not functioning properly etc.) 1699 * 2. VF reset might have been initiated due to some config 1700 * change. 1701 * 1702 * NOTE: Theres no clear way to detect above cases than to react 1703 * to the response of PF for this reset request. PF will ack the 1704 * 1b and 2. cases but we will not get any intimation about 1a 1705 * from PF as cmdq would be in unreliable state i.e. mailbox 1706 * communication between PF and VF would be broken. 1707 */ 1708 1709 /* if we are never geting into pending state it means either: 1710 * 1. PF is not receiving our request which could be due to IMP 1711 * reset 1712 * 2. PF is screwed 1713 * We cannot do much for 2. but to check first we can try reset 1714 * our PCIe + stack and see if it alleviates the problem. 1715 */ 1716 if (hdev->reset_attempts > 3) { 1717 /* prepare for full reset of stack + pcie interface */ 1718 set_bit(HNAE3_VF_FULL_RESET, &hdev->reset_pending); 1719 1720 /* "defer" schedule the reset task again */ 1721 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1722 } else { 1723 hdev->reset_attempts++; 1724 1725 set_bit(hdev->reset_level, &hdev->reset_pending); 1726 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1727 } 1728 hclgevf_reset_task_schedule(hdev); 1729 } 1730 1731 clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 1732 } 1733 1734 static void hclgevf_mailbox_service_task(struct work_struct *work) 1735 { 1736 struct hclgevf_dev *hdev; 1737 1738 hdev = container_of(work, struct hclgevf_dev, mbx_service_task); 1739 1740 if (test_and_set_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) 1741 return; 1742 1743 clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 1744 1745 hclgevf_mbx_async_handler(hdev); 1746 1747 clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 1748 } 1749 1750 static void hclgevf_keep_alive_timer(struct timer_list *t) 1751 { 1752 struct hclgevf_dev *hdev = from_timer(hdev, t, keep_alive_timer); 1753 1754 schedule_work(&hdev->keep_alive_task); 1755 mod_timer(&hdev->keep_alive_timer, jiffies + 2 * HZ); 1756 } 1757 1758 static void hclgevf_keep_alive_task(struct work_struct *work) 1759 { 1760 struct hclgevf_dev *hdev; 1761 u8 respmsg; 1762 int ret; 1763 1764 hdev = container_of(work, struct hclgevf_dev, keep_alive_task); 1765 1766 if (test_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state)) 1767 return; 1768 1769 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_KEEP_ALIVE, 0, NULL, 1770 0, false, &respmsg, sizeof(u8)); 1771 if (ret) 1772 dev_err(&hdev->pdev->dev, 1773 "VF sends keep alive cmd failed(=%d)\n", ret); 1774 } 1775 1776 static void hclgevf_service_task(struct work_struct *work) 1777 { 1778 struct hnae3_handle *handle; 1779 struct hclgevf_dev *hdev; 1780 1781 hdev = container_of(work, struct hclgevf_dev, service_task); 1782 handle = &hdev->nic; 1783 1784 if (hdev->stats_timer >= HCLGEVF_STATS_TIMER_INTERVAL) { 1785 hclgevf_tqps_update_stats(handle); 1786 hdev->stats_timer = 0; 1787 } 1788 1789 /* request the link status from the PF. PF would be able to tell VF 1790 * about such updates in future so we might remove this later 1791 */ 1792 hclgevf_request_link_info(hdev); 1793 1794 hclgevf_update_link_mode(hdev); 1795 1796 hclgevf_deferred_task_schedule(hdev); 1797 1798 clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 1799 } 1800 1801 static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regclr) 1802 { 1803 hclgevf_write_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_SRC_REG, regclr); 1804 } 1805 1806 static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev, 1807 u32 *clearval) 1808 { 1809 u32 cmdq_src_reg, rst_ing_reg; 1810 1811 /* fetch the events from their corresponding regs */ 1812 cmdq_src_reg = hclgevf_read_dev(&hdev->hw, 1813 HCLGEVF_VECTOR0_CMDQ_SRC_REG); 1814 1815 if (BIT(HCLGEVF_VECTOR0_RST_INT_B) & cmdq_src_reg) { 1816 rst_ing_reg = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 1817 dev_info(&hdev->pdev->dev, 1818 "receive reset interrupt 0x%x!\n", rst_ing_reg); 1819 set_bit(HNAE3_VF_RESET, &hdev->reset_pending); 1820 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1821 set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 1822 cmdq_src_reg &= ~BIT(HCLGEVF_VECTOR0_RST_INT_B); 1823 *clearval = cmdq_src_reg; 1824 hdev->rst_stats.vf_rst_cnt++; 1825 return HCLGEVF_VECTOR0_EVENT_RST; 1826 } 1827 1828 /* check for vector0 mailbox(=CMDQ RX) event source */ 1829 if (BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) { 1830 cmdq_src_reg &= ~BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 1831 *clearval = cmdq_src_reg; 1832 return HCLGEVF_VECTOR0_EVENT_MBX; 1833 } 1834 1835 dev_dbg(&hdev->pdev->dev, "vector 0 interrupt from unknown source\n"); 1836 1837 return HCLGEVF_VECTOR0_EVENT_OTHER; 1838 } 1839 1840 static void hclgevf_enable_vector(struct hclgevf_misc_vector *vector, bool en) 1841 { 1842 writel(en ? 1 : 0, vector->addr); 1843 } 1844 1845 static irqreturn_t hclgevf_misc_irq_handle(int irq, void *data) 1846 { 1847 enum hclgevf_evt_cause event_cause; 1848 struct hclgevf_dev *hdev = data; 1849 u32 clearval; 1850 1851 hclgevf_enable_vector(&hdev->misc_vector, false); 1852 event_cause = hclgevf_check_evt_cause(hdev, &clearval); 1853 1854 switch (event_cause) { 1855 case HCLGEVF_VECTOR0_EVENT_RST: 1856 hclgevf_reset_task_schedule(hdev); 1857 break; 1858 case HCLGEVF_VECTOR0_EVENT_MBX: 1859 hclgevf_mbx_handler(hdev); 1860 break; 1861 default: 1862 break; 1863 } 1864 1865 if (event_cause != HCLGEVF_VECTOR0_EVENT_OTHER) { 1866 hclgevf_clear_event_cause(hdev, clearval); 1867 hclgevf_enable_vector(&hdev->misc_vector, true); 1868 } 1869 1870 return IRQ_HANDLED; 1871 } 1872 1873 static int hclgevf_configure(struct hclgevf_dev *hdev) 1874 { 1875 int ret; 1876 1877 /* get current port based vlan state from PF */ 1878 ret = hclgevf_get_port_base_vlan_filter_state(hdev); 1879 if (ret) 1880 return ret; 1881 1882 /* get queue configuration from PF */ 1883 ret = hclgevf_get_queue_info(hdev); 1884 if (ret) 1885 return ret; 1886 1887 /* get queue depth info from PF */ 1888 ret = hclgevf_get_queue_depth(hdev); 1889 if (ret) 1890 return ret; 1891 1892 ret = hclgevf_get_pf_media_type(hdev); 1893 if (ret) 1894 return ret; 1895 1896 /* get tc configuration from PF */ 1897 return hclgevf_get_tc_info(hdev); 1898 } 1899 1900 static int hclgevf_alloc_hdev(struct hnae3_ae_dev *ae_dev) 1901 { 1902 struct pci_dev *pdev = ae_dev->pdev; 1903 struct hclgevf_dev *hdev; 1904 1905 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 1906 if (!hdev) 1907 return -ENOMEM; 1908 1909 hdev->pdev = pdev; 1910 hdev->ae_dev = ae_dev; 1911 ae_dev->priv = hdev; 1912 1913 return 0; 1914 } 1915 1916 static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev) 1917 { 1918 struct hnae3_handle *roce = &hdev->roce; 1919 struct hnae3_handle *nic = &hdev->nic; 1920 1921 roce->rinfo.num_vectors = hdev->num_roce_msix; 1922 1923 if (hdev->num_msi_left < roce->rinfo.num_vectors || 1924 hdev->num_msi_left == 0) 1925 return -EINVAL; 1926 1927 roce->rinfo.base_vector = hdev->roce_base_vector; 1928 1929 roce->rinfo.netdev = nic->kinfo.netdev; 1930 roce->rinfo.roce_io_base = hdev->hw.io_base; 1931 1932 roce->pdev = nic->pdev; 1933 roce->ae_algo = nic->ae_algo; 1934 roce->numa_node_mask = nic->numa_node_mask; 1935 1936 return 0; 1937 } 1938 1939 static int hclgevf_config_gro(struct hclgevf_dev *hdev, bool en) 1940 { 1941 struct hclgevf_cfg_gro_status_cmd *req; 1942 struct hclgevf_desc desc; 1943 int ret; 1944 1945 if (!hnae3_dev_gro_supported(hdev)) 1946 return 0; 1947 1948 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_GRO_GENERIC_CONFIG, 1949 false); 1950 req = (struct hclgevf_cfg_gro_status_cmd *)desc.data; 1951 1952 req->gro_en = cpu_to_le16(en ? 1 : 0); 1953 1954 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1955 if (ret) 1956 dev_err(&hdev->pdev->dev, 1957 "VF GRO hardware config cmd failed, ret = %d.\n", ret); 1958 1959 return ret; 1960 } 1961 1962 static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev) 1963 { 1964 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 1965 int i, ret; 1966 1967 rss_cfg->rss_size = hdev->rss_size_max; 1968 1969 if (hdev->pdev->revision >= 0x21) { 1970 rss_cfg->hash_algo = HCLGEVF_RSS_HASH_ALGO_SIMPLE; 1971 memcpy(rss_cfg->rss_hash_key, hclgevf_hash_key, 1972 HCLGEVF_RSS_KEY_SIZE); 1973 1974 ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 1975 rss_cfg->rss_hash_key); 1976 if (ret) 1977 return ret; 1978 1979 rss_cfg->rss_tuple_sets.ipv4_tcp_en = 1980 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1981 rss_cfg->rss_tuple_sets.ipv4_udp_en = 1982 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1983 rss_cfg->rss_tuple_sets.ipv4_sctp_en = 1984 HCLGEVF_RSS_INPUT_TUPLE_SCTP; 1985 rss_cfg->rss_tuple_sets.ipv4_fragment_en = 1986 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1987 rss_cfg->rss_tuple_sets.ipv6_tcp_en = 1988 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1989 rss_cfg->rss_tuple_sets.ipv6_udp_en = 1990 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1991 rss_cfg->rss_tuple_sets.ipv6_sctp_en = 1992 HCLGEVF_RSS_INPUT_TUPLE_SCTP; 1993 rss_cfg->rss_tuple_sets.ipv6_fragment_en = 1994 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1995 1996 ret = hclgevf_set_rss_input_tuple(hdev, rss_cfg); 1997 if (ret) 1998 return ret; 1999 2000 } 2001 2002 /* Initialize RSS indirect table for each vport */ 2003 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 2004 rss_cfg->rss_indirection_tbl[i] = i % hdev->rss_size_max; 2005 2006 ret = hclgevf_set_rss_indir_table(hdev); 2007 if (ret) 2008 return ret; 2009 2010 return hclgevf_set_rss_tc_mode(hdev, hdev->rss_size_max); 2011 } 2012 2013 static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev) 2014 { 2015 /* other vlan config(like, VLAN TX/RX offload) would also be added 2016 * here later 2017 */ 2018 return hclgevf_set_vlan_filter(&hdev->nic, htons(ETH_P_8021Q), 0, 2019 false); 2020 } 2021 2022 static void hclgevf_set_timer_task(struct hnae3_handle *handle, bool enable) 2023 { 2024 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2025 2026 if (enable) { 2027 mod_timer(&hdev->service_timer, jiffies + HZ); 2028 } else { 2029 del_timer_sync(&hdev->service_timer); 2030 cancel_work_sync(&hdev->service_task); 2031 clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 2032 } 2033 } 2034 2035 static int hclgevf_ae_start(struct hnae3_handle *handle) 2036 { 2037 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2038 2039 /* reset tqp stats */ 2040 hclgevf_reset_tqp_stats(handle); 2041 2042 hclgevf_request_link_info(hdev); 2043 2044 hclgevf_update_link_mode(hdev); 2045 2046 clear_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2047 2048 return 0; 2049 } 2050 2051 static void hclgevf_ae_stop(struct hnae3_handle *handle) 2052 { 2053 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2054 int i; 2055 2056 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2057 2058 if (hdev->reset_type != HNAE3_VF_RESET) 2059 for (i = 0; i < handle->kinfo.num_tqps; i++) 2060 if (hclgevf_reset_tqp(handle, i)) 2061 break; 2062 2063 /* reset tqp stats */ 2064 hclgevf_reset_tqp_stats(handle); 2065 hclgevf_update_link_status(hdev, 0); 2066 } 2067 2068 static int hclgevf_set_alive(struct hnae3_handle *handle, bool alive) 2069 { 2070 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2071 u8 msg_data; 2072 2073 msg_data = alive ? 1 : 0; 2074 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_ALIVE, 2075 0, &msg_data, 1, false, NULL, 0); 2076 } 2077 2078 static int hclgevf_client_start(struct hnae3_handle *handle) 2079 { 2080 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2081 int ret; 2082 2083 ret = hclgevf_set_alive(handle, true); 2084 if (ret) 2085 return ret; 2086 2087 mod_timer(&hdev->keep_alive_timer, jiffies + 2 * HZ); 2088 2089 return 0; 2090 } 2091 2092 static void hclgevf_client_stop(struct hnae3_handle *handle) 2093 { 2094 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2095 int ret; 2096 2097 ret = hclgevf_set_alive(handle, false); 2098 if (ret) 2099 dev_warn(&hdev->pdev->dev, 2100 "%s failed %d\n", __func__, ret); 2101 2102 del_timer_sync(&hdev->keep_alive_timer); 2103 cancel_work_sync(&hdev->keep_alive_task); 2104 } 2105 2106 static void hclgevf_state_init(struct hclgevf_dev *hdev) 2107 { 2108 /* setup tasks for the MBX */ 2109 INIT_WORK(&hdev->mbx_service_task, hclgevf_mailbox_service_task); 2110 clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 2111 clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 2112 2113 /* setup tasks for service timer */ 2114 timer_setup(&hdev->service_timer, hclgevf_service_timer, 0); 2115 2116 INIT_WORK(&hdev->service_task, hclgevf_service_task); 2117 clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 2118 2119 INIT_WORK(&hdev->rst_service_task, hclgevf_reset_service_task); 2120 2121 mutex_init(&hdev->mbx_resp.mbx_mutex); 2122 2123 /* bring the device down */ 2124 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2125 } 2126 2127 static void hclgevf_state_uninit(struct hclgevf_dev *hdev) 2128 { 2129 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2130 set_bit(HCLGEVF_STATE_REMOVING, &hdev->state); 2131 2132 if (hdev->keep_alive_timer.function) 2133 del_timer_sync(&hdev->keep_alive_timer); 2134 if (hdev->keep_alive_task.func) 2135 cancel_work_sync(&hdev->keep_alive_task); 2136 if (hdev->service_timer.function) 2137 del_timer_sync(&hdev->service_timer); 2138 if (hdev->service_task.func) 2139 cancel_work_sync(&hdev->service_task); 2140 if (hdev->mbx_service_task.func) 2141 cancel_work_sync(&hdev->mbx_service_task); 2142 if (hdev->rst_service_task.func) 2143 cancel_work_sync(&hdev->rst_service_task); 2144 2145 mutex_destroy(&hdev->mbx_resp.mbx_mutex); 2146 } 2147 2148 static int hclgevf_init_msi(struct hclgevf_dev *hdev) 2149 { 2150 struct pci_dev *pdev = hdev->pdev; 2151 int vectors; 2152 int i; 2153 2154 if (hnae3_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B)) 2155 vectors = pci_alloc_irq_vectors(pdev, 2156 hdev->roce_base_msix_offset + 1, 2157 hdev->num_msi, 2158 PCI_IRQ_MSIX); 2159 else 2160 vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi, 2161 PCI_IRQ_MSI | PCI_IRQ_MSIX); 2162 2163 if (vectors < 0) { 2164 dev_err(&pdev->dev, 2165 "failed(%d) to allocate MSI/MSI-X vectors\n", 2166 vectors); 2167 return vectors; 2168 } 2169 if (vectors < hdev->num_msi) 2170 dev_warn(&hdev->pdev->dev, 2171 "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n", 2172 hdev->num_msi, vectors); 2173 2174 hdev->num_msi = vectors; 2175 hdev->num_msi_left = vectors; 2176 hdev->base_msi_vector = pdev->irq; 2177 hdev->roce_base_vector = pdev->irq + hdev->roce_base_msix_offset; 2178 2179 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 2180 sizeof(u16), GFP_KERNEL); 2181 if (!hdev->vector_status) { 2182 pci_free_irq_vectors(pdev); 2183 return -ENOMEM; 2184 } 2185 2186 for (i = 0; i < hdev->num_msi; i++) 2187 hdev->vector_status[i] = HCLGEVF_INVALID_VPORT; 2188 2189 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 2190 sizeof(int), GFP_KERNEL); 2191 if (!hdev->vector_irq) { 2192 devm_kfree(&pdev->dev, hdev->vector_status); 2193 pci_free_irq_vectors(pdev); 2194 return -ENOMEM; 2195 } 2196 2197 return 0; 2198 } 2199 2200 static void hclgevf_uninit_msi(struct hclgevf_dev *hdev) 2201 { 2202 struct pci_dev *pdev = hdev->pdev; 2203 2204 devm_kfree(&pdev->dev, hdev->vector_status); 2205 devm_kfree(&pdev->dev, hdev->vector_irq); 2206 pci_free_irq_vectors(pdev); 2207 } 2208 2209 static int hclgevf_misc_irq_init(struct hclgevf_dev *hdev) 2210 { 2211 int ret = 0; 2212 2213 hclgevf_get_misc_vector(hdev); 2214 2215 ret = request_irq(hdev->misc_vector.vector_irq, hclgevf_misc_irq_handle, 2216 0, "hclgevf_cmd", hdev); 2217 if (ret) { 2218 dev_err(&hdev->pdev->dev, "VF failed to request misc irq(%d)\n", 2219 hdev->misc_vector.vector_irq); 2220 return ret; 2221 } 2222 2223 hclgevf_clear_event_cause(hdev, 0); 2224 2225 /* enable misc. vector(vector 0) */ 2226 hclgevf_enable_vector(&hdev->misc_vector, true); 2227 2228 return ret; 2229 } 2230 2231 static void hclgevf_misc_irq_uninit(struct hclgevf_dev *hdev) 2232 { 2233 /* disable misc vector(vector 0) */ 2234 hclgevf_enable_vector(&hdev->misc_vector, false); 2235 synchronize_irq(hdev->misc_vector.vector_irq); 2236 free_irq(hdev->misc_vector.vector_irq, hdev); 2237 hclgevf_free_vector(hdev, 0); 2238 } 2239 2240 static void hclgevf_info_show(struct hclgevf_dev *hdev) 2241 { 2242 struct device *dev = &hdev->pdev->dev; 2243 2244 dev_info(dev, "VF info begin:\n"); 2245 2246 dev_info(dev, "Task queue pairs numbers: %d\n", hdev->num_tqps); 2247 dev_info(dev, "Desc num per TX queue: %d\n", hdev->num_tx_desc); 2248 dev_info(dev, "Desc num per RX queue: %d\n", hdev->num_rx_desc); 2249 dev_info(dev, "Numbers of vports: %d\n", hdev->num_alloc_vport); 2250 dev_info(dev, "HW tc map: %d\n", hdev->hw_tc_map); 2251 dev_info(dev, "PF media type of this VF: %d\n", 2252 hdev->hw.mac.media_type); 2253 2254 dev_info(dev, "VF info end.\n"); 2255 } 2256 2257 static int hclgevf_init_nic_client_instance(struct hnae3_ae_dev *ae_dev, 2258 struct hnae3_client *client) 2259 { 2260 struct hclgevf_dev *hdev = ae_dev->priv; 2261 int ret; 2262 2263 ret = client->ops->init_instance(&hdev->nic); 2264 if (ret) 2265 return ret; 2266 2267 set_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 2268 hnae3_set_client_init_flag(client, ae_dev, 1); 2269 2270 if (netif_msg_drv(&hdev->nic)) 2271 hclgevf_info_show(hdev); 2272 2273 return 0; 2274 } 2275 2276 static int hclgevf_init_roce_client_instance(struct hnae3_ae_dev *ae_dev, 2277 struct hnae3_client *client) 2278 { 2279 struct hclgevf_dev *hdev = ae_dev->priv; 2280 int ret; 2281 2282 if (!hnae3_dev_roce_supported(hdev) || !hdev->roce_client || 2283 !hdev->nic_client) 2284 return 0; 2285 2286 ret = hclgevf_init_roce_base_info(hdev); 2287 if (ret) 2288 return ret; 2289 2290 ret = client->ops->init_instance(&hdev->roce); 2291 if (ret) 2292 return ret; 2293 2294 hnae3_set_client_init_flag(client, ae_dev, 1); 2295 2296 return 0; 2297 } 2298 2299 static int hclgevf_init_client_instance(struct hnae3_client *client, 2300 struct hnae3_ae_dev *ae_dev) 2301 { 2302 struct hclgevf_dev *hdev = ae_dev->priv; 2303 int ret; 2304 2305 switch (client->type) { 2306 case HNAE3_CLIENT_KNIC: 2307 hdev->nic_client = client; 2308 hdev->nic.client = client; 2309 2310 ret = hclgevf_init_nic_client_instance(ae_dev, client); 2311 if (ret) 2312 goto clear_nic; 2313 2314 ret = hclgevf_init_roce_client_instance(ae_dev, 2315 hdev->roce_client); 2316 if (ret) 2317 goto clear_roce; 2318 2319 break; 2320 case HNAE3_CLIENT_ROCE: 2321 if (hnae3_dev_roce_supported(hdev)) { 2322 hdev->roce_client = client; 2323 hdev->roce.client = client; 2324 } 2325 2326 ret = hclgevf_init_roce_client_instance(ae_dev, client); 2327 if (ret) 2328 goto clear_roce; 2329 2330 break; 2331 default: 2332 return -EINVAL; 2333 } 2334 2335 return 0; 2336 2337 clear_nic: 2338 hdev->nic_client = NULL; 2339 hdev->nic.client = NULL; 2340 return ret; 2341 clear_roce: 2342 hdev->roce_client = NULL; 2343 hdev->roce.client = NULL; 2344 return ret; 2345 } 2346 2347 static void hclgevf_uninit_client_instance(struct hnae3_client *client, 2348 struct hnae3_ae_dev *ae_dev) 2349 { 2350 struct hclgevf_dev *hdev = ae_dev->priv; 2351 2352 /* un-init roce, if it exists */ 2353 if (hdev->roce_client) { 2354 hdev->roce_client->ops->uninit_instance(&hdev->roce, 0); 2355 hdev->roce_client = NULL; 2356 hdev->roce.client = NULL; 2357 } 2358 2359 /* un-init nic/unic, if this was not called by roce client */ 2360 if (client->ops->uninit_instance && hdev->nic_client && 2361 client->type != HNAE3_CLIENT_ROCE) { 2362 clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 2363 2364 client->ops->uninit_instance(&hdev->nic, 0); 2365 hdev->nic_client = NULL; 2366 hdev->nic.client = NULL; 2367 } 2368 } 2369 2370 static int hclgevf_pci_init(struct hclgevf_dev *hdev) 2371 { 2372 struct pci_dev *pdev = hdev->pdev; 2373 struct hclgevf_hw *hw; 2374 int ret; 2375 2376 ret = pci_enable_device(pdev); 2377 if (ret) { 2378 dev_err(&pdev->dev, "failed to enable PCI device\n"); 2379 return ret; 2380 } 2381 2382 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 2383 if (ret) { 2384 dev_err(&pdev->dev, "can't set consistent PCI DMA, exiting"); 2385 goto err_disable_device; 2386 } 2387 2388 ret = pci_request_regions(pdev, HCLGEVF_DRIVER_NAME); 2389 if (ret) { 2390 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 2391 goto err_disable_device; 2392 } 2393 2394 pci_set_master(pdev); 2395 hw = &hdev->hw; 2396 hw->hdev = hdev; 2397 hw->io_base = pci_iomap(pdev, 2, 0); 2398 if (!hw->io_base) { 2399 dev_err(&pdev->dev, "can't map configuration register space\n"); 2400 ret = -ENOMEM; 2401 goto err_clr_master; 2402 } 2403 2404 return 0; 2405 2406 err_clr_master: 2407 pci_clear_master(pdev); 2408 pci_release_regions(pdev); 2409 err_disable_device: 2410 pci_disable_device(pdev); 2411 2412 return ret; 2413 } 2414 2415 static void hclgevf_pci_uninit(struct hclgevf_dev *hdev) 2416 { 2417 struct pci_dev *pdev = hdev->pdev; 2418 2419 pci_iounmap(pdev, hdev->hw.io_base); 2420 pci_clear_master(pdev); 2421 pci_release_regions(pdev); 2422 pci_disable_device(pdev); 2423 } 2424 2425 static int hclgevf_query_vf_resource(struct hclgevf_dev *hdev) 2426 { 2427 struct hclgevf_query_res_cmd *req; 2428 struct hclgevf_desc desc; 2429 int ret; 2430 2431 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_VF_RSRC, true); 2432 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 2433 if (ret) { 2434 dev_err(&hdev->pdev->dev, 2435 "query vf resource failed, ret = %d.\n", ret); 2436 return ret; 2437 } 2438 2439 req = (struct hclgevf_query_res_cmd *)desc.data; 2440 2441 if (hnae3_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B)) { 2442 hdev->roce_base_msix_offset = 2443 hnae3_get_field(__le16_to_cpu(req->msixcap_localid_ba_rocee), 2444 HCLGEVF_MSIX_OFT_ROCEE_M, 2445 HCLGEVF_MSIX_OFT_ROCEE_S); 2446 hdev->num_roce_msix = 2447 hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number), 2448 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 2449 2450 /* VF should have NIC vectors and Roce vectors, NIC vectors 2451 * are queued before Roce vectors. The offset is fixed to 64. 2452 */ 2453 hdev->num_msi = hdev->num_roce_msix + 2454 hdev->roce_base_msix_offset; 2455 } else { 2456 hdev->num_msi = 2457 hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number), 2458 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 2459 } 2460 2461 return 0; 2462 } 2463 2464 static int hclgevf_pci_reset(struct hclgevf_dev *hdev) 2465 { 2466 struct pci_dev *pdev = hdev->pdev; 2467 int ret = 0; 2468 2469 if (hdev->reset_type == HNAE3_VF_FULL_RESET && 2470 test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2471 hclgevf_misc_irq_uninit(hdev); 2472 hclgevf_uninit_msi(hdev); 2473 clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2474 } 2475 2476 if (!test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2477 pci_set_master(pdev); 2478 ret = hclgevf_init_msi(hdev); 2479 if (ret) { 2480 dev_err(&pdev->dev, 2481 "failed(%d) to init MSI/MSI-X\n", ret); 2482 return ret; 2483 } 2484 2485 ret = hclgevf_misc_irq_init(hdev); 2486 if (ret) { 2487 hclgevf_uninit_msi(hdev); 2488 dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 2489 ret); 2490 return ret; 2491 } 2492 2493 set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2494 } 2495 2496 return ret; 2497 } 2498 2499 static int hclgevf_reset_hdev(struct hclgevf_dev *hdev) 2500 { 2501 struct pci_dev *pdev = hdev->pdev; 2502 int ret; 2503 2504 ret = hclgevf_pci_reset(hdev); 2505 if (ret) { 2506 dev_err(&pdev->dev, "pci reset failed %d\n", ret); 2507 return ret; 2508 } 2509 2510 ret = hclgevf_cmd_init(hdev); 2511 if (ret) { 2512 dev_err(&pdev->dev, "cmd failed %d\n", ret); 2513 return ret; 2514 } 2515 2516 ret = hclgevf_rss_init_hw(hdev); 2517 if (ret) { 2518 dev_err(&hdev->pdev->dev, 2519 "failed(%d) to initialize RSS\n", ret); 2520 return ret; 2521 } 2522 2523 ret = hclgevf_config_gro(hdev, true); 2524 if (ret) 2525 return ret; 2526 2527 ret = hclgevf_init_vlan_config(hdev); 2528 if (ret) { 2529 dev_err(&hdev->pdev->dev, 2530 "failed(%d) to initialize VLAN config\n", ret); 2531 return ret; 2532 } 2533 2534 dev_info(&hdev->pdev->dev, "Reset done\n"); 2535 2536 return 0; 2537 } 2538 2539 static int hclgevf_init_hdev(struct hclgevf_dev *hdev) 2540 { 2541 struct pci_dev *pdev = hdev->pdev; 2542 int ret; 2543 2544 ret = hclgevf_pci_init(hdev); 2545 if (ret) { 2546 dev_err(&pdev->dev, "PCI initialization failed\n"); 2547 return ret; 2548 } 2549 2550 ret = hclgevf_cmd_queue_init(hdev); 2551 if (ret) { 2552 dev_err(&pdev->dev, "Cmd queue init failed: %d\n", ret); 2553 goto err_cmd_queue_init; 2554 } 2555 2556 ret = hclgevf_cmd_init(hdev); 2557 if (ret) 2558 goto err_cmd_init; 2559 2560 /* Get vf resource */ 2561 ret = hclgevf_query_vf_resource(hdev); 2562 if (ret) { 2563 dev_err(&hdev->pdev->dev, 2564 "Query vf status error, ret = %d.\n", ret); 2565 goto err_cmd_init; 2566 } 2567 2568 ret = hclgevf_init_msi(hdev); 2569 if (ret) { 2570 dev_err(&pdev->dev, "failed(%d) to init MSI/MSI-X\n", ret); 2571 goto err_cmd_init; 2572 } 2573 2574 hclgevf_state_init(hdev); 2575 hdev->reset_level = HNAE3_VF_FUNC_RESET; 2576 2577 ret = hclgevf_misc_irq_init(hdev); 2578 if (ret) { 2579 dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 2580 ret); 2581 goto err_misc_irq_init; 2582 } 2583 2584 set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2585 2586 ret = hclgevf_configure(hdev); 2587 if (ret) { 2588 dev_err(&pdev->dev, "failed(%d) to fetch configuration\n", ret); 2589 goto err_config; 2590 } 2591 2592 ret = hclgevf_alloc_tqps(hdev); 2593 if (ret) { 2594 dev_err(&pdev->dev, "failed(%d) to allocate TQPs\n", ret); 2595 goto err_config; 2596 } 2597 2598 ret = hclgevf_set_handle_info(hdev); 2599 if (ret) { 2600 dev_err(&pdev->dev, "failed(%d) to set handle info\n", ret); 2601 goto err_config; 2602 } 2603 2604 ret = hclgevf_config_gro(hdev, true); 2605 if (ret) 2606 goto err_config; 2607 2608 /* vf is not allowed to enable unicast/multicast promisc mode. 2609 * For revision 0x20, default to disable broadcast promisc mode, 2610 * firmware makes sure broadcast packets can be accepted. 2611 * For revision 0x21, default to enable broadcast promisc mode. 2612 */ 2613 ret = hclgevf_set_promisc_mode(hdev, true); 2614 if (ret) 2615 goto err_config; 2616 2617 /* Initialize RSS for this VF */ 2618 ret = hclgevf_rss_init_hw(hdev); 2619 if (ret) { 2620 dev_err(&hdev->pdev->dev, 2621 "failed(%d) to initialize RSS\n", ret); 2622 goto err_config; 2623 } 2624 2625 ret = hclgevf_init_vlan_config(hdev); 2626 if (ret) { 2627 dev_err(&hdev->pdev->dev, 2628 "failed(%d) to initialize VLAN config\n", ret); 2629 goto err_config; 2630 } 2631 2632 hdev->last_reset_time = jiffies; 2633 pr_info("finished initializing %s driver\n", HCLGEVF_DRIVER_NAME); 2634 2635 return 0; 2636 2637 err_config: 2638 hclgevf_misc_irq_uninit(hdev); 2639 err_misc_irq_init: 2640 hclgevf_state_uninit(hdev); 2641 hclgevf_uninit_msi(hdev); 2642 err_cmd_init: 2643 hclgevf_cmd_uninit(hdev); 2644 err_cmd_queue_init: 2645 hclgevf_pci_uninit(hdev); 2646 clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2647 return ret; 2648 } 2649 2650 static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev) 2651 { 2652 hclgevf_state_uninit(hdev); 2653 2654 if (test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2655 hclgevf_misc_irq_uninit(hdev); 2656 hclgevf_uninit_msi(hdev); 2657 } 2658 2659 hclgevf_pci_uninit(hdev); 2660 hclgevf_cmd_uninit(hdev); 2661 } 2662 2663 static int hclgevf_init_ae_dev(struct hnae3_ae_dev *ae_dev) 2664 { 2665 struct pci_dev *pdev = ae_dev->pdev; 2666 struct hclgevf_dev *hdev; 2667 int ret; 2668 2669 ret = hclgevf_alloc_hdev(ae_dev); 2670 if (ret) { 2671 dev_err(&pdev->dev, "hclge device allocation failed\n"); 2672 return ret; 2673 } 2674 2675 ret = hclgevf_init_hdev(ae_dev->priv); 2676 if (ret) { 2677 dev_err(&pdev->dev, "hclge device initialization failed\n"); 2678 return ret; 2679 } 2680 2681 hdev = ae_dev->priv; 2682 timer_setup(&hdev->keep_alive_timer, hclgevf_keep_alive_timer, 0); 2683 INIT_WORK(&hdev->keep_alive_task, hclgevf_keep_alive_task); 2684 2685 return 0; 2686 } 2687 2688 static void hclgevf_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 2689 { 2690 struct hclgevf_dev *hdev = ae_dev->priv; 2691 2692 hclgevf_uninit_hdev(hdev); 2693 ae_dev->priv = NULL; 2694 } 2695 2696 static u32 hclgevf_get_max_channels(struct hclgevf_dev *hdev) 2697 { 2698 struct hnae3_handle *nic = &hdev->nic; 2699 struct hnae3_knic_private_info *kinfo = &nic->kinfo; 2700 2701 return min_t(u32, hdev->rss_size_max, 2702 hdev->num_tqps / kinfo->num_tc); 2703 } 2704 2705 /** 2706 * hclgevf_get_channels - Get the current channels enabled and max supported. 2707 * @handle: hardware information for network interface 2708 * @ch: ethtool channels structure 2709 * 2710 * We don't support separate tx and rx queues as channels. The other count 2711 * represents how many queues are being used for control. max_combined counts 2712 * how many queue pairs we can support. They may not be mapped 1 to 1 with 2713 * q_vectors since we support a lot more queue pairs than q_vectors. 2714 **/ 2715 static void hclgevf_get_channels(struct hnae3_handle *handle, 2716 struct ethtool_channels *ch) 2717 { 2718 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2719 2720 ch->max_combined = hclgevf_get_max_channels(hdev); 2721 ch->other_count = 0; 2722 ch->max_other = 0; 2723 ch->combined_count = handle->kinfo.rss_size; 2724 } 2725 2726 static void hclgevf_get_tqps_and_rss_info(struct hnae3_handle *handle, 2727 u16 *alloc_tqps, u16 *max_rss_size) 2728 { 2729 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2730 2731 *alloc_tqps = hdev->num_tqps; 2732 *max_rss_size = hdev->rss_size_max; 2733 } 2734 2735 static int hclgevf_get_status(struct hnae3_handle *handle) 2736 { 2737 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2738 2739 return hdev->hw.mac.link; 2740 } 2741 2742 static void hclgevf_get_ksettings_an_result(struct hnae3_handle *handle, 2743 u8 *auto_neg, u32 *speed, 2744 u8 *duplex) 2745 { 2746 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2747 2748 if (speed) 2749 *speed = hdev->hw.mac.speed; 2750 if (duplex) 2751 *duplex = hdev->hw.mac.duplex; 2752 if (auto_neg) 2753 *auto_neg = AUTONEG_DISABLE; 2754 } 2755 2756 void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed, 2757 u8 duplex) 2758 { 2759 hdev->hw.mac.speed = speed; 2760 hdev->hw.mac.duplex = duplex; 2761 } 2762 2763 static int hclgevf_gro_en(struct hnae3_handle *handle, bool enable) 2764 { 2765 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2766 2767 return hclgevf_config_gro(hdev, enable); 2768 } 2769 2770 static void hclgevf_get_media_type(struct hnae3_handle *handle, u8 *media_type, 2771 u8 *module_type) 2772 { 2773 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2774 2775 if (media_type) 2776 *media_type = hdev->hw.mac.media_type; 2777 2778 if (module_type) 2779 *module_type = hdev->hw.mac.module_type; 2780 } 2781 2782 static bool hclgevf_get_hw_reset_stat(struct hnae3_handle *handle) 2783 { 2784 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2785 2786 return !!hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 2787 } 2788 2789 static bool hclgevf_ae_dev_resetting(struct hnae3_handle *handle) 2790 { 2791 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2792 2793 return test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 2794 } 2795 2796 static unsigned long hclgevf_ae_dev_reset_cnt(struct hnae3_handle *handle) 2797 { 2798 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2799 2800 return hdev->rst_stats.hw_rst_done_cnt; 2801 } 2802 2803 static void hclgevf_get_link_mode(struct hnae3_handle *handle, 2804 unsigned long *supported, 2805 unsigned long *advertising) 2806 { 2807 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2808 2809 *supported = hdev->hw.mac.supported; 2810 *advertising = hdev->hw.mac.advertising; 2811 } 2812 2813 #define MAX_SEPARATE_NUM 4 2814 #define SEPARATOR_VALUE 0xFFFFFFFF 2815 #define REG_NUM_PER_LINE 4 2816 #define REG_LEN_PER_LINE (REG_NUM_PER_LINE * sizeof(u32)) 2817 2818 static int hclgevf_get_regs_len(struct hnae3_handle *handle) 2819 { 2820 int cmdq_lines, common_lines, ring_lines, tqp_intr_lines; 2821 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2822 2823 cmdq_lines = sizeof(cmdq_reg_addr_list) / REG_LEN_PER_LINE + 1; 2824 common_lines = sizeof(common_reg_addr_list) / REG_LEN_PER_LINE + 1; 2825 ring_lines = sizeof(ring_reg_addr_list) / REG_LEN_PER_LINE + 1; 2826 tqp_intr_lines = sizeof(tqp_intr_reg_addr_list) / REG_LEN_PER_LINE + 1; 2827 2828 return (cmdq_lines + common_lines + ring_lines * hdev->num_tqps + 2829 tqp_intr_lines * (hdev->num_msi_used - 1)) * REG_LEN_PER_LINE; 2830 } 2831 2832 static void hclgevf_get_regs(struct hnae3_handle *handle, u32 *version, 2833 void *data) 2834 { 2835 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2836 int i, j, reg_um, separator_num; 2837 u32 *reg = data; 2838 2839 *version = hdev->fw_version; 2840 2841 /* fetching per-VF registers values from VF PCIe register space */ 2842 reg_um = sizeof(cmdq_reg_addr_list) / sizeof(u32); 2843 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 2844 for (i = 0; i < reg_um; i++) 2845 *reg++ = hclgevf_read_dev(&hdev->hw, cmdq_reg_addr_list[i]); 2846 for (i = 0; i < separator_num; i++) 2847 *reg++ = SEPARATOR_VALUE; 2848 2849 reg_um = sizeof(common_reg_addr_list) / sizeof(u32); 2850 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 2851 for (i = 0; i < reg_um; i++) 2852 *reg++ = hclgevf_read_dev(&hdev->hw, common_reg_addr_list[i]); 2853 for (i = 0; i < separator_num; i++) 2854 *reg++ = SEPARATOR_VALUE; 2855 2856 reg_um = sizeof(ring_reg_addr_list) / sizeof(u32); 2857 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 2858 for (j = 0; j < hdev->num_tqps; j++) { 2859 for (i = 0; i < reg_um; i++) 2860 *reg++ = hclgevf_read_dev(&hdev->hw, 2861 ring_reg_addr_list[i] + 2862 0x200 * j); 2863 for (i = 0; i < separator_num; i++) 2864 *reg++ = SEPARATOR_VALUE; 2865 } 2866 2867 reg_um = sizeof(tqp_intr_reg_addr_list) / sizeof(u32); 2868 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 2869 for (j = 0; j < hdev->num_msi_used - 1; j++) { 2870 for (i = 0; i < reg_um; i++) 2871 *reg++ = hclgevf_read_dev(&hdev->hw, 2872 tqp_intr_reg_addr_list[i] + 2873 4 * j); 2874 for (i = 0; i < separator_num; i++) 2875 *reg++ = SEPARATOR_VALUE; 2876 } 2877 } 2878 2879 void hclgevf_update_port_base_vlan_info(struct hclgevf_dev *hdev, u16 state, 2880 u8 *port_base_vlan_info, u8 data_size) 2881 { 2882 struct hnae3_handle *nic = &hdev->nic; 2883 2884 rtnl_lock(); 2885 hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 2886 rtnl_unlock(); 2887 2888 /* send msg to PF and wait update port based vlan info */ 2889 hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 2890 HCLGE_MBX_PORT_BASE_VLAN_CFG, 2891 port_base_vlan_info, data_size, 2892 false, NULL, 0); 2893 2894 if (state == HNAE3_PORT_BASE_VLAN_DISABLE) 2895 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_DISABLE; 2896 else 2897 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_ENABLE; 2898 2899 rtnl_lock(); 2900 hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 2901 rtnl_unlock(); 2902 } 2903 2904 static const struct hnae3_ae_ops hclgevf_ops = { 2905 .init_ae_dev = hclgevf_init_ae_dev, 2906 .uninit_ae_dev = hclgevf_uninit_ae_dev, 2907 .flr_prepare = hclgevf_flr_prepare, 2908 .flr_done = hclgevf_flr_done, 2909 .init_client_instance = hclgevf_init_client_instance, 2910 .uninit_client_instance = hclgevf_uninit_client_instance, 2911 .start = hclgevf_ae_start, 2912 .stop = hclgevf_ae_stop, 2913 .client_start = hclgevf_client_start, 2914 .client_stop = hclgevf_client_stop, 2915 .map_ring_to_vector = hclgevf_map_ring_to_vector, 2916 .unmap_ring_from_vector = hclgevf_unmap_ring_from_vector, 2917 .get_vector = hclgevf_get_vector, 2918 .put_vector = hclgevf_put_vector, 2919 .reset_queue = hclgevf_reset_tqp, 2920 .get_mac_addr = hclgevf_get_mac_addr, 2921 .set_mac_addr = hclgevf_set_mac_addr, 2922 .add_uc_addr = hclgevf_add_uc_addr, 2923 .rm_uc_addr = hclgevf_rm_uc_addr, 2924 .add_mc_addr = hclgevf_add_mc_addr, 2925 .rm_mc_addr = hclgevf_rm_mc_addr, 2926 .get_stats = hclgevf_get_stats, 2927 .update_stats = hclgevf_update_stats, 2928 .get_strings = hclgevf_get_strings, 2929 .get_sset_count = hclgevf_get_sset_count, 2930 .get_rss_key_size = hclgevf_get_rss_key_size, 2931 .get_rss_indir_size = hclgevf_get_rss_indir_size, 2932 .get_rss = hclgevf_get_rss, 2933 .set_rss = hclgevf_set_rss, 2934 .get_rss_tuple = hclgevf_get_rss_tuple, 2935 .set_rss_tuple = hclgevf_set_rss_tuple, 2936 .get_tc_size = hclgevf_get_tc_size, 2937 .get_fw_version = hclgevf_get_fw_version, 2938 .set_vlan_filter = hclgevf_set_vlan_filter, 2939 .enable_hw_strip_rxvtag = hclgevf_en_hw_strip_rxvtag, 2940 .reset_event = hclgevf_reset_event, 2941 .set_default_reset_request = hclgevf_set_def_reset_request, 2942 .get_channels = hclgevf_get_channels, 2943 .get_tqps_and_rss_info = hclgevf_get_tqps_and_rss_info, 2944 .get_regs_len = hclgevf_get_regs_len, 2945 .get_regs = hclgevf_get_regs, 2946 .get_status = hclgevf_get_status, 2947 .get_ksettings_an_result = hclgevf_get_ksettings_an_result, 2948 .get_media_type = hclgevf_get_media_type, 2949 .get_hw_reset_stat = hclgevf_get_hw_reset_stat, 2950 .ae_dev_resetting = hclgevf_ae_dev_resetting, 2951 .ae_dev_reset_cnt = hclgevf_ae_dev_reset_cnt, 2952 .set_gro_en = hclgevf_gro_en, 2953 .set_mtu = hclgevf_set_mtu, 2954 .get_global_queue_id = hclgevf_get_qid_global, 2955 .set_timer_task = hclgevf_set_timer_task, 2956 .get_link_mode = hclgevf_get_link_mode, 2957 }; 2958 2959 static struct hnae3_ae_algo ae_algovf = { 2960 .ops = &hclgevf_ops, 2961 .pdev_id_table = ae_algovf_pci_tbl, 2962 }; 2963 2964 static int hclgevf_init(void) 2965 { 2966 pr_info("%s is initializing\n", HCLGEVF_NAME); 2967 2968 hnae3_register_ae_algo(&ae_algovf); 2969 2970 return 0; 2971 } 2972 2973 static void hclgevf_exit(void) 2974 { 2975 hnae3_unregister_ae_algo(&ae_algovf); 2976 } 2977 module_init(hclgevf_init); 2978 module_exit(hclgevf_exit); 2979 2980 MODULE_LICENSE("GPL"); 2981 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 2982 MODULE_DESCRIPTION("HCLGEVF Driver"); 2983 MODULE_VERSION(HCLGEVF_MOD_VERSION); 2984