1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/etherdevice.h> 5 #include <linux/iopoll.h> 6 #include <net/rtnetlink.h> 7 #include "hclgevf_cmd.h" 8 #include "hclgevf_main.h" 9 #include "hclge_mbx.h" 10 #include "hnae3.h" 11 12 #define HCLGEVF_NAME "hclgevf" 13 14 #define HCLGEVF_RESET_MAX_FAIL_CNT 5 15 16 static int hclgevf_reset_hdev(struct hclgevf_dev *hdev); 17 static struct hnae3_ae_algo ae_algovf; 18 19 static struct workqueue_struct *hclgevf_wq; 20 21 static const struct pci_device_id ae_algovf_pci_tbl[] = { 22 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0}, 23 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF), 0}, 24 /* required last entry */ 25 {0, } 26 }; 27 28 static const u8 hclgevf_hash_key[] = { 29 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2, 30 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0, 31 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4, 32 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C, 33 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA 34 }; 35 36 MODULE_DEVICE_TABLE(pci, ae_algovf_pci_tbl); 37 38 static const u32 cmdq_reg_addr_list[] = {HCLGEVF_CMDQ_TX_ADDR_L_REG, 39 HCLGEVF_CMDQ_TX_ADDR_H_REG, 40 HCLGEVF_CMDQ_TX_DEPTH_REG, 41 HCLGEVF_CMDQ_TX_TAIL_REG, 42 HCLGEVF_CMDQ_TX_HEAD_REG, 43 HCLGEVF_CMDQ_RX_ADDR_L_REG, 44 HCLGEVF_CMDQ_RX_ADDR_H_REG, 45 HCLGEVF_CMDQ_RX_DEPTH_REG, 46 HCLGEVF_CMDQ_RX_TAIL_REG, 47 HCLGEVF_CMDQ_RX_HEAD_REG, 48 HCLGEVF_VECTOR0_CMDQ_SRC_REG, 49 HCLGEVF_CMDQ_INTR_STS_REG, 50 HCLGEVF_CMDQ_INTR_EN_REG, 51 HCLGEVF_CMDQ_INTR_GEN_REG}; 52 53 static const u32 common_reg_addr_list[] = {HCLGEVF_MISC_VECTOR_REG_BASE, 54 HCLGEVF_RST_ING, 55 HCLGEVF_GRO_EN_REG}; 56 57 static const u32 ring_reg_addr_list[] = {HCLGEVF_RING_RX_ADDR_L_REG, 58 HCLGEVF_RING_RX_ADDR_H_REG, 59 HCLGEVF_RING_RX_BD_NUM_REG, 60 HCLGEVF_RING_RX_BD_LENGTH_REG, 61 HCLGEVF_RING_RX_MERGE_EN_REG, 62 HCLGEVF_RING_RX_TAIL_REG, 63 HCLGEVF_RING_RX_HEAD_REG, 64 HCLGEVF_RING_RX_FBD_NUM_REG, 65 HCLGEVF_RING_RX_OFFSET_REG, 66 HCLGEVF_RING_RX_FBD_OFFSET_REG, 67 HCLGEVF_RING_RX_STASH_REG, 68 HCLGEVF_RING_RX_BD_ERR_REG, 69 HCLGEVF_RING_TX_ADDR_L_REG, 70 HCLGEVF_RING_TX_ADDR_H_REG, 71 HCLGEVF_RING_TX_BD_NUM_REG, 72 HCLGEVF_RING_TX_PRIORITY_REG, 73 HCLGEVF_RING_TX_TC_REG, 74 HCLGEVF_RING_TX_MERGE_EN_REG, 75 HCLGEVF_RING_TX_TAIL_REG, 76 HCLGEVF_RING_TX_HEAD_REG, 77 HCLGEVF_RING_TX_FBD_NUM_REG, 78 HCLGEVF_RING_TX_OFFSET_REG, 79 HCLGEVF_RING_TX_EBD_NUM_REG, 80 HCLGEVF_RING_TX_EBD_OFFSET_REG, 81 HCLGEVF_RING_TX_BD_ERR_REG, 82 HCLGEVF_RING_EN_REG}; 83 84 static const u32 tqp_intr_reg_addr_list[] = {HCLGEVF_TQP_INTR_CTRL_REG, 85 HCLGEVF_TQP_INTR_GL0_REG, 86 HCLGEVF_TQP_INTR_GL1_REG, 87 HCLGEVF_TQP_INTR_GL2_REG, 88 HCLGEVF_TQP_INTR_RL_REG}; 89 90 static struct hclgevf_dev *hclgevf_ae_get_hdev(struct hnae3_handle *handle) 91 { 92 if (!handle->client) 93 return container_of(handle, struct hclgevf_dev, nic); 94 else if (handle->client->type == HNAE3_CLIENT_ROCE) 95 return container_of(handle, struct hclgevf_dev, roce); 96 else 97 return container_of(handle, struct hclgevf_dev, nic); 98 } 99 100 static int hclgevf_tqps_update_stats(struct hnae3_handle *handle) 101 { 102 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 103 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 104 struct hclgevf_desc desc; 105 struct hclgevf_tqp *tqp; 106 int status; 107 int i; 108 109 for (i = 0; i < kinfo->num_tqps; i++) { 110 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 111 hclgevf_cmd_setup_basic_desc(&desc, 112 HCLGEVF_OPC_QUERY_RX_STATUS, 113 true); 114 115 desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 116 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 117 if (status) { 118 dev_err(&hdev->pdev->dev, 119 "Query tqp stat fail, status = %d,queue = %d\n", 120 status, i); 121 return status; 122 } 123 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd += 124 le32_to_cpu(desc.data[1]); 125 126 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_TX_STATUS, 127 true); 128 129 desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 130 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 131 if (status) { 132 dev_err(&hdev->pdev->dev, 133 "Query tqp stat fail, status = %d,queue = %d\n", 134 status, i); 135 return status; 136 } 137 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd += 138 le32_to_cpu(desc.data[1]); 139 } 140 141 return 0; 142 } 143 144 static u64 *hclgevf_tqps_get_stats(struct hnae3_handle *handle, u64 *data) 145 { 146 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 147 struct hclgevf_tqp *tqp; 148 u64 *buff = data; 149 int i; 150 151 for (i = 0; i < kinfo->num_tqps; i++) { 152 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 153 *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd; 154 } 155 for (i = 0; i < kinfo->num_tqps; i++) { 156 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 157 *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd; 158 } 159 160 return buff; 161 } 162 163 static int hclgevf_tqps_get_sset_count(struct hnae3_handle *handle, int strset) 164 { 165 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 166 167 return kinfo->num_tqps * 2; 168 } 169 170 static u8 *hclgevf_tqps_get_strings(struct hnae3_handle *handle, u8 *data) 171 { 172 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 173 u8 *buff = data; 174 int i = 0; 175 176 for (i = 0; i < kinfo->num_tqps; i++) { 177 struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 178 struct hclgevf_tqp, q); 179 snprintf(buff, ETH_GSTRING_LEN, "txq%d_pktnum_rcd", 180 tqp->index); 181 buff += ETH_GSTRING_LEN; 182 } 183 184 for (i = 0; i < kinfo->num_tqps; i++) { 185 struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 186 struct hclgevf_tqp, q); 187 snprintf(buff, ETH_GSTRING_LEN, "rxq%d_pktnum_rcd", 188 tqp->index); 189 buff += ETH_GSTRING_LEN; 190 } 191 192 return buff; 193 } 194 195 static void hclgevf_update_stats(struct hnae3_handle *handle, 196 struct net_device_stats *net_stats) 197 { 198 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 199 int status; 200 201 status = hclgevf_tqps_update_stats(handle); 202 if (status) 203 dev_err(&hdev->pdev->dev, 204 "VF update of TQPS stats fail, status = %d.\n", 205 status); 206 } 207 208 static int hclgevf_get_sset_count(struct hnae3_handle *handle, int strset) 209 { 210 if (strset == ETH_SS_TEST) 211 return -EOPNOTSUPP; 212 else if (strset == ETH_SS_STATS) 213 return hclgevf_tqps_get_sset_count(handle, strset); 214 215 return 0; 216 } 217 218 static void hclgevf_get_strings(struct hnae3_handle *handle, u32 strset, 219 u8 *data) 220 { 221 u8 *p = (char *)data; 222 223 if (strset == ETH_SS_STATS) 224 p = hclgevf_tqps_get_strings(handle, p); 225 } 226 227 static void hclgevf_get_stats(struct hnae3_handle *handle, u64 *data) 228 { 229 hclgevf_tqps_get_stats(handle, data); 230 } 231 232 static int hclgevf_get_tc_info(struct hclgevf_dev *hdev) 233 { 234 u8 resp_msg; 235 int status; 236 237 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_TCINFO, 0, NULL, 0, 238 true, &resp_msg, sizeof(resp_msg)); 239 if (status) { 240 dev_err(&hdev->pdev->dev, 241 "VF request to get TC info from PF failed %d", 242 status); 243 return status; 244 } 245 246 hdev->hw_tc_map = resp_msg; 247 248 return 0; 249 } 250 251 static int hclgevf_get_port_base_vlan_filter_state(struct hclgevf_dev *hdev) 252 { 253 struct hnae3_handle *nic = &hdev->nic; 254 u8 resp_msg; 255 int ret; 256 257 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 258 HCLGE_MBX_GET_PORT_BASE_VLAN_STATE, 259 NULL, 0, true, &resp_msg, sizeof(u8)); 260 if (ret) { 261 dev_err(&hdev->pdev->dev, 262 "VF request to get port based vlan state failed %d", 263 ret); 264 return ret; 265 } 266 267 nic->port_base_vlan_state = resp_msg; 268 269 return 0; 270 } 271 272 static int hclgevf_get_queue_info(struct hclgevf_dev *hdev) 273 { 274 #define HCLGEVF_TQPS_RSS_INFO_LEN 6 275 u8 resp_msg[HCLGEVF_TQPS_RSS_INFO_LEN]; 276 int status; 277 278 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QINFO, 0, NULL, 0, 279 true, resp_msg, 280 HCLGEVF_TQPS_RSS_INFO_LEN); 281 if (status) { 282 dev_err(&hdev->pdev->dev, 283 "VF request to get tqp info from PF failed %d", 284 status); 285 return status; 286 } 287 288 memcpy(&hdev->num_tqps, &resp_msg[0], sizeof(u16)); 289 memcpy(&hdev->rss_size_max, &resp_msg[2], sizeof(u16)); 290 memcpy(&hdev->rx_buf_len, &resp_msg[4], sizeof(u16)); 291 292 return 0; 293 } 294 295 static int hclgevf_get_queue_depth(struct hclgevf_dev *hdev) 296 { 297 #define HCLGEVF_TQPS_DEPTH_INFO_LEN 4 298 u8 resp_msg[HCLGEVF_TQPS_DEPTH_INFO_LEN]; 299 int ret; 300 301 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QDEPTH, 0, NULL, 0, 302 true, resp_msg, 303 HCLGEVF_TQPS_DEPTH_INFO_LEN); 304 if (ret) { 305 dev_err(&hdev->pdev->dev, 306 "VF request to get tqp depth info from PF failed %d", 307 ret); 308 return ret; 309 } 310 311 memcpy(&hdev->num_tx_desc, &resp_msg[0], sizeof(u16)); 312 memcpy(&hdev->num_rx_desc, &resp_msg[2], sizeof(u16)); 313 314 return 0; 315 } 316 317 static u16 hclgevf_get_qid_global(struct hnae3_handle *handle, u16 queue_id) 318 { 319 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 320 u8 msg_data[2], resp_data[2]; 321 u16 qid_in_pf = 0; 322 int ret; 323 324 memcpy(&msg_data[0], &queue_id, sizeof(queue_id)); 325 326 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QID_IN_PF, 0, msg_data, 327 sizeof(msg_data), true, resp_data, 328 sizeof(resp_data)); 329 if (!ret) 330 qid_in_pf = *(u16 *)resp_data; 331 332 return qid_in_pf; 333 } 334 335 static int hclgevf_get_pf_media_type(struct hclgevf_dev *hdev) 336 { 337 u8 resp_msg[2]; 338 int ret; 339 340 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_MEDIA_TYPE, 0, NULL, 0, 341 true, resp_msg, sizeof(resp_msg)); 342 if (ret) { 343 dev_err(&hdev->pdev->dev, 344 "VF request to get the pf port media type failed %d", 345 ret); 346 return ret; 347 } 348 349 hdev->hw.mac.media_type = resp_msg[0]; 350 hdev->hw.mac.module_type = resp_msg[1]; 351 352 return 0; 353 } 354 355 static int hclgevf_alloc_tqps(struct hclgevf_dev *hdev) 356 { 357 struct hclgevf_tqp *tqp; 358 int i; 359 360 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 361 sizeof(struct hclgevf_tqp), GFP_KERNEL); 362 if (!hdev->htqp) 363 return -ENOMEM; 364 365 tqp = hdev->htqp; 366 367 for (i = 0; i < hdev->num_tqps; i++) { 368 tqp->dev = &hdev->pdev->dev; 369 tqp->index = i; 370 371 tqp->q.ae_algo = &ae_algovf; 372 tqp->q.buf_size = hdev->rx_buf_len; 373 tqp->q.tx_desc_num = hdev->num_tx_desc; 374 tqp->q.rx_desc_num = hdev->num_rx_desc; 375 tqp->q.io_base = hdev->hw.io_base + HCLGEVF_TQP_REG_OFFSET + 376 i * HCLGEVF_TQP_REG_SIZE; 377 378 tqp++; 379 } 380 381 return 0; 382 } 383 384 static int hclgevf_knic_setup(struct hclgevf_dev *hdev) 385 { 386 struct hnae3_handle *nic = &hdev->nic; 387 struct hnae3_knic_private_info *kinfo; 388 u16 new_tqps = hdev->num_tqps; 389 unsigned int i; 390 391 kinfo = &nic->kinfo; 392 kinfo->num_tc = 0; 393 kinfo->num_tx_desc = hdev->num_tx_desc; 394 kinfo->num_rx_desc = hdev->num_rx_desc; 395 kinfo->rx_buf_len = hdev->rx_buf_len; 396 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) 397 if (hdev->hw_tc_map & BIT(i)) 398 kinfo->num_tc++; 399 400 kinfo->rss_size 401 = min_t(u16, hdev->rss_size_max, new_tqps / kinfo->num_tc); 402 new_tqps = kinfo->rss_size * kinfo->num_tc; 403 kinfo->num_tqps = min(new_tqps, hdev->num_tqps); 404 405 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps, 406 sizeof(struct hnae3_queue *), GFP_KERNEL); 407 if (!kinfo->tqp) 408 return -ENOMEM; 409 410 for (i = 0; i < kinfo->num_tqps; i++) { 411 hdev->htqp[i].q.handle = &hdev->nic; 412 hdev->htqp[i].q.tqp_index = i; 413 kinfo->tqp[i] = &hdev->htqp[i].q; 414 } 415 416 /* after init the max rss_size and tqps, adjust the default tqp numbers 417 * and rss size with the actual vector numbers 418 */ 419 kinfo->num_tqps = min_t(u16, hdev->num_nic_msix - 1, kinfo->num_tqps); 420 kinfo->rss_size = min_t(u16, kinfo->num_tqps / kinfo->num_tc, 421 kinfo->rss_size); 422 423 return 0; 424 } 425 426 static void hclgevf_request_link_info(struct hclgevf_dev *hdev) 427 { 428 int status; 429 u8 resp_msg; 430 431 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_STATUS, 0, NULL, 432 0, false, &resp_msg, sizeof(resp_msg)); 433 if (status) 434 dev_err(&hdev->pdev->dev, 435 "VF failed to fetch link status(%d) from PF", status); 436 } 437 438 void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state) 439 { 440 struct hnae3_handle *rhandle = &hdev->roce; 441 struct hnae3_handle *handle = &hdev->nic; 442 struct hnae3_client *rclient; 443 struct hnae3_client *client; 444 445 if (test_and_set_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state)) 446 return; 447 448 client = handle->client; 449 rclient = hdev->roce_client; 450 451 link_state = 452 test_bit(HCLGEVF_STATE_DOWN, &hdev->state) ? 0 : link_state; 453 454 if (link_state != hdev->hw.mac.link) { 455 client->ops->link_status_change(handle, !!link_state); 456 if (rclient && rclient->ops->link_status_change) 457 rclient->ops->link_status_change(rhandle, !!link_state); 458 hdev->hw.mac.link = link_state; 459 } 460 461 clear_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state); 462 } 463 464 static void hclgevf_update_link_mode(struct hclgevf_dev *hdev) 465 { 466 #define HCLGEVF_ADVERTISING 0 467 #define HCLGEVF_SUPPORTED 1 468 u8 send_msg; 469 u8 resp_msg; 470 471 send_msg = HCLGEVF_ADVERTISING; 472 hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_MODE, 0, 473 &send_msg, sizeof(send_msg), false, 474 &resp_msg, sizeof(resp_msg)); 475 send_msg = HCLGEVF_SUPPORTED; 476 hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_MODE, 0, 477 &send_msg, sizeof(send_msg), false, 478 &resp_msg, sizeof(resp_msg)); 479 } 480 481 static int hclgevf_set_handle_info(struct hclgevf_dev *hdev) 482 { 483 struct hnae3_handle *nic = &hdev->nic; 484 int ret; 485 486 nic->ae_algo = &ae_algovf; 487 nic->pdev = hdev->pdev; 488 nic->numa_node_mask = hdev->numa_node_mask; 489 nic->flags |= HNAE3_SUPPORT_VF; 490 491 ret = hclgevf_knic_setup(hdev); 492 if (ret) 493 dev_err(&hdev->pdev->dev, "VF knic setup failed %d\n", 494 ret); 495 return ret; 496 } 497 498 static void hclgevf_free_vector(struct hclgevf_dev *hdev, int vector_id) 499 { 500 if (hdev->vector_status[vector_id] == HCLGEVF_INVALID_VPORT) { 501 dev_warn(&hdev->pdev->dev, 502 "vector(vector_id %d) has been freed.\n", vector_id); 503 return; 504 } 505 506 hdev->vector_status[vector_id] = HCLGEVF_INVALID_VPORT; 507 hdev->num_msi_left += 1; 508 hdev->num_msi_used -= 1; 509 } 510 511 static int hclgevf_get_vector(struct hnae3_handle *handle, u16 vector_num, 512 struct hnae3_vector_info *vector_info) 513 { 514 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 515 struct hnae3_vector_info *vector = vector_info; 516 int alloc = 0; 517 int i, j; 518 519 vector_num = min_t(u16, hdev->num_nic_msix - 1, vector_num); 520 vector_num = min(hdev->num_msi_left, vector_num); 521 522 for (j = 0; j < vector_num; j++) { 523 for (i = HCLGEVF_MISC_VECTOR_NUM + 1; i < hdev->num_msi; i++) { 524 if (hdev->vector_status[i] == HCLGEVF_INVALID_VPORT) { 525 vector->vector = pci_irq_vector(hdev->pdev, i); 526 vector->io_addr = hdev->hw.io_base + 527 HCLGEVF_VECTOR_REG_BASE + 528 (i - 1) * HCLGEVF_VECTOR_REG_OFFSET; 529 hdev->vector_status[i] = 0; 530 hdev->vector_irq[i] = vector->vector; 531 532 vector++; 533 alloc++; 534 535 break; 536 } 537 } 538 } 539 hdev->num_msi_left -= alloc; 540 hdev->num_msi_used += alloc; 541 542 return alloc; 543 } 544 545 static int hclgevf_get_vector_index(struct hclgevf_dev *hdev, int vector) 546 { 547 int i; 548 549 for (i = 0; i < hdev->num_msi; i++) 550 if (vector == hdev->vector_irq[i]) 551 return i; 552 553 return -EINVAL; 554 } 555 556 static int hclgevf_set_rss_algo_key(struct hclgevf_dev *hdev, 557 const u8 hfunc, const u8 *key) 558 { 559 struct hclgevf_rss_config_cmd *req; 560 unsigned int key_offset = 0; 561 struct hclgevf_desc desc; 562 int key_counts; 563 int key_size; 564 int ret; 565 566 key_counts = HCLGEVF_RSS_KEY_SIZE; 567 req = (struct hclgevf_rss_config_cmd *)desc.data; 568 569 while (key_counts) { 570 hclgevf_cmd_setup_basic_desc(&desc, 571 HCLGEVF_OPC_RSS_GENERIC_CONFIG, 572 false); 573 574 req->hash_config |= (hfunc & HCLGEVF_RSS_HASH_ALGO_MASK); 575 req->hash_config |= 576 (key_offset << HCLGEVF_RSS_HASH_KEY_OFFSET_B); 577 578 key_size = min(HCLGEVF_RSS_HASH_KEY_NUM, key_counts); 579 memcpy(req->hash_key, 580 key + key_offset * HCLGEVF_RSS_HASH_KEY_NUM, key_size); 581 582 key_counts -= key_size; 583 key_offset++; 584 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 585 if (ret) { 586 dev_err(&hdev->pdev->dev, 587 "Configure RSS config fail, status = %d\n", 588 ret); 589 return ret; 590 } 591 } 592 593 return 0; 594 } 595 596 static u32 hclgevf_get_rss_key_size(struct hnae3_handle *handle) 597 { 598 return HCLGEVF_RSS_KEY_SIZE; 599 } 600 601 static u32 hclgevf_get_rss_indir_size(struct hnae3_handle *handle) 602 { 603 return HCLGEVF_RSS_IND_TBL_SIZE; 604 } 605 606 static int hclgevf_set_rss_indir_table(struct hclgevf_dev *hdev) 607 { 608 const u8 *indir = hdev->rss_cfg.rss_indirection_tbl; 609 struct hclgevf_rss_indirection_table_cmd *req; 610 struct hclgevf_desc desc; 611 int status; 612 int i, j; 613 614 req = (struct hclgevf_rss_indirection_table_cmd *)desc.data; 615 616 for (i = 0; i < HCLGEVF_RSS_CFG_TBL_NUM; i++) { 617 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INDIR_TABLE, 618 false); 619 req->start_table_index = i * HCLGEVF_RSS_CFG_TBL_SIZE; 620 req->rss_set_bitmap = HCLGEVF_RSS_SET_BITMAP_MSK; 621 for (j = 0; j < HCLGEVF_RSS_CFG_TBL_SIZE; j++) 622 req->rss_result[j] = 623 indir[i * HCLGEVF_RSS_CFG_TBL_SIZE + j]; 624 625 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 626 if (status) { 627 dev_err(&hdev->pdev->dev, 628 "VF failed(=%d) to set RSS indirection table\n", 629 status); 630 return status; 631 } 632 } 633 634 return 0; 635 } 636 637 static int hclgevf_set_rss_tc_mode(struct hclgevf_dev *hdev, u16 rss_size) 638 { 639 struct hclgevf_rss_tc_mode_cmd *req; 640 u16 tc_offset[HCLGEVF_MAX_TC_NUM]; 641 u16 tc_valid[HCLGEVF_MAX_TC_NUM]; 642 u16 tc_size[HCLGEVF_MAX_TC_NUM]; 643 struct hclgevf_desc desc; 644 u16 roundup_size; 645 int status; 646 unsigned int i; 647 648 req = (struct hclgevf_rss_tc_mode_cmd *)desc.data; 649 650 roundup_size = roundup_pow_of_two(rss_size); 651 roundup_size = ilog2(roundup_size); 652 653 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 654 tc_valid[i] = !!(hdev->hw_tc_map & BIT(i)); 655 tc_size[i] = roundup_size; 656 tc_offset[i] = rss_size * i; 657 } 658 659 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_TC_MODE, false); 660 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 661 hnae3_set_bit(req->rss_tc_mode[i], HCLGEVF_RSS_TC_VALID_B, 662 (tc_valid[i] & 0x1)); 663 hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_SIZE_M, 664 HCLGEVF_RSS_TC_SIZE_S, tc_size[i]); 665 hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_OFFSET_M, 666 HCLGEVF_RSS_TC_OFFSET_S, tc_offset[i]); 667 } 668 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 669 if (status) 670 dev_err(&hdev->pdev->dev, 671 "VF failed(=%d) to set rss tc mode\n", status); 672 673 return status; 674 } 675 676 /* for revision 0x20, vf shared the same rss config with pf */ 677 static int hclgevf_get_rss_hash_key(struct hclgevf_dev *hdev) 678 { 679 #define HCLGEVF_RSS_MBX_RESP_LEN 8 680 681 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 682 u8 resp_msg[HCLGEVF_RSS_MBX_RESP_LEN]; 683 u16 msg_num, hash_key_index; 684 u8 index; 685 int ret; 686 687 msg_num = (HCLGEVF_RSS_KEY_SIZE + HCLGEVF_RSS_MBX_RESP_LEN - 1) / 688 HCLGEVF_RSS_MBX_RESP_LEN; 689 for (index = 0; index < msg_num; index++) { 690 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_RSS_KEY, 0, 691 &index, sizeof(index), 692 true, resp_msg, 693 HCLGEVF_RSS_MBX_RESP_LEN); 694 if (ret) { 695 dev_err(&hdev->pdev->dev, 696 "VF get rss hash key from PF failed, ret=%d", 697 ret); 698 return ret; 699 } 700 701 hash_key_index = HCLGEVF_RSS_MBX_RESP_LEN * index; 702 if (index == msg_num - 1) 703 memcpy(&rss_cfg->rss_hash_key[hash_key_index], 704 &resp_msg[0], 705 HCLGEVF_RSS_KEY_SIZE - hash_key_index); 706 else 707 memcpy(&rss_cfg->rss_hash_key[hash_key_index], 708 &resp_msg[0], HCLGEVF_RSS_MBX_RESP_LEN); 709 } 710 711 return 0; 712 } 713 714 static int hclgevf_get_rss(struct hnae3_handle *handle, u32 *indir, u8 *key, 715 u8 *hfunc) 716 { 717 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 718 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 719 int i, ret; 720 721 if (handle->pdev->revision >= 0x21) { 722 /* Get hash algorithm */ 723 if (hfunc) { 724 switch (rss_cfg->hash_algo) { 725 case HCLGEVF_RSS_HASH_ALGO_TOEPLITZ: 726 *hfunc = ETH_RSS_HASH_TOP; 727 break; 728 case HCLGEVF_RSS_HASH_ALGO_SIMPLE: 729 *hfunc = ETH_RSS_HASH_XOR; 730 break; 731 default: 732 *hfunc = ETH_RSS_HASH_UNKNOWN; 733 break; 734 } 735 } 736 737 /* Get the RSS Key required by the user */ 738 if (key) 739 memcpy(key, rss_cfg->rss_hash_key, 740 HCLGEVF_RSS_KEY_SIZE); 741 } else { 742 if (hfunc) 743 *hfunc = ETH_RSS_HASH_TOP; 744 if (key) { 745 ret = hclgevf_get_rss_hash_key(hdev); 746 if (ret) 747 return ret; 748 memcpy(key, rss_cfg->rss_hash_key, 749 HCLGEVF_RSS_KEY_SIZE); 750 } 751 } 752 753 if (indir) 754 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 755 indir[i] = rss_cfg->rss_indirection_tbl[i]; 756 757 return 0; 758 } 759 760 static int hclgevf_set_rss(struct hnae3_handle *handle, const u32 *indir, 761 const u8 *key, const u8 hfunc) 762 { 763 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 764 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 765 int ret, i; 766 767 if (handle->pdev->revision >= 0x21) { 768 /* Set the RSS Hash Key if specififed by the user */ 769 if (key) { 770 switch (hfunc) { 771 case ETH_RSS_HASH_TOP: 772 rss_cfg->hash_algo = 773 HCLGEVF_RSS_HASH_ALGO_TOEPLITZ; 774 break; 775 case ETH_RSS_HASH_XOR: 776 rss_cfg->hash_algo = 777 HCLGEVF_RSS_HASH_ALGO_SIMPLE; 778 break; 779 case ETH_RSS_HASH_NO_CHANGE: 780 break; 781 default: 782 return -EINVAL; 783 } 784 785 ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 786 key); 787 if (ret) 788 return ret; 789 790 /* Update the shadow RSS key with user specified qids */ 791 memcpy(rss_cfg->rss_hash_key, key, 792 HCLGEVF_RSS_KEY_SIZE); 793 } 794 } 795 796 /* update the shadow RSS table with user specified qids */ 797 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 798 rss_cfg->rss_indirection_tbl[i] = indir[i]; 799 800 /* update the hardware */ 801 return hclgevf_set_rss_indir_table(hdev); 802 } 803 804 static u8 hclgevf_get_rss_hash_bits(struct ethtool_rxnfc *nfc) 805 { 806 u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGEVF_S_PORT_BIT : 0; 807 808 if (nfc->data & RXH_L4_B_2_3) 809 hash_sets |= HCLGEVF_D_PORT_BIT; 810 else 811 hash_sets &= ~HCLGEVF_D_PORT_BIT; 812 813 if (nfc->data & RXH_IP_SRC) 814 hash_sets |= HCLGEVF_S_IP_BIT; 815 else 816 hash_sets &= ~HCLGEVF_S_IP_BIT; 817 818 if (nfc->data & RXH_IP_DST) 819 hash_sets |= HCLGEVF_D_IP_BIT; 820 else 821 hash_sets &= ~HCLGEVF_D_IP_BIT; 822 823 if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW) 824 hash_sets |= HCLGEVF_V_TAG_BIT; 825 826 return hash_sets; 827 } 828 829 static int hclgevf_set_rss_tuple(struct hnae3_handle *handle, 830 struct ethtool_rxnfc *nfc) 831 { 832 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 833 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 834 struct hclgevf_rss_input_tuple_cmd *req; 835 struct hclgevf_desc desc; 836 u8 tuple_sets; 837 int ret; 838 839 if (handle->pdev->revision == 0x20) 840 return -EOPNOTSUPP; 841 842 if (nfc->data & 843 ~(RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3)) 844 return -EINVAL; 845 846 req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 847 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 848 849 req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 850 req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 851 req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 852 req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 853 req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 854 req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 855 req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 856 req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 857 858 tuple_sets = hclgevf_get_rss_hash_bits(nfc); 859 switch (nfc->flow_type) { 860 case TCP_V4_FLOW: 861 req->ipv4_tcp_en = tuple_sets; 862 break; 863 case TCP_V6_FLOW: 864 req->ipv6_tcp_en = tuple_sets; 865 break; 866 case UDP_V4_FLOW: 867 req->ipv4_udp_en = tuple_sets; 868 break; 869 case UDP_V6_FLOW: 870 req->ipv6_udp_en = tuple_sets; 871 break; 872 case SCTP_V4_FLOW: 873 req->ipv4_sctp_en = tuple_sets; 874 break; 875 case SCTP_V6_FLOW: 876 if ((nfc->data & RXH_L4_B_0_1) || 877 (nfc->data & RXH_L4_B_2_3)) 878 return -EINVAL; 879 880 req->ipv6_sctp_en = tuple_sets; 881 break; 882 case IPV4_FLOW: 883 req->ipv4_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 884 break; 885 case IPV6_FLOW: 886 req->ipv6_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 887 break; 888 default: 889 return -EINVAL; 890 } 891 892 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 893 if (ret) { 894 dev_err(&hdev->pdev->dev, 895 "Set rss tuple fail, status = %d\n", ret); 896 return ret; 897 } 898 899 rss_cfg->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en; 900 rss_cfg->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en; 901 rss_cfg->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en; 902 rss_cfg->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en; 903 rss_cfg->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en; 904 rss_cfg->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en; 905 rss_cfg->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en; 906 rss_cfg->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en; 907 return 0; 908 } 909 910 static int hclgevf_get_rss_tuple(struct hnae3_handle *handle, 911 struct ethtool_rxnfc *nfc) 912 { 913 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 914 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 915 u8 tuple_sets; 916 917 if (handle->pdev->revision == 0x20) 918 return -EOPNOTSUPP; 919 920 nfc->data = 0; 921 922 switch (nfc->flow_type) { 923 case TCP_V4_FLOW: 924 tuple_sets = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 925 break; 926 case UDP_V4_FLOW: 927 tuple_sets = rss_cfg->rss_tuple_sets.ipv4_udp_en; 928 break; 929 case TCP_V6_FLOW: 930 tuple_sets = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 931 break; 932 case UDP_V6_FLOW: 933 tuple_sets = rss_cfg->rss_tuple_sets.ipv6_udp_en; 934 break; 935 case SCTP_V4_FLOW: 936 tuple_sets = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 937 break; 938 case SCTP_V6_FLOW: 939 tuple_sets = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 940 break; 941 case IPV4_FLOW: 942 case IPV6_FLOW: 943 tuple_sets = HCLGEVF_S_IP_BIT | HCLGEVF_D_IP_BIT; 944 break; 945 default: 946 return -EINVAL; 947 } 948 949 if (!tuple_sets) 950 return 0; 951 952 if (tuple_sets & HCLGEVF_D_PORT_BIT) 953 nfc->data |= RXH_L4_B_2_3; 954 if (tuple_sets & HCLGEVF_S_PORT_BIT) 955 nfc->data |= RXH_L4_B_0_1; 956 if (tuple_sets & HCLGEVF_D_IP_BIT) 957 nfc->data |= RXH_IP_DST; 958 if (tuple_sets & HCLGEVF_S_IP_BIT) 959 nfc->data |= RXH_IP_SRC; 960 961 return 0; 962 } 963 964 static int hclgevf_set_rss_input_tuple(struct hclgevf_dev *hdev, 965 struct hclgevf_rss_cfg *rss_cfg) 966 { 967 struct hclgevf_rss_input_tuple_cmd *req; 968 struct hclgevf_desc desc; 969 int ret; 970 971 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 972 973 req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 974 975 req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 976 req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 977 req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 978 req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 979 req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 980 req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 981 req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 982 req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 983 984 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 985 if (ret) 986 dev_err(&hdev->pdev->dev, 987 "Configure rss input fail, status = %d\n", ret); 988 return ret; 989 } 990 991 static int hclgevf_get_tc_size(struct hnae3_handle *handle) 992 { 993 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 994 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 995 996 return rss_cfg->rss_size; 997 } 998 999 static int hclgevf_bind_ring_to_vector(struct hnae3_handle *handle, bool en, 1000 int vector_id, 1001 struct hnae3_ring_chain_node *ring_chain) 1002 { 1003 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1004 struct hnae3_ring_chain_node *node; 1005 struct hclge_mbx_vf_to_pf_cmd *req; 1006 struct hclgevf_desc desc; 1007 int i = 0; 1008 int status; 1009 u8 type; 1010 1011 req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data; 1012 type = en ? HCLGE_MBX_MAP_RING_TO_VECTOR : 1013 HCLGE_MBX_UNMAP_RING_TO_VECTOR; 1014 1015 for (node = ring_chain; node; node = node->next) { 1016 int idx_offset = HCLGE_MBX_RING_MAP_BASIC_MSG_NUM + 1017 HCLGE_MBX_RING_NODE_VARIABLE_NUM * i; 1018 1019 if (i == 0) { 1020 hclgevf_cmd_setup_basic_desc(&desc, 1021 HCLGEVF_OPC_MBX_VF_TO_PF, 1022 false); 1023 req->msg[0] = type; 1024 req->msg[1] = vector_id; 1025 } 1026 1027 req->msg[idx_offset] = 1028 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B); 1029 req->msg[idx_offset + 1] = node->tqp_index; 1030 req->msg[idx_offset + 2] = hnae3_get_field(node->int_gl_idx, 1031 HNAE3_RING_GL_IDX_M, 1032 HNAE3_RING_GL_IDX_S); 1033 1034 i++; 1035 if ((i == (HCLGE_MBX_VF_MSG_DATA_NUM - 1036 HCLGE_MBX_RING_MAP_BASIC_MSG_NUM) / 1037 HCLGE_MBX_RING_NODE_VARIABLE_NUM) || 1038 !node->next) { 1039 req->msg[2] = i; 1040 1041 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1042 if (status) { 1043 dev_err(&hdev->pdev->dev, 1044 "Map TQP fail, status is %d.\n", 1045 status); 1046 return status; 1047 } 1048 i = 0; 1049 hclgevf_cmd_setup_basic_desc(&desc, 1050 HCLGEVF_OPC_MBX_VF_TO_PF, 1051 false); 1052 req->msg[0] = type; 1053 req->msg[1] = vector_id; 1054 } 1055 } 1056 1057 return 0; 1058 } 1059 1060 static int hclgevf_map_ring_to_vector(struct hnae3_handle *handle, int vector, 1061 struct hnae3_ring_chain_node *ring_chain) 1062 { 1063 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1064 int vector_id; 1065 1066 vector_id = hclgevf_get_vector_index(hdev, vector); 1067 if (vector_id < 0) { 1068 dev_err(&handle->pdev->dev, 1069 "Get vector index fail. ret =%d\n", vector_id); 1070 return vector_id; 1071 } 1072 1073 return hclgevf_bind_ring_to_vector(handle, true, vector_id, ring_chain); 1074 } 1075 1076 static int hclgevf_unmap_ring_from_vector( 1077 struct hnae3_handle *handle, 1078 int vector, 1079 struct hnae3_ring_chain_node *ring_chain) 1080 { 1081 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1082 int ret, vector_id; 1083 1084 if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 1085 return 0; 1086 1087 vector_id = hclgevf_get_vector_index(hdev, vector); 1088 if (vector_id < 0) { 1089 dev_err(&handle->pdev->dev, 1090 "Get vector index fail. ret =%d\n", vector_id); 1091 return vector_id; 1092 } 1093 1094 ret = hclgevf_bind_ring_to_vector(handle, false, vector_id, ring_chain); 1095 if (ret) 1096 dev_err(&handle->pdev->dev, 1097 "Unmap ring from vector fail. vector=%d, ret =%d\n", 1098 vector_id, 1099 ret); 1100 1101 return ret; 1102 } 1103 1104 static int hclgevf_put_vector(struct hnae3_handle *handle, int vector) 1105 { 1106 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1107 int vector_id; 1108 1109 vector_id = hclgevf_get_vector_index(hdev, vector); 1110 if (vector_id < 0) { 1111 dev_err(&handle->pdev->dev, 1112 "hclgevf_put_vector get vector index fail. ret =%d\n", 1113 vector_id); 1114 return vector_id; 1115 } 1116 1117 hclgevf_free_vector(hdev, vector_id); 1118 1119 return 0; 1120 } 1121 1122 static int hclgevf_cmd_set_promisc_mode(struct hclgevf_dev *hdev, 1123 bool en_uc_pmc, bool en_mc_pmc, 1124 bool en_bc_pmc) 1125 { 1126 struct hclge_mbx_vf_to_pf_cmd *req; 1127 struct hclgevf_desc desc; 1128 int ret; 1129 1130 req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data; 1131 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_MBX_VF_TO_PF, false); 1132 req->msg[0] = HCLGE_MBX_SET_PROMISC_MODE; 1133 req->msg[1] = en_bc_pmc ? 1 : 0; 1134 req->msg[2] = en_uc_pmc ? 1 : 0; 1135 req->msg[3] = en_mc_pmc ? 1 : 0; 1136 1137 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1138 if (ret) 1139 dev_err(&hdev->pdev->dev, 1140 "Set promisc mode fail, status is %d.\n", ret); 1141 1142 return ret; 1143 } 1144 1145 static int hclgevf_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc, 1146 bool en_mc_pmc) 1147 { 1148 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1149 struct pci_dev *pdev = hdev->pdev; 1150 bool en_bc_pmc; 1151 1152 en_bc_pmc = pdev->revision != 0x20; 1153 1154 return hclgevf_cmd_set_promisc_mode(hdev, en_uc_pmc, en_mc_pmc, 1155 en_bc_pmc); 1156 } 1157 1158 static int hclgevf_tqp_enable(struct hclgevf_dev *hdev, unsigned int tqp_id, 1159 int stream_id, bool enable) 1160 { 1161 struct hclgevf_cfg_com_tqp_queue_cmd *req; 1162 struct hclgevf_desc desc; 1163 int status; 1164 1165 req = (struct hclgevf_cfg_com_tqp_queue_cmd *)desc.data; 1166 1167 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_CFG_COM_TQP_QUEUE, 1168 false); 1169 req->tqp_id = cpu_to_le16(tqp_id & HCLGEVF_RING_ID_MASK); 1170 req->stream_id = cpu_to_le16(stream_id); 1171 if (enable) 1172 req->enable |= 1U << HCLGEVF_TQP_ENABLE_B; 1173 1174 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1175 if (status) 1176 dev_err(&hdev->pdev->dev, 1177 "TQP enable fail, status =%d.\n", status); 1178 1179 return status; 1180 } 1181 1182 static void hclgevf_reset_tqp_stats(struct hnae3_handle *handle) 1183 { 1184 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 1185 struct hclgevf_tqp *tqp; 1186 int i; 1187 1188 for (i = 0; i < kinfo->num_tqps; i++) { 1189 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 1190 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats)); 1191 } 1192 } 1193 1194 static int hclgevf_get_host_mac_addr(struct hclgevf_dev *hdev, u8 *p) 1195 { 1196 u8 host_mac[ETH_ALEN]; 1197 int status; 1198 1199 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_MAC_ADDR, 0, NULL, 0, 1200 true, host_mac, ETH_ALEN); 1201 if (status) { 1202 dev_err(&hdev->pdev->dev, 1203 "fail to get VF MAC from host %d", status); 1204 return status; 1205 } 1206 1207 ether_addr_copy(p, host_mac); 1208 1209 return 0; 1210 } 1211 1212 static void hclgevf_get_mac_addr(struct hnae3_handle *handle, u8 *p) 1213 { 1214 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1215 u8 host_mac_addr[ETH_ALEN]; 1216 1217 if (hclgevf_get_host_mac_addr(hdev, host_mac_addr)) 1218 return; 1219 1220 hdev->has_pf_mac = !is_zero_ether_addr(host_mac_addr); 1221 if (hdev->has_pf_mac) 1222 ether_addr_copy(p, host_mac_addr); 1223 else 1224 ether_addr_copy(p, hdev->hw.mac.mac_addr); 1225 } 1226 1227 static int hclgevf_set_mac_addr(struct hnae3_handle *handle, void *p, 1228 bool is_first) 1229 { 1230 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1231 u8 *old_mac_addr = (u8 *)hdev->hw.mac.mac_addr; 1232 u8 *new_mac_addr = (u8 *)p; 1233 u8 msg_data[ETH_ALEN * 2]; 1234 u16 subcode; 1235 int status; 1236 1237 ether_addr_copy(msg_data, new_mac_addr); 1238 ether_addr_copy(&msg_data[ETH_ALEN], old_mac_addr); 1239 1240 subcode = is_first ? HCLGE_MBX_MAC_VLAN_UC_ADD : 1241 HCLGE_MBX_MAC_VLAN_UC_MODIFY; 1242 1243 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 1244 subcode, msg_data, sizeof(msg_data), 1245 true, NULL, 0); 1246 if (!status) 1247 ether_addr_copy(hdev->hw.mac.mac_addr, new_mac_addr); 1248 1249 return status; 1250 } 1251 1252 static int hclgevf_add_uc_addr(struct hnae3_handle *handle, 1253 const unsigned char *addr) 1254 { 1255 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1256 1257 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 1258 HCLGE_MBX_MAC_VLAN_UC_ADD, 1259 addr, ETH_ALEN, false, NULL, 0); 1260 } 1261 1262 static int hclgevf_rm_uc_addr(struct hnae3_handle *handle, 1263 const unsigned char *addr) 1264 { 1265 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1266 1267 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 1268 HCLGE_MBX_MAC_VLAN_UC_REMOVE, 1269 addr, ETH_ALEN, false, NULL, 0); 1270 } 1271 1272 static int hclgevf_add_mc_addr(struct hnae3_handle *handle, 1273 const unsigned char *addr) 1274 { 1275 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1276 1277 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 1278 HCLGE_MBX_MAC_VLAN_MC_ADD, 1279 addr, ETH_ALEN, false, NULL, 0); 1280 } 1281 1282 static int hclgevf_rm_mc_addr(struct hnae3_handle *handle, 1283 const unsigned char *addr) 1284 { 1285 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1286 1287 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 1288 HCLGE_MBX_MAC_VLAN_MC_REMOVE, 1289 addr, ETH_ALEN, false, NULL, 0); 1290 } 1291 1292 static int hclgevf_set_vlan_filter(struct hnae3_handle *handle, 1293 __be16 proto, u16 vlan_id, 1294 bool is_kill) 1295 { 1296 #define HCLGEVF_VLAN_MBX_MSG_LEN 5 1297 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1298 u8 msg_data[HCLGEVF_VLAN_MBX_MSG_LEN]; 1299 int ret; 1300 1301 if (vlan_id > HCLGEVF_MAX_VLAN_ID) 1302 return -EINVAL; 1303 1304 if (proto != htons(ETH_P_8021Q)) 1305 return -EPROTONOSUPPORT; 1306 1307 /* When device is resetting, firmware is unable to handle 1308 * mailbox. Just record the vlan id, and remove it after 1309 * reset finished. 1310 */ 1311 if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) && is_kill) { 1312 set_bit(vlan_id, hdev->vlan_del_fail_bmap); 1313 return -EBUSY; 1314 } 1315 1316 msg_data[0] = is_kill; 1317 memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id)); 1318 memcpy(&msg_data[3], &proto, sizeof(proto)); 1319 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 1320 HCLGE_MBX_VLAN_FILTER, msg_data, 1321 HCLGEVF_VLAN_MBX_MSG_LEN, true, NULL, 0); 1322 1323 /* when remove hw vlan filter failed, record the vlan id, 1324 * and try to remove it from hw later, to be consistence 1325 * with stack. 1326 */ 1327 if (is_kill && ret) 1328 set_bit(vlan_id, hdev->vlan_del_fail_bmap); 1329 1330 return ret; 1331 } 1332 1333 static void hclgevf_sync_vlan_filter(struct hclgevf_dev *hdev) 1334 { 1335 #define HCLGEVF_MAX_SYNC_COUNT 60 1336 struct hnae3_handle *handle = &hdev->nic; 1337 int ret, sync_cnt = 0; 1338 u16 vlan_id; 1339 1340 vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID); 1341 while (vlan_id != VLAN_N_VID) { 1342 ret = hclgevf_set_vlan_filter(handle, htons(ETH_P_8021Q), 1343 vlan_id, true); 1344 if (ret) 1345 return; 1346 1347 clear_bit(vlan_id, hdev->vlan_del_fail_bmap); 1348 sync_cnt++; 1349 if (sync_cnt >= HCLGEVF_MAX_SYNC_COUNT) 1350 return; 1351 1352 vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID); 1353 } 1354 } 1355 1356 static int hclgevf_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) 1357 { 1358 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1359 u8 msg_data; 1360 1361 msg_data = enable ? 1 : 0; 1362 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 1363 HCLGE_MBX_VLAN_RX_OFF_CFG, &msg_data, 1364 1, false, NULL, 0); 1365 } 1366 1367 static int hclgevf_reset_tqp(struct hnae3_handle *handle, u16 queue_id) 1368 { 1369 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1370 u8 msg_data[2]; 1371 int ret; 1372 1373 memcpy(msg_data, &queue_id, sizeof(queue_id)); 1374 1375 /* disable vf queue before send queue reset msg to PF */ 1376 ret = hclgevf_tqp_enable(hdev, queue_id, 0, false); 1377 if (ret) 1378 return ret; 1379 1380 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_QUEUE_RESET, 0, msg_data, 1381 sizeof(msg_data), true, NULL, 0); 1382 } 1383 1384 static int hclgevf_set_mtu(struct hnae3_handle *handle, int new_mtu) 1385 { 1386 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1387 1388 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MTU, 0, (u8 *)&new_mtu, 1389 sizeof(new_mtu), true, NULL, 0); 1390 } 1391 1392 static int hclgevf_notify_client(struct hclgevf_dev *hdev, 1393 enum hnae3_reset_notify_type type) 1394 { 1395 struct hnae3_client *client = hdev->nic_client; 1396 struct hnae3_handle *handle = &hdev->nic; 1397 int ret; 1398 1399 if (!test_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state) || 1400 !client) 1401 return 0; 1402 1403 if (!client->ops->reset_notify) 1404 return -EOPNOTSUPP; 1405 1406 ret = client->ops->reset_notify(handle, type); 1407 if (ret) 1408 dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n", 1409 type, ret); 1410 1411 return ret; 1412 } 1413 1414 static int hclgevf_reset_wait(struct hclgevf_dev *hdev) 1415 { 1416 #define HCLGEVF_RESET_WAIT_US 20000 1417 #define HCLGEVF_RESET_WAIT_CNT 2000 1418 #define HCLGEVF_RESET_WAIT_TIMEOUT_US \ 1419 (HCLGEVF_RESET_WAIT_US * HCLGEVF_RESET_WAIT_CNT) 1420 1421 u32 val; 1422 int ret; 1423 1424 if (hdev->reset_type == HNAE3_VF_RESET) 1425 ret = readl_poll_timeout(hdev->hw.io_base + 1426 HCLGEVF_VF_RST_ING, val, 1427 !(val & HCLGEVF_VF_RST_ING_BIT), 1428 HCLGEVF_RESET_WAIT_US, 1429 HCLGEVF_RESET_WAIT_TIMEOUT_US); 1430 else 1431 ret = readl_poll_timeout(hdev->hw.io_base + 1432 HCLGEVF_RST_ING, val, 1433 !(val & HCLGEVF_RST_ING_BITS), 1434 HCLGEVF_RESET_WAIT_US, 1435 HCLGEVF_RESET_WAIT_TIMEOUT_US); 1436 1437 /* hardware completion status should be available by this time */ 1438 if (ret) { 1439 dev_err(&hdev->pdev->dev, 1440 "could'nt get reset done status from h/w, timeout!\n"); 1441 return ret; 1442 } 1443 1444 /* we will wait a bit more to let reset of the stack to complete. This 1445 * might happen in case reset assertion was made by PF. Yes, this also 1446 * means we might end up waiting bit more even for VF reset. 1447 */ 1448 msleep(5000); 1449 1450 return 0; 1451 } 1452 1453 static void hclgevf_reset_handshake(struct hclgevf_dev *hdev, bool enable) 1454 { 1455 u32 reg_val; 1456 1457 reg_val = hclgevf_read_dev(&hdev->hw, HCLGEVF_NIC_CSQ_DEPTH_REG); 1458 if (enable) 1459 reg_val |= HCLGEVF_NIC_SW_RST_RDY; 1460 else 1461 reg_val &= ~HCLGEVF_NIC_SW_RST_RDY; 1462 1463 hclgevf_write_dev(&hdev->hw, HCLGEVF_NIC_CSQ_DEPTH_REG, 1464 reg_val); 1465 } 1466 1467 static int hclgevf_reset_stack(struct hclgevf_dev *hdev) 1468 { 1469 int ret; 1470 1471 /* uninitialize the nic client */ 1472 ret = hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT); 1473 if (ret) 1474 return ret; 1475 1476 /* re-initialize the hclge device */ 1477 ret = hclgevf_reset_hdev(hdev); 1478 if (ret) { 1479 dev_err(&hdev->pdev->dev, 1480 "hclge device re-init failed, VF is disabled!\n"); 1481 return ret; 1482 } 1483 1484 /* bring up the nic client again */ 1485 ret = hclgevf_notify_client(hdev, HNAE3_INIT_CLIENT); 1486 if (ret) 1487 return ret; 1488 1489 ret = hclgevf_notify_client(hdev, HNAE3_RESTORE_CLIENT); 1490 if (ret) 1491 return ret; 1492 1493 /* clear handshake status with IMP */ 1494 hclgevf_reset_handshake(hdev, false); 1495 1496 /* bring up the nic to enable TX/RX again */ 1497 return hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 1498 } 1499 1500 static int hclgevf_reset_prepare_wait(struct hclgevf_dev *hdev) 1501 { 1502 #define HCLGEVF_RESET_SYNC_TIME 100 1503 1504 int ret = 0; 1505 1506 if (hdev->reset_type == HNAE3_VF_FUNC_RESET) { 1507 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_RESET, 0, NULL, 1508 0, true, NULL, sizeof(u8)); 1509 hdev->rst_stats.vf_func_rst_cnt++; 1510 } 1511 1512 set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 1513 /* inform hardware that preparatory work is done */ 1514 msleep(HCLGEVF_RESET_SYNC_TIME); 1515 hclgevf_reset_handshake(hdev, true); 1516 dev_info(&hdev->pdev->dev, "prepare reset(%d) wait done, ret:%d\n", 1517 hdev->reset_type, ret); 1518 1519 return ret; 1520 } 1521 1522 static void hclgevf_dump_rst_info(struct hclgevf_dev *hdev) 1523 { 1524 dev_info(&hdev->pdev->dev, "VF function reset count: %u\n", 1525 hdev->rst_stats.vf_func_rst_cnt); 1526 dev_info(&hdev->pdev->dev, "FLR reset count: %u\n", 1527 hdev->rst_stats.flr_rst_cnt); 1528 dev_info(&hdev->pdev->dev, "VF reset count: %u\n", 1529 hdev->rst_stats.vf_rst_cnt); 1530 dev_info(&hdev->pdev->dev, "reset done count: %u\n", 1531 hdev->rst_stats.rst_done_cnt); 1532 dev_info(&hdev->pdev->dev, "HW reset done count: %u\n", 1533 hdev->rst_stats.hw_rst_done_cnt); 1534 dev_info(&hdev->pdev->dev, "reset count: %u\n", 1535 hdev->rst_stats.rst_cnt); 1536 dev_info(&hdev->pdev->dev, "reset fail count: %u\n", 1537 hdev->rst_stats.rst_fail_cnt); 1538 dev_info(&hdev->pdev->dev, "vector0 interrupt enable status: 0x%x\n", 1539 hclgevf_read_dev(&hdev->hw, HCLGEVF_MISC_VECTOR_REG_BASE)); 1540 dev_info(&hdev->pdev->dev, "vector0 interrupt status: 0x%x\n", 1541 hclgevf_read_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_STAT_REG)); 1542 dev_info(&hdev->pdev->dev, "handshake status: 0x%x\n", 1543 hclgevf_read_dev(&hdev->hw, HCLGEVF_CMDQ_TX_DEPTH_REG)); 1544 dev_info(&hdev->pdev->dev, "function reset status: 0x%x\n", 1545 hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING)); 1546 dev_info(&hdev->pdev->dev, "hdev state: 0x%lx\n", hdev->state); 1547 } 1548 1549 static void hclgevf_reset_err_handle(struct hclgevf_dev *hdev) 1550 { 1551 /* recover handshake status with IMP when reset fail */ 1552 hclgevf_reset_handshake(hdev, true); 1553 hdev->rst_stats.rst_fail_cnt++; 1554 dev_err(&hdev->pdev->dev, "failed to reset VF(%u)\n", 1555 hdev->rst_stats.rst_fail_cnt); 1556 1557 if (hdev->rst_stats.rst_fail_cnt < HCLGEVF_RESET_MAX_FAIL_CNT) 1558 set_bit(hdev->reset_type, &hdev->reset_pending); 1559 1560 if (hclgevf_is_reset_pending(hdev)) { 1561 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1562 hclgevf_reset_task_schedule(hdev); 1563 } else { 1564 set_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state); 1565 hclgevf_dump_rst_info(hdev); 1566 } 1567 } 1568 1569 static int hclgevf_reset_prepare(struct hclgevf_dev *hdev) 1570 { 1571 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1572 int ret; 1573 1574 /* Initialize ae_dev reset status as well, in case enet layer wants to 1575 * know if device is undergoing reset 1576 */ 1577 ae_dev->reset_type = hdev->reset_type; 1578 hdev->rst_stats.rst_cnt++; 1579 1580 rtnl_lock(); 1581 /* bring down the nic to stop any ongoing TX/RX */ 1582 ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 1583 rtnl_unlock(); 1584 if (ret) 1585 return ret; 1586 1587 return hclgevf_reset_prepare_wait(hdev); 1588 } 1589 1590 static int hclgevf_reset_rebuild(struct hclgevf_dev *hdev) 1591 { 1592 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1593 int ret; 1594 1595 hdev->rst_stats.hw_rst_done_cnt++; 1596 1597 rtnl_lock(); 1598 /* now, re-initialize the nic client and ae device */ 1599 ret = hclgevf_reset_stack(hdev); 1600 rtnl_unlock(); 1601 if (ret) { 1602 dev_err(&hdev->pdev->dev, "failed to reset VF stack\n"); 1603 return ret; 1604 } 1605 1606 hdev->last_reset_time = jiffies; 1607 ae_dev->reset_type = HNAE3_NONE_RESET; 1608 hdev->rst_stats.rst_done_cnt++; 1609 hdev->rst_stats.rst_fail_cnt = 0; 1610 clear_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state); 1611 1612 return 0; 1613 } 1614 1615 static void hclgevf_reset(struct hclgevf_dev *hdev) 1616 { 1617 if (hclgevf_reset_prepare(hdev)) 1618 goto err_reset; 1619 1620 /* check if VF could successfully fetch the hardware reset completion 1621 * status from the hardware 1622 */ 1623 if (hclgevf_reset_wait(hdev)) { 1624 /* can't do much in this situation, will disable VF */ 1625 dev_err(&hdev->pdev->dev, 1626 "failed to fetch H/W reset completion status\n"); 1627 goto err_reset; 1628 } 1629 1630 if (hclgevf_reset_rebuild(hdev)) 1631 goto err_reset; 1632 1633 return; 1634 1635 err_reset: 1636 hclgevf_reset_err_handle(hdev); 1637 } 1638 1639 static enum hnae3_reset_type hclgevf_get_reset_level(struct hclgevf_dev *hdev, 1640 unsigned long *addr) 1641 { 1642 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; 1643 1644 /* return the highest priority reset level amongst all */ 1645 if (test_bit(HNAE3_VF_RESET, addr)) { 1646 rst_level = HNAE3_VF_RESET; 1647 clear_bit(HNAE3_VF_RESET, addr); 1648 clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1649 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1650 } else if (test_bit(HNAE3_VF_FULL_RESET, addr)) { 1651 rst_level = HNAE3_VF_FULL_RESET; 1652 clear_bit(HNAE3_VF_FULL_RESET, addr); 1653 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1654 } else if (test_bit(HNAE3_VF_PF_FUNC_RESET, addr)) { 1655 rst_level = HNAE3_VF_PF_FUNC_RESET; 1656 clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1657 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1658 } else if (test_bit(HNAE3_VF_FUNC_RESET, addr)) { 1659 rst_level = HNAE3_VF_FUNC_RESET; 1660 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1661 } else if (test_bit(HNAE3_FLR_RESET, addr)) { 1662 rst_level = HNAE3_FLR_RESET; 1663 clear_bit(HNAE3_FLR_RESET, addr); 1664 } 1665 1666 return rst_level; 1667 } 1668 1669 static void hclgevf_reset_event(struct pci_dev *pdev, 1670 struct hnae3_handle *handle) 1671 { 1672 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 1673 struct hclgevf_dev *hdev = ae_dev->priv; 1674 1675 dev_info(&hdev->pdev->dev, "received reset request from VF enet\n"); 1676 1677 if (hdev->default_reset_request) 1678 hdev->reset_level = 1679 hclgevf_get_reset_level(hdev, 1680 &hdev->default_reset_request); 1681 else 1682 hdev->reset_level = HNAE3_VF_FUNC_RESET; 1683 1684 /* reset of this VF requested */ 1685 set_bit(HCLGEVF_RESET_REQUESTED, &hdev->reset_state); 1686 hclgevf_reset_task_schedule(hdev); 1687 1688 hdev->last_reset_time = jiffies; 1689 } 1690 1691 static void hclgevf_set_def_reset_request(struct hnae3_ae_dev *ae_dev, 1692 enum hnae3_reset_type rst_type) 1693 { 1694 struct hclgevf_dev *hdev = ae_dev->priv; 1695 1696 set_bit(rst_type, &hdev->default_reset_request); 1697 } 1698 1699 static void hclgevf_enable_vector(struct hclgevf_misc_vector *vector, bool en) 1700 { 1701 writel(en ? 1 : 0, vector->addr); 1702 } 1703 1704 static void hclgevf_flr_prepare(struct hnae3_ae_dev *ae_dev) 1705 { 1706 #define HCLGEVF_FLR_RETRY_WAIT_MS 500 1707 #define HCLGEVF_FLR_RETRY_CNT 5 1708 1709 struct hclgevf_dev *hdev = ae_dev->priv; 1710 int retry_cnt = 0; 1711 int ret; 1712 1713 retry: 1714 down(&hdev->reset_sem); 1715 set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 1716 hdev->reset_type = HNAE3_FLR_RESET; 1717 ret = hclgevf_reset_prepare(hdev); 1718 if (ret) { 1719 dev_err(&hdev->pdev->dev, "fail to prepare FLR, ret=%d\n", 1720 ret); 1721 if (hdev->reset_pending || 1722 retry_cnt++ < HCLGEVF_FLR_RETRY_CNT) { 1723 dev_err(&hdev->pdev->dev, 1724 "reset_pending:0x%lx, retry_cnt:%d\n", 1725 hdev->reset_pending, retry_cnt); 1726 clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 1727 up(&hdev->reset_sem); 1728 msleep(HCLGEVF_FLR_RETRY_WAIT_MS); 1729 goto retry; 1730 } 1731 } 1732 1733 /* disable misc vector before FLR done */ 1734 hclgevf_enable_vector(&hdev->misc_vector, false); 1735 hdev->rst_stats.flr_rst_cnt++; 1736 } 1737 1738 static void hclgevf_flr_done(struct hnae3_ae_dev *ae_dev) 1739 { 1740 struct hclgevf_dev *hdev = ae_dev->priv; 1741 int ret; 1742 1743 hclgevf_enable_vector(&hdev->misc_vector, true); 1744 1745 ret = hclgevf_reset_rebuild(hdev); 1746 if (ret) 1747 dev_warn(&hdev->pdev->dev, "fail to rebuild, ret=%d\n", 1748 ret); 1749 1750 hdev->reset_type = HNAE3_NONE_RESET; 1751 clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 1752 up(&hdev->reset_sem); 1753 } 1754 1755 static u32 hclgevf_get_fw_version(struct hnae3_handle *handle) 1756 { 1757 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1758 1759 return hdev->fw_version; 1760 } 1761 1762 static void hclgevf_get_misc_vector(struct hclgevf_dev *hdev) 1763 { 1764 struct hclgevf_misc_vector *vector = &hdev->misc_vector; 1765 1766 vector->vector_irq = pci_irq_vector(hdev->pdev, 1767 HCLGEVF_MISC_VECTOR_NUM); 1768 vector->addr = hdev->hw.io_base + HCLGEVF_MISC_VECTOR_REG_BASE; 1769 /* vector status always valid for Vector 0 */ 1770 hdev->vector_status[HCLGEVF_MISC_VECTOR_NUM] = 0; 1771 hdev->vector_irq[HCLGEVF_MISC_VECTOR_NUM] = vector->vector_irq; 1772 1773 hdev->num_msi_left -= 1; 1774 hdev->num_msi_used += 1; 1775 } 1776 1777 void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev) 1778 { 1779 if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) && 1780 !test_and_set_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, 1781 &hdev->state)) 1782 mod_delayed_work(hclgevf_wq, &hdev->service_task, 0); 1783 } 1784 1785 void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev) 1786 { 1787 if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) && 1788 !test_and_set_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, 1789 &hdev->state)) 1790 mod_delayed_work(hclgevf_wq, &hdev->service_task, 0); 1791 } 1792 1793 static void hclgevf_task_schedule(struct hclgevf_dev *hdev, 1794 unsigned long delay) 1795 { 1796 if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) && 1797 !test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) 1798 mod_delayed_work(hclgevf_wq, &hdev->service_task, delay); 1799 } 1800 1801 static void hclgevf_reset_service_task(struct hclgevf_dev *hdev) 1802 { 1803 #define HCLGEVF_MAX_RESET_ATTEMPTS_CNT 3 1804 1805 if (!test_and_clear_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state)) 1806 return; 1807 1808 down(&hdev->reset_sem); 1809 set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 1810 1811 if (test_and_clear_bit(HCLGEVF_RESET_PENDING, 1812 &hdev->reset_state)) { 1813 /* PF has initmated that it is about to reset the hardware. 1814 * We now have to poll & check if hardware has actually 1815 * completed the reset sequence. On hardware reset completion, 1816 * VF needs to reset the client and ae device. 1817 */ 1818 hdev->reset_attempts = 0; 1819 1820 hdev->last_reset_time = jiffies; 1821 while ((hdev->reset_type = 1822 hclgevf_get_reset_level(hdev, &hdev->reset_pending)) 1823 != HNAE3_NONE_RESET) 1824 hclgevf_reset(hdev); 1825 } else if (test_and_clear_bit(HCLGEVF_RESET_REQUESTED, 1826 &hdev->reset_state)) { 1827 /* we could be here when either of below happens: 1828 * 1. reset was initiated due to watchdog timeout caused by 1829 * a. IMP was earlier reset and our TX got choked down and 1830 * which resulted in watchdog reacting and inducing VF 1831 * reset. This also means our cmdq would be unreliable. 1832 * b. problem in TX due to other lower layer(example link 1833 * layer not functioning properly etc.) 1834 * 2. VF reset might have been initiated due to some config 1835 * change. 1836 * 1837 * NOTE: Theres no clear way to detect above cases than to react 1838 * to the response of PF for this reset request. PF will ack the 1839 * 1b and 2. cases but we will not get any intimation about 1a 1840 * from PF as cmdq would be in unreliable state i.e. mailbox 1841 * communication between PF and VF would be broken. 1842 * 1843 * if we are never geting into pending state it means either: 1844 * 1. PF is not receiving our request which could be due to IMP 1845 * reset 1846 * 2. PF is screwed 1847 * We cannot do much for 2. but to check first we can try reset 1848 * our PCIe + stack and see if it alleviates the problem. 1849 */ 1850 if (hdev->reset_attempts > HCLGEVF_MAX_RESET_ATTEMPTS_CNT) { 1851 /* prepare for full reset of stack + pcie interface */ 1852 set_bit(HNAE3_VF_FULL_RESET, &hdev->reset_pending); 1853 1854 /* "defer" schedule the reset task again */ 1855 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1856 } else { 1857 hdev->reset_attempts++; 1858 1859 set_bit(hdev->reset_level, &hdev->reset_pending); 1860 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1861 } 1862 hclgevf_reset_task_schedule(hdev); 1863 } 1864 1865 hdev->reset_type = HNAE3_NONE_RESET; 1866 clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 1867 up(&hdev->reset_sem); 1868 } 1869 1870 static void hclgevf_mailbox_service_task(struct hclgevf_dev *hdev) 1871 { 1872 if (!test_and_clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state)) 1873 return; 1874 1875 if (test_and_set_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) 1876 return; 1877 1878 hclgevf_mbx_async_handler(hdev); 1879 1880 clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 1881 } 1882 1883 static void hclgevf_keep_alive(struct hclgevf_dev *hdev) 1884 { 1885 u8 respmsg; 1886 int ret; 1887 1888 if (test_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state)) 1889 return; 1890 1891 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_KEEP_ALIVE, 0, NULL, 1892 0, false, &respmsg, sizeof(respmsg)); 1893 if (ret) 1894 dev_err(&hdev->pdev->dev, 1895 "VF sends keep alive cmd failed(=%d)\n", ret); 1896 } 1897 1898 static void hclgevf_periodic_service_task(struct hclgevf_dev *hdev) 1899 { 1900 unsigned long delta = round_jiffies_relative(HZ); 1901 struct hnae3_handle *handle = &hdev->nic; 1902 1903 if (time_is_after_jiffies(hdev->last_serv_processed + HZ)) { 1904 delta = jiffies - hdev->last_serv_processed; 1905 1906 if (delta < round_jiffies_relative(HZ)) { 1907 delta = round_jiffies_relative(HZ) - delta; 1908 goto out; 1909 } 1910 } 1911 1912 hdev->serv_processed_cnt++; 1913 if (!(hdev->serv_processed_cnt % HCLGEVF_KEEP_ALIVE_TASK_INTERVAL)) 1914 hclgevf_keep_alive(hdev); 1915 1916 if (test_bit(HCLGEVF_STATE_DOWN, &hdev->state)) { 1917 hdev->last_serv_processed = jiffies; 1918 goto out; 1919 } 1920 1921 if (!(hdev->serv_processed_cnt % HCLGEVF_STATS_TIMER_INTERVAL)) 1922 hclgevf_tqps_update_stats(handle); 1923 1924 /* request the link status from the PF. PF would be able to tell VF 1925 * about such updates in future so we might remove this later 1926 */ 1927 hclgevf_request_link_info(hdev); 1928 1929 hclgevf_update_link_mode(hdev); 1930 1931 hclgevf_sync_vlan_filter(hdev); 1932 1933 hdev->last_serv_processed = jiffies; 1934 1935 out: 1936 hclgevf_task_schedule(hdev, delta); 1937 } 1938 1939 static void hclgevf_service_task(struct work_struct *work) 1940 { 1941 struct hclgevf_dev *hdev = container_of(work, struct hclgevf_dev, 1942 service_task.work); 1943 1944 hclgevf_reset_service_task(hdev); 1945 hclgevf_mailbox_service_task(hdev); 1946 hclgevf_periodic_service_task(hdev); 1947 1948 /* Handle reset and mbx again in case periodical task delays the 1949 * handling by calling hclgevf_task_schedule() in 1950 * hclgevf_periodic_service_task() 1951 */ 1952 hclgevf_reset_service_task(hdev); 1953 hclgevf_mailbox_service_task(hdev); 1954 } 1955 1956 static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regclr) 1957 { 1958 hclgevf_write_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_SRC_REG, regclr); 1959 } 1960 1961 static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev, 1962 u32 *clearval) 1963 { 1964 u32 val, cmdq_stat_reg, rst_ing_reg; 1965 1966 /* fetch the events from their corresponding regs */ 1967 cmdq_stat_reg = hclgevf_read_dev(&hdev->hw, 1968 HCLGEVF_VECTOR0_CMDQ_STAT_REG); 1969 1970 if (BIT(HCLGEVF_VECTOR0_RST_INT_B) & cmdq_stat_reg) { 1971 rst_ing_reg = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 1972 dev_info(&hdev->pdev->dev, 1973 "receive reset interrupt 0x%x!\n", rst_ing_reg); 1974 set_bit(HNAE3_VF_RESET, &hdev->reset_pending); 1975 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1976 set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 1977 *clearval = ~(1U << HCLGEVF_VECTOR0_RST_INT_B); 1978 hdev->rst_stats.vf_rst_cnt++; 1979 /* set up VF hardware reset status, its PF will clear 1980 * this status when PF has initialized done. 1981 */ 1982 val = hclgevf_read_dev(&hdev->hw, HCLGEVF_VF_RST_ING); 1983 hclgevf_write_dev(&hdev->hw, HCLGEVF_VF_RST_ING, 1984 val | HCLGEVF_VF_RST_ING_BIT); 1985 return HCLGEVF_VECTOR0_EVENT_RST; 1986 } 1987 1988 /* check for vector0 mailbox(=CMDQ RX) event source */ 1989 if (BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) { 1990 /* for revision 0x21, clearing interrupt is writing bit 0 1991 * to the clear register, writing bit 1 means to keep the 1992 * old value. 1993 * for revision 0x20, the clear register is a read & write 1994 * register, so we should just write 0 to the bit we are 1995 * handling, and keep other bits as cmdq_stat_reg. 1996 */ 1997 if (hdev->pdev->revision >= 0x21) 1998 *clearval = ~(1U << HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 1999 else 2000 *clearval = cmdq_stat_reg & 2001 ~BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 2002 2003 return HCLGEVF_VECTOR0_EVENT_MBX; 2004 } 2005 2006 dev_dbg(&hdev->pdev->dev, "vector 0 interrupt from unknown source\n"); 2007 2008 return HCLGEVF_VECTOR0_EVENT_OTHER; 2009 } 2010 2011 static irqreturn_t hclgevf_misc_irq_handle(int irq, void *data) 2012 { 2013 enum hclgevf_evt_cause event_cause; 2014 struct hclgevf_dev *hdev = data; 2015 u32 clearval; 2016 2017 hclgevf_enable_vector(&hdev->misc_vector, false); 2018 event_cause = hclgevf_check_evt_cause(hdev, &clearval); 2019 2020 switch (event_cause) { 2021 case HCLGEVF_VECTOR0_EVENT_RST: 2022 hclgevf_reset_task_schedule(hdev); 2023 break; 2024 case HCLGEVF_VECTOR0_EVENT_MBX: 2025 hclgevf_mbx_handler(hdev); 2026 break; 2027 default: 2028 break; 2029 } 2030 2031 if (event_cause != HCLGEVF_VECTOR0_EVENT_OTHER) { 2032 hclgevf_clear_event_cause(hdev, clearval); 2033 hclgevf_enable_vector(&hdev->misc_vector, true); 2034 } 2035 2036 return IRQ_HANDLED; 2037 } 2038 2039 static int hclgevf_configure(struct hclgevf_dev *hdev) 2040 { 2041 int ret; 2042 2043 /* get current port based vlan state from PF */ 2044 ret = hclgevf_get_port_base_vlan_filter_state(hdev); 2045 if (ret) 2046 return ret; 2047 2048 /* get queue configuration from PF */ 2049 ret = hclgevf_get_queue_info(hdev); 2050 if (ret) 2051 return ret; 2052 2053 /* get queue depth info from PF */ 2054 ret = hclgevf_get_queue_depth(hdev); 2055 if (ret) 2056 return ret; 2057 2058 ret = hclgevf_get_pf_media_type(hdev); 2059 if (ret) 2060 return ret; 2061 2062 /* get tc configuration from PF */ 2063 return hclgevf_get_tc_info(hdev); 2064 } 2065 2066 static int hclgevf_alloc_hdev(struct hnae3_ae_dev *ae_dev) 2067 { 2068 struct pci_dev *pdev = ae_dev->pdev; 2069 struct hclgevf_dev *hdev; 2070 2071 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 2072 if (!hdev) 2073 return -ENOMEM; 2074 2075 hdev->pdev = pdev; 2076 hdev->ae_dev = ae_dev; 2077 ae_dev->priv = hdev; 2078 2079 return 0; 2080 } 2081 2082 static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev) 2083 { 2084 struct hnae3_handle *roce = &hdev->roce; 2085 struct hnae3_handle *nic = &hdev->nic; 2086 2087 roce->rinfo.num_vectors = hdev->num_roce_msix; 2088 2089 if (hdev->num_msi_left < roce->rinfo.num_vectors || 2090 hdev->num_msi_left == 0) 2091 return -EINVAL; 2092 2093 roce->rinfo.base_vector = hdev->roce_base_vector; 2094 2095 roce->rinfo.netdev = nic->kinfo.netdev; 2096 roce->rinfo.roce_io_base = hdev->hw.io_base; 2097 2098 roce->pdev = nic->pdev; 2099 roce->ae_algo = nic->ae_algo; 2100 roce->numa_node_mask = nic->numa_node_mask; 2101 2102 return 0; 2103 } 2104 2105 static int hclgevf_config_gro(struct hclgevf_dev *hdev, bool en) 2106 { 2107 struct hclgevf_cfg_gro_status_cmd *req; 2108 struct hclgevf_desc desc; 2109 int ret; 2110 2111 if (!hnae3_dev_gro_supported(hdev)) 2112 return 0; 2113 2114 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_GRO_GENERIC_CONFIG, 2115 false); 2116 req = (struct hclgevf_cfg_gro_status_cmd *)desc.data; 2117 2118 req->gro_en = cpu_to_le16(en ? 1 : 0); 2119 2120 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 2121 if (ret) 2122 dev_err(&hdev->pdev->dev, 2123 "VF GRO hardware config cmd failed, ret = %d.\n", ret); 2124 2125 return ret; 2126 } 2127 2128 static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev) 2129 { 2130 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 2131 int ret; 2132 u32 i; 2133 2134 rss_cfg->rss_size = hdev->nic.kinfo.rss_size; 2135 2136 if (hdev->pdev->revision >= 0x21) { 2137 rss_cfg->hash_algo = HCLGEVF_RSS_HASH_ALGO_SIMPLE; 2138 memcpy(rss_cfg->rss_hash_key, hclgevf_hash_key, 2139 HCLGEVF_RSS_KEY_SIZE); 2140 2141 ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 2142 rss_cfg->rss_hash_key); 2143 if (ret) 2144 return ret; 2145 2146 rss_cfg->rss_tuple_sets.ipv4_tcp_en = 2147 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2148 rss_cfg->rss_tuple_sets.ipv4_udp_en = 2149 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2150 rss_cfg->rss_tuple_sets.ipv4_sctp_en = 2151 HCLGEVF_RSS_INPUT_TUPLE_SCTP; 2152 rss_cfg->rss_tuple_sets.ipv4_fragment_en = 2153 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2154 rss_cfg->rss_tuple_sets.ipv6_tcp_en = 2155 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2156 rss_cfg->rss_tuple_sets.ipv6_udp_en = 2157 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2158 rss_cfg->rss_tuple_sets.ipv6_sctp_en = 2159 HCLGEVF_RSS_INPUT_TUPLE_SCTP; 2160 rss_cfg->rss_tuple_sets.ipv6_fragment_en = 2161 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2162 2163 ret = hclgevf_set_rss_input_tuple(hdev, rss_cfg); 2164 if (ret) 2165 return ret; 2166 } 2167 2168 /* Initialize RSS indirect table */ 2169 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 2170 rss_cfg->rss_indirection_tbl[i] = i % rss_cfg->rss_size; 2171 2172 ret = hclgevf_set_rss_indir_table(hdev); 2173 if (ret) 2174 return ret; 2175 2176 return hclgevf_set_rss_tc_mode(hdev, rss_cfg->rss_size); 2177 } 2178 2179 static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev) 2180 { 2181 return hclgevf_set_vlan_filter(&hdev->nic, htons(ETH_P_8021Q), 0, 2182 false); 2183 } 2184 2185 static void hclgevf_flush_link_update(struct hclgevf_dev *hdev) 2186 { 2187 #define HCLGEVF_FLUSH_LINK_TIMEOUT 100000 2188 2189 unsigned long last = hdev->serv_processed_cnt; 2190 int i = 0; 2191 2192 while (test_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state) && 2193 i++ < HCLGEVF_FLUSH_LINK_TIMEOUT && 2194 last == hdev->serv_processed_cnt) 2195 usleep_range(1, 1); 2196 } 2197 2198 static void hclgevf_set_timer_task(struct hnae3_handle *handle, bool enable) 2199 { 2200 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2201 2202 if (enable) { 2203 hclgevf_task_schedule(hdev, 0); 2204 } else { 2205 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2206 2207 /* flush memory to make sure DOWN is seen by service task */ 2208 smp_mb__before_atomic(); 2209 hclgevf_flush_link_update(hdev); 2210 } 2211 } 2212 2213 static int hclgevf_ae_start(struct hnae3_handle *handle) 2214 { 2215 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2216 2217 hclgevf_reset_tqp_stats(handle); 2218 2219 hclgevf_request_link_info(hdev); 2220 2221 hclgevf_update_link_mode(hdev); 2222 2223 clear_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2224 2225 return 0; 2226 } 2227 2228 static void hclgevf_ae_stop(struct hnae3_handle *handle) 2229 { 2230 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2231 int i; 2232 2233 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2234 2235 if (hdev->reset_type != HNAE3_VF_RESET) 2236 for (i = 0; i < handle->kinfo.num_tqps; i++) 2237 if (hclgevf_reset_tqp(handle, i)) 2238 break; 2239 2240 hclgevf_reset_tqp_stats(handle); 2241 hclgevf_update_link_status(hdev, 0); 2242 } 2243 2244 static int hclgevf_set_alive(struct hnae3_handle *handle, bool alive) 2245 { 2246 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2247 u8 msg_data; 2248 2249 msg_data = alive ? 1 : 0; 2250 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_ALIVE, 2251 0, &msg_data, 1, false, NULL, 0); 2252 } 2253 2254 static int hclgevf_client_start(struct hnae3_handle *handle) 2255 { 2256 int ret; 2257 2258 ret = hclgevf_set_alive(handle, true); 2259 if (ret) 2260 return ret; 2261 2262 return 0; 2263 } 2264 2265 static void hclgevf_client_stop(struct hnae3_handle *handle) 2266 { 2267 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2268 int ret; 2269 2270 ret = hclgevf_set_alive(handle, false); 2271 if (ret) 2272 dev_warn(&hdev->pdev->dev, 2273 "%s failed %d\n", __func__, ret); 2274 } 2275 2276 static void hclgevf_state_init(struct hclgevf_dev *hdev) 2277 { 2278 clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 2279 clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 2280 clear_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state); 2281 2282 INIT_DELAYED_WORK(&hdev->service_task, hclgevf_service_task); 2283 2284 mutex_init(&hdev->mbx_resp.mbx_mutex); 2285 sema_init(&hdev->reset_sem, 1); 2286 2287 /* bring the device down */ 2288 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2289 } 2290 2291 static void hclgevf_state_uninit(struct hclgevf_dev *hdev) 2292 { 2293 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2294 set_bit(HCLGEVF_STATE_REMOVING, &hdev->state); 2295 2296 if (hdev->service_task.work.func) 2297 cancel_delayed_work_sync(&hdev->service_task); 2298 2299 mutex_destroy(&hdev->mbx_resp.mbx_mutex); 2300 } 2301 2302 static int hclgevf_init_msi(struct hclgevf_dev *hdev) 2303 { 2304 struct pci_dev *pdev = hdev->pdev; 2305 int vectors; 2306 int i; 2307 2308 if (hnae3_dev_roce_supported(hdev)) 2309 vectors = pci_alloc_irq_vectors(pdev, 2310 hdev->roce_base_msix_offset + 1, 2311 hdev->num_msi, 2312 PCI_IRQ_MSIX); 2313 else 2314 vectors = pci_alloc_irq_vectors(pdev, HNAE3_MIN_VECTOR_NUM, 2315 hdev->num_msi, 2316 PCI_IRQ_MSI | PCI_IRQ_MSIX); 2317 2318 if (vectors < 0) { 2319 dev_err(&pdev->dev, 2320 "failed(%d) to allocate MSI/MSI-X vectors\n", 2321 vectors); 2322 return vectors; 2323 } 2324 if (vectors < hdev->num_msi) 2325 dev_warn(&hdev->pdev->dev, 2326 "requested %u MSI/MSI-X, but allocated %d MSI/MSI-X\n", 2327 hdev->num_msi, vectors); 2328 2329 hdev->num_msi = vectors; 2330 hdev->num_msi_left = vectors; 2331 2332 hdev->base_msi_vector = pdev->irq; 2333 hdev->roce_base_vector = pdev->irq + hdev->roce_base_msix_offset; 2334 2335 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 2336 sizeof(u16), GFP_KERNEL); 2337 if (!hdev->vector_status) { 2338 pci_free_irq_vectors(pdev); 2339 return -ENOMEM; 2340 } 2341 2342 for (i = 0; i < hdev->num_msi; i++) 2343 hdev->vector_status[i] = HCLGEVF_INVALID_VPORT; 2344 2345 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 2346 sizeof(int), GFP_KERNEL); 2347 if (!hdev->vector_irq) { 2348 devm_kfree(&pdev->dev, hdev->vector_status); 2349 pci_free_irq_vectors(pdev); 2350 return -ENOMEM; 2351 } 2352 2353 return 0; 2354 } 2355 2356 static void hclgevf_uninit_msi(struct hclgevf_dev *hdev) 2357 { 2358 struct pci_dev *pdev = hdev->pdev; 2359 2360 devm_kfree(&pdev->dev, hdev->vector_status); 2361 devm_kfree(&pdev->dev, hdev->vector_irq); 2362 pci_free_irq_vectors(pdev); 2363 } 2364 2365 static int hclgevf_misc_irq_init(struct hclgevf_dev *hdev) 2366 { 2367 int ret; 2368 2369 hclgevf_get_misc_vector(hdev); 2370 2371 snprintf(hdev->misc_vector.name, HNAE3_INT_NAME_LEN, "%s-misc-%s", 2372 HCLGEVF_NAME, pci_name(hdev->pdev)); 2373 ret = request_irq(hdev->misc_vector.vector_irq, hclgevf_misc_irq_handle, 2374 0, hdev->misc_vector.name, hdev); 2375 if (ret) { 2376 dev_err(&hdev->pdev->dev, "VF failed to request misc irq(%d)\n", 2377 hdev->misc_vector.vector_irq); 2378 return ret; 2379 } 2380 2381 hclgevf_clear_event_cause(hdev, 0); 2382 2383 /* enable misc. vector(vector 0) */ 2384 hclgevf_enable_vector(&hdev->misc_vector, true); 2385 2386 return ret; 2387 } 2388 2389 static void hclgevf_misc_irq_uninit(struct hclgevf_dev *hdev) 2390 { 2391 /* disable misc vector(vector 0) */ 2392 hclgevf_enable_vector(&hdev->misc_vector, false); 2393 synchronize_irq(hdev->misc_vector.vector_irq); 2394 free_irq(hdev->misc_vector.vector_irq, hdev); 2395 hclgevf_free_vector(hdev, 0); 2396 } 2397 2398 static void hclgevf_info_show(struct hclgevf_dev *hdev) 2399 { 2400 struct device *dev = &hdev->pdev->dev; 2401 2402 dev_info(dev, "VF info begin:\n"); 2403 2404 dev_info(dev, "Task queue pairs numbers: %u\n", hdev->num_tqps); 2405 dev_info(dev, "Desc num per TX queue: %u\n", hdev->num_tx_desc); 2406 dev_info(dev, "Desc num per RX queue: %u\n", hdev->num_rx_desc); 2407 dev_info(dev, "Numbers of vports: %u\n", hdev->num_alloc_vport); 2408 dev_info(dev, "HW tc map: 0x%x\n", hdev->hw_tc_map); 2409 dev_info(dev, "PF media type of this VF: %u\n", 2410 hdev->hw.mac.media_type); 2411 2412 dev_info(dev, "VF info end.\n"); 2413 } 2414 2415 static int hclgevf_init_nic_client_instance(struct hnae3_ae_dev *ae_dev, 2416 struct hnae3_client *client) 2417 { 2418 struct hclgevf_dev *hdev = ae_dev->priv; 2419 int ret; 2420 2421 ret = client->ops->init_instance(&hdev->nic); 2422 if (ret) 2423 return ret; 2424 2425 set_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 2426 hnae3_set_client_init_flag(client, ae_dev, 1); 2427 2428 if (netif_msg_drv(&hdev->nic)) 2429 hclgevf_info_show(hdev); 2430 2431 return 0; 2432 } 2433 2434 static int hclgevf_init_roce_client_instance(struct hnae3_ae_dev *ae_dev, 2435 struct hnae3_client *client) 2436 { 2437 struct hclgevf_dev *hdev = ae_dev->priv; 2438 int ret; 2439 2440 if (!hnae3_dev_roce_supported(hdev) || !hdev->roce_client || 2441 !hdev->nic_client) 2442 return 0; 2443 2444 ret = hclgevf_init_roce_base_info(hdev); 2445 if (ret) 2446 return ret; 2447 2448 ret = client->ops->init_instance(&hdev->roce); 2449 if (ret) 2450 return ret; 2451 2452 hnae3_set_client_init_flag(client, ae_dev, 1); 2453 2454 return 0; 2455 } 2456 2457 static int hclgevf_init_client_instance(struct hnae3_client *client, 2458 struct hnae3_ae_dev *ae_dev) 2459 { 2460 struct hclgevf_dev *hdev = ae_dev->priv; 2461 int ret; 2462 2463 switch (client->type) { 2464 case HNAE3_CLIENT_KNIC: 2465 hdev->nic_client = client; 2466 hdev->nic.client = client; 2467 2468 ret = hclgevf_init_nic_client_instance(ae_dev, client); 2469 if (ret) 2470 goto clear_nic; 2471 2472 ret = hclgevf_init_roce_client_instance(ae_dev, 2473 hdev->roce_client); 2474 if (ret) 2475 goto clear_roce; 2476 2477 break; 2478 case HNAE3_CLIENT_ROCE: 2479 if (hnae3_dev_roce_supported(hdev)) { 2480 hdev->roce_client = client; 2481 hdev->roce.client = client; 2482 } 2483 2484 ret = hclgevf_init_roce_client_instance(ae_dev, client); 2485 if (ret) 2486 goto clear_roce; 2487 2488 break; 2489 default: 2490 return -EINVAL; 2491 } 2492 2493 return 0; 2494 2495 clear_nic: 2496 hdev->nic_client = NULL; 2497 hdev->nic.client = NULL; 2498 return ret; 2499 clear_roce: 2500 hdev->roce_client = NULL; 2501 hdev->roce.client = NULL; 2502 return ret; 2503 } 2504 2505 static void hclgevf_uninit_client_instance(struct hnae3_client *client, 2506 struct hnae3_ae_dev *ae_dev) 2507 { 2508 struct hclgevf_dev *hdev = ae_dev->priv; 2509 2510 /* un-init roce, if it exists */ 2511 if (hdev->roce_client) { 2512 hdev->roce_client->ops->uninit_instance(&hdev->roce, 0); 2513 hdev->roce_client = NULL; 2514 hdev->roce.client = NULL; 2515 } 2516 2517 /* un-init nic/unic, if this was not called by roce client */ 2518 if (client->ops->uninit_instance && hdev->nic_client && 2519 client->type != HNAE3_CLIENT_ROCE) { 2520 clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 2521 2522 client->ops->uninit_instance(&hdev->nic, 0); 2523 hdev->nic_client = NULL; 2524 hdev->nic.client = NULL; 2525 } 2526 } 2527 2528 static int hclgevf_pci_init(struct hclgevf_dev *hdev) 2529 { 2530 struct pci_dev *pdev = hdev->pdev; 2531 struct hclgevf_hw *hw; 2532 int ret; 2533 2534 ret = pci_enable_device(pdev); 2535 if (ret) { 2536 dev_err(&pdev->dev, "failed to enable PCI device\n"); 2537 return ret; 2538 } 2539 2540 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 2541 if (ret) { 2542 dev_err(&pdev->dev, "can't set consistent PCI DMA, exiting"); 2543 goto err_disable_device; 2544 } 2545 2546 ret = pci_request_regions(pdev, HCLGEVF_DRIVER_NAME); 2547 if (ret) { 2548 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 2549 goto err_disable_device; 2550 } 2551 2552 pci_set_master(pdev); 2553 hw = &hdev->hw; 2554 hw->hdev = hdev; 2555 hw->io_base = pci_iomap(pdev, 2, 0); 2556 if (!hw->io_base) { 2557 dev_err(&pdev->dev, "can't map configuration register space\n"); 2558 ret = -ENOMEM; 2559 goto err_clr_master; 2560 } 2561 2562 return 0; 2563 2564 err_clr_master: 2565 pci_clear_master(pdev); 2566 pci_release_regions(pdev); 2567 err_disable_device: 2568 pci_disable_device(pdev); 2569 2570 return ret; 2571 } 2572 2573 static void hclgevf_pci_uninit(struct hclgevf_dev *hdev) 2574 { 2575 struct pci_dev *pdev = hdev->pdev; 2576 2577 pci_iounmap(pdev, hdev->hw.io_base); 2578 pci_clear_master(pdev); 2579 pci_release_regions(pdev); 2580 pci_disable_device(pdev); 2581 } 2582 2583 static int hclgevf_query_vf_resource(struct hclgevf_dev *hdev) 2584 { 2585 struct hclgevf_query_res_cmd *req; 2586 struct hclgevf_desc desc; 2587 int ret; 2588 2589 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_VF_RSRC, true); 2590 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 2591 if (ret) { 2592 dev_err(&hdev->pdev->dev, 2593 "query vf resource failed, ret = %d.\n", ret); 2594 return ret; 2595 } 2596 2597 req = (struct hclgevf_query_res_cmd *)desc.data; 2598 2599 if (hnae3_dev_roce_supported(hdev)) { 2600 hdev->roce_base_msix_offset = 2601 hnae3_get_field(__le16_to_cpu(req->msixcap_localid_ba_rocee), 2602 HCLGEVF_MSIX_OFT_ROCEE_M, 2603 HCLGEVF_MSIX_OFT_ROCEE_S); 2604 hdev->num_roce_msix = 2605 hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number), 2606 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 2607 2608 /* nic's msix numbers is always equals to the roce's. */ 2609 hdev->num_nic_msix = hdev->num_roce_msix; 2610 2611 /* VF should have NIC vectors and Roce vectors, NIC vectors 2612 * are queued before Roce vectors. The offset is fixed to 64. 2613 */ 2614 hdev->num_msi = hdev->num_roce_msix + 2615 hdev->roce_base_msix_offset; 2616 } else { 2617 hdev->num_msi = 2618 hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number), 2619 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 2620 2621 hdev->num_nic_msix = hdev->num_msi; 2622 } 2623 2624 if (hdev->num_nic_msix < HNAE3_MIN_VECTOR_NUM) { 2625 dev_err(&hdev->pdev->dev, 2626 "Just %u msi resources, not enough for vf(min:2).\n", 2627 hdev->num_nic_msix); 2628 return -EINVAL; 2629 } 2630 2631 return 0; 2632 } 2633 2634 static int hclgevf_pci_reset(struct hclgevf_dev *hdev) 2635 { 2636 struct pci_dev *pdev = hdev->pdev; 2637 int ret = 0; 2638 2639 if (hdev->reset_type == HNAE3_VF_FULL_RESET && 2640 test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2641 hclgevf_misc_irq_uninit(hdev); 2642 hclgevf_uninit_msi(hdev); 2643 clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2644 } 2645 2646 if (!test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2647 pci_set_master(pdev); 2648 ret = hclgevf_init_msi(hdev); 2649 if (ret) { 2650 dev_err(&pdev->dev, 2651 "failed(%d) to init MSI/MSI-X\n", ret); 2652 return ret; 2653 } 2654 2655 ret = hclgevf_misc_irq_init(hdev); 2656 if (ret) { 2657 hclgevf_uninit_msi(hdev); 2658 dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 2659 ret); 2660 return ret; 2661 } 2662 2663 set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2664 } 2665 2666 return ret; 2667 } 2668 2669 static int hclgevf_reset_hdev(struct hclgevf_dev *hdev) 2670 { 2671 struct pci_dev *pdev = hdev->pdev; 2672 int ret; 2673 2674 ret = hclgevf_pci_reset(hdev); 2675 if (ret) { 2676 dev_err(&pdev->dev, "pci reset failed %d\n", ret); 2677 return ret; 2678 } 2679 2680 ret = hclgevf_cmd_init(hdev); 2681 if (ret) { 2682 dev_err(&pdev->dev, "cmd failed %d\n", ret); 2683 return ret; 2684 } 2685 2686 ret = hclgevf_rss_init_hw(hdev); 2687 if (ret) { 2688 dev_err(&hdev->pdev->dev, 2689 "failed(%d) to initialize RSS\n", ret); 2690 return ret; 2691 } 2692 2693 ret = hclgevf_config_gro(hdev, true); 2694 if (ret) 2695 return ret; 2696 2697 ret = hclgevf_init_vlan_config(hdev); 2698 if (ret) { 2699 dev_err(&hdev->pdev->dev, 2700 "failed(%d) to initialize VLAN config\n", ret); 2701 return ret; 2702 } 2703 2704 dev_info(&hdev->pdev->dev, "Reset done\n"); 2705 2706 return 0; 2707 } 2708 2709 static int hclgevf_init_hdev(struct hclgevf_dev *hdev) 2710 { 2711 struct pci_dev *pdev = hdev->pdev; 2712 int ret; 2713 2714 ret = hclgevf_pci_init(hdev); 2715 if (ret) { 2716 dev_err(&pdev->dev, "PCI initialization failed\n"); 2717 return ret; 2718 } 2719 2720 ret = hclgevf_cmd_queue_init(hdev); 2721 if (ret) { 2722 dev_err(&pdev->dev, "Cmd queue init failed: %d\n", ret); 2723 goto err_cmd_queue_init; 2724 } 2725 2726 ret = hclgevf_cmd_init(hdev); 2727 if (ret) 2728 goto err_cmd_init; 2729 2730 /* Get vf resource */ 2731 ret = hclgevf_query_vf_resource(hdev); 2732 if (ret) { 2733 dev_err(&hdev->pdev->dev, 2734 "Query vf status error, ret = %d.\n", ret); 2735 goto err_cmd_init; 2736 } 2737 2738 ret = hclgevf_init_msi(hdev); 2739 if (ret) { 2740 dev_err(&pdev->dev, "failed(%d) to init MSI/MSI-X\n", ret); 2741 goto err_cmd_init; 2742 } 2743 2744 hclgevf_state_init(hdev); 2745 hdev->reset_level = HNAE3_VF_FUNC_RESET; 2746 hdev->reset_type = HNAE3_NONE_RESET; 2747 2748 ret = hclgevf_misc_irq_init(hdev); 2749 if (ret) { 2750 dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 2751 ret); 2752 goto err_misc_irq_init; 2753 } 2754 2755 set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2756 2757 ret = hclgevf_configure(hdev); 2758 if (ret) { 2759 dev_err(&pdev->dev, "failed(%d) to fetch configuration\n", ret); 2760 goto err_config; 2761 } 2762 2763 ret = hclgevf_alloc_tqps(hdev); 2764 if (ret) { 2765 dev_err(&pdev->dev, "failed(%d) to allocate TQPs\n", ret); 2766 goto err_config; 2767 } 2768 2769 ret = hclgevf_set_handle_info(hdev); 2770 if (ret) { 2771 dev_err(&pdev->dev, "failed(%d) to set handle info\n", ret); 2772 goto err_config; 2773 } 2774 2775 ret = hclgevf_config_gro(hdev, true); 2776 if (ret) 2777 goto err_config; 2778 2779 /* Initialize RSS for this VF */ 2780 ret = hclgevf_rss_init_hw(hdev); 2781 if (ret) { 2782 dev_err(&hdev->pdev->dev, 2783 "failed(%d) to initialize RSS\n", ret); 2784 goto err_config; 2785 } 2786 2787 ret = hclgevf_init_vlan_config(hdev); 2788 if (ret) { 2789 dev_err(&hdev->pdev->dev, 2790 "failed(%d) to initialize VLAN config\n", ret); 2791 goto err_config; 2792 } 2793 2794 hdev->last_reset_time = jiffies; 2795 dev_info(&hdev->pdev->dev, "finished initializing %s driver\n", 2796 HCLGEVF_DRIVER_NAME); 2797 2798 hclgevf_task_schedule(hdev, round_jiffies_relative(HZ)); 2799 2800 return 0; 2801 2802 err_config: 2803 hclgevf_misc_irq_uninit(hdev); 2804 err_misc_irq_init: 2805 hclgevf_state_uninit(hdev); 2806 hclgevf_uninit_msi(hdev); 2807 err_cmd_init: 2808 hclgevf_cmd_uninit(hdev); 2809 err_cmd_queue_init: 2810 hclgevf_pci_uninit(hdev); 2811 clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2812 return ret; 2813 } 2814 2815 static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev) 2816 { 2817 hclgevf_state_uninit(hdev); 2818 2819 if (test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2820 hclgevf_misc_irq_uninit(hdev); 2821 hclgevf_uninit_msi(hdev); 2822 } 2823 2824 hclgevf_pci_uninit(hdev); 2825 hclgevf_cmd_uninit(hdev); 2826 } 2827 2828 static int hclgevf_init_ae_dev(struct hnae3_ae_dev *ae_dev) 2829 { 2830 struct pci_dev *pdev = ae_dev->pdev; 2831 int ret; 2832 2833 ret = hclgevf_alloc_hdev(ae_dev); 2834 if (ret) { 2835 dev_err(&pdev->dev, "hclge device allocation failed\n"); 2836 return ret; 2837 } 2838 2839 ret = hclgevf_init_hdev(ae_dev->priv); 2840 if (ret) { 2841 dev_err(&pdev->dev, "hclge device initialization failed\n"); 2842 return ret; 2843 } 2844 2845 return 0; 2846 } 2847 2848 static void hclgevf_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 2849 { 2850 struct hclgevf_dev *hdev = ae_dev->priv; 2851 2852 hclgevf_uninit_hdev(hdev); 2853 ae_dev->priv = NULL; 2854 } 2855 2856 static u32 hclgevf_get_max_channels(struct hclgevf_dev *hdev) 2857 { 2858 struct hnae3_handle *nic = &hdev->nic; 2859 struct hnae3_knic_private_info *kinfo = &nic->kinfo; 2860 2861 return min_t(u32, hdev->rss_size_max, 2862 hdev->num_tqps / kinfo->num_tc); 2863 } 2864 2865 /** 2866 * hclgevf_get_channels - Get the current channels enabled and max supported. 2867 * @handle: hardware information for network interface 2868 * @ch: ethtool channels structure 2869 * 2870 * We don't support separate tx and rx queues as channels. The other count 2871 * represents how many queues are being used for control. max_combined counts 2872 * how many queue pairs we can support. They may not be mapped 1 to 1 with 2873 * q_vectors since we support a lot more queue pairs than q_vectors. 2874 **/ 2875 static void hclgevf_get_channels(struct hnae3_handle *handle, 2876 struct ethtool_channels *ch) 2877 { 2878 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2879 2880 ch->max_combined = hclgevf_get_max_channels(hdev); 2881 ch->other_count = 0; 2882 ch->max_other = 0; 2883 ch->combined_count = handle->kinfo.rss_size; 2884 } 2885 2886 static void hclgevf_get_tqps_and_rss_info(struct hnae3_handle *handle, 2887 u16 *alloc_tqps, u16 *max_rss_size) 2888 { 2889 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2890 2891 *alloc_tqps = hdev->num_tqps; 2892 *max_rss_size = hdev->rss_size_max; 2893 } 2894 2895 static void hclgevf_update_rss_size(struct hnae3_handle *handle, 2896 u32 new_tqps_num) 2897 { 2898 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 2899 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2900 u16 max_rss_size; 2901 2902 kinfo->req_rss_size = new_tqps_num; 2903 2904 max_rss_size = min_t(u16, hdev->rss_size_max, 2905 hdev->num_tqps / kinfo->num_tc); 2906 2907 /* Use the user's configuration when it is not larger than 2908 * max_rss_size, otherwise, use the maximum specification value. 2909 */ 2910 if (kinfo->req_rss_size != kinfo->rss_size && kinfo->req_rss_size && 2911 kinfo->req_rss_size <= max_rss_size) 2912 kinfo->rss_size = kinfo->req_rss_size; 2913 else if (kinfo->rss_size > max_rss_size || 2914 (!kinfo->req_rss_size && kinfo->rss_size < max_rss_size)) 2915 kinfo->rss_size = max_rss_size; 2916 2917 kinfo->num_tqps = kinfo->num_tc * kinfo->rss_size; 2918 } 2919 2920 static int hclgevf_set_channels(struct hnae3_handle *handle, u32 new_tqps_num, 2921 bool rxfh_configured) 2922 { 2923 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2924 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 2925 u16 cur_rss_size = kinfo->rss_size; 2926 u16 cur_tqps = kinfo->num_tqps; 2927 u32 *rss_indir; 2928 unsigned int i; 2929 int ret; 2930 2931 hclgevf_update_rss_size(handle, new_tqps_num); 2932 2933 ret = hclgevf_set_rss_tc_mode(hdev, kinfo->rss_size); 2934 if (ret) 2935 return ret; 2936 2937 /* RSS indirection table has been configuared by user */ 2938 if (rxfh_configured) 2939 goto out; 2940 2941 /* Reinitializes the rss indirect table according to the new RSS size */ 2942 rss_indir = kcalloc(HCLGEVF_RSS_IND_TBL_SIZE, sizeof(u32), GFP_KERNEL); 2943 if (!rss_indir) 2944 return -ENOMEM; 2945 2946 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 2947 rss_indir[i] = i % kinfo->rss_size; 2948 2949 ret = hclgevf_set_rss(handle, rss_indir, NULL, 0); 2950 if (ret) 2951 dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n", 2952 ret); 2953 2954 kfree(rss_indir); 2955 2956 out: 2957 if (!ret) 2958 dev_info(&hdev->pdev->dev, 2959 "Channels changed, rss_size from %u to %u, tqps from %u to %u", 2960 cur_rss_size, kinfo->rss_size, 2961 cur_tqps, kinfo->rss_size * kinfo->num_tc); 2962 2963 return ret; 2964 } 2965 2966 static int hclgevf_get_status(struct hnae3_handle *handle) 2967 { 2968 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2969 2970 return hdev->hw.mac.link; 2971 } 2972 2973 static void hclgevf_get_ksettings_an_result(struct hnae3_handle *handle, 2974 u8 *auto_neg, u32 *speed, 2975 u8 *duplex) 2976 { 2977 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2978 2979 if (speed) 2980 *speed = hdev->hw.mac.speed; 2981 if (duplex) 2982 *duplex = hdev->hw.mac.duplex; 2983 if (auto_neg) 2984 *auto_neg = AUTONEG_DISABLE; 2985 } 2986 2987 void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed, 2988 u8 duplex) 2989 { 2990 hdev->hw.mac.speed = speed; 2991 hdev->hw.mac.duplex = duplex; 2992 } 2993 2994 static int hclgevf_gro_en(struct hnae3_handle *handle, bool enable) 2995 { 2996 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2997 2998 return hclgevf_config_gro(hdev, enable); 2999 } 3000 3001 static void hclgevf_get_media_type(struct hnae3_handle *handle, u8 *media_type, 3002 u8 *module_type) 3003 { 3004 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3005 3006 if (media_type) 3007 *media_type = hdev->hw.mac.media_type; 3008 3009 if (module_type) 3010 *module_type = hdev->hw.mac.module_type; 3011 } 3012 3013 static bool hclgevf_get_hw_reset_stat(struct hnae3_handle *handle) 3014 { 3015 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3016 3017 return !!hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 3018 } 3019 3020 static bool hclgevf_ae_dev_resetting(struct hnae3_handle *handle) 3021 { 3022 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3023 3024 return test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 3025 } 3026 3027 static unsigned long hclgevf_ae_dev_reset_cnt(struct hnae3_handle *handle) 3028 { 3029 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3030 3031 return hdev->rst_stats.hw_rst_done_cnt; 3032 } 3033 3034 static void hclgevf_get_link_mode(struct hnae3_handle *handle, 3035 unsigned long *supported, 3036 unsigned long *advertising) 3037 { 3038 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3039 3040 *supported = hdev->hw.mac.supported; 3041 *advertising = hdev->hw.mac.advertising; 3042 } 3043 3044 #define MAX_SEPARATE_NUM 4 3045 #define SEPARATOR_VALUE 0xFFFFFFFF 3046 #define REG_NUM_PER_LINE 4 3047 #define REG_LEN_PER_LINE (REG_NUM_PER_LINE * sizeof(u32)) 3048 3049 static int hclgevf_get_regs_len(struct hnae3_handle *handle) 3050 { 3051 int cmdq_lines, common_lines, ring_lines, tqp_intr_lines; 3052 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3053 3054 cmdq_lines = sizeof(cmdq_reg_addr_list) / REG_LEN_PER_LINE + 1; 3055 common_lines = sizeof(common_reg_addr_list) / REG_LEN_PER_LINE + 1; 3056 ring_lines = sizeof(ring_reg_addr_list) / REG_LEN_PER_LINE + 1; 3057 tqp_intr_lines = sizeof(tqp_intr_reg_addr_list) / REG_LEN_PER_LINE + 1; 3058 3059 return (cmdq_lines + common_lines + ring_lines * hdev->num_tqps + 3060 tqp_intr_lines * (hdev->num_msi_used - 1)) * REG_LEN_PER_LINE; 3061 } 3062 3063 static void hclgevf_get_regs(struct hnae3_handle *handle, u32 *version, 3064 void *data) 3065 { 3066 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3067 int i, j, reg_um, separator_num; 3068 u32 *reg = data; 3069 3070 *version = hdev->fw_version; 3071 3072 /* fetching per-VF registers values from VF PCIe register space */ 3073 reg_um = sizeof(cmdq_reg_addr_list) / sizeof(u32); 3074 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 3075 for (i = 0; i < reg_um; i++) 3076 *reg++ = hclgevf_read_dev(&hdev->hw, cmdq_reg_addr_list[i]); 3077 for (i = 0; i < separator_num; i++) 3078 *reg++ = SEPARATOR_VALUE; 3079 3080 reg_um = sizeof(common_reg_addr_list) / sizeof(u32); 3081 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 3082 for (i = 0; i < reg_um; i++) 3083 *reg++ = hclgevf_read_dev(&hdev->hw, common_reg_addr_list[i]); 3084 for (i = 0; i < separator_num; i++) 3085 *reg++ = SEPARATOR_VALUE; 3086 3087 reg_um = sizeof(ring_reg_addr_list) / sizeof(u32); 3088 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 3089 for (j = 0; j < hdev->num_tqps; j++) { 3090 for (i = 0; i < reg_um; i++) 3091 *reg++ = hclgevf_read_dev(&hdev->hw, 3092 ring_reg_addr_list[i] + 3093 0x200 * j); 3094 for (i = 0; i < separator_num; i++) 3095 *reg++ = SEPARATOR_VALUE; 3096 } 3097 3098 reg_um = sizeof(tqp_intr_reg_addr_list) / sizeof(u32); 3099 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 3100 for (j = 0; j < hdev->num_msi_used - 1; j++) { 3101 for (i = 0; i < reg_um; i++) 3102 *reg++ = hclgevf_read_dev(&hdev->hw, 3103 tqp_intr_reg_addr_list[i] + 3104 4 * j); 3105 for (i = 0; i < separator_num; i++) 3106 *reg++ = SEPARATOR_VALUE; 3107 } 3108 } 3109 3110 void hclgevf_update_port_base_vlan_info(struct hclgevf_dev *hdev, u16 state, 3111 u8 *port_base_vlan_info, u8 data_size) 3112 { 3113 struct hnae3_handle *nic = &hdev->nic; 3114 3115 rtnl_lock(); 3116 hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 3117 rtnl_unlock(); 3118 3119 /* send msg to PF and wait update port based vlan info */ 3120 hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 3121 HCLGE_MBX_PORT_BASE_VLAN_CFG, 3122 port_base_vlan_info, data_size, 3123 false, NULL, 0); 3124 3125 if (state == HNAE3_PORT_BASE_VLAN_DISABLE) 3126 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_DISABLE; 3127 else 3128 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_ENABLE; 3129 3130 rtnl_lock(); 3131 hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 3132 rtnl_unlock(); 3133 } 3134 3135 static const struct hnae3_ae_ops hclgevf_ops = { 3136 .init_ae_dev = hclgevf_init_ae_dev, 3137 .uninit_ae_dev = hclgevf_uninit_ae_dev, 3138 .flr_prepare = hclgevf_flr_prepare, 3139 .flr_done = hclgevf_flr_done, 3140 .init_client_instance = hclgevf_init_client_instance, 3141 .uninit_client_instance = hclgevf_uninit_client_instance, 3142 .start = hclgevf_ae_start, 3143 .stop = hclgevf_ae_stop, 3144 .client_start = hclgevf_client_start, 3145 .client_stop = hclgevf_client_stop, 3146 .map_ring_to_vector = hclgevf_map_ring_to_vector, 3147 .unmap_ring_from_vector = hclgevf_unmap_ring_from_vector, 3148 .get_vector = hclgevf_get_vector, 3149 .put_vector = hclgevf_put_vector, 3150 .reset_queue = hclgevf_reset_tqp, 3151 .get_mac_addr = hclgevf_get_mac_addr, 3152 .set_mac_addr = hclgevf_set_mac_addr, 3153 .add_uc_addr = hclgevf_add_uc_addr, 3154 .rm_uc_addr = hclgevf_rm_uc_addr, 3155 .add_mc_addr = hclgevf_add_mc_addr, 3156 .rm_mc_addr = hclgevf_rm_mc_addr, 3157 .get_stats = hclgevf_get_stats, 3158 .update_stats = hclgevf_update_stats, 3159 .get_strings = hclgevf_get_strings, 3160 .get_sset_count = hclgevf_get_sset_count, 3161 .get_rss_key_size = hclgevf_get_rss_key_size, 3162 .get_rss_indir_size = hclgevf_get_rss_indir_size, 3163 .get_rss = hclgevf_get_rss, 3164 .set_rss = hclgevf_set_rss, 3165 .get_rss_tuple = hclgevf_get_rss_tuple, 3166 .set_rss_tuple = hclgevf_set_rss_tuple, 3167 .get_tc_size = hclgevf_get_tc_size, 3168 .get_fw_version = hclgevf_get_fw_version, 3169 .set_vlan_filter = hclgevf_set_vlan_filter, 3170 .enable_hw_strip_rxvtag = hclgevf_en_hw_strip_rxvtag, 3171 .reset_event = hclgevf_reset_event, 3172 .set_default_reset_request = hclgevf_set_def_reset_request, 3173 .set_channels = hclgevf_set_channels, 3174 .get_channels = hclgevf_get_channels, 3175 .get_tqps_and_rss_info = hclgevf_get_tqps_and_rss_info, 3176 .get_regs_len = hclgevf_get_regs_len, 3177 .get_regs = hclgevf_get_regs, 3178 .get_status = hclgevf_get_status, 3179 .get_ksettings_an_result = hclgevf_get_ksettings_an_result, 3180 .get_media_type = hclgevf_get_media_type, 3181 .get_hw_reset_stat = hclgevf_get_hw_reset_stat, 3182 .ae_dev_resetting = hclgevf_ae_dev_resetting, 3183 .ae_dev_reset_cnt = hclgevf_ae_dev_reset_cnt, 3184 .set_gro_en = hclgevf_gro_en, 3185 .set_mtu = hclgevf_set_mtu, 3186 .get_global_queue_id = hclgevf_get_qid_global, 3187 .set_timer_task = hclgevf_set_timer_task, 3188 .get_link_mode = hclgevf_get_link_mode, 3189 .set_promisc_mode = hclgevf_set_promisc_mode, 3190 }; 3191 3192 static struct hnae3_ae_algo ae_algovf = { 3193 .ops = &hclgevf_ops, 3194 .pdev_id_table = ae_algovf_pci_tbl, 3195 }; 3196 3197 static int hclgevf_init(void) 3198 { 3199 pr_info("%s is initializing\n", HCLGEVF_NAME); 3200 3201 hclgevf_wq = alloc_workqueue("%s", WQ_MEM_RECLAIM, 0, HCLGEVF_NAME); 3202 if (!hclgevf_wq) { 3203 pr_err("%s: failed to create workqueue\n", HCLGEVF_NAME); 3204 return -ENOMEM; 3205 } 3206 3207 hnae3_register_ae_algo(&ae_algovf); 3208 3209 return 0; 3210 } 3211 3212 static void hclgevf_exit(void) 3213 { 3214 hnae3_unregister_ae_algo(&ae_algovf); 3215 destroy_workqueue(hclgevf_wq); 3216 } 3217 module_init(hclgevf_init); 3218 module_exit(hclgevf_exit); 3219 3220 MODULE_LICENSE("GPL"); 3221 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 3222 MODULE_DESCRIPTION("HCLGEVF Driver"); 3223 MODULE_VERSION(HCLGEVF_MOD_VERSION); 3224