1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright (c) 2016-2017 Hisilicon Limited.
3 
4 #include <linux/etherdevice.h>
5 #include <linux/iopoll.h>
6 #include <net/rtnetlink.h>
7 #include "hclgevf_cmd.h"
8 #include "hclgevf_main.h"
9 #include "hclgevf_regs.h"
10 #include "hclge_mbx.h"
11 #include "hnae3.h"
12 #include "hclgevf_devlink.h"
13 #include "hclge_comm_rss.h"
14 
15 #define HCLGEVF_NAME	"hclgevf"
16 
17 #define HCLGEVF_RESET_MAX_FAIL_CNT	5
18 
19 static int hclgevf_reset_hdev(struct hclgevf_dev *hdev);
20 static void hclgevf_task_schedule(struct hclgevf_dev *hdev,
21 				  unsigned long delay);
22 
23 static struct hnae3_ae_algo ae_algovf;
24 
25 static struct workqueue_struct *hclgevf_wq;
26 
27 static const struct pci_device_id ae_algovf_pci_tbl[] = {
28 	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_VF), 0},
29 	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF),
30 	 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
31 	/* required last entry */
32 	{0, }
33 };
34 
35 MODULE_DEVICE_TABLE(pci, ae_algovf_pci_tbl);
36 
37 /* hclgevf_cmd_send - send command to command queue
38  * @hw: pointer to the hw struct
39  * @desc: prefilled descriptor for describing the command
40  * @num : the number of descriptors to be sent
41  *
42  * This is the main send command for command queue, it
43  * sends the queue, cleans the queue, etc
44  */
45 int hclgevf_cmd_send(struct hclgevf_hw *hw, struct hclge_desc *desc, int num)
46 {
47 	return hclge_comm_cmd_send(&hw->hw, desc, num);
48 }
49 
50 void hclgevf_arq_init(struct hclgevf_dev *hdev)
51 {
52 	struct hclge_comm_cmq *cmdq = &hdev->hw.hw.cmq;
53 
54 	spin_lock(&cmdq->crq.lock);
55 	/* initialize the pointers of async rx queue of mailbox */
56 	hdev->arq.hdev = hdev;
57 	hdev->arq.head = 0;
58 	hdev->arq.tail = 0;
59 	atomic_set(&hdev->arq.count, 0);
60 	spin_unlock(&cmdq->crq.lock);
61 }
62 
63 struct hclgevf_dev *hclgevf_ae_get_hdev(struct hnae3_handle *handle)
64 {
65 	if (!handle->client)
66 		return container_of(handle, struct hclgevf_dev, nic);
67 	else if (handle->client->type == HNAE3_CLIENT_ROCE)
68 		return container_of(handle, struct hclgevf_dev, roce);
69 	else
70 		return container_of(handle, struct hclgevf_dev, nic);
71 }
72 
73 static void hclgevf_update_stats(struct hnae3_handle *handle)
74 {
75 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
76 	int status;
77 
78 	status = hclge_comm_tqps_update_stats(handle, &hdev->hw.hw);
79 	if (status)
80 		dev_err(&hdev->pdev->dev,
81 			"VF update of TQPS stats fail, status = %d.\n",
82 			status);
83 }
84 
85 static int hclgevf_get_sset_count(struct hnae3_handle *handle, int strset)
86 {
87 	if (strset == ETH_SS_TEST)
88 		return -EOPNOTSUPP;
89 	else if (strset == ETH_SS_STATS)
90 		return hclge_comm_tqps_get_sset_count(handle);
91 
92 	return 0;
93 }
94 
95 static void hclgevf_get_strings(struct hnae3_handle *handle, u32 strset,
96 				u8 *data)
97 {
98 	u8 *p = (char *)data;
99 
100 	if (strset == ETH_SS_STATS)
101 		p = hclge_comm_tqps_get_strings(handle, p);
102 }
103 
104 static void hclgevf_get_stats(struct hnae3_handle *handle, u64 *data)
105 {
106 	hclge_comm_tqps_get_stats(handle, data);
107 }
108 
109 static void hclgevf_build_send_msg(struct hclge_vf_to_pf_msg *msg, u8 code,
110 				   u8 subcode)
111 {
112 	if (msg) {
113 		memset(msg, 0, sizeof(struct hclge_vf_to_pf_msg));
114 		msg->code = code;
115 		msg->subcode = subcode;
116 	}
117 }
118 
119 static int hclgevf_get_basic_info(struct hclgevf_dev *hdev)
120 {
121 	struct hnae3_ae_dev *ae_dev = hdev->ae_dev;
122 	u8 resp_msg[HCLGE_MBX_MAX_RESP_DATA_SIZE];
123 	struct hclge_basic_info *basic_info;
124 	struct hclge_vf_to_pf_msg send_msg;
125 	unsigned long caps;
126 	int status;
127 
128 	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_BASIC_INFO, 0);
129 	status = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg,
130 				      sizeof(resp_msg));
131 	if (status) {
132 		dev_err(&hdev->pdev->dev,
133 			"failed to get basic info from pf, ret = %d", status);
134 		return status;
135 	}
136 
137 	basic_info = (struct hclge_basic_info *)resp_msg;
138 
139 	hdev->hw_tc_map = basic_info->hw_tc_map;
140 	hdev->mbx_api_version = le16_to_cpu(basic_info->mbx_api_version);
141 	caps = le32_to_cpu(basic_info->pf_caps);
142 	if (test_bit(HNAE3_PF_SUPPORT_VLAN_FLTR_MDF_B, &caps))
143 		set_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps);
144 
145 	return 0;
146 }
147 
148 static int hclgevf_get_port_base_vlan_filter_state(struct hclgevf_dev *hdev)
149 {
150 	struct hnae3_handle *nic = &hdev->nic;
151 	struct hclge_vf_to_pf_msg send_msg;
152 	u8 resp_msg;
153 	int ret;
154 
155 	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN,
156 			       HCLGE_MBX_GET_PORT_BASE_VLAN_STATE);
157 	ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, &resp_msg,
158 				   sizeof(u8));
159 	if (ret) {
160 		dev_err(&hdev->pdev->dev,
161 			"VF request to get port based vlan state failed %d",
162 			ret);
163 		return ret;
164 	}
165 
166 	nic->port_base_vlan_state = resp_msg;
167 
168 	return 0;
169 }
170 
171 static int hclgevf_get_queue_info(struct hclgevf_dev *hdev)
172 {
173 #define HCLGEVF_TQPS_RSS_INFO_LEN	6
174 
175 	struct hclge_mbx_vf_queue_info *queue_info;
176 	u8 resp_msg[HCLGEVF_TQPS_RSS_INFO_LEN];
177 	struct hclge_vf_to_pf_msg send_msg;
178 	int status;
179 
180 	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QINFO, 0);
181 	status = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg,
182 				      HCLGEVF_TQPS_RSS_INFO_LEN);
183 	if (status) {
184 		dev_err(&hdev->pdev->dev,
185 			"VF request to get tqp info from PF failed %d",
186 			status);
187 		return status;
188 	}
189 
190 	queue_info = (struct hclge_mbx_vf_queue_info *)resp_msg;
191 	hdev->num_tqps = le16_to_cpu(queue_info->num_tqps);
192 	hdev->rss_size_max = le16_to_cpu(queue_info->rss_size);
193 	hdev->rx_buf_len = le16_to_cpu(queue_info->rx_buf_len);
194 
195 	return 0;
196 }
197 
198 static int hclgevf_get_queue_depth(struct hclgevf_dev *hdev)
199 {
200 #define HCLGEVF_TQPS_DEPTH_INFO_LEN	4
201 
202 	struct hclge_mbx_vf_queue_depth *queue_depth;
203 	u8 resp_msg[HCLGEVF_TQPS_DEPTH_INFO_LEN];
204 	struct hclge_vf_to_pf_msg send_msg;
205 	int ret;
206 
207 	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QDEPTH, 0);
208 	ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg,
209 				   HCLGEVF_TQPS_DEPTH_INFO_LEN);
210 	if (ret) {
211 		dev_err(&hdev->pdev->dev,
212 			"VF request to get tqp depth info from PF failed %d",
213 			ret);
214 		return ret;
215 	}
216 
217 	queue_depth = (struct hclge_mbx_vf_queue_depth *)resp_msg;
218 	hdev->num_tx_desc = le16_to_cpu(queue_depth->num_tx_desc);
219 	hdev->num_rx_desc = le16_to_cpu(queue_depth->num_rx_desc);
220 
221 	return 0;
222 }
223 
224 static u16 hclgevf_get_qid_global(struct hnae3_handle *handle, u16 queue_id)
225 {
226 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
227 	struct hclge_vf_to_pf_msg send_msg;
228 	u16 qid_in_pf = 0;
229 	u8 resp_data[2];
230 	int ret;
231 
232 	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QID_IN_PF, 0);
233 	*(__le16 *)send_msg.data = cpu_to_le16(queue_id);
234 	ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_data,
235 				   sizeof(resp_data));
236 	if (!ret)
237 		qid_in_pf = le16_to_cpu(*(__le16 *)resp_data);
238 
239 	return qid_in_pf;
240 }
241 
242 static int hclgevf_get_pf_media_type(struct hclgevf_dev *hdev)
243 {
244 	struct hclge_vf_to_pf_msg send_msg;
245 	u8 resp_msg[2];
246 	int ret;
247 
248 	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_MEDIA_TYPE, 0);
249 	ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg,
250 				   sizeof(resp_msg));
251 	if (ret) {
252 		dev_err(&hdev->pdev->dev,
253 			"VF request to get the pf port media type failed %d",
254 			ret);
255 		return ret;
256 	}
257 
258 	hdev->hw.mac.media_type = resp_msg[0];
259 	hdev->hw.mac.module_type = resp_msg[1];
260 
261 	return 0;
262 }
263 
264 static int hclgevf_alloc_tqps(struct hclgevf_dev *hdev)
265 {
266 	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
267 	struct hclge_comm_tqp *tqp;
268 	int i;
269 
270 	hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps,
271 				  sizeof(struct hclge_comm_tqp), GFP_KERNEL);
272 	if (!hdev->htqp)
273 		return -ENOMEM;
274 
275 	tqp = hdev->htqp;
276 
277 	for (i = 0; i < hdev->num_tqps; i++) {
278 		tqp->dev = &hdev->pdev->dev;
279 		tqp->index = i;
280 
281 		tqp->q.ae_algo = &ae_algovf;
282 		tqp->q.buf_size = hdev->rx_buf_len;
283 		tqp->q.tx_desc_num = hdev->num_tx_desc;
284 		tqp->q.rx_desc_num = hdev->num_rx_desc;
285 
286 		/* need an extended offset to configure queues >=
287 		 * HCLGEVF_TQP_MAX_SIZE_DEV_V2.
288 		 */
289 		if (i < HCLGEVF_TQP_MAX_SIZE_DEV_V2)
290 			tqp->q.io_base = hdev->hw.hw.io_base +
291 					 HCLGEVF_TQP_REG_OFFSET +
292 					 i * HCLGEVF_TQP_REG_SIZE;
293 		else
294 			tqp->q.io_base = hdev->hw.hw.io_base +
295 					 HCLGEVF_TQP_REG_OFFSET +
296 					 HCLGEVF_TQP_EXT_REG_OFFSET +
297 					 (i - HCLGEVF_TQP_MAX_SIZE_DEV_V2) *
298 					 HCLGEVF_TQP_REG_SIZE;
299 
300 		/* when device supports tx push and has device memory,
301 		 * the queue can execute push mode or doorbell mode on
302 		 * device memory.
303 		 */
304 		if (test_bit(HNAE3_DEV_SUPPORT_TX_PUSH_B, ae_dev->caps))
305 			tqp->q.mem_base = hdev->hw.hw.mem_base +
306 					  HCLGEVF_TQP_MEM_OFFSET(hdev, i);
307 
308 		tqp++;
309 	}
310 
311 	return 0;
312 }
313 
314 static int hclgevf_knic_setup(struct hclgevf_dev *hdev)
315 {
316 	struct hnae3_handle *nic = &hdev->nic;
317 	struct hnae3_knic_private_info *kinfo;
318 	u16 new_tqps = hdev->num_tqps;
319 	unsigned int i;
320 	u8 num_tc = 0;
321 
322 	kinfo = &nic->kinfo;
323 	kinfo->num_tx_desc = hdev->num_tx_desc;
324 	kinfo->num_rx_desc = hdev->num_rx_desc;
325 	kinfo->rx_buf_len = hdev->rx_buf_len;
326 	for (i = 0; i < HCLGE_COMM_MAX_TC_NUM; i++)
327 		if (hdev->hw_tc_map & BIT(i))
328 			num_tc++;
329 
330 	num_tc = num_tc ? num_tc : 1;
331 	kinfo->tc_info.num_tc = num_tc;
332 	kinfo->rss_size = min_t(u16, hdev->rss_size_max, new_tqps / num_tc);
333 	new_tqps = kinfo->rss_size * num_tc;
334 	kinfo->num_tqps = min(new_tqps, hdev->num_tqps);
335 
336 	kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps,
337 				  sizeof(struct hnae3_queue *), GFP_KERNEL);
338 	if (!kinfo->tqp)
339 		return -ENOMEM;
340 
341 	for (i = 0; i < kinfo->num_tqps; i++) {
342 		hdev->htqp[i].q.handle = &hdev->nic;
343 		hdev->htqp[i].q.tqp_index = i;
344 		kinfo->tqp[i] = &hdev->htqp[i].q;
345 	}
346 
347 	/* after init the max rss_size and tqps, adjust the default tqp numbers
348 	 * and rss size with the actual vector numbers
349 	 */
350 	kinfo->num_tqps = min_t(u16, hdev->num_nic_msix - 1, kinfo->num_tqps);
351 	kinfo->rss_size = min_t(u16, kinfo->num_tqps / num_tc,
352 				kinfo->rss_size);
353 
354 	return 0;
355 }
356 
357 static void hclgevf_request_link_info(struct hclgevf_dev *hdev)
358 {
359 	struct hclge_vf_to_pf_msg send_msg;
360 	int status;
361 
362 	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_LINK_STATUS, 0);
363 	status = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
364 	if (status)
365 		dev_err(&hdev->pdev->dev,
366 			"VF failed to fetch link status(%d) from PF", status);
367 }
368 
369 void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state)
370 {
371 	struct hnae3_handle *rhandle = &hdev->roce;
372 	struct hnae3_handle *handle = &hdev->nic;
373 	struct hnae3_client *rclient;
374 	struct hnae3_client *client;
375 
376 	if (test_and_set_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state))
377 		return;
378 
379 	client = handle->client;
380 	rclient = hdev->roce_client;
381 
382 	link_state =
383 		test_bit(HCLGEVF_STATE_DOWN, &hdev->state) ? 0 : link_state;
384 	if (link_state != hdev->hw.mac.link) {
385 		hdev->hw.mac.link = link_state;
386 		client->ops->link_status_change(handle, !!link_state);
387 		if (rclient && rclient->ops->link_status_change)
388 			rclient->ops->link_status_change(rhandle, !!link_state);
389 	}
390 
391 	clear_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state);
392 }
393 
394 static void hclgevf_update_link_mode(struct hclgevf_dev *hdev)
395 {
396 #define HCLGEVF_ADVERTISING	0
397 #define HCLGEVF_SUPPORTED	1
398 
399 	struct hclge_vf_to_pf_msg send_msg;
400 
401 	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_LINK_MODE, 0);
402 	send_msg.data[0] = HCLGEVF_ADVERTISING;
403 	hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
404 	send_msg.data[0] = HCLGEVF_SUPPORTED;
405 	hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
406 }
407 
408 static int hclgevf_set_handle_info(struct hclgevf_dev *hdev)
409 {
410 	struct hnae3_handle *nic = &hdev->nic;
411 	int ret;
412 
413 	nic->ae_algo = &ae_algovf;
414 	nic->pdev = hdev->pdev;
415 	nic->numa_node_mask = hdev->numa_node_mask;
416 	nic->flags |= HNAE3_SUPPORT_VF;
417 	nic->kinfo.io_base = hdev->hw.hw.io_base;
418 
419 	ret = hclgevf_knic_setup(hdev);
420 	if (ret)
421 		dev_err(&hdev->pdev->dev, "VF knic setup failed %d\n",
422 			ret);
423 	return ret;
424 }
425 
426 static void hclgevf_free_vector(struct hclgevf_dev *hdev, int vector_id)
427 {
428 	if (hdev->vector_status[vector_id] == HCLGEVF_INVALID_VPORT) {
429 		dev_warn(&hdev->pdev->dev,
430 			 "vector(vector_id %d) has been freed.\n", vector_id);
431 		return;
432 	}
433 
434 	hdev->vector_status[vector_id] = HCLGEVF_INVALID_VPORT;
435 	hdev->num_msi_left += 1;
436 	hdev->num_msi_used -= 1;
437 }
438 
439 static int hclgevf_get_vector(struct hnae3_handle *handle, u16 vector_num,
440 			      struct hnae3_vector_info *vector_info)
441 {
442 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
443 	struct hnae3_vector_info *vector = vector_info;
444 	int alloc = 0;
445 	int i, j;
446 
447 	vector_num = min_t(u16, hdev->num_nic_msix - 1, vector_num);
448 	vector_num = min(hdev->num_msi_left, vector_num);
449 
450 	for (j = 0; j < vector_num; j++) {
451 		for (i = HCLGEVF_MISC_VECTOR_NUM + 1; i < hdev->num_msi; i++) {
452 			if (hdev->vector_status[i] == HCLGEVF_INVALID_VPORT) {
453 				vector->vector = pci_irq_vector(hdev->pdev, i);
454 				vector->io_addr = hdev->hw.hw.io_base +
455 					HCLGEVF_VECTOR_REG_BASE +
456 					(i - 1) * HCLGEVF_VECTOR_REG_OFFSET;
457 				hdev->vector_status[i] = 0;
458 				hdev->vector_irq[i] = vector->vector;
459 
460 				vector++;
461 				alloc++;
462 
463 				break;
464 			}
465 		}
466 	}
467 	hdev->num_msi_left -= alloc;
468 	hdev->num_msi_used += alloc;
469 
470 	return alloc;
471 }
472 
473 static int hclgevf_get_vector_index(struct hclgevf_dev *hdev, int vector)
474 {
475 	int i;
476 
477 	for (i = 0; i < hdev->num_msi; i++)
478 		if (vector == hdev->vector_irq[i])
479 			return i;
480 
481 	return -EINVAL;
482 }
483 
484 /* for revision 0x20, vf shared the same rss config with pf */
485 static int hclgevf_get_rss_hash_key(struct hclgevf_dev *hdev)
486 {
487 #define HCLGEVF_RSS_MBX_RESP_LEN	8
488 	struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg;
489 	u8 resp_msg[HCLGEVF_RSS_MBX_RESP_LEN];
490 	struct hclge_vf_to_pf_msg send_msg;
491 	u16 msg_num, hash_key_index;
492 	u8 index;
493 	int ret;
494 
495 	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_RSS_KEY, 0);
496 	msg_num = (HCLGE_COMM_RSS_KEY_SIZE + HCLGEVF_RSS_MBX_RESP_LEN - 1) /
497 			HCLGEVF_RSS_MBX_RESP_LEN;
498 	for (index = 0; index < msg_num; index++) {
499 		send_msg.data[0] = index;
500 		ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg,
501 					   HCLGEVF_RSS_MBX_RESP_LEN);
502 		if (ret) {
503 			dev_err(&hdev->pdev->dev,
504 				"VF get rss hash key from PF failed, ret=%d",
505 				ret);
506 			return ret;
507 		}
508 
509 		hash_key_index = HCLGEVF_RSS_MBX_RESP_LEN * index;
510 		if (index == msg_num - 1)
511 			memcpy(&rss_cfg->rss_hash_key[hash_key_index],
512 			       &resp_msg[0],
513 			       HCLGE_COMM_RSS_KEY_SIZE - hash_key_index);
514 		else
515 			memcpy(&rss_cfg->rss_hash_key[hash_key_index],
516 			       &resp_msg[0], HCLGEVF_RSS_MBX_RESP_LEN);
517 	}
518 
519 	return 0;
520 }
521 
522 static int hclgevf_get_rss(struct hnae3_handle *handle, u32 *indir, u8 *key,
523 			   u8 *hfunc)
524 {
525 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
526 	struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg;
527 	int ret;
528 
529 	if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) {
530 		hclge_comm_get_rss_hash_info(rss_cfg, key, hfunc);
531 	} else {
532 		if (hfunc)
533 			*hfunc = ETH_RSS_HASH_TOP;
534 		if (key) {
535 			ret = hclgevf_get_rss_hash_key(hdev);
536 			if (ret)
537 				return ret;
538 			memcpy(key, rss_cfg->rss_hash_key,
539 			       HCLGE_COMM_RSS_KEY_SIZE);
540 		}
541 	}
542 
543 	hclge_comm_get_rss_indir_tbl(rss_cfg, indir,
544 				     hdev->ae_dev->dev_specs.rss_ind_tbl_size);
545 
546 	return 0;
547 }
548 
549 static int hclgevf_set_rss(struct hnae3_handle *handle, const u32 *indir,
550 			   const u8 *key, const u8 hfunc)
551 {
552 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
553 	struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg;
554 	int ret, i;
555 
556 	if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) {
557 		ret = hclge_comm_set_rss_hash_key(rss_cfg, &hdev->hw.hw, key,
558 						  hfunc);
559 		if (ret)
560 			return ret;
561 	}
562 
563 	/* update the shadow RSS table with user specified qids */
564 	for (i = 0; i < hdev->ae_dev->dev_specs.rss_ind_tbl_size; i++)
565 		rss_cfg->rss_indirection_tbl[i] = indir[i];
566 
567 	/* update the hardware */
568 	return hclge_comm_set_rss_indir_table(hdev->ae_dev, &hdev->hw.hw,
569 					      rss_cfg->rss_indirection_tbl);
570 }
571 
572 static int hclgevf_set_rss_tuple(struct hnae3_handle *handle,
573 				 struct ethtool_rxnfc *nfc)
574 {
575 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
576 	int ret;
577 
578 	if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)
579 		return -EOPNOTSUPP;
580 
581 	ret = hclge_comm_set_rss_tuple(hdev->ae_dev, &hdev->hw.hw,
582 				       &hdev->rss_cfg, nfc);
583 	if (ret)
584 		dev_err(&hdev->pdev->dev,
585 		"failed to set rss tuple, ret = %d.\n", ret);
586 
587 	return ret;
588 }
589 
590 static int hclgevf_get_rss_tuple(struct hnae3_handle *handle,
591 				 struct ethtool_rxnfc *nfc)
592 {
593 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
594 	u8 tuple_sets;
595 	int ret;
596 
597 	if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)
598 		return -EOPNOTSUPP;
599 
600 	nfc->data = 0;
601 
602 	ret = hclge_comm_get_rss_tuple(&hdev->rss_cfg, nfc->flow_type,
603 				       &tuple_sets);
604 	if (ret || !tuple_sets)
605 		return ret;
606 
607 	nfc->data = hclge_comm_convert_rss_tuple(tuple_sets);
608 
609 	return 0;
610 }
611 
612 static int hclgevf_get_tc_size(struct hnae3_handle *handle)
613 {
614 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
615 	struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg;
616 
617 	return rss_cfg->rss_size;
618 }
619 
620 static int hclgevf_bind_ring_to_vector(struct hnae3_handle *handle, bool en,
621 				       int vector_id,
622 				       struct hnae3_ring_chain_node *ring_chain)
623 {
624 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
625 	struct hclge_vf_to_pf_msg send_msg;
626 	struct hnae3_ring_chain_node *node;
627 	int status;
628 	int i = 0;
629 
630 	memset(&send_msg, 0, sizeof(send_msg));
631 	send_msg.code = en ? HCLGE_MBX_MAP_RING_TO_VECTOR :
632 		HCLGE_MBX_UNMAP_RING_TO_VECTOR;
633 	send_msg.vector_id = vector_id;
634 
635 	for (node = ring_chain; node; node = node->next) {
636 		send_msg.param[i].ring_type =
637 				hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B);
638 
639 		send_msg.param[i].tqp_index = node->tqp_index;
640 		send_msg.param[i].int_gl_index =
641 					hnae3_get_field(node->int_gl_idx,
642 							HNAE3_RING_GL_IDX_M,
643 							HNAE3_RING_GL_IDX_S);
644 
645 		i++;
646 		if (i == HCLGE_MBX_MAX_RING_CHAIN_PARAM_NUM || !node->next) {
647 			send_msg.ring_num = i;
648 
649 			status = hclgevf_send_mbx_msg(hdev, &send_msg, false,
650 						      NULL, 0);
651 			if (status) {
652 				dev_err(&hdev->pdev->dev,
653 					"Map TQP fail, status is %d.\n",
654 					status);
655 				return status;
656 			}
657 			i = 0;
658 		}
659 	}
660 
661 	return 0;
662 }
663 
664 static int hclgevf_map_ring_to_vector(struct hnae3_handle *handle, int vector,
665 				      struct hnae3_ring_chain_node *ring_chain)
666 {
667 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
668 	int vector_id;
669 
670 	vector_id = hclgevf_get_vector_index(hdev, vector);
671 	if (vector_id < 0) {
672 		dev_err(&handle->pdev->dev,
673 			"Get vector index fail. ret =%d\n", vector_id);
674 		return vector_id;
675 	}
676 
677 	return hclgevf_bind_ring_to_vector(handle, true, vector_id, ring_chain);
678 }
679 
680 static int hclgevf_unmap_ring_from_vector(
681 				struct hnae3_handle *handle,
682 				int vector,
683 				struct hnae3_ring_chain_node *ring_chain)
684 {
685 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
686 	int ret, vector_id;
687 
688 	if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state))
689 		return 0;
690 
691 	vector_id = hclgevf_get_vector_index(hdev, vector);
692 	if (vector_id < 0) {
693 		dev_err(&handle->pdev->dev,
694 			"Get vector index fail. ret =%d\n", vector_id);
695 		return vector_id;
696 	}
697 
698 	ret = hclgevf_bind_ring_to_vector(handle, false, vector_id, ring_chain);
699 	if (ret)
700 		dev_err(&handle->pdev->dev,
701 			"Unmap ring from vector fail. vector=%d, ret =%d\n",
702 			vector_id,
703 			ret);
704 
705 	return ret;
706 }
707 
708 static int hclgevf_put_vector(struct hnae3_handle *handle, int vector)
709 {
710 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
711 	int vector_id;
712 
713 	vector_id = hclgevf_get_vector_index(hdev, vector);
714 	if (vector_id < 0) {
715 		dev_err(&handle->pdev->dev,
716 			"hclgevf_put_vector get vector index fail. ret =%d\n",
717 			vector_id);
718 		return vector_id;
719 	}
720 
721 	hclgevf_free_vector(hdev, vector_id);
722 
723 	return 0;
724 }
725 
726 static int hclgevf_cmd_set_promisc_mode(struct hclgevf_dev *hdev,
727 					bool en_uc_pmc, bool en_mc_pmc,
728 					bool en_bc_pmc)
729 {
730 	struct hnae3_handle *handle = &hdev->nic;
731 	struct hclge_vf_to_pf_msg send_msg;
732 	int ret;
733 
734 	memset(&send_msg, 0, sizeof(send_msg));
735 	send_msg.code = HCLGE_MBX_SET_PROMISC_MODE;
736 	send_msg.en_bc = en_bc_pmc ? 1 : 0;
737 	send_msg.en_uc = en_uc_pmc ? 1 : 0;
738 	send_msg.en_mc = en_mc_pmc ? 1 : 0;
739 	send_msg.en_limit_promisc = test_bit(HNAE3_PFLAG_LIMIT_PROMISC,
740 					     &handle->priv_flags) ? 1 : 0;
741 
742 	ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
743 	if (ret)
744 		dev_err(&hdev->pdev->dev,
745 			"Set promisc mode fail, status is %d.\n", ret);
746 
747 	return ret;
748 }
749 
750 static int hclgevf_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc,
751 				    bool en_mc_pmc)
752 {
753 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
754 	bool en_bc_pmc;
755 
756 	en_bc_pmc = hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2;
757 
758 	return hclgevf_cmd_set_promisc_mode(hdev, en_uc_pmc, en_mc_pmc,
759 					    en_bc_pmc);
760 }
761 
762 static void hclgevf_request_update_promisc_mode(struct hnae3_handle *handle)
763 {
764 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
765 
766 	set_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state);
767 	hclgevf_task_schedule(hdev, 0);
768 }
769 
770 static void hclgevf_sync_promisc_mode(struct hclgevf_dev *hdev)
771 {
772 	struct hnae3_handle *handle = &hdev->nic;
773 	bool en_uc_pmc = handle->netdev_flags & HNAE3_UPE;
774 	bool en_mc_pmc = handle->netdev_flags & HNAE3_MPE;
775 	int ret;
776 
777 	if (test_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state)) {
778 		ret = hclgevf_set_promisc_mode(handle, en_uc_pmc, en_mc_pmc);
779 		if (!ret)
780 			clear_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state);
781 	}
782 }
783 
784 static int hclgevf_tqp_enable_cmd_send(struct hclgevf_dev *hdev, u16 tqp_id,
785 				       u16 stream_id, bool enable)
786 {
787 	struct hclgevf_cfg_com_tqp_queue_cmd *req;
788 	struct hclge_desc desc;
789 
790 	req = (struct hclgevf_cfg_com_tqp_queue_cmd *)desc.data;
791 
792 	hclgevf_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false);
793 	req->tqp_id = cpu_to_le16(tqp_id & HCLGEVF_RING_ID_MASK);
794 	req->stream_id = cpu_to_le16(stream_id);
795 	if (enable)
796 		req->enable |= 1U << HCLGEVF_TQP_ENABLE_B;
797 
798 	return hclgevf_cmd_send(&hdev->hw, &desc, 1);
799 }
800 
801 static int hclgevf_tqp_enable(struct hnae3_handle *handle, bool enable)
802 {
803 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
804 	int ret;
805 	u16 i;
806 
807 	for (i = 0; i < handle->kinfo.num_tqps; i++) {
808 		ret = hclgevf_tqp_enable_cmd_send(hdev, i, 0, enable);
809 		if (ret)
810 			return ret;
811 	}
812 
813 	return 0;
814 }
815 
816 static int hclgevf_get_host_mac_addr(struct hclgevf_dev *hdev, u8 *p)
817 {
818 	struct hclge_vf_to_pf_msg send_msg;
819 	u8 host_mac[ETH_ALEN];
820 	int status;
821 
822 	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_MAC_ADDR, 0);
823 	status = hclgevf_send_mbx_msg(hdev, &send_msg, true, host_mac,
824 				      ETH_ALEN);
825 	if (status) {
826 		dev_err(&hdev->pdev->dev,
827 			"fail to get VF MAC from host %d", status);
828 		return status;
829 	}
830 
831 	ether_addr_copy(p, host_mac);
832 
833 	return 0;
834 }
835 
836 static void hclgevf_get_mac_addr(struct hnae3_handle *handle, u8 *p)
837 {
838 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
839 	u8 host_mac_addr[ETH_ALEN];
840 
841 	if (hclgevf_get_host_mac_addr(hdev, host_mac_addr))
842 		return;
843 
844 	hdev->has_pf_mac = !is_zero_ether_addr(host_mac_addr);
845 	if (hdev->has_pf_mac)
846 		ether_addr_copy(p, host_mac_addr);
847 	else
848 		ether_addr_copy(p, hdev->hw.mac.mac_addr);
849 }
850 
851 static int hclgevf_set_mac_addr(struct hnae3_handle *handle, const void *p,
852 				bool is_first)
853 {
854 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
855 	u8 *old_mac_addr = (u8 *)hdev->hw.mac.mac_addr;
856 	struct hclge_vf_to_pf_msg send_msg;
857 	u8 *new_mac_addr = (u8 *)p;
858 	int status;
859 
860 	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_UNICAST, 0);
861 	send_msg.subcode = HCLGE_MBX_MAC_VLAN_UC_MODIFY;
862 	ether_addr_copy(send_msg.data, new_mac_addr);
863 	if (is_first && !hdev->has_pf_mac)
864 		eth_zero_addr(&send_msg.data[ETH_ALEN]);
865 	else
866 		ether_addr_copy(&send_msg.data[ETH_ALEN], old_mac_addr);
867 	status = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0);
868 	if (!status)
869 		ether_addr_copy(hdev->hw.mac.mac_addr, new_mac_addr);
870 
871 	return status;
872 }
873 
874 static struct hclgevf_mac_addr_node *
875 hclgevf_find_mac_node(struct list_head *list, const u8 *mac_addr)
876 {
877 	struct hclgevf_mac_addr_node *mac_node, *tmp;
878 
879 	list_for_each_entry_safe(mac_node, tmp, list, node)
880 		if (ether_addr_equal(mac_addr, mac_node->mac_addr))
881 			return mac_node;
882 
883 	return NULL;
884 }
885 
886 static void hclgevf_update_mac_node(struct hclgevf_mac_addr_node *mac_node,
887 				    enum HCLGEVF_MAC_NODE_STATE state)
888 {
889 	switch (state) {
890 	/* from set_rx_mode or tmp_add_list */
891 	case HCLGEVF_MAC_TO_ADD:
892 		if (mac_node->state == HCLGEVF_MAC_TO_DEL)
893 			mac_node->state = HCLGEVF_MAC_ACTIVE;
894 		break;
895 	/* only from set_rx_mode */
896 	case HCLGEVF_MAC_TO_DEL:
897 		if (mac_node->state == HCLGEVF_MAC_TO_ADD) {
898 			list_del(&mac_node->node);
899 			kfree(mac_node);
900 		} else {
901 			mac_node->state = HCLGEVF_MAC_TO_DEL;
902 		}
903 		break;
904 	/* only from tmp_add_list, the mac_node->state won't be
905 	 * HCLGEVF_MAC_ACTIVE
906 	 */
907 	case HCLGEVF_MAC_ACTIVE:
908 		if (mac_node->state == HCLGEVF_MAC_TO_ADD)
909 			mac_node->state = HCLGEVF_MAC_ACTIVE;
910 		break;
911 	}
912 }
913 
914 static int hclgevf_update_mac_list(struct hnae3_handle *handle,
915 				   enum HCLGEVF_MAC_NODE_STATE state,
916 				   enum HCLGEVF_MAC_ADDR_TYPE mac_type,
917 				   const unsigned char *addr)
918 {
919 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
920 	struct hclgevf_mac_addr_node *mac_node;
921 	struct list_head *list;
922 
923 	list = (mac_type == HCLGEVF_MAC_ADDR_UC) ?
924 	       &hdev->mac_table.uc_mac_list : &hdev->mac_table.mc_mac_list;
925 
926 	spin_lock_bh(&hdev->mac_table.mac_list_lock);
927 
928 	/* if the mac addr is already in the mac list, no need to add a new
929 	 * one into it, just check the mac addr state, convert it to a new
930 	 * state, or just remove it, or do nothing.
931 	 */
932 	mac_node = hclgevf_find_mac_node(list, addr);
933 	if (mac_node) {
934 		hclgevf_update_mac_node(mac_node, state);
935 		spin_unlock_bh(&hdev->mac_table.mac_list_lock);
936 		return 0;
937 	}
938 	/* if this address is never added, unnecessary to delete */
939 	if (state == HCLGEVF_MAC_TO_DEL) {
940 		spin_unlock_bh(&hdev->mac_table.mac_list_lock);
941 		return -ENOENT;
942 	}
943 
944 	mac_node = kzalloc(sizeof(*mac_node), GFP_ATOMIC);
945 	if (!mac_node) {
946 		spin_unlock_bh(&hdev->mac_table.mac_list_lock);
947 		return -ENOMEM;
948 	}
949 
950 	mac_node->state = state;
951 	ether_addr_copy(mac_node->mac_addr, addr);
952 	list_add_tail(&mac_node->node, list);
953 
954 	spin_unlock_bh(&hdev->mac_table.mac_list_lock);
955 	return 0;
956 }
957 
958 static int hclgevf_add_uc_addr(struct hnae3_handle *handle,
959 			       const unsigned char *addr)
960 {
961 	return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_ADD,
962 				       HCLGEVF_MAC_ADDR_UC, addr);
963 }
964 
965 static int hclgevf_rm_uc_addr(struct hnae3_handle *handle,
966 			      const unsigned char *addr)
967 {
968 	return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_DEL,
969 				       HCLGEVF_MAC_ADDR_UC, addr);
970 }
971 
972 static int hclgevf_add_mc_addr(struct hnae3_handle *handle,
973 			       const unsigned char *addr)
974 {
975 	return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_ADD,
976 				       HCLGEVF_MAC_ADDR_MC, addr);
977 }
978 
979 static int hclgevf_rm_mc_addr(struct hnae3_handle *handle,
980 			      const unsigned char *addr)
981 {
982 	return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_DEL,
983 				       HCLGEVF_MAC_ADDR_MC, addr);
984 }
985 
986 static int hclgevf_add_del_mac_addr(struct hclgevf_dev *hdev,
987 				    struct hclgevf_mac_addr_node *mac_node,
988 				    enum HCLGEVF_MAC_ADDR_TYPE mac_type)
989 {
990 	struct hclge_vf_to_pf_msg send_msg;
991 	u8 code, subcode;
992 
993 	if (mac_type == HCLGEVF_MAC_ADDR_UC) {
994 		code = HCLGE_MBX_SET_UNICAST;
995 		if (mac_node->state == HCLGEVF_MAC_TO_ADD)
996 			subcode = HCLGE_MBX_MAC_VLAN_UC_ADD;
997 		else
998 			subcode = HCLGE_MBX_MAC_VLAN_UC_REMOVE;
999 	} else {
1000 		code = HCLGE_MBX_SET_MULTICAST;
1001 		if (mac_node->state == HCLGEVF_MAC_TO_ADD)
1002 			subcode = HCLGE_MBX_MAC_VLAN_MC_ADD;
1003 		else
1004 			subcode = HCLGE_MBX_MAC_VLAN_MC_REMOVE;
1005 	}
1006 
1007 	hclgevf_build_send_msg(&send_msg, code, subcode);
1008 	ether_addr_copy(send_msg.data, mac_node->mac_addr);
1009 	return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
1010 }
1011 
1012 static void hclgevf_config_mac_list(struct hclgevf_dev *hdev,
1013 				    struct list_head *list,
1014 				    enum HCLGEVF_MAC_ADDR_TYPE mac_type)
1015 {
1016 	char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN];
1017 	struct hclgevf_mac_addr_node *mac_node, *tmp;
1018 	int ret;
1019 
1020 	list_for_each_entry_safe(mac_node, tmp, list, node) {
1021 		ret = hclgevf_add_del_mac_addr(hdev, mac_node, mac_type);
1022 		if  (ret) {
1023 			hnae3_format_mac_addr(format_mac_addr,
1024 					      mac_node->mac_addr);
1025 			dev_err(&hdev->pdev->dev,
1026 				"failed to configure mac %s, state = %d, ret = %d\n",
1027 				format_mac_addr, mac_node->state, ret);
1028 			return;
1029 		}
1030 		if (mac_node->state == HCLGEVF_MAC_TO_ADD) {
1031 			mac_node->state = HCLGEVF_MAC_ACTIVE;
1032 		} else {
1033 			list_del(&mac_node->node);
1034 			kfree(mac_node);
1035 		}
1036 	}
1037 }
1038 
1039 static void hclgevf_sync_from_add_list(struct list_head *add_list,
1040 				       struct list_head *mac_list)
1041 {
1042 	struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node;
1043 
1044 	list_for_each_entry_safe(mac_node, tmp, add_list, node) {
1045 		/* if the mac address from tmp_add_list is not in the
1046 		 * uc/mc_mac_list, it means have received a TO_DEL request
1047 		 * during the time window of sending mac config request to PF
1048 		 * If mac_node state is ACTIVE, then change its state to TO_DEL,
1049 		 * then it will be removed at next time. If is TO_ADD, it means
1050 		 * send TO_ADD request failed, so just remove the mac node.
1051 		 */
1052 		new_node = hclgevf_find_mac_node(mac_list, mac_node->mac_addr);
1053 		if (new_node) {
1054 			hclgevf_update_mac_node(new_node, mac_node->state);
1055 			list_del(&mac_node->node);
1056 			kfree(mac_node);
1057 		} else if (mac_node->state == HCLGEVF_MAC_ACTIVE) {
1058 			mac_node->state = HCLGEVF_MAC_TO_DEL;
1059 			list_move_tail(&mac_node->node, mac_list);
1060 		} else {
1061 			list_del(&mac_node->node);
1062 			kfree(mac_node);
1063 		}
1064 	}
1065 }
1066 
1067 static void hclgevf_sync_from_del_list(struct list_head *del_list,
1068 				       struct list_head *mac_list)
1069 {
1070 	struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node;
1071 
1072 	list_for_each_entry_safe(mac_node, tmp, del_list, node) {
1073 		new_node = hclgevf_find_mac_node(mac_list, mac_node->mac_addr);
1074 		if (new_node) {
1075 			/* If the mac addr is exist in the mac list, it means
1076 			 * received a new request TO_ADD during the time window
1077 			 * of sending mac addr configurrequest to PF, so just
1078 			 * change the mac state to ACTIVE.
1079 			 */
1080 			new_node->state = HCLGEVF_MAC_ACTIVE;
1081 			list_del(&mac_node->node);
1082 			kfree(mac_node);
1083 		} else {
1084 			list_move_tail(&mac_node->node, mac_list);
1085 		}
1086 	}
1087 }
1088 
1089 static void hclgevf_clear_list(struct list_head *list)
1090 {
1091 	struct hclgevf_mac_addr_node *mac_node, *tmp;
1092 
1093 	list_for_each_entry_safe(mac_node, tmp, list, node) {
1094 		list_del(&mac_node->node);
1095 		kfree(mac_node);
1096 	}
1097 }
1098 
1099 static void hclgevf_sync_mac_list(struct hclgevf_dev *hdev,
1100 				  enum HCLGEVF_MAC_ADDR_TYPE mac_type)
1101 {
1102 	struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node;
1103 	struct list_head tmp_add_list, tmp_del_list;
1104 	struct list_head *list;
1105 
1106 	INIT_LIST_HEAD(&tmp_add_list);
1107 	INIT_LIST_HEAD(&tmp_del_list);
1108 
1109 	/* move the mac addr to the tmp_add_list and tmp_del_list, then
1110 	 * we can add/delete these mac addr outside the spin lock
1111 	 */
1112 	list = (mac_type == HCLGEVF_MAC_ADDR_UC) ?
1113 		&hdev->mac_table.uc_mac_list : &hdev->mac_table.mc_mac_list;
1114 
1115 	spin_lock_bh(&hdev->mac_table.mac_list_lock);
1116 
1117 	list_for_each_entry_safe(mac_node, tmp, list, node) {
1118 		switch (mac_node->state) {
1119 		case HCLGEVF_MAC_TO_DEL:
1120 			list_move_tail(&mac_node->node, &tmp_del_list);
1121 			break;
1122 		case HCLGEVF_MAC_TO_ADD:
1123 			new_node = kzalloc(sizeof(*new_node), GFP_ATOMIC);
1124 			if (!new_node)
1125 				goto stop_traverse;
1126 
1127 			ether_addr_copy(new_node->mac_addr, mac_node->mac_addr);
1128 			new_node->state = mac_node->state;
1129 			list_add_tail(&new_node->node, &tmp_add_list);
1130 			break;
1131 		default:
1132 			break;
1133 		}
1134 	}
1135 
1136 stop_traverse:
1137 	spin_unlock_bh(&hdev->mac_table.mac_list_lock);
1138 
1139 	/* delete first, in order to get max mac table space for adding */
1140 	hclgevf_config_mac_list(hdev, &tmp_del_list, mac_type);
1141 	hclgevf_config_mac_list(hdev, &tmp_add_list, mac_type);
1142 
1143 	/* if some mac addresses were added/deleted fail, move back to the
1144 	 * mac_list, and retry at next time.
1145 	 */
1146 	spin_lock_bh(&hdev->mac_table.mac_list_lock);
1147 
1148 	hclgevf_sync_from_del_list(&tmp_del_list, list);
1149 	hclgevf_sync_from_add_list(&tmp_add_list, list);
1150 
1151 	spin_unlock_bh(&hdev->mac_table.mac_list_lock);
1152 }
1153 
1154 static void hclgevf_sync_mac_table(struct hclgevf_dev *hdev)
1155 {
1156 	hclgevf_sync_mac_list(hdev, HCLGEVF_MAC_ADDR_UC);
1157 	hclgevf_sync_mac_list(hdev, HCLGEVF_MAC_ADDR_MC);
1158 }
1159 
1160 static void hclgevf_uninit_mac_list(struct hclgevf_dev *hdev)
1161 {
1162 	spin_lock_bh(&hdev->mac_table.mac_list_lock);
1163 
1164 	hclgevf_clear_list(&hdev->mac_table.uc_mac_list);
1165 	hclgevf_clear_list(&hdev->mac_table.mc_mac_list);
1166 
1167 	spin_unlock_bh(&hdev->mac_table.mac_list_lock);
1168 }
1169 
1170 static int hclgevf_enable_vlan_filter(struct hnae3_handle *handle, bool enable)
1171 {
1172 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1173 	struct hnae3_ae_dev *ae_dev = hdev->ae_dev;
1174 	struct hclge_vf_to_pf_msg send_msg;
1175 
1176 	if (!test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps))
1177 		return -EOPNOTSUPP;
1178 
1179 	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN,
1180 			       HCLGE_MBX_ENABLE_VLAN_FILTER);
1181 	send_msg.data[0] = enable ? 1 : 0;
1182 
1183 	return hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0);
1184 }
1185 
1186 static int hclgevf_set_vlan_filter(struct hnae3_handle *handle,
1187 				   __be16 proto, u16 vlan_id,
1188 				   bool is_kill)
1189 {
1190 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1191 	struct hclge_mbx_vlan_filter *vlan_filter;
1192 	struct hclge_vf_to_pf_msg send_msg;
1193 	int ret;
1194 
1195 	if (vlan_id > HCLGEVF_MAX_VLAN_ID)
1196 		return -EINVAL;
1197 
1198 	if (proto != htons(ETH_P_8021Q))
1199 		return -EPROTONOSUPPORT;
1200 
1201 	/* When device is resetting or reset failed, firmware is unable to
1202 	 * handle mailbox. Just record the vlan id, and remove it after
1203 	 * reset finished.
1204 	 */
1205 	if ((test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) ||
1206 	     test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) && is_kill) {
1207 		set_bit(vlan_id, hdev->vlan_del_fail_bmap);
1208 		return -EBUSY;
1209 	} else if (!is_kill && test_bit(vlan_id, hdev->vlan_del_fail_bmap)) {
1210 		clear_bit(vlan_id, hdev->vlan_del_fail_bmap);
1211 	}
1212 
1213 	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN,
1214 			       HCLGE_MBX_VLAN_FILTER);
1215 	vlan_filter = (struct hclge_mbx_vlan_filter *)send_msg.data;
1216 	vlan_filter->is_kill = is_kill;
1217 	vlan_filter->vlan_id = cpu_to_le16(vlan_id);
1218 	vlan_filter->proto = cpu_to_le16(be16_to_cpu(proto));
1219 
1220 	/* when remove hw vlan filter failed, record the vlan id,
1221 	 * and try to remove it from hw later, to be consistence
1222 	 * with stack.
1223 	 */
1224 	ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0);
1225 	if (is_kill && ret)
1226 		set_bit(vlan_id, hdev->vlan_del_fail_bmap);
1227 
1228 	return ret;
1229 }
1230 
1231 static void hclgevf_sync_vlan_filter(struct hclgevf_dev *hdev)
1232 {
1233 #define HCLGEVF_MAX_SYNC_COUNT	60
1234 	struct hnae3_handle *handle = &hdev->nic;
1235 	int ret, sync_cnt = 0;
1236 	u16 vlan_id;
1237 
1238 	if (bitmap_empty(hdev->vlan_del_fail_bmap, VLAN_N_VID))
1239 		return;
1240 
1241 	rtnl_lock();
1242 	vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID);
1243 	while (vlan_id != VLAN_N_VID) {
1244 		ret = hclgevf_set_vlan_filter(handle, htons(ETH_P_8021Q),
1245 					      vlan_id, true);
1246 		if (ret)
1247 			break;
1248 
1249 		clear_bit(vlan_id, hdev->vlan_del_fail_bmap);
1250 		sync_cnt++;
1251 		if (sync_cnt >= HCLGEVF_MAX_SYNC_COUNT)
1252 			break;
1253 
1254 		vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID);
1255 	}
1256 	rtnl_unlock();
1257 }
1258 
1259 static int hclgevf_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable)
1260 {
1261 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1262 	struct hclge_vf_to_pf_msg send_msg;
1263 
1264 	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN,
1265 			       HCLGE_MBX_VLAN_RX_OFF_CFG);
1266 	send_msg.data[0] = enable ? 1 : 0;
1267 	return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
1268 }
1269 
1270 static int hclgevf_reset_tqp(struct hnae3_handle *handle)
1271 {
1272 #define HCLGEVF_RESET_ALL_QUEUE_DONE	1U
1273 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1274 	struct hclge_vf_to_pf_msg send_msg;
1275 	u8 return_status = 0;
1276 	int ret;
1277 	u16 i;
1278 
1279 	/* disable vf queue before send queue reset msg to PF */
1280 	ret = hclgevf_tqp_enable(handle, false);
1281 	if (ret) {
1282 		dev_err(&hdev->pdev->dev, "failed to disable tqp, ret = %d\n",
1283 			ret);
1284 		return ret;
1285 	}
1286 
1287 	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_QUEUE_RESET, 0);
1288 
1289 	ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, &return_status,
1290 				   sizeof(return_status));
1291 	if (ret || return_status == HCLGEVF_RESET_ALL_QUEUE_DONE)
1292 		return ret;
1293 
1294 	for (i = 1; i < handle->kinfo.num_tqps; i++) {
1295 		hclgevf_build_send_msg(&send_msg, HCLGE_MBX_QUEUE_RESET, 0);
1296 		*(__le16 *)send_msg.data = cpu_to_le16(i);
1297 		ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0);
1298 		if (ret)
1299 			return ret;
1300 	}
1301 
1302 	return 0;
1303 }
1304 
1305 static int hclgevf_set_mtu(struct hnae3_handle *handle, int new_mtu)
1306 {
1307 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1308 	struct hclge_mbx_mtu_info *mtu_info;
1309 	struct hclge_vf_to_pf_msg send_msg;
1310 
1311 	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_MTU, 0);
1312 	mtu_info = (struct hclge_mbx_mtu_info *)send_msg.data;
1313 	mtu_info->mtu = cpu_to_le32(new_mtu);
1314 
1315 	return hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0);
1316 }
1317 
1318 static int hclgevf_notify_client(struct hclgevf_dev *hdev,
1319 				 enum hnae3_reset_notify_type type)
1320 {
1321 	struct hnae3_client *client = hdev->nic_client;
1322 	struct hnae3_handle *handle = &hdev->nic;
1323 	int ret;
1324 
1325 	if (!test_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state) ||
1326 	    !client)
1327 		return 0;
1328 
1329 	if (!client->ops->reset_notify)
1330 		return -EOPNOTSUPP;
1331 
1332 	ret = client->ops->reset_notify(handle, type);
1333 	if (ret)
1334 		dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n",
1335 			type, ret);
1336 
1337 	return ret;
1338 }
1339 
1340 static int hclgevf_notify_roce_client(struct hclgevf_dev *hdev,
1341 				      enum hnae3_reset_notify_type type)
1342 {
1343 	struct hnae3_client *client = hdev->roce_client;
1344 	struct hnae3_handle *handle = &hdev->roce;
1345 	int ret;
1346 
1347 	if (!test_bit(HCLGEVF_STATE_ROCE_REGISTERED, &hdev->state) || !client)
1348 		return 0;
1349 
1350 	if (!client->ops->reset_notify)
1351 		return -EOPNOTSUPP;
1352 
1353 	ret = client->ops->reset_notify(handle, type);
1354 	if (ret)
1355 		dev_err(&hdev->pdev->dev, "notify roce client failed %d(%d)",
1356 			type, ret);
1357 	return ret;
1358 }
1359 
1360 static int hclgevf_reset_wait(struct hclgevf_dev *hdev)
1361 {
1362 #define HCLGEVF_RESET_WAIT_US	20000
1363 #define HCLGEVF_RESET_WAIT_CNT	2000
1364 #define HCLGEVF_RESET_WAIT_TIMEOUT_US	\
1365 	(HCLGEVF_RESET_WAIT_US * HCLGEVF_RESET_WAIT_CNT)
1366 
1367 	u32 val;
1368 	int ret;
1369 
1370 	if (hdev->reset_type == HNAE3_VF_RESET)
1371 		ret = readl_poll_timeout(hdev->hw.hw.io_base +
1372 					 HCLGEVF_VF_RST_ING, val,
1373 					 !(val & HCLGEVF_VF_RST_ING_BIT),
1374 					 HCLGEVF_RESET_WAIT_US,
1375 					 HCLGEVF_RESET_WAIT_TIMEOUT_US);
1376 	else
1377 		ret = readl_poll_timeout(hdev->hw.hw.io_base +
1378 					 HCLGEVF_RST_ING, val,
1379 					 !(val & HCLGEVF_RST_ING_BITS),
1380 					 HCLGEVF_RESET_WAIT_US,
1381 					 HCLGEVF_RESET_WAIT_TIMEOUT_US);
1382 
1383 	/* hardware completion status should be available by this time */
1384 	if (ret) {
1385 		dev_err(&hdev->pdev->dev,
1386 			"couldn't get reset done status from h/w, timeout!\n");
1387 		return ret;
1388 	}
1389 
1390 	/* we will wait a bit more to let reset of the stack to complete. This
1391 	 * might happen in case reset assertion was made by PF. Yes, this also
1392 	 * means we might end up waiting bit more even for VF reset.
1393 	 */
1394 	if (hdev->reset_type == HNAE3_VF_FULL_RESET)
1395 		msleep(5000);
1396 	else
1397 		msleep(500);
1398 
1399 	return 0;
1400 }
1401 
1402 static void hclgevf_reset_handshake(struct hclgevf_dev *hdev, bool enable)
1403 {
1404 	u32 reg_val;
1405 
1406 	reg_val = hclgevf_read_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG);
1407 	if (enable)
1408 		reg_val |= HCLGEVF_NIC_SW_RST_RDY;
1409 	else
1410 		reg_val &= ~HCLGEVF_NIC_SW_RST_RDY;
1411 
1412 	hclgevf_write_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG,
1413 			  reg_val);
1414 }
1415 
1416 static int hclgevf_reset_stack(struct hclgevf_dev *hdev)
1417 {
1418 	int ret;
1419 
1420 	/* uninitialize the nic client */
1421 	ret = hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT);
1422 	if (ret)
1423 		return ret;
1424 
1425 	/* re-initialize the hclge device */
1426 	ret = hclgevf_reset_hdev(hdev);
1427 	if (ret) {
1428 		dev_err(&hdev->pdev->dev,
1429 			"hclge device re-init failed, VF is disabled!\n");
1430 		return ret;
1431 	}
1432 
1433 	/* bring up the nic client again */
1434 	ret = hclgevf_notify_client(hdev, HNAE3_INIT_CLIENT);
1435 	if (ret)
1436 		return ret;
1437 
1438 	/* clear handshake status with IMP */
1439 	hclgevf_reset_handshake(hdev, false);
1440 
1441 	/* bring up the nic to enable TX/RX again */
1442 	return hclgevf_notify_client(hdev, HNAE3_UP_CLIENT);
1443 }
1444 
1445 static int hclgevf_reset_prepare_wait(struct hclgevf_dev *hdev)
1446 {
1447 #define HCLGEVF_RESET_SYNC_TIME 100
1448 
1449 	if (hdev->reset_type == HNAE3_VF_FUNC_RESET) {
1450 		struct hclge_vf_to_pf_msg send_msg;
1451 		int ret;
1452 
1453 		hclgevf_build_send_msg(&send_msg, HCLGE_MBX_RESET, 0);
1454 		ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0);
1455 		if (ret) {
1456 			dev_err(&hdev->pdev->dev,
1457 				"failed to assert VF reset, ret = %d\n", ret);
1458 			return ret;
1459 		}
1460 		hdev->rst_stats.vf_func_rst_cnt++;
1461 	}
1462 
1463 	set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state);
1464 	/* inform hardware that preparatory work is done */
1465 	msleep(HCLGEVF_RESET_SYNC_TIME);
1466 	hclgevf_reset_handshake(hdev, true);
1467 	dev_info(&hdev->pdev->dev, "prepare reset(%d) wait done\n",
1468 		 hdev->reset_type);
1469 
1470 	return 0;
1471 }
1472 
1473 static void hclgevf_dump_rst_info(struct hclgevf_dev *hdev)
1474 {
1475 	dev_info(&hdev->pdev->dev, "VF function reset count: %u\n",
1476 		 hdev->rst_stats.vf_func_rst_cnt);
1477 	dev_info(&hdev->pdev->dev, "FLR reset count: %u\n",
1478 		 hdev->rst_stats.flr_rst_cnt);
1479 	dev_info(&hdev->pdev->dev, "VF reset count: %u\n",
1480 		 hdev->rst_stats.vf_rst_cnt);
1481 	dev_info(&hdev->pdev->dev, "reset done count: %u\n",
1482 		 hdev->rst_stats.rst_done_cnt);
1483 	dev_info(&hdev->pdev->dev, "HW reset done count: %u\n",
1484 		 hdev->rst_stats.hw_rst_done_cnt);
1485 	dev_info(&hdev->pdev->dev, "reset count: %u\n",
1486 		 hdev->rst_stats.rst_cnt);
1487 	dev_info(&hdev->pdev->dev, "reset fail count: %u\n",
1488 		 hdev->rst_stats.rst_fail_cnt);
1489 	dev_info(&hdev->pdev->dev, "vector0 interrupt enable status: 0x%x\n",
1490 		 hclgevf_read_dev(&hdev->hw, HCLGEVF_MISC_VECTOR_REG_BASE));
1491 	dev_info(&hdev->pdev->dev, "vector0 interrupt status: 0x%x\n",
1492 		 hclgevf_read_dev(&hdev->hw, HCLGE_COMM_VECTOR0_CMDQ_STATE_REG));
1493 	dev_info(&hdev->pdev->dev, "handshake status: 0x%x\n",
1494 		 hclgevf_read_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG));
1495 	dev_info(&hdev->pdev->dev, "function reset status: 0x%x\n",
1496 		 hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING));
1497 	dev_info(&hdev->pdev->dev, "hdev state: 0x%lx\n", hdev->state);
1498 }
1499 
1500 static void hclgevf_reset_err_handle(struct hclgevf_dev *hdev)
1501 {
1502 	/* recover handshake status with IMP when reset fail */
1503 	hclgevf_reset_handshake(hdev, true);
1504 	hdev->rst_stats.rst_fail_cnt++;
1505 	dev_err(&hdev->pdev->dev, "failed to reset VF(%u)\n",
1506 		hdev->rst_stats.rst_fail_cnt);
1507 
1508 	if (hdev->rst_stats.rst_fail_cnt < HCLGEVF_RESET_MAX_FAIL_CNT)
1509 		set_bit(hdev->reset_type, &hdev->reset_pending);
1510 
1511 	if (hclgevf_is_reset_pending(hdev)) {
1512 		set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state);
1513 		hclgevf_reset_task_schedule(hdev);
1514 	} else {
1515 		set_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state);
1516 		hclgevf_dump_rst_info(hdev);
1517 	}
1518 }
1519 
1520 static int hclgevf_reset_prepare(struct hclgevf_dev *hdev)
1521 {
1522 	int ret;
1523 
1524 	hdev->rst_stats.rst_cnt++;
1525 
1526 	/* perform reset of the stack & ae device for a client */
1527 	ret = hclgevf_notify_roce_client(hdev, HNAE3_DOWN_CLIENT);
1528 	if (ret)
1529 		return ret;
1530 
1531 	rtnl_lock();
1532 	/* bring down the nic to stop any ongoing TX/RX */
1533 	ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT);
1534 	rtnl_unlock();
1535 	if (ret)
1536 		return ret;
1537 
1538 	return hclgevf_reset_prepare_wait(hdev);
1539 }
1540 
1541 static int hclgevf_reset_rebuild(struct hclgevf_dev *hdev)
1542 {
1543 	int ret;
1544 
1545 	hdev->rst_stats.hw_rst_done_cnt++;
1546 	ret = hclgevf_notify_roce_client(hdev, HNAE3_UNINIT_CLIENT);
1547 	if (ret)
1548 		return ret;
1549 
1550 	rtnl_lock();
1551 	/* now, re-initialize the nic client and ae device */
1552 	ret = hclgevf_reset_stack(hdev);
1553 	rtnl_unlock();
1554 	if (ret) {
1555 		dev_err(&hdev->pdev->dev, "failed to reset VF stack\n");
1556 		return ret;
1557 	}
1558 
1559 	ret = hclgevf_notify_roce_client(hdev, HNAE3_INIT_CLIENT);
1560 	/* ignore RoCE notify error if it fails HCLGEVF_RESET_MAX_FAIL_CNT - 1
1561 	 * times
1562 	 */
1563 	if (ret &&
1564 	    hdev->rst_stats.rst_fail_cnt < HCLGEVF_RESET_MAX_FAIL_CNT - 1)
1565 		return ret;
1566 
1567 	ret = hclgevf_notify_roce_client(hdev, HNAE3_UP_CLIENT);
1568 	if (ret)
1569 		return ret;
1570 
1571 	hdev->last_reset_time = jiffies;
1572 	hdev->rst_stats.rst_done_cnt++;
1573 	hdev->rst_stats.rst_fail_cnt = 0;
1574 	clear_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state);
1575 
1576 	return 0;
1577 }
1578 
1579 static void hclgevf_reset(struct hclgevf_dev *hdev)
1580 {
1581 	if (hclgevf_reset_prepare(hdev))
1582 		goto err_reset;
1583 
1584 	/* check if VF could successfully fetch the hardware reset completion
1585 	 * status from the hardware
1586 	 */
1587 	if (hclgevf_reset_wait(hdev)) {
1588 		/* can't do much in this situation, will disable VF */
1589 		dev_err(&hdev->pdev->dev,
1590 			"failed to fetch H/W reset completion status\n");
1591 		goto err_reset;
1592 	}
1593 
1594 	if (hclgevf_reset_rebuild(hdev))
1595 		goto err_reset;
1596 
1597 	return;
1598 
1599 err_reset:
1600 	hclgevf_reset_err_handle(hdev);
1601 }
1602 
1603 static enum hnae3_reset_type hclgevf_get_reset_level(unsigned long *addr)
1604 {
1605 	enum hnae3_reset_type rst_level = HNAE3_NONE_RESET;
1606 
1607 	/* return the highest priority reset level amongst all */
1608 	if (test_bit(HNAE3_VF_RESET, addr)) {
1609 		rst_level = HNAE3_VF_RESET;
1610 		clear_bit(HNAE3_VF_RESET, addr);
1611 		clear_bit(HNAE3_VF_PF_FUNC_RESET, addr);
1612 		clear_bit(HNAE3_VF_FUNC_RESET, addr);
1613 	} else if (test_bit(HNAE3_VF_FULL_RESET, addr)) {
1614 		rst_level = HNAE3_VF_FULL_RESET;
1615 		clear_bit(HNAE3_VF_FULL_RESET, addr);
1616 		clear_bit(HNAE3_VF_FUNC_RESET, addr);
1617 	} else if (test_bit(HNAE3_VF_PF_FUNC_RESET, addr)) {
1618 		rst_level = HNAE3_VF_PF_FUNC_RESET;
1619 		clear_bit(HNAE3_VF_PF_FUNC_RESET, addr);
1620 		clear_bit(HNAE3_VF_FUNC_RESET, addr);
1621 	} else if (test_bit(HNAE3_VF_FUNC_RESET, addr)) {
1622 		rst_level = HNAE3_VF_FUNC_RESET;
1623 		clear_bit(HNAE3_VF_FUNC_RESET, addr);
1624 	} else if (test_bit(HNAE3_FLR_RESET, addr)) {
1625 		rst_level = HNAE3_FLR_RESET;
1626 		clear_bit(HNAE3_FLR_RESET, addr);
1627 	}
1628 
1629 	return rst_level;
1630 }
1631 
1632 static void hclgevf_reset_event(struct pci_dev *pdev,
1633 				struct hnae3_handle *handle)
1634 {
1635 	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
1636 	struct hclgevf_dev *hdev = ae_dev->priv;
1637 
1638 	dev_info(&hdev->pdev->dev, "received reset request from VF enet\n");
1639 
1640 	if (hdev->default_reset_request)
1641 		hdev->reset_level =
1642 			hclgevf_get_reset_level(&hdev->default_reset_request);
1643 	else
1644 		hdev->reset_level = HNAE3_VF_FUNC_RESET;
1645 
1646 	/* reset of this VF requested */
1647 	set_bit(HCLGEVF_RESET_REQUESTED, &hdev->reset_state);
1648 	hclgevf_reset_task_schedule(hdev);
1649 
1650 	hdev->last_reset_time = jiffies;
1651 }
1652 
1653 static void hclgevf_set_def_reset_request(struct hnae3_ae_dev *ae_dev,
1654 					  enum hnae3_reset_type rst_type)
1655 {
1656 	struct hclgevf_dev *hdev = ae_dev->priv;
1657 
1658 	set_bit(rst_type, &hdev->default_reset_request);
1659 }
1660 
1661 static void hclgevf_enable_vector(struct hclgevf_misc_vector *vector, bool en)
1662 {
1663 	writel(en ? 1 : 0, vector->addr);
1664 }
1665 
1666 static void hclgevf_reset_prepare_general(struct hnae3_ae_dev *ae_dev,
1667 					  enum hnae3_reset_type rst_type)
1668 {
1669 #define HCLGEVF_RESET_RETRY_WAIT_MS	500
1670 #define HCLGEVF_RESET_RETRY_CNT		5
1671 
1672 	struct hclgevf_dev *hdev = ae_dev->priv;
1673 	int retry_cnt = 0;
1674 	int ret;
1675 
1676 	while (retry_cnt++ < HCLGEVF_RESET_RETRY_CNT) {
1677 		down(&hdev->reset_sem);
1678 		set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state);
1679 		hdev->reset_type = rst_type;
1680 		ret = hclgevf_reset_prepare(hdev);
1681 		if (!ret && !hdev->reset_pending)
1682 			break;
1683 
1684 		dev_err(&hdev->pdev->dev,
1685 			"failed to prepare to reset, ret=%d, reset_pending:0x%lx, retry_cnt:%d\n",
1686 			ret, hdev->reset_pending, retry_cnt);
1687 		clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state);
1688 		up(&hdev->reset_sem);
1689 		msleep(HCLGEVF_RESET_RETRY_WAIT_MS);
1690 	}
1691 
1692 	/* disable misc vector before reset done */
1693 	hclgevf_enable_vector(&hdev->misc_vector, false);
1694 
1695 	if (hdev->reset_type == HNAE3_FLR_RESET)
1696 		hdev->rst_stats.flr_rst_cnt++;
1697 }
1698 
1699 static void hclgevf_reset_done(struct hnae3_ae_dev *ae_dev)
1700 {
1701 	struct hclgevf_dev *hdev = ae_dev->priv;
1702 	int ret;
1703 
1704 	hclgevf_enable_vector(&hdev->misc_vector, true);
1705 
1706 	ret = hclgevf_reset_rebuild(hdev);
1707 	if (ret)
1708 		dev_warn(&hdev->pdev->dev, "fail to rebuild, ret=%d\n",
1709 			 ret);
1710 
1711 	hdev->reset_type = HNAE3_NONE_RESET;
1712 	clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state);
1713 	up(&hdev->reset_sem);
1714 }
1715 
1716 static u32 hclgevf_get_fw_version(struct hnae3_handle *handle)
1717 {
1718 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1719 
1720 	return hdev->fw_version;
1721 }
1722 
1723 static void hclgevf_get_misc_vector(struct hclgevf_dev *hdev)
1724 {
1725 	struct hclgevf_misc_vector *vector = &hdev->misc_vector;
1726 
1727 	vector->vector_irq = pci_irq_vector(hdev->pdev,
1728 					    HCLGEVF_MISC_VECTOR_NUM);
1729 	vector->addr = hdev->hw.hw.io_base + HCLGEVF_MISC_VECTOR_REG_BASE;
1730 	/* vector status always valid for Vector 0 */
1731 	hdev->vector_status[HCLGEVF_MISC_VECTOR_NUM] = 0;
1732 	hdev->vector_irq[HCLGEVF_MISC_VECTOR_NUM] = vector->vector_irq;
1733 
1734 	hdev->num_msi_left -= 1;
1735 	hdev->num_msi_used += 1;
1736 }
1737 
1738 void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev)
1739 {
1740 	if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) &&
1741 	    test_bit(HCLGEVF_STATE_SERVICE_INITED, &hdev->state) &&
1742 	    !test_and_set_bit(HCLGEVF_STATE_RST_SERVICE_SCHED,
1743 			      &hdev->state))
1744 		mod_delayed_work(hclgevf_wq, &hdev->service_task, 0);
1745 }
1746 
1747 void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev)
1748 {
1749 	if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) &&
1750 	    !test_and_set_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED,
1751 			      &hdev->state))
1752 		mod_delayed_work(hclgevf_wq, &hdev->service_task, 0);
1753 }
1754 
1755 static void hclgevf_task_schedule(struct hclgevf_dev *hdev,
1756 				  unsigned long delay)
1757 {
1758 	if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) &&
1759 	    !test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state))
1760 		mod_delayed_work(hclgevf_wq, &hdev->service_task, delay);
1761 }
1762 
1763 static void hclgevf_reset_service_task(struct hclgevf_dev *hdev)
1764 {
1765 #define	HCLGEVF_MAX_RESET_ATTEMPTS_CNT	3
1766 
1767 	if (!test_and_clear_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state))
1768 		return;
1769 
1770 	down(&hdev->reset_sem);
1771 	set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state);
1772 
1773 	if (test_and_clear_bit(HCLGEVF_RESET_PENDING,
1774 			       &hdev->reset_state)) {
1775 		/* PF has intimated that it is about to reset the hardware.
1776 		 * We now have to poll & check if hardware has actually
1777 		 * completed the reset sequence. On hardware reset completion,
1778 		 * VF needs to reset the client and ae device.
1779 		 */
1780 		hdev->reset_attempts = 0;
1781 
1782 		hdev->last_reset_time = jiffies;
1783 		hdev->reset_type =
1784 			hclgevf_get_reset_level(&hdev->reset_pending);
1785 		if (hdev->reset_type != HNAE3_NONE_RESET)
1786 			hclgevf_reset(hdev);
1787 	} else if (test_and_clear_bit(HCLGEVF_RESET_REQUESTED,
1788 				      &hdev->reset_state)) {
1789 		/* we could be here when either of below happens:
1790 		 * 1. reset was initiated due to watchdog timeout caused by
1791 		 *    a. IMP was earlier reset and our TX got choked down and
1792 		 *       which resulted in watchdog reacting and inducing VF
1793 		 *       reset. This also means our cmdq would be unreliable.
1794 		 *    b. problem in TX due to other lower layer(example link
1795 		 *       layer not functioning properly etc.)
1796 		 * 2. VF reset might have been initiated due to some config
1797 		 *    change.
1798 		 *
1799 		 * NOTE: Theres no clear way to detect above cases than to react
1800 		 * to the response of PF for this reset request. PF will ack the
1801 		 * 1b and 2. cases but we will not get any intimation about 1a
1802 		 * from PF as cmdq would be in unreliable state i.e. mailbox
1803 		 * communication between PF and VF would be broken.
1804 		 *
1805 		 * if we are never geting into pending state it means either:
1806 		 * 1. PF is not receiving our request which could be due to IMP
1807 		 *    reset
1808 		 * 2. PF is screwed
1809 		 * We cannot do much for 2. but to check first we can try reset
1810 		 * our PCIe + stack and see if it alleviates the problem.
1811 		 */
1812 		if (hdev->reset_attempts > HCLGEVF_MAX_RESET_ATTEMPTS_CNT) {
1813 			/* prepare for full reset of stack + pcie interface */
1814 			set_bit(HNAE3_VF_FULL_RESET, &hdev->reset_pending);
1815 
1816 			/* "defer" schedule the reset task again */
1817 			set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state);
1818 		} else {
1819 			hdev->reset_attempts++;
1820 
1821 			set_bit(hdev->reset_level, &hdev->reset_pending);
1822 			set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state);
1823 		}
1824 		hclgevf_reset_task_schedule(hdev);
1825 	}
1826 
1827 	hdev->reset_type = HNAE3_NONE_RESET;
1828 	clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state);
1829 	up(&hdev->reset_sem);
1830 }
1831 
1832 static void hclgevf_mailbox_service_task(struct hclgevf_dev *hdev)
1833 {
1834 	if (!test_and_clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state))
1835 		return;
1836 
1837 	if (test_and_set_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state))
1838 		return;
1839 
1840 	hclgevf_mbx_async_handler(hdev);
1841 
1842 	clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state);
1843 }
1844 
1845 static void hclgevf_keep_alive(struct hclgevf_dev *hdev)
1846 {
1847 	struct hclge_vf_to_pf_msg send_msg;
1848 	int ret;
1849 
1850 	if (test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state))
1851 		return;
1852 
1853 	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_KEEP_ALIVE, 0);
1854 	ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
1855 	if (ret)
1856 		dev_err(&hdev->pdev->dev,
1857 			"VF sends keep alive cmd failed(=%d)\n", ret);
1858 }
1859 
1860 static void hclgevf_periodic_service_task(struct hclgevf_dev *hdev)
1861 {
1862 	unsigned long delta = round_jiffies_relative(HZ);
1863 	struct hnae3_handle *handle = &hdev->nic;
1864 
1865 	if (test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state) ||
1866 	    test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state))
1867 		return;
1868 
1869 	if (time_is_after_jiffies(hdev->last_serv_processed + HZ)) {
1870 		delta = jiffies - hdev->last_serv_processed;
1871 
1872 		if (delta < round_jiffies_relative(HZ)) {
1873 			delta = round_jiffies_relative(HZ) - delta;
1874 			goto out;
1875 		}
1876 	}
1877 
1878 	hdev->serv_processed_cnt++;
1879 	if (!(hdev->serv_processed_cnt % HCLGEVF_KEEP_ALIVE_TASK_INTERVAL))
1880 		hclgevf_keep_alive(hdev);
1881 
1882 	if (test_bit(HCLGEVF_STATE_DOWN, &hdev->state)) {
1883 		hdev->last_serv_processed = jiffies;
1884 		goto out;
1885 	}
1886 
1887 	if (!(hdev->serv_processed_cnt % HCLGEVF_STATS_TIMER_INTERVAL))
1888 		hclge_comm_tqps_update_stats(handle, &hdev->hw.hw);
1889 
1890 	/* VF does not need to request link status when this bit is set, because
1891 	 * PF will push its link status to VFs when link status changed.
1892 	 */
1893 	if (!test_bit(HCLGEVF_STATE_PF_PUSH_LINK_STATUS, &hdev->state))
1894 		hclgevf_request_link_info(hdev);
1895 
1896 	hclgevf_update_link_mode(hdev);
1897 
1898 	hclgevf_sync_vlan_filter(hdev);
1899 
1900 	hclgevf_sync_mac_table(hdev);
1901 
1902 	hclgevf_sync_promisc_mode(hdev);
1903 
1904 	hdev->last_serv_processed = jiffies;
1905 
1906 out:
1907 	hclgevf_task_schedule(hdev, delta);
1908 }
1909 
1910 static void hclgevf_service_task(struct work_struct *work)
1911 {
1912 	struct hclgevf_dev *hdev = container_of(work, struct hclgevf_dev,
1913 						service_task.work);
1914 
1915 	hclgevf_reset_service_task(hdev);
1916 	hclgevf_mailbox_service_task(hdev);
1917 	hclgevf_periodic_service_task(hdev);
1918 
1919 	/* Handle reset and mbx again in case periodical task delays the
1920 	 * handling by calling hclgevf_task_schedule() in
1921 	 * hclgevf_periodic_service_task()
1922 	 */
1923 	hclgevf_reset_service_task(hdev);
1924 	hclgevf_mailbox_service_task(hdev);
1925 }
1926 
1927 static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regclr)
1928 {
1929 	hclgevf_write_dev(&hdev->hw, HCLGE_COMM_VECTOR0_CMDQ_SRC_REG, regclr);
1930 }
1931 
1932 static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev,
1933 						      u32 *clearval)
1934 {
1935 	u32 val, cmdq_stat_reg, rst_ing_reg;
1936 
1937 	/* fetch the events from their corresponding regs */
1938 	cmdq_stat_reg = hclgevf_read_dev(&hdev->hw,
1939 					 HCLGE_COMM_VECTOR0_CMDQ_STATE_REG);
1940 	if (BIT(HCLGEVF_VECTOR0_RST_INT_B) & cmdq_stat_reg) {
1941 		rst_ing_reg = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING);
1942 		dev_info(&hdev->pdev->dev,
1943 			 "receive reset interrupt 0x%x!\n", rst_ing_reg);
1944 		set_bit(HNAE3_VF_RESET, &hdev->reset_pending);
1945 		set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state);
1946 		set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state);
1947 		*clearval = ~(1U << HCLGEVF_VECTOR0_RST_INT_B);
1948 		hdev->rst_stats.vf_rst_cnt++;
1949 		/* set up VF hardware reset status, its PF will clear
1950 		 * this status when PF has initialized done.
1951 		 */
1952 		val = hclgevf_read_dev(&hdev->hw, HCLGEVF_VF_RST_ING);
1953 		hclgevf_write_dev(&hdev->hw, HCLGEVF_VF_RST_ING,
1954 				  val | HCLGEVF_VF_RST_ING_BIT);
1955 		return HCLGEVF_VECTOR0_EVENT_RST;
1956 	}
1957 
1958 	/* check for vector0 mailbox(=CMDQ RX) event source */
1959 	if (BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) {
1960 		/* for revision 0x21, clearing interrupt is writing bit 0
1961 		 * to the clear register, writing bit 1 means to keep the
1962 		 * old value.
1963 		 * for revision 0x20, the clear register is a read & write
1964 		 * register, so we should just write 0 to the bit we are
1965 		 * handling, and keep other bits as cmdq_stat_reg.
1966 		 */
1967 		if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2)
1968 			*clearval = ~(1U << HCLGEVF_VECTOR0_RX_CMDQ_INT_B);
1969 		else
1970 			*clearval = cmdq_stat_reg &
1971 				    ~BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B);
1972 
1973 		return HCLGEVF_VECTOR0_EVENT_MBX;
1974 	}
1975 
1976 	/* print other vector0 event source */
1977 	dev_info(&hdev->pdev->dev,
1978 		 "vector 0 interrupt from unknown source, cmdq_src = %#x\n",
1979 		 cmdq_stat_reg);
1980 
1981 	return HCLGEVF_VECTOR0_EVENT_OTHER;
1982 }
1983 
1984 static void hclgevf_reset_timer(struct timer_list *t)
1985 {
1986 	struct hclgevf_dev *hdev = from_timer(hdev, t, reset_timer);
1987 
1988 	hclgevf_clear_event_cause(hdev, HCLGEVF_VECTOR0_EVENT_RST);
1989 	hclgevf_reset_task_schedule(hdev);
1990 }
1991 
1992 static irqreturn_t hclgevf_misc_irq_handle(int irq, void *data)
1993 {
1994 #define HCLGEVF_RESET_DELAY	5
1995 
1996 	enum hclgevf_evt_cause event_cause;
1997 	struct hclgevf_dev *hdev = data;
1998 	u32 clearval;
1999 
2000 	hclgevf_enable_vector(&hdev->misc_vector, false);
2001 	event_cause = hclgevf_check_evt_cause(hdev, &clearval);
2002 	if (event_cause != HCLGEVF_VECTOR0_EVENT_OTHER)
2003 		hclgevf_clear_event_cause(hdev, clearval);
2004 
2005 	switch (event_cause) {
2006 	case HCLGEVF_VECTOR0_EVENT_RST:
2007 		mod_timer(&hdev->reset_timer,
2008 			  jiffies + msecs_to_jiffies(HCLGEVF_RESET_DELAY));
2009 		break;
2010 	case HCLGEVF_VECTOR0_EVENT_MBX:
2011 		hclgevf_mbx_handler(hdev);
2012 		break;
2013 	default:
2014 		break;
2015 	}
2016 
2017 	hclgevf_enable_vector(&hdev->misc_vector, true);
2018 
2019 	return IRQ_HANDLED;
2020 }
2021 
2022 static int hclgevf_configure(struct hclgevf_dev *hdev)
2023 {
2024 	int ret;
2025 
2026 	hdev->gro_en = true;
2027 
2028 	ret = hclgevf_get_basic_info(hdev);
2029 	if (ret)
2030 		return ret;
2031 
2032 	/* get current port based vlan state from PF */
2033 	ret = hclgevf_get_port_base_vlan_filter_state(hdev);
2034 	if (ret)
2035 		return ret;
2036 
2037 	/* get queue configuration from PF */
2038 	ret = hclgevf_get_queue_info(hdev);
2039 	if (ret)
2040 		return ret;
2041 
2042 	/* get queue depth info from PF */
2043 	ret = hclgevf_get_queue_depth(hdev);
2044 	if (ret)
2045 		return ret;
2046 
2047 	return hclgevf_get_pf_media_type(hdev);
2048 }
2049 
2050 static int hclgevf_alloc_hdev(struct hnae3_ae_dev *ae_dev)
2051 {
2052 	struct pci_dev *pdev = ae_dev->pdev;
2053 	struct hclgevf_dev *hdev;
2054 
2055 	hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL);
2056 	if (!hdev)
2057 		return -ENOMEM;
2058 
2059 	hdev->pdev = pdev;
2060 	hdev->ae_dev = ae_dev;
2061 	ae_dev->priv = hdev;
2062 
2063 	return 0;
2064 }
2065 
2066 static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev)
2067 {
2068 	struct hnae3_handle *roce = &hdev->roce;
2069 	struct hnae3_handle *nic = &hdev->nic;
2070 
2071 	roce->rinfo.num_vectors = hdev->num_roce_msix;
2072 
2073 	if (hdev->num_msi_left < roce->rinfo.num_vectors ||
2074 	    hdev->num_msi_left == 0)
2075 		return -EINVAL;
2076 
2077 	roce->rinfo.base_vector = hdev->roce_base_msix_offset;
2078 
2079 	roce->rinfo.netdev = nic->kinfo.netdev;
2080 	roce->rinfo.roce_io_base = hdev->hw.hw.io_base;
2081 	roce->rinfo.roce_mem_base = hdev->hw.hw.mem_base;
2082 
2083 	roce->pdev = nic->pdev;
2084 	roce->ae_algo = nic->ae_algo;
2085 	roce->numa_node_mask = nic->numa_node_mask;
2086 
2087 	return 0;
2088 }
2089 
2090 static int hclgevf_config_gro(struct hclgevf_dev *hdev)
2091 {
2092 	struct hclgevf_cfg_gro_status_cmd *req;
2093 	struct hclge_desc desc;
2094 	int ret;
2095 
2096 	if (!hnae3_ae_dev_gro_supported(hdev->ae_dev))
2097 		return 0;
2098 
2099 	hclgevf_cmd_setup_basic_desc(&desc, HCLGE_OPC_GRO_GENERIC_CONFIG,
2100 				     false);
2101 	req = (struct hclgevf_cfg_gro_status_cmd *)desc.data;
2102 
2103 	req->gro_en = hdev->gro_en ? 1 : 0;
2104 
2105 	ret = hclgevf_cmd_send(&hdev->hw, &desc, 1);
2106 	if (ret)
2107 		dev_err(&hdev->pdev->dev,
2108 			"VF GRO hardware config cmd failed, ret = %d.\n", ret);
2109 
2110 	return ret;
2111 }
2112 
2113 static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev)
2114 {
2115 	struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg;
2116 	u16 tc_offset[HCLGE_COMM_MAX_TC_NUM];
2117 	u16 tc_valid[HCLGE_COMM_MAX_TC_NUM];
2118 	u16 tc_size[HCLGE_COMM_MAX_TC_NUM];
2119 	int ret;
2120 
2121 	if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) {
2122 		ret = hclge_comm_set_rss_algo_key(&hdev->hw.hw,
2123 						  rss_cfg->rss_algo,
2124 						  rss_cfg->rss_hash_key);
2125 		if (ret)
2126 			return ret;
2127 
2128 		ret = hclge_comm_set_rss_input_tuple(&hdev->hw.hw, rss_cfg);
2129 		if (ret)
2130 			return ret;
2131 	}
2132 
2133 	ret = hclge_comm_set_rss_indir_table(hdev->ae_dev, &hdev->hw.hw,
2134 					     rss_cfg->rss_indirection_tbl);
2135 	if (ret)
2136 		return ret;
2137 
2138 	hclge_comm_get_rss_tc_info(rss_cfg->rss_size, hdev->hw_tc_map,
2139 				   tc_offset, tc_valid, tc_size);
2140 
2141 	return hclge_comm_set_rss_tc_mode(&hdev->hw.hw, tc_offset,
2142 					  tc_valid, tc_size);
2143 }
2144 
2145 static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev)
2146 {
2147 	struct hnae3_handle *nic = &hdev->nic;
2148 	int ret;
2149 
2150 	ret = hclgevf_en_hw_strip_rxvtag(nic, true);
2151 	if (ret) {
2152 		dev_err(&hdev->pdev->dev,
2153 			"failed to enable rx vlan offload, ret = %d\n", ret);
2154 		return ret;
2155 	}
2156 
2157 	return hclgevf_set_vlan_filter(&hdev->nic, htons(ETH_P_8021Q), 0,
2158 				       false);
2159 }
2160 
2161 static void hclgevf_flush_link_update(struct hclgevf_dev *hdev)
2162 {
2163 #define HCLGEVF_FLUSH_LINK_TIMEOUT	100000
2164 
2165 	unsigned long last = hdev->serv_processed_cnt;
2166 	int i = 0;
2167 
2168 	while (test_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state) &&
2169 	       i++ < HCLGEVF_FLUSH_LINK_TIMEOUT &&
2170 	       last == hdev->serv_processed_cnt)
2171 		usleep_range(1, 1);
2172 }
2173 
2174 static void hclgevf_set_timer_task(struct hnae3_handle *handle, bool enable)
2175 {
2176 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2177 
2178 	if (enable) {
2179 		hclgevf_task_schedule(hdev, 0);
2180 	} else {
2181 		set_bit(HCLGEVF_STATE_DOWN, &hdev->state);
2182 
2183 		/* flush memory to make sure DOWN is seen by service task */
2184 		smp_mb__before_atomic();
2185 		hclgevf_flush_link_update(hdev);
2186 	}
2187 }
2188 
2189 static int hclgevf_ae_start(struct hnae3_handle *handle)
2190 {
2191 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2192 
2193 	clear_bit(HCLGEVF_STATE_DOWN, &hdev->state);
2194 	clear_bit(HCLGEVF_STATE_PF_PUSH_LINK_STATUS, &hdev->state);
2195 
2196 	hclge_comm_reset_tqp_stats(handle);
2197 
2198 	hclgevf_request_link_info(hdev);
2199 
2200 	hclgevf_update_link_mode(hdev);
2201 
2202 	return 0;
2203 }
2204 
2205 static void hclgevf_ae_stop(struct hnae3_handle *handle)
2206 {
2207 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2208 
2209 	set_bit(HCLGEVF_STATE_DOWN, &hdev->state);
2210 
2211 	if (hdev->reset_type != HNAE3_VF_RESET)
2212 		hclgevf_reset_tqp(handle);
2213 
2214 	hclge_comm_reset_tqp_stats(handle);
2215 	hclgevf_update_link_status(hdev, 0);
2216 }
2217 
2218 static int hclgevf_set_alive(struct hnae3_handle *handle, bool alive)
2219 {
2220 #define HCLGEVF_STATE_ALIVE	1
2221 #define HCLGEVF_STATE_NOT_ALIVE	0
2222 
2223 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2224 	struct hclge_vf_to_pf_msg send_msg;
2225 
2226 	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_ALIVE, 0);
2227 	send_msg.data[0] = alive ? HCLGEVF_STATE_ALIVE :
2228 				HCLGEVF_STATE_NOT_ALIVE;
2229 	return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
2230 }
2231 
2232 static int hclgevf_client_start(struct hnae3_handle *handle)
2233 {
2234 	return hclgevf_set_alive(handle, true);
2235 }
2236 
2237 static void hclgevf_client_stop(struct hnae3_handle *handle)
2238 {
2239 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2240 	int ret;
2241 
2242 	ret = hclgevf_set_alive(handle, false);
2243 	if (ret)
2244 		dev_warn(&hdev->pdev->dev,
2245 			 "%s failed %d\n", __func__, ret);
2246 }
2247 
2248 static void hclgevf_state_init(struct hclgevf_dev *hdev)
2249 {
2250 	clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state);
2251 	clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state);
2252 	clear_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state);
2253 
2254 	INIT_DELAYED_WORK(&hdev->service_task, hclgevf_service_task);
2255 
2256 	mutex_init(&hdev->mbx_resp.mbx_mutex);
2257 	sema_init(&hdev->reset_sem, 1);
2258 
2259 	spin_lock_init(&hdev->mac_table.mac_list_lock);
2260 	INIT_LIST_HEAD(&hdev->mac_table.uc_mac_list);
2261 	INIT_LIST_HEAD(&hdev->mac_table.mc_mac_list);
2262 
2263 	/* bring the device down */
2264 	set_bit(HCLGEVF_STATE_DOWN, &hdev->state);
2265 }
2266 
2267 static void hclgevf_state_uninit(struct hclgevf_dev *hdev)
2268 {
2269 	set_bit(HCLGEVF_STATE_DOWN, &hdev->state);
2270 	set_bit(HCLGEVF_STATE_REMOVING, &hdev->state);
2271 
2272 	if (hdev->service_task.work.func)
2273 		cancel_delayed_work_sync(&hdev->service_task);
2274 
2275 	mutex_destroy(&hdev->mbx_resp.mbx_mutex);
2276 }
2277 
2278 static int hclgevf_init_msi(struct hclgevf_dev *hdev)
2279 {
2280 	struct pci_dev *pdev = hdev->pdev;
2281 	int vectors;
2282 	int i;
2283 
2284 	if (hnae3_dev_roce_supported(hdev))
2285 		vectors = pci_alloc_irq_vectors(pdev,
2286 						hdev->roce_base_msix_offset + 1,
2287 						hdev->num_msi,
2288 						PCI_IRQ_MSIX);
2289 	else
2290 		vectors = pci_alloc_irq_vectors(pdev, HNAE3_MIN_VECTOR_NUM,
2291 						hdev->num_msi,
2292 						PCI_IRQ_MSI | PCI_IRQ_MSIX);
2293 
2294 	if (vectors < 0) {
2295 		dev_err(&pdev->dev,
2296 			"failed(%d) to allocate MSI/MSI-X vectors\n",
2297 			vectors);
2298 		return vectors;
2299 	}
2300 	if (vectors < hdev->num_msi)
2301 		dev_warn(&hdev->pdev->dev,
2302 			 "requested %u MSI/MSI-X, but allocated %d MSI/MSI-X\n",
2303 			 hdev->num_msi, vectors);
2304 
2305 	hdev->num_msi = vectors;
2306 	hdev->num_msi_left = vectors;
2307 
2308 	hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
2309 					   sizeof(u16), GFP_KERNEL);
2310 	if (!hdev->vector_status) {
2311 		pci_free_irq_vectors(pdev);
2312 		return -ENOMEM;
2313 	}
2314 
2315 	for (i = 0; i < hdev->num_msi; i++)
2316 		hdev->vector_status[i] = HCLGEVF_INVALID_VPORT;
2317 
2318 	hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi,
2319 					sizeof(int), GFP_KERNEL);
2320 	if (!hdev->vector_irq) {
2321 		devm_kfree(&pdev->dev, hdev->vector_status);
2322 		pci_free_irq_vectors(pdev);
2323 		return -ENOMEM;
2324 	}
2325 
2326 	return 0;
2327 }
2328 
2329 static void hclgevf_uninit_msi(struct hclgevf_dev *hdev)
2330 {
2331 	struct pci_dev *pdev = hdev->pdev;
2332 
2333 	devm_kfree(&pdev->dev, hdev->vector_status);
2334 	devm_kfree(&pdev->dev, hdev->vector_irq);
2335 	pci_free_irq_vectors(pdev);
2336 }
2337 
2338 static int hclgevf_misc_irq_init(struct hclgevf_dev *hdev)
2339 {
2340 	int ret;
2341 
2342 	hclgevf_get_misc_vector(hdev);
2343 
2344 	snprintf(hdev->misc_vector.name, HNAE3_INT_NAME_LEN, "%s-misc-%s",
2345 		 HCLGEVF_NAME, pci_name(hdev->pdev));
2346 	ret = request_irq(hdev->misc_vector.vector_irq, hclgevf_misc_irq_handle,
2347 			  0, hdev->misc_vector.name, hdev);
2348 	if (ret) {
2349 		dev_err(&hdev->pdev->dev, "VF failed to request misc irq(%d)\n",
2350 			hdev->misc_vector.vector_irq);
2351 		return ret;
2352 	}
2353 
2354 	hclgevf_clear_event_cause(hdev, 0);
2355 
2356 	/* enable misc. vector(vector 0) */
2357 	hclgevf_enable_vector(&hdev->misc_vector, true);
2358 
2359 	return ret;
2360 }
2361 
2362 static void hclgevf_misc_irq_uninit(struct hclgevf_dev *hdev)
2363 {
2364 	/* disable misc vector(vector 0) */
2365 	hclgevf_enable_vector(&hdev->misc_vector, false);
2366 	synchronize_irq(hdev->misc_vector.vector_irq);
2367 	free_irq(hdev->misc_vector.vector_irq, hdev);
2368 	hclgevf_free_vector(hdev, 0);
2369 }
2370 
2371 static void hclgevf_info_show(struct hclgevf_dev *hdev)
2372 {
2373 	struct device *dev = &hdev->pdev->dev;
2374 
2375 	dev_info(dev, "VF info begin:\n");
2376 
2377 	dev_info(dev, "Task queue pairs numbers: %u\n", hdev->num_tqps);
2378 	dev_info(dev, "Desc num per TX queue: %u\n", hdev->num_tx_desc);
2379 	dev_info(dev, "Desc num per RX queue: %u\n", hdev->num_rx_desc);
2380 	dev_info(dev, "Numbers of vports: %u\n", hdev->num_alloc_vport);
2381 	dev_info(dev, "HW tc map: 0x%x\n", hdev->hw_tc_map);
2382 	dev_info(dev, "PF media type of this VF: %u\n",
2383 		 hdev->hw.mac.media_type);
2384 
2385 	dev_info(dev, "VF info end.\n");
2386 }
2387 
2388 static int hclgevf_init_nic_client_instance(struct hnae3_ae_dev *ae_dev,
2389 					    struct hnae3_client *client)
2390 {
2391 	struct hclgevf_dev *hdev = ae_dev->priv;
2392 	int rst_cnt = hdev->rst_stats.rst_cnt;
2393 	int ret;
2394 
2395 	ret = client->ops->init_instance(&hdev->nic);
2396 	if (ret)
2397 		return ret;
2398 
2399 	set_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state);
2400 	if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) ||
2401 	    rst_cnt != hdev->rst_stats.rst_cnt) {
2402 		clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state);
2403 
2404 		client->ops->uninit_instance(&hdev->nic, 0);
2405 		return -EBUSY;
2406 	}
2407 
2408 	hnae3_set_client_init_flag(client, ae_dev, 1);
2409 
2410 	if (netif_msg_drv(&hdev->nic))
2411 		hclgevf_info_show(hdev);
2412 
2413 	return 0;
2414 }
2415 
2416 static int hclgevf_init_roce_client_instance(struct hnae3_ae_dev *ae_dev,
2417 					     struct hnae3_client *client)
2418 {
2419 	struct hclgevf_dev *hdev = ae_dev->priv;
2420 	int ret;
2421 
2422 	if (!hnae3_dev_roce_supported(hdev) || !hdev->roce_client ||
2423 	    !hdev->nic_client)
2424 		return 0;
2425 
2426 	ret = hclgevf_init_roce_base_info(hdev);
2427 	if (ret)
2428 		return ret;
2429 
2430 	ret = client->ops->init_instance(&hdev->roce);
2431 	if (ret)
2432 		return ret;
2433 
2434 	set_bit(HCLGEVF_STATE_ROCE_REGISTERED, &hdev->state);
2435 	hnae3_set_client_init_flag(client, ae_dev, 1);
2436 
2437 	return 0;
2438 }
2439 
2440 static int hclgevf_init_client_instance(struct hnae3_client *client,
2441 					struct hnae3_ae_dev *ae_dev)
2442 {
2443 	struct hclgevf_dev *hdev = ae_dev->priv;
2444 	int ret;
2445 
2446 	switch (client->type) {
2447 	case HNAE3_CLIENT_KNIC:
2448 		hdev->nic_client = client;
2449 		hdev->nic.client = client;
2450 
2451 		ret = hclgevf_init_nic_client_instance(ae_dev, client);
2452 		if (ret)
2453 			goto clear_nic;
2454 
2455 		ret = hclgevf_init_roce_client_instance(ae_dev,
2456 							hdev->roce_client);
2457 		if (ret)
2458 			goto clear_roce;
2459 
2460 		break;
2461 	case HNAE3_CLIENT_ROCE:
2462 		if (hnae3_dev_roce_supported(hdev)) {
2463 			hdev->roce_client = client;
2464 			hdev->roce.client = client;
2465 		}
2466 
2467 		ret = hclgevf_init_roce_client_instance(ae_dev, client);
2468 		if (ret)
2469 			goto clear_roce;
2470 
2471 		break;
2472 	default:
2473 		return -EINVAL;
2474 	}
2475 
2476 	return 0;
2477 
2478 clear_nic:
2479 	hdev->nic_client = NULL;
2480 	hdev->nic.client = NULL;
2481 	return ret;
2482 clear_roce:
2483 	hdev->roce_client = NULL;
2484 	hdev->roce.client = NULL;
2485 	return ret;
2486 }
2487 
2488 static void hclgevf_uninit_client_instance(struct hnae3_client *client,
2489 					   struct hnae3_ae_dev *ae_dev)
2490 {
2491 	struct hclgevf_dev *hdev = ae_dev->priv;
2492 
2493 	/* un-init roce, if it exists */
2494 	if (hdev->roce_client) {
2495 		while (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state))
2496 			msleep(HCLGEVF_WAIT_RESET_DONE);
2497 		clear_bit(HCLGEVF_STATE_ROCE_REGISTERED, &hdev->state);
2498 
2499 		hdev->roce_client->ops->uninit_instance(&hdev->roce, 0);
2500 		hdev->roce_client = NULL;
2501 		hdev->roce.client = NULL;
2502 	}
2503 
2504 	/* un-init nic/unic, if this was not called by roce client */
2505 	if (client->ops->uninit_instance && hdev->nic_client &&
2506 	    client->type != HNAE3_CLIENT_ROCE) {
2507 		while (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state))
2508 			msleep(HCLGEVF_WAIT_RESET_DONE);
2509 		clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state);
2510 
2511 		client->ops->uninit_instance(&hdev->nic, 0);
2512 		hdev->nic_client = NULL;
2513 		hdev->nic.client = NULL;
2514 	}
2515 }
2516 
2517 static int hclgevf_dev_mem_map(struct hclgevf_dev *hdev)
2518 {
2519 	struct pci_dev *pdev = hdev->pdev;
2520 	struct hclgevf_hw *hw = &hdev->hw;
2521 
2522 	/* for device does not have device memory, return directly */
2523 	if (!(pci_select_bars(pdev, IORESOURCE_MEM) & BIT(HCLGEVF_MEM_BAR)))
2524 		return 0;
2525 
2526 	hw->hw.mem_base =
2527 		devm_ioremap_wc(&pdev->dev,
2528 				pci_resource_start(pdev, HCLGEVF_MEM_BAR),
2529 				pci_resource_len(pdev, HCLGEVF_MEM_BAR));
2530 	if (!hw->hw.mem_base) {
2531 		dev_err(&pdev->dev, "failed to map device memory\n");
2532 		return -EFAULT;
2533 	}
2534 
2535 	return 0;
2536 }
2537 
2538 static int hclgevf_pci_init(struct hclgevf_dev *hdev)
2539 {
2540 	struct pci_dev *pdev = hdev->pdev;
2541 	struct hclgevf_hw *hw;
2542 	int ret;
2543 
2544 	ret = pci_enable_device(pdev);
2545 	if (ret) {
2546 		dev_err(&pdev->dev, "failed to enable PCI device\n");
2547 		return ret;
2548 	}
2549 
2550 	ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
2551 	if (ret) {
2552 		dev_err(&pdev->dev, "can't set consistent PCI DMA, exiting");
2553 		goto err_disable_device;
2554 	}
2555 
2556 	ret = pci_request_regions(pdev, HCLGEVF_DRIVER_NAME);
2557 	if (ret) {
2558 		dev_err(&pdev->dev, "PCI request regions failed %d\n", ret);
2559 		goto err_disable_device;
2560 	}
2561 
2562 	pci_set_master(pdev);
2563 	hw = &hdev->hw;
2564 	hw->hw.io_base = pci_iomap(pdev, 2, 0);
2565 	if (!hw->hw.io_base) {
2566 		dev_err(&pdev->dev, "can't map configuration register space\n");
2567 		ret = -ENOMEM;
2568 		goto err_release_regions;
2569 	}
2570 
2571 	ret = hclgevf_dev_mem_map(hdev);
2572 	if (ret)
2573 		goto err_unmap_io_base;
2574 
2575 	return 0;
2576 
2577 err_unmap_io_base:
2578 	pci_iounmap(pdev, hdev->hw.hw.io_base);
2579 err_release_regions:
2580 	pci_release_regions(pdev);
2581 err_disable_device:
2582 	pci_disable_device(pdev);
2583 
2584 	return ret;
2585 }
2586 
2587 static void hclgevf_pci_uninit(struct hclgevf_dev *hdev)
2588 {
2589 	struct pci_dev *pdev = hdev->pdev;
2590 
2591 	if (hdev->hw.hw.mem_base)
2592 		devm_iounmap(&pdev->dev, hdev->hw.hw.mem_base);
2593 
2594 	pci_iounmap(pdev, hdev->hw.hw.io_base);
2595 	pci_release_regions(pdev);
2596 	pci_disable_device(pdev);
2597 }
2598 
2599 static int hclgevf_query_vf_resource(struct hclgevf_dev *hdev)
2600 {
2601 	struct hclgevf_query_res_cmd *req;
2602 	struct hclge_desc desc;
2603 	int ret;
2604 
2605 	hclgevf_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_VF_RSRC, true);
2606 	ret = hclgevf_cmd_send(&hdev->hw, &desc, 1);
2607 	if (ret) {
2608 		dev_err(&hdev->pdev->dev,
2609 			"query vf resource failed, ret = %d.\n", ret);
2610 		return ret;
2611 	}
2612 
2613 	req = (struct hclgevf_query_res_cmd *)desc.data;
2614 
2615 	if (hnae3_dev_roce_supported(hdev)) {
2616 		hdev->roce_base_msix_offset =
2617 		hnae3_get_field(le16_to_cpu(req->msixcap_localid_ba_rocee),
2618 				HCLGEVF_MSIX_OFT_ROCEE_M,
2619 				HCLGEVF_MSIX_OFT_ROCEE_S);
2620 		hdev->num_roce_msix =
2621 		hnae3_get_field(le16_to_cpu(req->vf_intr_vector_number),
2622 				HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S);
2623 
2624 		/* nic's msix numbers is always equals to the roce's. */
2625 		hdev->num_nic_msix = hdev->num_roce_msix;
2626 
2627 		/* VF should have NIC vectors and Roce vectors, NIC vectors
2628 		 * are queued before Roce vectors. The offset is fixed to 64.
2629 		 */
2630 		hdev->num_msi = hdev->num_roce_msix +
2631 				hdev->roce_base_msix_offset;
2632 	} else {
2633 		hdev->num_msi =
2634 		hnae3_get_field(le16_to_cpu(req->vf_intr_vector_number),
2635 				HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S);
2636 
2637 		hdev->num_nic_msix = hdev->num_msi;
2638 	}
2639 
2640 	if (hdev->num_nic_msix < HNAE3_MIN_VECTOR_NUM) {
2641 		dev_err(&hdev->pdev->dev,
2642 			"Just %u msi resources, not enough for vf(min:2).\n",
2643 			hdev->num_nic_msix);
2644 		return -EINVAL;
2645 	}
2646 
2647 	return 0;
2648 }
2649 
2650 static void hclgevf_set_default_dev_specs(struct hclgevf_dev *hdev)
2651 {
2652 #define HCLGEVF_MAX_NON_TSO_BD_NUM			8U
2653 
2654 	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
2655 
2656 	ae_dev->dev_specs.max_non_tso_bd_num =
2657 					HCLGEVF_MAX_NON_TSO_BD_NUM;
2658 	ae_dev->dev_specs.rss_ind_tbl_size = HCLGEVF_RSS_IND_TBL_SIZE;
2659 	ae_dev->dev_specs.rss_key_size = HCLGE_COMM_RSS_KEY_SIZE;
2660 	ae_dev->dev_specs.max_int_gl = HCLGEVF_DEF_MAX_INT_GL;
2661 	ae_dev->dev_specs.max_frm_size = HCLGEVF_MAC_MAX_FRAME;
2662 }
2663 
2664 static void hclgevf_parse_dev_specs(struct hclgevf_dev *hdev,
2665 				    struct hclge_desc *desc)
2666 {
2667 	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
2668 	struct hclgevf_dev_specs_0_cmd *req0;
2669 	struct hclgevf_dev_specs_1_cmd *req1;
2670 
2671 	req0 = (struct hclgevf_dev_specs_0_cmd *)desc[0].data;
2672 	req1 = (struct hclgevf_dev_specs_1_cmd *)desc[1].data;
2673 
2674 	ae_dev->dev_specs.max_non_tso_bd_num = req0->max_non_tso_bd_num;
2675 	ae_dev->dev_specs.rss_ind_tbl_size =
2676 					le16_to_cpu(req0->rss_ind_tbl_size);
2677 	ae_dev->dev_specs.int_ql_max = le16_to_cpu(req0->int_ql_max);
2678 	ae_dev->dev_specs.rss_key_size = le16_to_cpu(req0->rss_key_size);
2679 	ae_dev->dev_specs.max_int_gl = le16_to_cpu(req1->max_int_gl);
2680 	ae_dev->dev_specs.max_frm_size = le16_to_cpu(req1->max_frm_size);
2681 }
2682 
2683 static void hclgevf_check_dev_specs(struct hclgevf_dev *hdev)
2684 {
2685 	struct hnae3_dev_specs *dev_specs = &hdev->ae_dev->dev_specs;
2686 
2687 	if (!dev_specs->max_non_tso_bd_num)
2688 		dev_specs->max_non_tso_bd_num = HCLGEVF_MAX_NON_TSO_BD_NUM;
2689 	if (!dev_specs->rss_ind_tbl_size)
2690 		dev_specs->rss_ind_tbl_size = HCLGEVF_RSS_IND_TBL_SIZE;
2691 	if (!dev_specs->rss_key_size)
2692 		dev_specs->rss_key_size = HCLGE_COMM_RSS_KEY_SIZE;
2693 	if (!dev_specs->max_int_gl)
2694 		dev_specs->max_int_gl = HCLGEVF_DEF_MAX_INT_GL;
2695 	if (!dev_specs->max_frm_size)
2696 		dev_specs->max_frm_size = HCLGEVF_MAC_MAX_FRAME;
2697 }
2698 
2699 static int hclgevf_query_dev_specs(struct hclgevf_dev *hdev)
2700 {
2701 	struct hclge_desc desc[HCLGEVF_QUERY_DEV_SPECS_BD_NUM];
2702 	int ret;
2703 	int i;
2704 
2705 	/* set default specifications as devices lower than version V3 do not
2706 	 * support querying specifications from firmware.
2707 	 */
2708 	if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3) {
2709 		hclgevf_set_default_dev_specs(hdev);
2710 		return 0;
2711 	}
2712 
2713 	for (i = 0; i < HCLGEVF_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
2714 		hclgevf_cmd_setup_basic_desc(&desc[i],
2715 					     HCLGE_OPC_QUERY_DEV_SPECS, true);
2716 		desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
2717 	}
2718 	hclgevf_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_DEV_SPECS, true);
2719 
2720 	ret = hclgevf_cmd_send(&hdev->hw, desc, HCLGEVF_QUERY_DEV_SPECS_BD_NUM);
2721 	if (ret)
2722 		return ret;
2723 
2724 	hclgevf_parse_dev_specs(hdev, desc);
2725 	hclgevf_check_dev_specs(hdev);
2726 
2727 	return 0;
2728 }
2729 
2730 static int hclgevf_pci_reset(struct hclgevf_dev *hdev)
2731 {
2732 	struct pci_dev *pdev = hdev->pdev;
2733 	int ret = 0;
2734 
2735 	if ((hdev->reset_type == HNAE3_VF_FULL_RESET ||
2736 	     hdev->reset_type == HNAE3_FLR_RESET) &&
2737 	    test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) {
2738 		hclgevf_misc_irq_uninit(hdev);
2739 		hclgevf_uninit_msi(hdev);
2740 		clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state);
2741 	}
2742 
2743 	if (!test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) {
2744 		pci_set_master(pdev);
2745 		ret = hclgevf_init_msi(hdev);
2746 		if (ret) {
2747 			dev_err(&pdev->dev,
2748 				"failed(%d) to init MSI/MSI-X\n", ret);
2749 			return ret;
2750 		}
2751 
2752 		ret = hclgevf_misc_irq_init(hdev);
2753 		if (ret) {
2754 			hclgevf_uninit_msi(hdev);
2755 			dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n",
2756 				ret);
2757 			return ret;
2758 		}
2759 
2760 		set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state);
2761 	}
2762 
2763 	return ret;
2764 }
2765 
2766 static int hclgevf_clear_vport_list(struct hclgevf_dev *hdev)
2767 {
2768 	struct hclge_vf_to_pf_msg send_msg;
2769 
2770 	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_HANDLE_VF_TBL,
2771 			       HCLGE_MBX_VPORT_LIST_CLEAR);
2772 	return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
2773 }
2774 
2775 static void hclgevf_init_rxd_adv_layout(struct hclgevf_dev *hdev)
2776 {
2777 	if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev))
2778 		hclgevf_write_dev(&hdev->hw, HCLGEVF_RXD_ADV_LAYOUT_EN_REG, 1);
2779 }
2780 
2781 static void hclgevf_uninit_rxd_adv_layout(struct hclgevf_dev *hdev)
2782 {
2783 	if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev))
2784 		hclgevf_write_dev(&hdev->hw, HCLGEVF_RXD_ADV_LAYOUT_EN_REG, 0);
2785 }
2786 
2787 static int hclgevf_reset_hdev(struct hclgevf_dev *hdev)
2788 {
2789 	struct pci_dev *pdev = hdev->pdev;
2790 	int ret;
2791 
2792 	ret = hclgevf_pci_reset(hdev);
2793 	if (ret) {
2794 		dev_err(&pdev->dev, "pci reset failed %d\n", ret);
2795 		return ret;
2796 	}
2797 
2798 	hclgevf_arq_init(hdev);
2799 	ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw,
2800 				  &hdev->fw_version, false,
2801 				  hdev->reset_pending);
2802 	if (ret) {
2803 		dev_err(&pdev->dev, "cmd failed %d\n", ret);
2804 		return ret;
2805 	}
2806 
2807 	ret = hclgevf_rss_init_hw(hdev);
2808 	if (ret) {
2809 		dev_err(&hdev->pdev->dev,
2810 			"failed(%d) to initialize RSS\n", ret);
2811 		return ret;
2812 	}
2813 
2814 	ret = hclgevf_config_gro(hdev);
2815 	if (ret)
2816 		return ret;
2817 
2818 	ret = hclgevf_init_vlan_config(hdev);
2819 	if (ret) {
2820 		dev_err(&hdev->pdev->dev,
2821 			"failed(%d) to initialize VLAN config\n", ret);
2822 		return ret;
2823 	}
2824 
2825 	/* get current port based vlan state from PF */
2826 	ret = hclgevf_get_port_base_vlan_filter_state(hdev);
2827 	if (ret)
2828 		return ret;
2829 
2830 	set_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state);
2831 
2832 	hclgevf_init_rxd_adv_layout(hdev);
2833 
2834 	dev_info(&hdev->pdev->dev, "Reset done\n");
2835 
2836 	return 0;
2837 }
2838 
2839 static int hclgevf_init_hdev(struct hclgevf_dev *hdev)
2840 {
2841 	struct pci_dev *pdev = hdev->pdev;
2842 	int ret;
2843 
2844 	ret = hclgevf_pci_init(hdev);
2845 	if (ret)
2846 		return ret;
2847 
2848 	ret = hclgevf_devlink_init(hdev);
2849 	if (ret)
2850 		goto err_devlink_init;
2851 
2852 	ret = hclge_comm_cmd_queue_init(hdev->pdev, &hdev->hw.hw);
2853 	if (ret)
2854 		goto err_cmd_queue_init;
2855 
2856 	hclgevf_arq_init(hdev);
2857 	ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw,
2858 				  &hdev->fw_version, false,
2859 				  hdev->reset_pending);
2860 	if (ret)
2861 		goto err_cmd_init;
2862 
2863 	/* Get vf resource */
2864 	ret = hclgevf_query_vf_resource(hdev);
2865 	if (ret)
2866 		goto err_cmd_init;
2867 
2868 	ret = hclgevf_query_dev_specs(hdev);
2869 	if (ret) {
2870 		dev_err(&pdev->dev,
2871 			"failed to query dev specifications, ret = %d\n", ret);
2872 		goto err_cmd_init;
2873 	}
2874 
2875 	ret = hclgevf_init_msi(hdev);
2876 	if (ret) {
2877 		dev_err(&pdev->dev, "failed(%d) to init MSI/MSI-X\n", ret);
2878 		goto err_cmd_init;
2879 	}
2880 
2881 	hclgevf_state_init(hdev);
2882 	hdev->reset_level = HNAE3_VF_FUNC_RESET;
2883 	hdev->reset_type = HNAE3_NONE_RESET;
2884 
2885 	ret = hclgevf_misc_irq_init(hdev);
2886 	if (ret)
2887 		goto err_misc_irq_init;
2888 
2889 	set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state);
2890 
2891 	ret = hclgevf_configure(hdev);
2892 	if (ret) {
2893 		dev_err(&pdev->dev, "failed(%d) to fetch configuration\n", ret);
2894 		goto err_config;
2895 	}
2896 
2897 	ret = hclgevf_alloc_tqps(hdev);
2898 	if (ret) {
2899 		dev_err(&pdev->dev, "failed(%d) to allocate TQPs\n", ret);
2900 		goto err_config;
2901 	}
2902 
2903 	ret = hclgevf_set_handle_info(hdev);
2904 	if (ret)
2905 		goto err_config;
2906 
2907 	ret = hclgevf_config_gro(hdev);
2908 	if (ret)
2909 		goto err_config;
2910 
2911 	/* Initialize RSS for this VF */
2912 	ret = hclge_comm_rss_init_cfg(&hdev->nic, hdev->ae_dev,
2913 				      &hdev->rss_cfg);
2914 	if (ret) {
2915 		dev_err(&pdev->dev, "failed to init rss cfg, ret = %d\n", ret);
2916 		goto err_config;
2917 	}
2918 
2919 	ret = hclgevf_rss_init_hw(hdev);
2920 	if (ret) {
2921 		dev_err(&hdev->pdev->dev,
2922 			"failed(%d) to initialize RSS\n", ret);
2923 		goto err_config;
2924 	}
2925 
2926 	/* ensure vf tbl list as empty before init */
2927 	ret = hclgevf_clear_vport_list(hdev);
2928 	if (ret) {
2929 		dev_err(&pdev->dev,
2930 			"failed to clear tbl list configuration, ret = %d.\n",
2931 			ret);
2932 		goto err_config;
2933 	}
2934 
2935 	ret = hclgevf_init_vlan_config(hdev);
2936 	if (ret) {
2937 		dev_err(&hdev->pdev->dev,
2938 			"failed(%d) to initialize VLAN config\n", ret);
2939 		goto err_config;
2940 	}
2941 
2942 	hclgevf_init_rxd_adv_layout(hdev);
2943 
2944 	set_bit(HCLGEVF_STATE_SERVICE_INITED, &hdev->state);
2945 
2946 	hdev->last_reset_time = jiffies;
2947 	dev_info(&hdev->pdev->dev, "finished initializing %s driver\n",
2948 		 HCLGEVF_DRIVER_NAME);
2949 
2950 	hclgevf_task_schedule(hdev, round_jiffies_relative(HZ));
2951 	timer_setup(&hdev->reset_timer, hclgevf_reset_timer, 0);
2952 
2953 	return 0;
2954 
2955 err_config:
2956 	hclgevf_misc_irq_uninit(hdev);
2957 err_misc_irq_init:
2958 	hclgevf_state_uninit(hdev);
2959 	hclgevf_uninit_msi(hdev);
2960 err_cmd_init:
2961 	hclge_comm_cmd_uninit(hdev->ae_dev, &hdev->hw.hw);
2962 err_cmd_queue_init:
2963 	hclgevf_devlink_uninit(hdev);
2964 err_devlink_init:
2965 	hclgevf_pci_uninit(hdev);
2966 	clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state);
2967 	return ret;
2968 }
2969 
2970 static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev)
2971 {
2972 	struct hclge_vf_to_pf_msg send_msg;
2973 
2974 	hclgevf_state_uninit(hdev);
2975 	hclgevf_uninit_rxd_adv_layout(hdev);
2976 
2977 	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_VF_UNINIT, 0);
2978 	hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
2979 
2980 	if (test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) {
2981 		hclgevf_misc_irq_uninit(hdev);
2982 		hclgevf_uninit_msi(hdev);
2983 	}
2984 
2985 	hclge_comm_cmd_uninit(hdev->ae_dev, &hdev->hw.hw);
2986 	hclgevf_devlink_uninit(hdev);
2987 	hclgevf_pci_uninit(hdev);
2988 	hclgevf_uninit_mac_list(hdev);
2989 }
2990 
2991 static int hclgevf_init_ae_dev(struct hnae3_ae_dev *ae_dev)
2992 {
2993 	struct pci_dev *pdev = ae_dev->pdev;
2994 	int ret;
2995 
2996 	ret = hclgevf_alloc_hdev(ae_dev);
2997 	if (ret) {
2998 		dev_err(&pdev->dev, "hclge device allocation failed\n");
2999 		return ret;
3000 	}
3001 
3002 	ret = hclgevf_init_hdev(ae_dev->priv);
3003 	if (ret) {
3004 		dev_err(&pdev->dev, "hclge device initialization failed\n");
3005 		return ret;
3006 	}
3007 
3008 	return 0;
3009 }
3010 
3011 static void hclgevf_uninit_ae_dev(struct hnae3_ae_dev *ae_dev)
3012 {
3013 	struct hclgevf_dev *hdev = ae_dev->priv;
3014 
3015 	hclgevf_uninit_hdev(hdev);
3016 	ae_dev->priv = NULL;
3017 }
3018 
3019 static u32 hclgevf_get_max_channels(struct hclgevf_dev *hdev)
3020 {
3021 	struct hnae3_handle *nic = &hdev->nic;
3022 	struct hnae3_knic_private_info *kinfo = &nic->kinfo;
3023 
3024 	return min_t(u32, hdev->rss_size_max,
3025 		     hdev->num_tqps / kinfo->tc_info.num_tc);
3026 }
3027 
3028 /**
3029  * hclgevf_get_channels - Get the current channels enabled and max supported.
3030  * @handle: hardware information for network interface
3031  * @ch: ethtool channels structure
3032  *
3033  * We don't support separate tx and rx queues as channels. The other count
3034  * represents how many queues are being used for control. max_combined counts
3035  * how many queue pairs we can support. They may not be mapped 1 to 1 with
3036  * q_vectors since we support a lot more queue pairs than q_vectors.
3037  **/
3038 static void hclgevf_get_channels(struct hnae3_handle *handle,
3039 				 struct ethtool_channels *ch)
3040 {
3041 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3042 
3043 	ch->max_combined = hclgevf_get_max_channels(hdev);
3044 	ch->other_count = 0;
3045 	ch->max_other = 0;
3046 	ch->combined_count = handle->kinfo.rss_size;
3047 }
3048 
3049 static void hclgevf_get_tqps_and_rss_info(struct hnae3_handle *handle,
3050 					  u16 *alloc_tqps, u16 *max_rss_size)
3051 {
3052 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3053 
3054 	*alloc_tqps = hdev->num_tqps;
3055 	*max_rss_size = hdev->rss_size_max;
3056 }
3057 
3058 static void hclgevf_update_rss_size(struct hnae3_handle *handle,
3059 				    u32 new_tqps_num)
3060 {
3061 	struct hnae3_knic_private_info *kinfo = &handle->kinfo;
3062 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3063 	u16 max_rss_size;
3064 
3065 	kinfo->req_rss_size = new_tqps_num;
3066 
3067 	max_rss_size = min_t(u16, hdev->rss_size_max,
3068 			     hdev->num_tqps / kinfo->tc_info.num_tc);
3069 
3070 	/* Use the user's configuration when it is not larger than
3071 	 * max_rss_size, otherwise, use the maximum specification value.
3072 	 */
3073 	if (kinfo->req_rss_size != kinfo->rss_size && kinfo->req_rss_size &&
3074 	    kinfo->req_rss_size <= max_rss_size)
3075 		kinfo->rss_size = kinfo->req_rss_size;
3076 	else if (kinfo->rss_size > max_rss_size ||
3077 		 (!kinfo->req_rss_size && kinfo->rss_size < max_rss_size))
3078 		kinfo->rss_size = max_rss_size;
3079 
3080 	kinfo->num_tqps = kinfo->tc_info.num_tc * kinfo->rss_size;
3081 }
3082 
3083 static int hclgevf_set_channels(struct hnae3_handle *handle, u32 new_tqps_num,
3084 				bool rxfh_configured)
3085 {
3086 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3087 	struct hnae3_knic_private_info *kinfo = &handle->kinfo;
3088 	u16 tc_offset[HCLGE_COMM_MAX_TC_NUM];
3089 	u16 tc_valid[HCLGE_COMM_MAX_TC_NUM];
3090 	u16 tc_size[HCLGE_COMM_MAX_TC_NUM];
3091 	u16 cur_rss_size = kinfo->rss_size;
3092 	u16 cur_tqps = kinfo->num_tqps;
3093 	u32 *rss_indir;
3094 	unsigned int i;
3095 	int ret;
3096 
3097 	hclgevf_update_rss_size(handle, new_tqps_num);
3098 
3099 	hclge_comm_get_rss_tc_info(kinfo->rss_size, hdev->hw_tc_map,
3100 				   tc_offset, tc_valid, tc_size);
3101 	ret = hclge_comm_set_rss_tc_mode(&hdev->hw.hw, tc_offset,
3102 					 tc_valid, tc_size);
3103 	if (ret)
3104 		return ret;
3105 
3106 	/* RSS indirection table has been configured by user */
3107 	if (rxfh_configured)
3108 		goto out;
3109 
3110 	/* Reinitializes the rss indirect table according to the new RSS size */
3111 	rss_indir = kcalloc(hdev->ae_dev->dev_specs.rss_ind_tbl_size,
3112 			    sizeof(u32), GFP_KERNEL);
3113 	if (!rss_indir)
3114 		return -ENOMEM;
3115 
3116 	for (i = 0; i < hdev->ae_dev->dev_specs.rss_ind_tbl_size; i++)
3117 		rss_indir[i] = i % kinfo->rss_size;
3118 
3119 	hdev->rss_cfg.rss_size = kinfo->rss_size;
3120 
3121 	ret = hclgevf_set_rss(handle, rss_indir, NULL, 0);
3122 	if (ret)
3123 		dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n",
3124 			ret);
3125 
3126 	kfree(rss_indir);
3127 
3128 out:
3129 	if (!ret)
3130 		dev_info(&hdev->pdev->dev,
3131 			 "Channels changed, rss_size from %u to %u, tqps from %u to %u",
3132 			 cur_rss_size, kinfo->rss_size,
3133 			 cur_tqps, kinfo->rss_size * kinfo->tc_info.num_tc);
3134 
3135 	return ret;
3136 }
3137 
3138 static int hclgevf_get_status(struct hnae3_handle *handle)
3139 {
3140 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3141 
3142 	return hdev->hw.mac.link;
3143 }
3144 
3145 static void hclgevf_get_ksettings_an_result(struct hnae3_handle *handle,
3146 					    u8 *auto_neg, u32 *speed,
3147 					    u8 *duplex, u32 *lane_num)
3148 {
3149 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3150 
3151 	if (speed)
3152 		*speed = hdev->hw.mac.speed;
3153 	if (duplex)
3154 		*duplex = hdev->hw.mac.duplex;
3155 	if (auto_neg)
3156 		*auto_neg = AUTONEG_DISABLE;
3157 }
3158 
3159 void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed,
3160 				 u8 duplex)
3161 {
3162 	hdev->hw.mac.speed = speed;
3163 	hdev->hw.mac.duplex = duplex;
3164 }
3165 
3166 static int hclgevf_gro_en(struct hnae3_handle *handle, bool enable)
3167 {
3168 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3169 	bool gro_en_old = hdev->gro_en;
3170 	int ret;
3171 
3172 	hdev->gro_en = enable;
3173 	ret = hclgevf_config_gro(hdev);
3174 	if (ret)
3175 		hdev->gro_en = gro_en_old;
3176 
3177 	return ret;
3178 }
3179 
3180 static void hclgevf_get_media_type(struct hnae3_handle *handle, u8 *media_type,
3181 				   u8 *module_type)
3182 {
3183 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3184 
3185 	if (media_type)
3186 		*media_type = hdev->hw.mac.media_type;
3187 
3188 	if (module_type)
3189 		*module_type = hdev->hw.mac.module_type;
3190 }
3191 
3192 static bool hclgevf_get_hw_reset_stat(struct hnae3_handle *handle)
3193 {
3194 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3195 
3196 	return !!hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING);
3197 }
3198 
3199 static bool hclgevf_get_cmdq_stat(struct hnae3_handle *handle)
3200 {
3201 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3202 
3203 	return test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state);
3204 }
3205 
3206 static bool hclgevf_ae_dev_resetting(struct hnae3_handle *handle)
3207 {
3208 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3209 
3210 	return test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state);
3211 }
3212 
3213 static unsigned long hclgevf_ae_dev_reset_cnt(struct hnae3_handle *handle)
3214 {
3215 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3216 
3217 	return hdev->rst_stats.hw_rst_done_cnt;
3218 }
3219 
3220 static void hclgevf_get_link_mode(struct hnae3_handle *handle,
3221 				  unsigned long *supported,
3222 				  unsigned long *advertising)
3223 {
3224 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3225 
3226 	*supported = hdev->hw.mac.supported;
3227 	*advertising = hdev->hw.mac.advertising;
3228 }
3229 
3230 void hclgevf_update_port_base_vlan_info(struct hclgevf_dev *hdev, u16 state,
3231 				struct hclge_mbx_port_base_vlan *port_base_vlan)
3232 {
3233 	struct hnae3_handle *nic = &hdev->nic;
3234 	struct hclge_vf_to_pf_msg send_msg;
3235 	int ret;
3236 
3237 	rtnl_lock();
3238 
3239 	if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) ||
3240 	    test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) {
3241 		dev_warn(&hdev->pdev->dev,
3242 			 "is resetting when updating port based vlan info\n");
3243 		rtnl_unlock();
3244 		return;
3245 	}
3246 
3247 	ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT);
3248 	if (ret) {
3249 		rtnl_unlock();
3250 		return;
3251 	}
3252 
3253 	/* send msg to PF and wait update port based vlan info */
3254 	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN,
3255 			       HCLGE_MBX_PORT_BASE_VLAN_CFG);
3256 	memcpy(send_msg.data, port_base_vlan, sizeof(*port_base_vlan));
3257 	ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
3258 	if (!ret) {
3259 		if (state == HNAE3_PORT_BASE_VLAN_DISABLE)
3260 			nic->port_base_vlan_state = state;
3261 		else
3262 			nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_ENABLE;
3263 	}
3264 
3265 	hclgevf_notify_client(hdev, HNAE3_UP_CLIENT);
3266 	rtnl_unlock();
3267 }
3268 
3269 static const struct hnae3_ae_ops hclgevf_ops = {
3270 	.init_ae_dev = hclgevf_init_ae_dev,
3271 	.uninit_ae_dev = hclgevf_uninit_ae_dev,
3272 	.reset_prepare = hclgevf_reset_prepare_general,
3273 	.reset_done = hclgevf_reset_done,
3274 	.init_client_instance = hclgevf_init_client_instance,
3275 	.uninit_client_instance = hclgevf_uninit_client_instance,
3276 	.start = hclgevf_ae_start,
3277 	.stop = hclgevf_ae_stop,
3278 	.client_start = hclgevf_client_start,
3279 	.client_stop = hclgevf_client_stop,
3280 	.map_ring_to_vector = hclgevf_map_ring_to_vector,
3281 	.unmap_ring_from_vector = hclgevf_unmap_ring_from_vector,
3282 	.get_vector = hclgevf_get_vector,
3283 	.put_vector = hclgevf_put_vector,
3284 	.reset_queue = hclgevf_reset_tqp,
3285 	.get_mac_addr = hclgevf_get_mac_addr,
3286 	.set_mac_addr = hclgevf_set_mac_addr,
3287 	.add_uc_addr = hclgevf_add_uc_addr,
3288 	.rm_uc_addr = hclgevf_rm_uc_addr,
3289 	.add_mc_addr = hclgevf_add_mc_addr,
3290 	.rm_mc_addr = hclgevf_rm_mc_addr,
3291 	.get_stats = hclgevf_get_stats,
3292 	.update_stats = hclgevf_update_stats,
3293 	.get_strings = hclgevf_get_strings,
3294 	.get_sset_count = hclgevf_get_sset_count,
3295 	.get_rss_key_size = hclge_comm_get_rss_key_size,
3296 	.get_rss = hclgevf_get_rss,
3297 	.set_rss = hclgevf_set_rss,
3298 	.get_rss_tuple = hclgevf_get_rss_tuple,
3299 	.set_rss_tuple = hclgevf_set_rss_tuple,
3300 	.get_tc_size = hclgevf_get_tc_size,
3301 	.get_fw_version = hclgevf_get_fw_version,
3302 	.set_vlan_filter = hclgevf_set_vlan_filter,
3303 	.enable_vlan_filter = hclgevf_enable_vlan_filter,
3304 	.enable_hw_strip_rxvtag = hclgevf_en_hw_strip_rxvtag,
3305 	.reset_event = hclgevf_reset_event,
3306 	.set_default_reset_request = hclgevf_set_def_reset_request,
3307 	.set_channels = hclgevf_set_channels,
3308 	.get_channels = hclgevf_get_channels,
3309 	.get_tqps_and_rss_info = hclgevf_get_tqps_and_rss_info,
3310 	.get_regs_len = hclgevf_get_regs_len,
3311 	.get_regs = hclgevf_get_regs,
3312 	.get_status = hclgevf_get_status,
3313 	.get_ksettings_an_result = hclgevf_get_ksettings_an_result,
3314 	.get_media_type = hclgevf_get_media_type,
3315 	.get_hw_reset_stat = hclgevf_get_hw_reset_stat,
3316 	.ae_dev_resetting = hclgevf_ae_dev_resetting,
3317 	.ae_dev_reset_cnt = hclgevf_ae_dev_reset_cnt,
3318 	.set_gro_en = hclgevf_gro_en,
3319 	.set_mtu = hclgevf_set_mtu,
3320 	.get_global_queue_id = hclgevf_get_qid_global,
3321 	.set_timer_task = hclgevf_set_timer_task,
3322 	.get_link_mode = hclgevf_get_link_mode,
3323 	.set_promisc_mode = hclgevf_set_promisc_mode,
3324 	.request_update_promisc_mode = hclgevf_request_update_promisc_mode,
3325 	.get_cmdq_stat = hclgevf_get_cmdq_stat,
3326 };
3327 
3328 static struct hnae3_ae_algo ae_algovf = {
3329 	.ops = &hclgevf_ops,
3330 	.pdev_id_table = ae_algovf_pci_tbl,
3331 };
3332 
3333 static int __init hclgevf_init(void)
3334 {
3335 	pr_info("%s is initializing\n", HCLGEVF_NAME);
3336 
3337 	hclgevf_wq = alloc_workqueue("%s", WQ_UNBOUND, 0, HCLGEVF_NAME);
3338 	if (!hclgevf_wq) {
3339 		pr_err("%s: failed to create workqueue\n", HCLGEVF_NAME);
3340 		return -ENOMEM;
3341 	}
3342 
3343 	hnae3_register_ae_algo(&ae_algovf);
3344 
3345 	return 0;
3346 }
3347 
3348 static void __exit hclgevf_exit(void)
3349 {
3350 	hnae3_unregister_ae_algo(&ae_algovf);
3351 	destroy_workqueue(hclgevf_wq);
3352 }
3353 module_init(hclgevf_init);
3354 module_exit(hclgevf_exit);
3355 
3356 MODULE_LICENSE("GPL");
3357 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
3358 MODULE_DESCRIPTION("HCLGEVF Driver");
3359 MODULE_VERSION(HCLGEVF_MOD_VERSION);
3360