1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/etherdevice.h> 5 #include <linux/iopoll.h> 6 #include <net/rtnetlink.h> 7 #include "hclgevf_cmd.h" 8 #include "hclgevf_main.h" 9 #include "hclge_mbx.h" 10 #include "hnae3.h" 11 12 #define HCLGEVF_NAME "hclgevf" 13 14 #define HCLGEVF_RESET_MAX_FAIL_CNT 5 15 16 static int hclgevf_reset_hdev(struct hclgevf_dev *hdev); 17 static struct hnae3_ae_algo ae_algovf; 18 19 static struct workqueue_struct *hclgevf_wq; 20 21 static const struct pci_device_id ae_algovf_pci_tbl[] = { 22 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0}, 23 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF), 0}, 24 /* required last entry */ 25 {0, } 26 }; 27 28 static const u8 hclgevf_hash_key[] = { 29 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2, 30 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0, 31 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4, 32 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C, 33 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA 34 }; 35 36 MODULE_DEVICE_TABLE(pci, ae_algovf_pci_tbl); 37 38 static const u32 cmdq_reg_addr_list[] = {HCLGEVF_CMDQ_TX_ADDR_L_REG, 39 HCLGEVF_CMDQ_TX_ADDR_H_REG, 40 HCLGEVF_CMDQ_TX_DEPTH_REG, 41 HCLGEVF_CMDQ_TX_TAIL_REG, 42 HCLGEVF_CMDQ_TX_HEAD_REG, 43 HCLGEVF_CMDQ_RX_ADDR_L_REG, 44 HCLGEVF_CMDQ_RX_ADDR_H_REG, 45 HCLGEVF_CMDQ_RX_DEPTH_REG, 46 HCLGEVF_CMDQ_RX_TAIL_REG, 47 HCLGEVF_CMDQ_RX_HEAD_REG, 48 HCLGEVF_VECTOR0_CMDQ_SRC_REG, 49 HCLGEVF_VECTOR0_CMDQ_STATE_REG, 50 HCLGEVF_CMDQ_INTR_EN_REG, 51 HCLGEVF_CMDQ_INTR_GEN_REG}; 52 53 static const u32 common_reg_addr_list[] = {HCLGEVF_MISC_VECTOR_REG_BASE, 54 HCLGEVF_RST_ING, 55 HCLGEVF_GRO_EN_REG}; 56 57 static const u32 ring_reg_addr_list[] = {HCLGEVF_RING_RX_ADDR_L_REG, 58 HCLGEVF_RING_RX_ADDR_H_REG, 59 HCLGEVF_RING_RX_BD_NUM_REG, 60 HCLGEVF_RING_RX_BD_LENGTH_REG, 61 HCLGEVF_RING_RX_MERGE_EN_REG, 62 HCLGEVF_RING_RX_TAIL_REG, 63 HCLGEVF_RING_RX_HEAD_REG, 64 HCLGEVF_RING_RX_FBD_NUM_REG, 65 HCLGEVF_RING_RX_OFFSET_REG, 66 HCLGEVF_RING_RX_FBD_OFFSET_REG, 67 HCLGEVF_RING_RX_STASH_REG, 68 HCLGEVF_RING_RX_BD_ERR_REG, 69 HCLGEVF_RING_TX_ADDR_L_REG, 70 HCLGEVF_RING_TX_ADDR_H_REG, 71 HCLGEVF_RING_TX_BD_NUM_REG, 72 HCLGEVF_RING_TX_PRIORITY_REG, 73 HCLGEVF_RING_TX_TC_REG, 74 HCLGEVF_RING_TX_MERGE_EN_REG, 75 HCLGEVF_RING_TX_TAIL_REG, 76 HCLGEVF_RING_TX_HEAD_REG, 77 HCLGEVF_RING_TX_FBD_NUM_REG, 78 HCLGEVF_RING_TX_OFFSET_REG, 79 HCLGEVF_RING_TX_EBD_NUM_REG, 80 HCLGEVF_RING_TX_EBD_OFFSET_REG, 81 HCLGEVF_RING_TX_BD_ERR_REG, 82 HCLGEVF_RING_EN_REG}; 83 84 static const u32 tqp_intr_reg_addr_list[] = {HCLGEVF_TQP_INTR_CTRL_REG, 85 HCLGEVF_TQP_INTR_GL0_REG, 86 HCLGEVF_TQP_INTR_GL1_REG, 87 HCLGEVF_TQP_INTR_GL2_REG, 88 HCLGEVF_TQP_INTR_RL_REG}; 89 90 static struct hclgevf_dev *hclgevf_ae_get_hdev(struct hnae3_handle *handle) 91 { 92 if (!handle->client) 93 return container_of(handle, struct hclgevf_dev, nic); 94 else if (handle->client->type == HNAE3_CLIENT_ROCE) 95 return container_of(handle, struct hclgevf_dev, roce); 96 else 97 return container_of(handle, struct hclgevf_dev, nic); 98 } 99 100 static int hclgevf_tqps_update_stats(struct hnae3_handle *handle) 101 { 102 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 103 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 104 struct hclgevf_desc desc; 105 struct hclgevf_tqp *tqp; 106 int status; 107 int i; 108 109 for (i = 0; i < kinfo->num_tqps; i++) { 110 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 111 hclgevf_cmd_setup_basic_desc(&desc, 112 HCLGEVF_OPC_QUERY_RX_STATUS, 113 true); 114 115 desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 116 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 117 if (status) { 118 dev_err(&hdev->pdev->dev, 119 "Query tqp stat fail, status = %d,queue = %d\n", 120 status, i); 121 return status; 122 } 123 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd += 124 le32_to_cpu(desc.data[1]); 125 126 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_TX_STATUS, 127 true); 128 129 desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 130 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 131 if (status) { 132 dev_err(&hdev->pdev->dev, 133 "Query tqp stat fail, status = %d,queue = %d\n", 134 status, i); 135 return status; 136 } 137 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd += 138 le32_to_cpu(desc.data[1]); 139 } 140 141 return 0; 142 } 143 144 static u64 *hclgevf_tqps_get_stats(struct hnae3_handle *handle, u64 *data) 145 { 146 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 147 struct hclgevf_tqp *tqp; 148 u64 *buff = data; 149 int i; 150 151 for (i = 0; i < kinfo->num_tqps; i++) { 152 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 153 *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd; 154 } 155 for (i = 0; i < kinfo->num_tqps; i++) { 156 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 157 *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd; 158 } 159 160 return buff; 161 } 162 163 static int hclgevf_tqps_get_sset_count(struct hnae3_handle *handle, int strset) 164 { 165 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 166 167 return kinfo->num_tqps * 2; 168 } 169 170 static u8 *hclgevf_tqps_get_strings(struct hnae3_handle *handle, u8 *data) 171 { 172 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 173 u8 *buff = data; 174 int i = 0; 175 176 for (i = 0; i < kinfo->num_tqps; i++) { 177 struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 178 struct hclgevf_tqp, q); 179 snprintf(buff, ETH_GSTRING_LEN, "txq%d_pktnum_rcd", 180 tqp->index); 181 buff += ETH_GSTRING_LEN; 182 } 183 184 for (i = 0; i < kinfo->num_tqps; i++) { 185 struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 186 struct hclgevf_tqp, q); 187 snprintf(buff, ETH_GSTRING_LEN, "rxq%d_pktnum_rcd", 188 tqp->index); 189 buff += ETH_GSTRING_LEN; 190 } 191 192 return buff; 193 } 194 195 static void hclgevf_update_stats(struct hnae3_handle *handle, 196 struct net_device_stats *net_stats) 197 { 198 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 199 int status; 200 201 status = hclgevf_tqps_update_stats(handle); 202 if (status) 203 dev_err(&hdev->pdev->dev, 204 "VF update of TQPS stats fail, status = %d.\n", 205 status); 206 } 207 208 static int hclgevf_get_sset_count(struct hnae3_handle *handle, int strset) 209 { 210 if (strset == ETH_SS_TEST) 211 return -EOPNOTSUPP; 212 else if (strset == ETH_SS_STATS) 213 return hclgevf_tqps_get_sset_count(handle, strset); 214 215 return 0; 216 } 217 218 static void hclgevf_get_strings(struct hnae3_handle *handle, u32 strset, 219 u8 *data) 220 { 221 u8 *p = (char *)data; 222 223 if (strset == ETH_SS_STATS) 224 p = hclgevf_tqps_get_strings(handle, p); 225 } 226 227 static void hclgevf_get_stats(struct hnae3_handle *handle, u64 *data) 228 { 229 hclgevf_tqps_get_stats(handle, data); 230 } 231 232 static void hclgevf_build_send_msg(struct hclge_vf_to_pf_msg *msg, u8 code, 233 u8 subcode) 234 { 235 if (msg) { 236 memset(msg, 0, sizeof(struct hclge_vf_to_pf_msg)); 237 msg->code = code; 238 msg->subcode = subcode; 239 } 240 } 241 242 static int hclgevf_get_tc_info(struct hclgevf_dev *hdev) 243 { 244 struct hclge_vf_to_pf_msg send_msg; 245 u8 resp_msg; 246 int status; 247 248 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_TCINFO, 0); 249 status = hclgevf_send_mbx_msg(hdev, &send_msg, true, &resp_msg, 250 sizeof(resp_msg)); 251 if (status) { 252 dev_err(&hdev->pdev->dev, 253 "VF request to get TC info from PF failed %d", 254 status); 255 return status; 256 } 257 258 hdev->hw_tc_map = resp_msg; 259 260 return 0; 261 } 262 263 static int hclgevf_get_port_base_vlan_filter_state(struct hclgevf_dev *hdev) 264 { 265 struct hnae3_handle *nic = &hdev->nic; 266 struct hclge_vf_to_pf_msg send_msg; 267 u8 resp_msg; 268 int ret; 269 270 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 271 HCLGE_MBX_GET_PORT_BASE_VLAN_STATE); 272 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, &resp_msg, 273 sizeof(u8)); 274 if (ret) { 275 dev_err(&hdev->pdev->dev, 276 "VF request to get port based vlan state failed %d", 277 ret); 278 return ret; 279 } 280 281 nic->port_base_vlan_state = resp_msg; 282 283 return 0; 284 } 285 286 static int hclgevf_get_queue_info(struct hclgevf_dev *hdev) 287 { 288 #define HCLGEVF_TQPS_RSS_INFO_LEN 6 289 #define HCLGEVF_TQPS_ALLOC_OFFSET 0 290 #define HCLGEVF_TQPS_RSS_SIZE_OFFSET 2 291 #define HCLGEVF_TQPS_RX_BUFFER_LEN_OFFSET 4 292 293 u8 resp_msg[HCLGEVF_TQPS_RSS_INFO_LEN]; 294 struct hclge_vf_to_pf_msg send_msg; 295 int status; 296 297 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QINFO, 0); 298 status = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 299 HCLGEVF_TQPS_RSS_INFO_LEN); 300 if (status) { 301 dev_err(&hdev->pdev->dev, 302 "VF request to get tqp info from PF failed %d", 303 status); 304 return status; 305 } 306 307 memcpy(&hdev->num_tqps, &resp_msg[HCLGEVF_TQPS_ALLOC_OFFSET], 308 sizeof(u16)); 309 memcpy(&hdev->rss_size_max, &resp_msg[HCLGEVF_TQPS_RSS_SIZE_OFFSET], 310 sizeof(u16)); 311 memcpy(&hdev->rx_buf_len, &resp_msg[HCLGEVF_TQPS_RX_BUFFER_LEN_OFFSET], 312 sizeof(u16)); 313 314 return 0; 315 } 316 317 static int hclgevf_get_queue_depth(struct hclgevf_dev *hdev) 318 { 319 #define HCLGEVF_TQPS_DEPTH_INFO_LEN 4 320 #define HCLGEVF_TQPS_NUM_TX_DESC_OFFSET 0 321 #define HCLGEVF_TQPS_NUM_RX_DESC_OFFSET 2 322 323 u8 resp_msg[HCLGEVF_TQPS_DEPTH_INFO_LEN]; 324 struct hclge_vf_to_pf_msg send_msg; 325 int ret; 326 327 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QDEPTH, 0); 328 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 329 HCLGEVF_TQPS_DEPTH_INFO_LEN); 330 if (ret) { 331 dev_err(&hdev->pdev->dev, 332 "VF request to get tqp depth info from PF failed %d", 333 ret); 334 return ret; 335 } 336 337 memcpy(&hdev->num_tx_desc, &resp_msg[HCLGEVF_TQPS_NUM_TX_DESC_OFFSET], 338 sizeof(u16)); 339 memcpy(&hdev->num_rx_desc, &resp_msg[HCLGEVF_TQPS_NUM_RX_DESC_OFFSET], 340 sizeof(u16)); 341 342 return 0; 343 } 344 345 static u16 hclgevf_get_qid_global(struct hnae3_handle *handle, u16 queue_id) 346 { 347 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 348 struct hclge_vf_to_pf_msg send_msg; 349 u16 qid_in_pf = 0; 350 u8 resp_data[2]; 351 int ret; 352 353 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QID_IN_PF, 0); 354 memcpy(send_msg.data, &queue_id, sizeof(queue_id)); 355 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_data, 356 sizeof(resp_data)); 357 if (!ret) 358 qid_in_pf = *(u16 *)resp_data; 359 360 return qid_in_pf; 361 } 362 363 static int hclgevf_get_pf_media_type(struct hclgevf_dev *hdev) 364 { 365 struct hclge_vf_to_pf_msg send_msg; 366 u8 resp_msg[2]; 367 int ret; 368 369 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_MEDIA_TYPE, 0); 370 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 371 sizeof(resp_msg)); 372 if (ret) { 373 dev_err(&hdev->pdev->dev, 374 "VF request to get the pf port media type failed %d", 375 ret); 376 return ret; 377 } 378 379 hdev->hw.mac.media_type = resp_msg[0]; 380 hdev->hw.mac.module_type = resp_msg[1]; 381 382 return 0; 383 } 384 385 static int hclgevf_alloc_tqps(struct hclgevf_dev *hdev) 386 { 387 struct hclgevf_tqp *tqp; 388 int i; 389 390 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 391 sizeof(struct hclgevf_tqp), GFP_KERNEL); 392 if (!hdev->htqp) 393 return -ENOMEM; 394 395 tqp = hdev->htqp; 396 397 for (i = 0; i < hdev->num_tqps; i++) { 398 tqp->dev = &hdev->pdev->dev; 399 tqp->index = i; 400 401 tqp->q.ae_algo = &ae_algovf; 402 tqp->q.buf_size = hdev->rx_buf_len; 403 tqp->q.tx_desc_num = hdev->num_tx_desc; 404 tqp->q.rx_desc_num = hdev->num_rx_desc; 405 tqp->q.io_base = hdev->hw.io_base + HCLGEVF_TQP_REG_OFFSET + 406 i * HCLGEVF_TQP_REG_SIZE; 407 408 tqp++; 409 } 410 411 return 0; 412 } 413 414 static int hclgevf_knic_setup(struct hclgevf_dev *hdev) 415 { 416 struct hnae3_handle *nic = &hdev->nic; 417 struct hnae3_knic_private_info *kinfo; 418 u16 new_tqps = hdev->num_tqps; 419 unsigned int i; 420 421 kinfo = &nic->kinfo; 422 kinfo->num_tc = 0; 423 kinfo->num_tx_desc = hdev->num_tx_desc; 424 kinfo->num_rx_desc = hdev->num_rx_desc; 425 kinfo->rx_buf_len = hdev->rx_buf_len; 426 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) 427 if (hdev->hw_tc_map & BIT(i)) 428 kinfo->num_tc++; 429 430 kinfo->rss_size 431 = min_t(u16, hdev->rss_size_max, new_tqps / kinfo->num_tc); 432 new_tqps = kinfo->rss_size * kinfo->num_tc; 433 kinfo->num_tqps = min(new_tqps, hdev->num_tqps); 434 435 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps, 436 sizeof(struct hnae3_queue *), GFP_KERNEL); 437 if (!kinfo->tqp) 438 return -ENOMEM; 439 440 for (i = 0; i < kinfo->num_tqps; i++) { 441 hdev->htqp[i].q.handle = &hdev->nic; 442 hdev->htqp[i].q.tqp_index = i; 443 kinfo->tqp[i] = &hdev->htqp[i].q; 444 } 445 446 /* after init the max rss_size and tqps, adjust the default tqp numbers 447 * and rss size with the actual vector numbers 448 */ 449 kinfo->num_tqps = min_t(u16, hdev->num_nic_msix - 1, kinfo->num_tqps); 450 kinfo->rss_size = min_t(u16, kinfo->num_tqps / kinfo->num_tc, 451 kinfo->rss_size); 452 453 return 0; 454 } 455 456 static void hclgevf_request_link_info(struct hclgevf_dev *hdev) 457 { 458 struct hclge_vf_to_pf_msg send_msg; 459 int status; 460 461 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_LINK_STATUS, 0); 462 status = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 463 if (status) 464 dev_err(&hdev->pdev->dev, 465 "VF failed to fetch link status(%d) from PF", status); 466 } 467 468 void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state) 469 { 470 struct hnae3_handle *rhandle = &hdev->roce; 471 struct hnae3_handle *handle = &hdev->nic; 472 struct hnae3_client *rclient; 473 struct hnae3_client *client; 474 475 if (test_and_set_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state)) 476 return; 477 478 client = handle->client; 479 rclient = hdev->roce_client; 480 481 link_state = 482 test_bit(HCLGEVF_STATE_DOWN, &hdev->state) ? 0 : link_state; 483 484 if (link_state != hdev->hw.mac.link) { 485 client->ops->link_status_change(handle, !!link_state); 486 if (rclient && rclient->ops->link_status_change) 487 rclient->ops->link_status_change(rhandle, !!link_state); 488 hdev->hw.mac.link = link_state; 489 } 490 491 clear_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state); 492 } 493 494 static void hclgevf_update_link_mode(struct hclgevf_dev *hdev) 495 { 496 #define HCLGEVF_ADVERTISING 0 497 #define HCLGEVF_SUPPORTED 1 498 499 struct hclge_vf_to_pf_msg send_msg; 500 501 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_LINK_MODE, 0); 502 send_msg.data[0] = HCLGEVF_ADVERTISING; 503 hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 504 send_msg.data[0] = HCLGEVF_SUPPORTED; 505 hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 506 } 507 508 static int hclgevf_set_handle_info(struct hclgevf_dev *hdev) 509 { 510 struct hnae3_handle *nic = &hdev->nic; 511 int ret; 512 513 nic->ae_algo = &ae_algovf; 514 nic->pdev = hdev->pdev; 515 nic->numa_node_mask = hdev->numa_node_mask; 516 nic->flags |= HNAE3_SUPPORT_VF; 517 518 ret = hclgevf_knic_setup(hdev); 519 if (ret) 520 dev_err(&hdev->pdev->dev, "VF knic setup failed %d\n", 521 ret); 522 return ret; 523 } 524 525 static void hclgevf_free_vector(struct hclgevf_dev *hdev, int vector_id) 526 { 527 if (hdev->vector_status[vector_id] == HCLGEVF_INVALID_VPORT) { 528 dev_warn(&hdev->pdev->dev, 529 "vector(vector_id %d) has been freed.\n", vector_id); 530 return; 531 } 532 533 hdev->vector_status[vector_id] = HCLGEVF_INVALID_VPORT; 534 hdev->num_msi_left += 1; 535 hdev->num_msi_used -= 1; 536 } 537 538 static int hclgevf_get_vector(struct hnae3_handle *handle, u16 vector_num, 539 struct hnae3_vector_info *vector_info) 540 { 541 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 542 struct hnae3_vector_info *vector = vector_info; 543 int alloc = 0; 544 int i, j; 545 546 vector_num = min_t(u16, hdev->num_nic_msix - 1, vector_num); 547 vector_num = min(hdev->num_msi_left, vector_num); 548 549 for (j = 0; j < vector_num; j++) { 550 for (i = HCLGEVF_MISC_VECTOR_NUM + 1; i < hdev->num_msi; i++) { 551 if (hdev->vector_status[i] == HCLGEVF_INVALID_VPORT) { 552 vector->vector = pci_irq_vector(hdev->pdev, i); 553 vector->io_addr = hdev->hw.io_base + 554 HCLGEVF_VECTOR_REG_BASE + 555 (i - 1) * HCLGEVF_VECTOR_REG_OFFSET; 556 hdev->vector_status[i] = 0; 557 hdev->vector_irq[i] = vector->vector; 558 559 vector++; 560 alloc++; 561 562 break; 563 } 564 } 565 } 566 hdev->num_msi_left -= alloc; 567 hdev->num_msi_used += alloc; 568 569 return alloc; 570 } 571 572 static int hclgevf_get_vector_index(struct hclgevf_dev *hdev, int vector) 573 { 574 int i; 575 576 for (i = 0; i < hdev->num_msi; i++) 577 if (vector == hdev->vector_irq[i]) 578 return i; 579 580 return -EINVAL; 581 } 582 583 static int hclgevf_set_rss_algo_key(struct hclgevf_dev *hdev, 584 const u8 hfunc, const u8 *key) 585 { 586 struct hclgevf_rss_config_cmd *req; 587 unsigned int key_offset = 0; 588 struct hclgevf_desc desc; 589 int key_counts; 590 int key_size; 591 int ret; 592 593 key_counts = HCLGEVF_RSS_KEY_SIZE; 594 req = (struct hclgevf_rss_config_cmd *)desc.data; 595 596 while (key_counts) { 597 hclgevf_cmd_setup_basic_desc(&desc, 598 HCLGEVF_OPC_RSS_GENERIC_CONFIG, 599 false); 600 601 req->hash_config |= (hfunc & HCLGEVF_RSS_HASH_ALGO_MASK); 602 req->hash_config |= 603 (key_offset << HCLGEVF_RSS_HASH_KEY_OFFSET_B); 604 605 key_size = min(HCLGEVF_RSS_HASH_KEY_NUM, key_counts); 606 memcpy(req->hash_key, 607 key + key_offset * HCLGEVF_RSS_HASH_KEY_NUM, key_size); 608 609 key_counts -= key_size; 610 key_offset++; 611 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 612 if (ret) { 613 dev_err(&hdev->pdev->dev, 614 "Configure RSS config fail, status = %d\n", 615 ret); 616 return ret; 617 } 618 } 619 620 return 0; 621 } 622 623 static u32 hclgevf_get_rss_key_size(struct hnae3_handle *handle) 624 { 625 return HCLGEVF_RSS_KEY_SIZE; 626 } 627 628 static u32 hclgevf_get_rss_indir_size(struct hnae3_handle *handle) 629 { 630 return HCLGEVF_RSS_IND_TBL_SIZE; 631 } 632 633 static int hclgevf_set_rss_indir_table(struct hclgevf_dev *hdev) 634 { 635 const u8 *indir = hdev->rss_cfg.rss_indirection_tbl; 636 struct hclgevf_rss_indirection_table_cmd *req; 637 struct hclgevf_desc desc; 638 int status; 639 int i, j; 640 641 req = (struct hclgevf_rss_indirection_table_cmd *)desc.data; 642 643 for (i = 0; i < HCLGEVF_RSS_CFG_TBL_NUM; i++) { 644 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INDIR_TABLE, 645 false); 646 req->start_table_index = i * HCLGEVF_RSS_CFG_TBL_SIZE; 647 req->rss_set_bitmap = HCLGEVF_RSS_SET_BITMAP_MSK; 648 for (j = 0; j < HCLGEVF_RSS_CFG_TBL_SIZE; j++) 649 req->rss_result[j] = 650 indir[i * HCLGEVF_RSS_CFG_TBL_SIZE + j]; 651 652 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 653 if (status) { 654 dev_err(&hdev->pdev->dev, 655 "VF failed(=%d) to set RSS indirection table\n", 656 status); 657 return status; 658 } 659 } 660 661 return 0; 662 } 663 664 static int hclgevf_set_rss_tc_mode(struct hclgevf_dev *hdev, u16 rss_size) 665 { 666 struct hclgevf_rss_tc_mode_cmd *req; 667 u16 tc_offset[HCLGEVF_MAX_TC_NUM]; 668 u16 tc_valid[HCLGEVF_MAX_TC_NUM]; 669 u16 tc_size[HCLGEVF_MAX_TC_NUM]; 670 struct hclgevf_desc desc; 671 u16 roundup_size; 672 unsigned int i; 673 int status; 674 675 req = (struct hclgevf_rss_tc_mode_cmd *)desc.data; 676 677 roundup_size = roundup_pow_of_two(rss_size); 678 roundup_size = ilog2(roundup_size); 679 680 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 681 tc_valid[i] = !!(hdev->hw_tc_map & BIT(i)); 682 tc_size[i] = roundup_size; 683 tc_offset[i] = rss_size * i; 684 } 685 686 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_TC_MODE, false); 687 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 688 hnae3_set_bit(req->rss_tc_mode[i], HCLGEVF_RSS_TC_VALID_B, 689 (tc_valid[i] & 0x1)); 690 hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_SIZE_M, 691 HCLGEVF_RSS_TC_SIZE_S, tc_size[i]); 692 hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_OFFSET_M, 693 HCLGEVF_RSS_TC_OFFSET_S, tc_offset[i]); 694 } 695 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 696 if (status) 697 dev_err(&hdev->pdev->dev, 698 "VF failed(=%d) to set rss tc mode\n", status); 699 700 return status; 701 } 702 703 /* for revision 0x20, vf shared the same rss config with pf */ 704 static int hclgevf_get_rss_hash_key(struct hclgevf_dev *hdev) 705 { 706 #define HCLGEVF_RSS_MBX_RESP_LEN 8 707 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 708 u8 resp_msg[HCLGEVF_RSS_MBX_RESP_LEN]; 709 struct hclge_vf_to_pf_msg send_msg; 710 u16 msg_num, hash_key_index; 711 u8 index; 712 int ret; 713 714 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_RSS_KEY, 0); 715 msg_num = (HCLGEVF_RSS_KEY_SIZE + HCLGEVF_RSS_MBX_RESP_LEN - 1) / 716 HCLGEVF_RSS_MBX_RESP_LEN; 717 for (index = 0; index < msg_num; index++) { 718 send_msg.data[0] = index; 719 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 720 HCLGEVF_RSS_MBX_RESP_LEN); 721 if (ret) { 722 dev_err(&hdev->pdev->dev, 723 "VF get rss hash key from PF failed, ret=%d", 724 ret); 725 return ret; 726 } 727 728 hash_key_index = HCLGEVF_RSS_MBX_RESP_LEN * index; 729 if (index == msg_num - 1) 730 memcpy(&rss_cfg->rss_hash_key[hash_key_index], 731 &resp_msg[0], 732 HCLGEVF_RSS_KEY_SIZE - hash_key_index); 733 else 734 memcpy(&rss_cfg->rss_hash_key[hash_key_index], 735 &resp_msg[0], HCLGEVF_RSS_MBX_RESP_LEN); 736 } 737 738 return 0; 739 } 740 741 static int hclgevf_get_rss(struct hnae3_handle *handle, u32 *indir, u8 *key, 742 u8 *hfunc) 743 { 744 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 745 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 746 int i, ret; 747 748 if (handle->pdev->revision >= 0x21) { 749 /* Get hash algorithm */ 750 if (hfunc) { 751 switch (rss_cfg->hash_algo) { 752 case HCLGEVF_RSS_HASH_ALGO_TOEPLITZ: 753 *hfunc = ETH_RSS_HASH_TOP; 754 break; 755 case HCLGEVF_RSS_HASH_ALGO_SIMPLE: 756 *hfunc = ETH_RSS_HASH_XOR; 757 break; 758 default: 759 *hfunc = ETH_RSS_HASH_UNKNOWN; 760 break; 761 } 762 } 763 764 /* Get the RSS Key required by the user */ 765 if (key) 766 memcpy(key, rss_cfg->rss_hash_key, 767 HCLGEVF_RSS_KEY_SIZE); 768 } else { 769 if (hfunc) 770 *hfunc = ETH_RSS_HASH_TOP; 771 if (key) { 772 ret = hclgevf_get_rss_hash_key(hdev); 773 if (ret) 774 return ret; 775 memcpy(key, rss_cfg->rss_hash_key, 776 HCLGEVF_RSS_KEY_SIZE); 777 } 778 } 779 780 if (indir) 781 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 782 indir[i] = rss_cfg->rss_indirection_tbl[i]; 783 784 return 0; 785 } 786 787 static int hclgevf_set_rss(struct hnae3_handle *handle, const u32 *indir, 788 const u8 *key, const u8 hfunc) 789 { 790 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 791 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 792 int ret, i; 793 794 if (handle->pdev->revision >= 0x21) { 795 /* Set the RSS Hash Key if specififed by the user */ 796 if (key) { 797 switch (hfunc) { 798 case ETH_RSS_HASH_TOP: 799 rss_cfg->hash_algo = 800 HCLGEVF_RSS_HASH_ALGO_TOEPLITZ; 801 break; 802 case ETH_RSS_HASH_XOR: 803 rss_cfg->hash_algo = 804 HCLGEVF_RSS_HASH_ALGO_SIMPLE; 805 break; 806 case ETH_RSS_HASH_NO_CHANGE: 807 break; 808 default: 809 return -EINVAL; 810 } 811 812 ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 813 key); 814 if (ret) 815 return ret; 816 817 /* Update the shadow RSS key with user specified qids */ 818 memcpy(rss_cfg->rss_hash_key, key, 819 HCLGEVF_RSS_KEY_SIZE); 820 } 821 } 822 823 /* update the shadow RSS table with user specified qids */ 824 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 825 rss_cfg->rss_indirection_tbl[i] = indir[i]; 826 827 /* update the hardware */ 828 return hclgevf_set_rss_indir_table(hdev); 829 } 830 831 static u8 hclgevf_get_rss_hash_bits(struct ethtool_rxnfc *nfc) 832 { 833 u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGEVF_S_PORT_BIT : 0; 834 835 if (nfc->data & RXH_L4_B_2_3) 836 hash_sets |= HCLGEVF_D_PORT_BIT; 837 else 838 hash_sets &= ~HCLGEVF_D_PORT_BIT; 839 840 if (nfc->data & RXH_IP_SRC) 841 hash_sets |= HCLGEVF_S_IP_BIT; 842 else 843 hash_sets &= ~HCLGEVF_S_IP_BIT; 844 845 if (nfc->data & RXH_IP_DST) 846 hash_sets |= HCLGEVF_D_IP_BIT; 847 else 848 hash_sets &= ~HCLGEVF_D_IP_BIT; 849 850 if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW) 851 hash_sets |= HCLGEVF_V_TAG_BIT; 852 853 return hash_sets; 854 } 855 856 static int hclgevf_set_rss_tuple(struct hnae3_handle *handle, 857 struct ethtool_rxnfc *nfc) 858 { 859 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 860 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 861 struct hclgevf_rss_input_tuple_cmd *req; 862 struct hclgevf_desc desc; 863 u8 tuple_sets; 864 int ret; 865 866 if (handle->pdev->revision == 0x20) 867 return -EOPNOTSUPP; 868 869 if (nfc->data & 870 ~(RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3)) 871 return -EINVAL; 872 873 req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 874 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 875 876 req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 877 req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 878 req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 879 req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 880 req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 881 req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 882 req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 883 req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 884 885 tuple_sets = hclgevf_get_rss_hash_bits(nfc); 886 switch (nfc->flow_type) { 887 case TCP_V4_FLOW: 888 req->ipv4_tcp_en = tuple_sets; 889 break; 890 case TCP_V6_FLOW: 891 req->ipv6_tcp_en = tuple_sets; 892 break; 893 case UDP_V4_FLOW: 894 req->ipv4_udp_en = tuple_sets; 895 break; 896 case UDP_V6_FLOW: 897 req->ipv6_udp_en = tuple_sets; 898 break; 899 case SCTP_V4_FLOW: 900 req->ipv4_sctp_en = tuple_sets; 901 break; 902 case SCTP_V6_FLOW: 903 if ((nfc->data & RXH_L4_B_0_1) || 904 (nfc->data & RXH_L4_B_2_3)) 905 return -EINVAL; 906 907 req->ipv6_sctp_en = tuple_sets; 908 break; 909 case IPV4_FLOW: 910 req->ipv4_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 911 break; 912 case IPV6_FLOW: 913 req->ipv6_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 914 break; 915 default: 916 return -EINVAL; 917 } 918 919 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 920 if (ret) { 921 dev_err(&hdev->pdev->dev, 922 "Set rss tuple fail, status = %d\n", ret); 923 return ret; 924 } 925 926 rss_cfg->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en; 927 rss_cfg->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en; 928 rss_cfg->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en; 929 rss_cfg->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en; 930 rss_cfg->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en; 931 rss_cfg->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en; 932 rss_cfg->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en; 933 rss_cfg->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en; 934 return 0; 935 } 936 937 static int hclgevf_get_rss_tuple(struct hnae3_handle *handle, 938 struct ethtool_rxnfc *nfc) 939 { 940 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 941 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 942 u8 tuple_sets; 943 944 if (handle->pdev->revision == 0x20) 945 return -EOPNOTSUPP; 946 947 nfc->data = 0; 948 949 switch (nfc->flow_type) { 950 case TCP_V4_FLOW: 951 tuple_sets = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 952 break; 953 case UDP_V4_FLOW: 954 tuple_sets = rss_cfg->rss_tuple_sets.ipv4_udp_en; 955 break; 956 case TCP_V6_FLOW: 957 tuple_sets = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 958 break; 959 case UDP_V6_FLOW: 960 tuple_sets = rss_cfg->rss_tuple_sets.ipv6_udp_en; 961 break; 962 case SCTP_V4_FLOW: 963 tuple_sets = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 964 break; 965 case SCTP_V6_FLOW: 966 tuple_sets = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 967 break; 968 case IPV4_FLOW: 969 case IPV6_FLOW: 970 tuple_sets = HCLGEVF_S_IP_BIT | HCLGEVF_D_IP_BIT; 971 break; 972 default: 973 return -EINVAL; 974 } 975 976 if (!tuple_sets) 977 return 0; 978 979 if (tuple_sets & HCLGEVF_D_PORT_BIT) 980 nfc->data |= RXH_L4_B_2_3; 981 if (tuple_sets & HCLGEVF_S_PORT_BIT) 982 nfc->data |= RXH_L4_B_0_1; 983 if (tuple_sets & HCLGEVF_D_IP_BIT) 984 nfc->data |= RXH_IP_DST; 985 if (tuple_sets & HCLGEVF_S_IP_BIT) 986 nfc->data |= RXH_IP_SRC; 987 988 return 0; 989 } 990 991 static int hclgevf_set_rss_input_tuple(struct hclgevf_dev *hdev, 992 struct hclgevf_rss_cfg *rss_cfg) 993 { 994 struct hclgevf_rss_input_tuple_cmd *req; 995 struct hclgevf_desc desc; 996 int ret; 997 998 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 999 1000 req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 1001 1002 req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 1003 req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 1004 req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 1005 req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 1006 req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 1007 req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 1008 req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 1009 req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 1010 1011 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1012 if (ret) 1013 dev_err(&hdev->pdev->dev, 1014 "Configure rss input fail, status = %d\n", ret); 1015 return ret; 1016 } 1017 1018 static int hclgevf_get_tc_size(struct hnae3_handle *handle) 1019 { 1020 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1021 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 1022 1023 return rss_cfg->rss_size; 1024 } 1025 1026 static int hclgevf_bind_ring_to_vector(struct hnae3_handle *handle, bool en, 1027 int vector_id, 1028 struct hnae3_ring_chain_node *ring_chain) 1029 { 1030 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1031 struct hclge_vf_to_pf_msg send_msg; 1032 struct hnae3_ring_chain_node *node; 1033 int status; 1034 int i = 0; 1035 1036 memset(&send_msg, 0, sizeof(send_msg)); 1037 send_msg.code = en ? HCLGE_MBX_MAP_RING_TO_VECTOR : 1038 HCLGE_MBX_UNMAP_RING_TO_VECTOR; 1039 send_msg.vector_id = vector_id; 1040 1041 for (node = ring_chain; node; node = node->next) { 1042 send_msg.param[i].ring_type = 1043 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B); 1044 1045 send_msg.param[i].tqp_index = node->tqp_index; 1046 send_msg.param[i].int_gl_index = 1047 hnae3_get_field(node->int_gl_idx, 1048 HNAE3_RING_GL_IDX_M, 1049 HNAE3_RING_GL_IDX_S); 1050 1051 i++; 1052 if (i == HCLGE_MBX_MAX_RING_CHAIN_PARAM_NUM || !node->next) { 1053 send_msg.ring_num = i; 1054 1055 status = hclgevf_send_mbx_msg(hdev, &send_msg, false, 1056 NULL, 0); 1057 if (status) { 1058 dev_err(&hdev->pdev->dev, 1059 "Map TQP fail, status is %d.\n", 1060 status); 1061 return status; 1062 } 1063 i = 0; 1064 } 1065 } 1066 1067 return 0; 1068 } 1069 1070 static int hclgevf_map_ring_to_vector(struct hnae3_handle *handle, int vector, 1071 struct hnae3_ring_chain_node *ring_chain) 1072 { 1073 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1074 int vector_id; 1075 1076 vector_id = hclgevf_get_vector_index(hdev, vector); 1077 if (vector_id < 0) { 1078 dev_err(&handle->pdev->dev, 1079 "Get vector index fail. ret =%d\n", vector_id); 1080 return vector_id; 1081 } 1082 1083 return hclgevf_bind_ring_to_vector(handle, true, vector_id, ring_chain); 1084 } 1085 1086 static int hclgevf_unmap_ring_from_vector( 1087 struct hnae3_handle *handle, 1088 int vector, 1089 struct hnae3_ring_chain_node *ring_chain) 1090 { 1091 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1092 int ret, vector_id; 1093 1094 if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 1095 return 0; 1096 1097 vector_id = hclgevf_get_vector_index(hdev, vector); 1098 if (vector_id < 0) { 1099 dev_err(&handle->pdev->dev, 1100 "Get vector index fail. ret =%d\n", vector_id); 1101 return vector_id; 1102 } 1103 1104 ret = hclgevf_bind_ring_to_vector(handle, false, vector_id, ring_chain); 1105 if (ret) 1106 dev_err(&handle->pdev->dev, 1107 "Unmap ring from vector fail. vector=%d, ret =%d\n", 1108 vector_id, 1109 ret); 1110 1111 return ret; 1112 } 1113 1114 static int hclgevf_put_vector(struct hnae3_handle *handle, int vector) 1115 { 1116 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1117 int vector_id; 1118 1119 vector_id = hclgevf_get_vector_index(hdev, vector); 1120 if (vector_id < 0) { 1121 dev_err(&handle->pdev->dev, 1122 "hclgevf_put_vector get vector index fail. ret =%d\n", 1123 vector_id); 1124 return vector_id; 1125 } 1126 1127 hclgevf_free_vector(hdev, vector_id); 1128 1129 return 0; 1130 } 1131 1132 static int hclgevf_cmd_set_promisc_mode(struct hclgevf_dev *hdev, 1133 bool en_uc_pmc, bool en_mc_pmc, 1134 bool en_bc_pmc) 1135 { 1136 struct hclge_vf_to_pf_msg send_msg; 1137 int ret; 1138 1139 memset(&send_msg, 0, sizeof(send_msg)); 1140 send_msg.code = HCLGE_MBX_SET_PROMISC_MODE; 1141 send_msg.en_bc = en_bc_pmc ? 1 : 0; 1142 send_msg.en_uc = en_uc_pmc ? 1 : 0; 1143 send_msg.en_mc = en_mc_pmc ? 1 : 0; 1144 1145 ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 1146 if (ret) 1147 dev_err(&hdev->pdev->dev, 1148 "Set promisc mode fail, status is %d.\n", ret); 1149 1150 return ret; 1151 } 1152 1153 static int hclgevf_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc, 1154 bool en_mc_pmc) 1155 { 1156 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1157 struct pci_dev *pdev = hdev->pdev; 1158 bool en_bc_pmc; 1159 1160 en_bc_pmc = pdev->revision != 0x20; 1161 1162 return hclgevf_cmd_set_promisc_mode(hdev, en_uc_pmc, en_mc_pmc, 1163 en_bc_pmc); 1164 } 1165 1166 static void hclgevf_request_update_promisc_mode(struct hnae3_handle *handle) 1167 { 1168 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1169 1170 set_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state); 1171 } 1172 1173 static void hclgevf_sync_promisc_mode(struct hclgevf_dev *hdev) 1174 { 1175 struct hnae3_handle *handle = &hdev->nic; 1176 bool en_uc_pmc = handle->netdev_flags & HNAE3_UPE; 1177 bool en_mc_pmc = handle->netdev_flags & HNAE3_MPE; 1178 int ret; 1179 1180 if (test_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state)) { 1181 ret = hclgevf_set_promisc_mode(handle, en_uc_pmc, en_mc_pmc); 1182 if (!ret) 1183 clear_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state); 1184 } 1185 } 1186 1187 static int hclgevf_tqp_enable(struct hclgevf_dev *hdev, unsigned int tqp_id, 1188 int stream_id, bool enable) 1189 { 1190 struct hclgevf_cfg_com_tqp_queue_cmd *req; 1191 struct hclgevf_desc desc; 1192 int status; 1193 1194 req = (struct hclgevf_cfg_com_tqp_queue_cmd *)desc.data; 1195 1196 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_CFG_COM_TQP_QUEUE, 1197 false); 1198 req->tqp_id = cpu_to_le16(tqp_id & HCLGEVF_RING_ID_MASK); 1199 req->stream_id = cpu_to_le16(stream_id); 1200 if (enable) 1201 req->enable |= 1U << HCLGEVF_TQP_ENABLE_B; 1202 1203 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1204 if (status) 1205 dev_err(&hdev->pdev->dev, 1206 "TQP enable fail, status =%d.\n", status); 1207 1208 return status; 1209 } 1210 1211 static void hclgevf_reset_tqp_stats(struct hnae3_handle *handle) 1212 { 1213 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 1214 struct hclgevf_tqp *tqp; 1215 int i; 1216 1217 for (i = 0; i < kinfo->num_tqps; i++) { 1218 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 1219 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats)); 1220 } 1221 } 1222 1223 static int hclgevf_get_host_mac_addr(struct hclgevf_dev *hdev, u8 *p) 1224 { 1225 struct hclge_vf_to_pf_msg send_msg; 1226 u8 host_mac[ETH_ALEN]; 1227 int status; 1228 1229 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_MAC_ADDR, 0); 1230 status = hclgevf_send_mbx_msg(hdev, &send_msg, true, host_mac, 1231 ETH_ALEN); 1232 if (status) { 1233 dev_err(&hdev->pdev->dev, 1234 "fail to get VF MAC from host %d", status); 1235 return status; 1236 } 1237 1238 ether_addr_copy(p, host_mac); 1239 1240 return 0; 1241 } 1242 1243 static void hclgevf_get_mac_addr(struct hnae3_handle *handle, u8 *p) 1244 { 1245 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1246 u8 host_mac_addr[ETH_ALEN]; 1247 1248 if (hclgevf_get_host_mac_addr(hdev, host_mac_addr)) 1249 return; 1250 1251 hdev->has_pf_mac = !is_zero_ether_addr(host_mac_addr); 1252 if (hdev->has_pf_mac) 1253 ether_addr_copy(p, host_mac_addr); 1254 else 1255 ether_addr_copy(p, hdev->hw.mac.mac_addr); 1256 } 1257 1258 static int hclgevf_set_mac_addr(struct hnae3_handle *handle, void *p, 1259 bool is_first) 1260 { 1261 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1262 u8 *old_mac_addr = (u8 *)hdev->hw.mac.mac_addr; 1263 struct hclge_vf_to_pf_msg send_msg; 1264 u8 *new_mac_addr = (u8 *)p; 1265 int status; 1266 1267 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_UNICAST, 0); 1268 send_msg.subcode = HCLGE_MBX_MAC_VLAN_UC_MODIFY; 1269 ether_addr_copy(send_msg.data, new_mac_addr); 1270 if (is_first && !hdev->has_pf_mac) 1271 eth_zero_addr(&send_msg.data[ETH_ALEN]); 1272 else 1273 ether_addr_copy(&send_msg.data[ETH_ALEN], old_mac_addr); 1274 status = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1275 if (!status) 1276 ether_addr_copy(hdev->hw.mac.mac_addr, new_mac_addr); 1277 1278 return status; 1279 } 1280 1281 static struct hclgevf_mac_addr_node * 1282 hclgevf_find_mac_node(struct list_head *list, const u8 *mac_addr) 1283 { 1284 struct hclgevf_mac_addr_node *mac_node, *tmp; 1285 1286 list_for_each_entry_safe(mac_node, tmp, list, node) 1287 if (ether_addr_equal(mac_addr, mac_node->mac_addr)) 1288 return mac_node; 1289 1290 return NULL; 1291 } 1292 1293 static void hclgevf_update_mac_node(struct hclgevf_mac_addr_node *mac_node, 1294 enum HCLGEVF_MAC_NODE_STATE state) 1295 { 1296 switch (state) { 1297 /* from set_rx_mode or tmp_add_list */ 1298 case HCLGEVF_MAC_TO_ADD: 1299 if (mac_node->state == HCLGEVF_MAC_TO_DEL) 1300 mac_node->state = HCLGEVF_MAC_ACTIVE; 1301 break; 1302 /* only from set_rx_mode */ 1303 case HCLGEVF_MAC_TO_DEL: 1304 if (mac_node->state == HCLGEVF_MAC_TO_ADD) { 1305 list_del(&mac_node->node); 1306 kfree(mac_node); 1307 } else { 1308 mac_node->state = HCLGEVF_MAC_TO_DEL; 1309 } 1310 break; 1311 /* only from tmp_add_list, the mac_node->state won't be 1312 * HCLGEVF_MAC_ACTIVE 1313 */ 1314 case HCLGEVF_MAC_ACTIVE: 1315 if (mac_node->state == HCLGEVF_MAC_TO_ADD) 1316 mac_node->state = HCLGEVF_MAC_ACTIVE; 1317 break; 1318 } 1319 } 1320 1321 static int hclgevf_update_mac_list(struct hnae3_handle *handle, 1322 enum HCLGEVF_MAC_NODE_STATE state, 1323 enum HCLGEVF_MAC_ADDR_TYPE mac_type, 1324 const unsigned char *addr) 1325 { 1326 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1327 struct hclgevf_mac_addr_node *mac_node; 1328 struct list_head *list; 1329 1330 list = (mac_type == HCLGEVF_MAC_ADDR_UC) ? 1331 &hdev->mac_table.uc_mac_list : &hdev->mac_table.mc_mac_list; 1332 1333 spin_lock_bh(&hdev->mac_table.mac_list_lock); 1334 1335 /* if the mac addr is already in the mac list, no need to add a new 1336 * one into it, just check the mac addr state, convert it to a new 1337 * new state, or just remove it, or do nothing. 1338 */ 1339 mac_node = hclgevf_find_mac_node(list, addr); 1340 if (mac_node) { 1341 hclgevf_update_mac_node(mac_node, state); 1342 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1343 return 0; 1344 } 1345 /* if this address is never added, unnecessary to delete */ 1346 if (state == HCLGEVF_MAC_TO_DEL) { 1347 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1348 return -ENOENT; 1349 } 1350 1351 mac_node = kzalloc(sizeof(*mac_node), GFP_ATOMIC); 1352 if (!mac_node) { 1353 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1354 return -ENOMEM; 1355 } 1356 1357 mac_node->state = state; 1358 ether_addr_copy(mac_node->mac_addr, addr); 1359 list_add_tail(&mac_node->node, list); 1360 1361 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1362 return 0; 1363 } 1364 1365 static int hclgevf_add_uc_addr(struct hnae3_handle *handle, 1366 const unsigned char *addr) 1367 { 1368 return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_ADD, 1369 HCLGEVF_MAC_ADDR_UC, addr); 1370 } 1371 1372 static int hclgevf_rm_uc_addr(struct hnae3_handle *handle, 1373 const unsigned char *addr) 1374 { 1375 return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_DEL, 1376 HCLGEVF_MAC_ADDR_UC, addr); 1377 } 1378 1379 static int hclgevf_add_mc_addr(struct hnae3_handle *handle, 1380 const unsigned char *addr) 1381 { 1382 return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_ADD, 1383 HCLGEVF_MAC_ADDR_MC, addr); 1384 } 1385 1386 static int hclgevf_rm_mc_addr(struct hnae3_handle *handle, 1387 const unsigned char *addr) 1388 { 1389 return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_DEL, 1390 HCLGEVF_MAC_ADDR_MC, addr); 1391 } 1392 1393 static int hclgevf_add_del_mac_addr(struct hclgevf_dev *hdev, 1394 struct hclgevf_mac_addr_node *mac_node, 1395 enum HCLGEVF_MAC_ADDR_TYPE mac_type) 1396 { 1397 struct hclge_vf_to_pf_msg send_msg; 1398 u8 code, subcode; 1399 1400 if (mac_type == HCLGEVF_MAC_ADDR_UC) { 1401 code = HCLGE_MBX_SET_UNICAST; 1402 if (mac_node->state == HCLGEVF_MAC_TO_ADD) 1403 subcode = HCLGE_MBX_MAC_VLAN_UC_ADD; 1404 else 1405 subcode = HCLGE_MBX_MAC_VLAN_UC_REMOVE; 1406 } else { 1407 code = HCLGE_MBX_SET_MULTICAST; 1408 if (mac_node->state == HCLGEVF_MAC_TO_ADD) 1409 subcode = HCLGE_MBX_MAC_VLAN_MC_ADD; 1410 else 1411 subcode = HCLGE_MBX_MAC_VLAN_MC_REMOVE; 1412 } 1413 1414 hclgevf_build_send_msg(&send_msg, code, subcode); 1415 ether_addr_copy(send_msg.data, mac_node->mac_addr); 1416 return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 1417 } 1418 1419 static void hclgevf_config_mac_list(struct hclgevf_dev *hdev, 1420 struct list_head *list, 1421 enum HCLGEVF_MAC_ADDR_TYPE mac_type) 1422 { 1423 struct hclgevf_mac_addr_node *mac_node, *tmp; 1424 int ret; 1425 1426 list_for_each_entry_safe(mac_node, tmp, list, node) { 1427 ret = hclgevf_add_del_mac_addr(hdev, mac_node, mac_type); 1428 if (ret) { 1429 dev_err(&hdev->pdev->dev, 1430 "failed to configure mac %pM, state = %d, ret = %d\n", 1431 mac_node->mac_addr, mac_node->state, ret); 1432 return; 1433 } 1434 if (mac_node->state == HCLGEVF_MAC_TO_ADD) { 1435 mac_node->state = HCLGEVF_MAC_ACTIVE; 1436 } else { 1437 list_del(&mac_node->node); 1438 kfree(mac_node); 1439 } 1440 } 1441 } 1442 1443 static void hclgevf_sync_from_add_list(struct list_head *add_list, 1444 struct list_head *mac_list) 1445 { 1446 struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node; 1447 1448 list_for_each_entry_safe(mac_node, tmp, add_list, node) { 1449 /* if the mac address from tmp_add_list is not in the 1450 * uc/mc_mac_list, it means have received a TO_DEL request 1451 * during the time window of sending mac config request to PF 1452 * If mac_node state is ACTIVE, then change its state to TO_DEL, 1453 * then it will be removed at next time. If is TO_ADD, it means 1454 * send TO_ADD request failed, so just remove the mac node. 1455 */ 1456 new_node = hclgevf_find_mac_node(mac_list, mac_node->mac_addr); 1457 if (new_node) { 1458 hclgevf_update_mac_node(new_node, mac_node->state); 1459 list_del(&mac_node->node); 1460 kfree(mac_node); 1461 } else if (mac_node->state == HCLGEVF_MAC_ACTIVE) { 1462 mac_node->state = HCLGEVF_MAC_TO_DEL; 1463 list_del(&mac_node->node); 1464 list_add_tail(&mac_node->node, mac_list); 1465 } else { 1466 list_del(&mac_node->node); 1467 kfree(mac_node); 1468 } 1469 } 1470 } 1471 1472 static void hclgevf_sync_from_del_list(struct list_head *del_list, 1473 struct list_head *mac_list) 1474 { 1475 struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node; 1476 1477 list_for_each_entry_safe(mac_node, tmp, del_list, node) { 1478 new_node = hclgevf_find_mac_node(mac_list, mac_node->mac_addr); 1479 if (new_node) { 1480 /* If the mac addr is exist in the mac list, it means 1481 * received a new request TO_ADD during the time window 1482 * of sending mac addr configurrequest to PF, so just 1483 * change the mac state to ACTIVE. 1484 */ 1485 new_node->state = HCLGEVF_MAC_ACTIVE; 1486 list_del(&mac_node->node); 1487 kfree(mac_node); 1488 } else { 1489 list_del(&mac_node->node); 1490 list_add_tail(&mac_node->node, mac_list); 1491 } 1492 } 1493 } 1494 1495 static void hclgevf_clear_list(struct list_head *list) 1496 { 1497 struct hclgevf_mac_addr_node *mac_node, *tmp; 1498 1499 list_for_each_entry_safe(mac_node, tmp, list, node) { 1500 list_del(&mac_node->node); 1501 kfree(mac_node); 1502 } 1503 } 1504 1505 static void hclgevf_sync_mac_list(struct hclgevf_dev *hdev, 1506 enum HCLGEVF_MAC_ADDR_TYPE mac_type) 1507 { 1508 struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node; 1509 struct list_head tmp_add_list, tmp_del_list; 1510 struct list_head *list; 1511 1512 INIT_LIST_HEAD(&tmp_add_list); 1513 INIT_LIST_HEAD(&tmp_del_list); 1514 1515 /* move the mac addr to the tmp_add_list and tmp_del_list, then 1516 * we can add/delete these mac addr outside the spin lock 1517 */ 1518 list = (mac_type == HCLGEVF_MAC_ADDR_UC) ? 1519 &hdev->mac_table.uc_mac_list : &hdev->mac_table.mc_mac_list; 1520 1521 spin_lock_bh(&hdev->mac_table.mac_list_lock); 1522 1523 list_for_each_entry_safe(mac_node, tmp, list, node) { 1524 switch (mac_node->state) { 1525 case HCLGEVF_MAC_TO_DEL: 1526 list_del(&mac_node->node); 1527 list_add_tail(&mac_node->node, &tmp_del_list); 1528 break; 1529 case HCLGEVF_MAC_TO_ADD: 1530 new_node = kzalloc(sizeof(*new_node), GFP_ATOMIC); 1531 if (!new_node) 1532 goto stop_traverse; 1533 1534 ether_addr_copy(new_node->mac_addr, mac_node->mac_addr); 1535 new_node->state = mac_node->state; 1536 list_add_tail(&new_node->node, &tmp_add_list); 1537 break; 1538 default: 1539 break; 1540 } 1541 } 1542 1543 stop_traverse: 1544 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1545 1546 /* delete first, in order to get max mac table space for adding */ 1547 hclgevf_config_mac_list(hdev, &tmp_del_list, mac_type); 1548 hclgevf_config_mac_list(hdev, &tmp_add_list, mac_type); 1549 1550 /* if some mac addresses were added/deleted fail, move back to the 1551 * mac_list, and retry at next time. 1552 */ 1553 spin_lock_bh(&hdev->mac_table.mac_list_lock); 1554 1555 hclgevf_sync_from_del_list(&tmp_del_list, list); 1556 hclgevf_sync_from_add_list(&tmp_add_list, list); 1557 1558 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1559 } 1560 1561 static void hclgevf_sync_mac_table(struct hclgevf_dev *hdev) 1562 { 1563 hclgevf_sync_mac_list(hdev, HCLGEVF_MAC_ADDR_UC); 1564 hclgevf_sync_mac_list(hdev, HCLGEVF_MAC_ADDR_MC); 1565 } 1566 1567 static void hclgevf_uninit_mac_list(struct hclgevf_dev *hdev) 1568 { 1569 spin_lock_bh(&hdev->mac_table.mac_list_lock); 1570 1571 hclgevf_clear_list(&hdev->mac_table.uc_mac_list); 1572 hclgevf_clear_list(&hdev->mac_table.mc_mac_list); 1573 1574 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1575 } 1576 1577 static int hclgevf_set_vlan_filter(struct hnae3_handle *handle, 1578 __be16 proto, u16 vlan_id, 1579 bool is_kill) 1580 { 1581 #define HCLGEVF_VLAN_MBX_IS_KILL_OFFSET 0 1582 #define HCLGEVF_VLAN_MBX_VLAN_ID_OFFSET 1 1583 #define HCLGEVF_VLAN_MBX_PROTO_OFFSET 3 1584 1585 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1586 struct hclge_vf_to_pf_msg send_msg; 1587 int ret; 1588 1589 if (vlan_id > HCLGEVF_MAX_VLAN_ID) 1590 return -EINVAL; 1591 1592 if (proto != htons(ETH_P_8021Q)) 1593 return -EPROTONOSUPPORT; 1594 1595 /* When device is resetting, firmware is unable to handle 1596 * mailbox. Just record the vlan id, and remove it after 1597 * reset finished. 1598 */ 1599 if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) && is_kill) { 1600 set_bit(vlan_id, hdev->vlan_del_fail_bmap); 1601 return -EBUSY; 1602 } 1603 1604 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 1605 HCLGE_MBX_VLAN_FILTER); 1606 send_msg.data[HCLGEVF_VLAN_MBX_IS_KILL_OFFSET] = is_kill; 1607 memcpy(&send_msg.data[HCLGEVF_VLAN_MBX_VLAN_ID_OFFSET], &vlan_id, 1608 sizeof(vlan_id)); 1609 memcpy(&send_msg.data[HCLGEVF_VLAN_MBX_PROTO_OFFSET], &proto, 1610 sizeof(proto)); 1611 /* when remove hw vlan filter failed, record the vlan id, 1612 * and try to remove it from hw later, to be consistence 1613 * with stack. 1614 */ 1615 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1616 if (is_kill && ret) 1617 set_bit(vlan_id, hdev->vlan_del_fail_bmap); 1618 1619 return ret; 1620 } 1621 1622 static void hclgevf_sync_vlan_filter(struct hclgevf_dev *hdev) 1623 { 1624 #define HCLGEVF_MAX_SYNC_COUNT 60 1625 struct hnae3_handle *handle = &hdev->nic; 1626 int ret, sync_cnt = 0; 1627 u16 vlan_id; 1628 1629 vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID); 1630 while (vlan_id != VLAN_N_VID) { 1631 ret = hclgevf_set_vlan_filter(handle, htons(ETH_P_8021Q), 1632 vlan_id, true); 1633 if (ret) 1634 return; 1635 1636 clear_bit(vlan_id, hdev->vlan_del_fail_bmap); 1637 sync_cnt++; 1638 if (sync_cnt >= HCLGEVF_MAX_SYNC_COUNT) 1639 return; 1640 1641 vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID); 1642 } 1643 } 1644 1645 static int hclgevf_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) 1646 { 1647 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1648 struct hclge_vf_to_pf_msg send_msg; 1649 1650 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 1651 HCLGE_MBX_VLAN_RX_OFF_CFG); 1652 send_msg.data[0] = enable ? 1 : 0; 1653 return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 1654 } 1655 1656 static int hclgevf_reset_tqp(struct hnae3_handle *handle, u16 queue_id) 1657 { 1658 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1659 struct hclge_vf_to_pf_msg send_msg; 1660 int ret; 1661 1662 /* disable vf queue before send queue reset msg to PF */ 1663 ret = hclgevf_tqp_enable(hdev, queue_id, 0, false); 1664 if (ret) 1665 return ret; 1666 1667 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_QUEUE_RESET, 0); 1668 memcpy(send_msg.data, &queue_id, sizeof(queue_id)); 1669 return hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1670 } 1671 1672 static int hclgevf_set_mtu(struct hnae3_handle *handle, int new_mtu) 1673 { 1674 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1675 struct hclge_vf_to_pf_msg send_msg; 1676 1677 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_MTU, 0); 1678 memcpy(send_msg.data, &new_mtu, sizeof(new_mtu)); 1679 return hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1680 } 1681 1682 static int hclgevf_notify_client(struct hclgevf_dev *hdev, 1683 enum hnae3_reset_notify_type type) 1684 { 1685 struct hnae3_client *client = hdev->nic_client; 1686 struct hnae3_handle *handle = &hdev->nic; 1687 int ret; 1688 1689 if (!test_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state) || 1690 !client) 1691 return 0; 1692 1693 if (!client->ops->reset_notify) 1694 return -EOPNOTSUPP; 1695 1696 ret = client->ops->reset_notify(handle, type); 1697 if (ret) 1698 dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n", 1699 type, ret); 1700 1701 return ret; 1702 } 1703 1704 static int hclgevf_reset_wait(struct hclgevf_dev *hdev) 1705 { 1706 #define HCLGEVF_RESET_WAIT_US 20000 1707 #define HCLGEVF_RESET_WAIT_CNT 2000 1708 #define HCLGEVF_RESET_WAIT_TIMEOUT_US \ 1709 (HCLGEVF_RESET_WAIT_US * HCLGEVF_RESET_WAIT_CNT) 1710 1711 u32 val; 1712 int ret; 1713 1714 if (hdev->reset_type == HNAE3_VF_RESET) 1715 ret = readl_poll_timeout(hdev->hw.io_base + 1716 HCLGEVF_VF_RST_ING, val, 1717 !(val & HCLGEVF_VF_RST_ING_BIT), 1718 HCLGEVF_RESET_WAIT_US, 1719 HCLGEVF_RESET_WAIT_TIMEOUT_US); 1720 else 1721 ret = readl_poll_timeout(hdev->hw.io_base + 1722 HCLGEVF_RST_ING, val, 1723 !(val & HCLGEVF_RST_ING_BITS), 1724 HCLGEVF_RESET_WAIT_US, 1725 HCLGEVF_RESET_WAIT_TIMEOUT_US); 1726 1727 /* hardware completion status should be available by this time */ 1728 if (ret) { 1729 dev_err(&hdev->pdev->dev, 1730 "could'nt get reset done status from h/w, timeout!\n"); 1731 return ret; 1732 } 1733 1734 /* we will wait a bit more to let reset of the stack to complete. This 1735 * might happen in case reset assertion was made by PF. Yes, this also 1736 * means we might end up waiting bit more even for VF reset. 1737 */ 1738 msleep(5000); 1739 1740 return 0; 1741 } 1742 1743 static void hclgevf_reset_handshake(struct hclgevf_dev *hdev, bool enable) 1744 { 1745 u32 reg_val; 1746 1747 reg_val = hclgevf_read_dev(&hdev->hw, HCLGEVF_NIC_CSQ_DEPTH_REG); 1748 if (enable) 1749 reg_val |= HCLGEVF_NIC_SW_RST_RDY; 1750 else 1751 reg_val &= ~HCLGEVF_NIC_SW_RST_RDY; 1752 1753 hclgevf_write_dev(&hdev->hw, HCLGEVF_NIC_CSQ_DEPTH_REG, 1754 reg_val); 1755 } 1756 1757 static int hclgevf_reset_stack(struct hclgevf_dev *hdev) 1758 { 1759 int ret; 1760 1761 /* uninitialize the nic client */ 1762 ret = hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT); 1763 if (ret) 1764 return ret; 1765 1766 /* re-initialize the hclge device */ 1767 ret = hclgevf_reset_hdev(hdev); 1768 if (ret) { 1769 dev_err(&hdev->pdev->dev, 1770 "hclge device re-init failed, VF is disabled!\n"); 1771 return ret; 1772 } 1773 1774 /* bring up the nic client again */ 1775 ret = hclgevf_notify_client(hdev, HNAE3_INIT_CLIENT); 1776 if (ret) 1777 return ret; 1778 1779 /* clear handshake status with IMP */ 1780 hclgevf_reset_handshake(hdev, false); 1781 1782 /* bring up the nic to enable TX/RX again */ 1783 return hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 1784 } 1785 1786 static int hclgevf_reset_prepare_wait(struct hclgevf_dev *hdev) 1787 { 1788 #define HCLGEVF_RESET_SYNC_TIME 100 1789 1790 struct hclge_vf_to_pf_msg send_msg; 1791 int ret = 0; 1792 1793 if (hdev->reset_type == HNAE3_VF_FUNC_RESET) { 1794 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_RESET, 0); 1795 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1796 if (ret) { 1797 dev_err(&hdev->pdev->dev, 1798 "failed to assert VF reset, ret = %d\n", ret); 1799 return ret; 1800 } 1801 hdev->rst_stats.vf_func_rst_cnt++; 1802 } 1803 1804 set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 1805 /* inform hardware that preparatory work is done */ 1806 msleep(HCLGEVF_RESET_SYNC_TIME); 1807 hclgevf_reset_handshake(hdev, true); 1808 dev_info(&hdev->pdev->dev, "prepare reset(%d) wait done, ret:%d\n", 1809 hdev->reset_type, ret); 1810 1811 return ret; 1812 } 1813 1814 static void hclgevf_dump_rst_info(struct hclgevf_dev *hdev) 1815 { 1816 dev_info(&hdev->pdev->dev, "VF function reset count: %u\n", 1817 hdev->rst_stats.vf_func_rst_cnt); 1818 dev_info(&hdev->pdev->dev, "FLR reset count: %u\n", 1819 hdev->rst_stats.flr_rst_cnt); 1820 dev_info(&hdev->pdev->dev, "VF reset count: %u\n", 1821 hdev->rst_stats.vf_rst_cnt); 1822 dev_info(&hdev->pdev->dev, "reset done count: %u\n", 1823 hdev->rst_stats.rst_done_cnt); 1824 dev_info(&hdev->pdev->dev, "HW reset done count: %u\n", 1825 hdev->rst_stats.hw_rst_done_cnt); 1826 dev_info(&hdev->pdev->dev, "reset count: %u\n", 1827 hdev->rst_stats.rst_cnt); 1828 dev_info(&hdev->pdev->dev, "reset fail count: %u\n", 1829 hdev->rst_stats.rst_fail_cnt); 1830 dev_info(&hdev->pdev->dev, "vector0 interrupt enable status: 0x%x\n", 1831 hclgevf_read_dev(&hdev->hw, HCLGEVF_MISC_VECTOR_REG_BASE)); 1832 dev_info(&hdev->pdev->dev, "vector0 interrupt status: 0x%x\n", 1833 hclgevf_read_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_STATE_REG)); 1834 dev_info(&hdev->pdev->dev, "handshake status: 0x%x\n", 1835 hclgevf_read_dev(&hdev->hw, HCLGEVF_CMDQ_TX_DEPTH_REG)); 1836 dev_info(&hdev->pdev->dev, "function reset status: 0x%x\n", 1837 hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING)); 1838 dev_info(&hdev->pdev->dev, "hdev state: 0x%lx\n", hdev->state); 1839 } 1840 1841 static void hclgevf_reset_err_handle(struct hclgevf_dev *hdev) 1842 { 1843 /* recover handshake status with IMP when reset fail */ 1844 hclgevf_reset_handshake(hdev, true); 1845 hdev->rst_stats.rst_fail_cnt++; 1846 dev_err(&hdev->pdev->dev, "failed to reset VF(%u)\n", 1847 hdev->rst_stats.rst_fail_cnt); 1848 1849 if (hdev->rst_stats.rst_fail_cnt < HCLGEVF_RESET_MAX_FAIL_CNT) 1850 set_bit(hdev->reset_type, &hdev->reset_pending); 1851 1852 if (hclgevf_is_reset_pending(hdev)) { 1853 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1854 hclgevf_reset_task_schedule(hdev); 1855 } else { 1856 set_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state); 1857 hclgevf_dump_rst_info(hdev); 1858 } 1859 } 1860 1861 static int hclgevf_reset_prepare(struct hclgevf_dev *hdev) 1862 { 1863 int ret; 1864 1865 hdev->rst_stats.rst_cnt++; 1866 1867 rtnl_lock(); 1868 /* bring down the nic to stop any ongoing TX/RX */ 1869 ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 1870 rtnl_unlock(); 1871 if (ret) 1872 return ret; 1873 1874 return hclgevf_reset_prepare_wait(hdev); 1875 } 1876 1877 static int hclgevf_reset_rebuild(struct hclgevf_dev *hdev) 1878 { 1879 int ret; 1880 1881 hdev->rst_stats.hw_rst_done_cnt++; 1882 1883 rtnl_lock(); 1884 /* now, re-initialize the nic client and ae device */ 1885 ret = hclgevf_reset_stack(hdev); 1886 rtnl_unlock(); 1887 if (ret) { 1888 dev_err(&hdev->pdev->dev, "failed to reset VF stack\n"); 1889 return ret; 1890 } 1891 1892 hdev->last_reset_time = jiffies; 1893 hdev->rst_stats.rst_done_cnt++; 1894 hdev->rst_stats.rst_fail_cnt = 0; 1895 clear_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state); 1896 1897 return 0; 1898 } 1899 1900 static void hclgevf_reset(struct hclgevf_dev *hdev) 1901 { 1902 if (hclgevf_reset_prepare(hdev)) 1903 goto err_reset; 1904 1905 /* check if VF could successfully fetch the hardware reset completion 1906 * status from the hardware 1907 */ 1908 if (hclgevf_reset_wait(hdev)) { 1909 /* can't do much in this situation, will disable VF */ 1910 dev_err(&hdev->pdev->dev, 1911 "failed to fetch H/W reset completion status\n"); 1912 goto err_reset; 1913 } 1914 1915 if (hclgevf_reset_rebuild(hdev)) 1916 goto err_reset; 1917 1918 return; 1919 1920 err_reset: 1921 hclgevf_reset_err_handle(hdev); 1922 } 1923 1924 static enum hnae3_reset_type hclgevf_get_reset_level(struct hclgevf_dev *hdev, 1925 unsigned long *addr) 1926 { 1927 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; 1928 1929 /* return the highest priority reset level amongst all */ 1930 if (test_bit(HNAE3_VF_RESET, addr)) { 1931 rst_level = HNAE3_VF_RESET; 1932 clear_bit(HNAE3_VF_RESET, addr); 1933 clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1934 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1935 } else if (test_bit(HNAE3_VF_FULL_RESET, addr)) { 1936 rst_level = HNAE3_VF_FULL_RESET; 1937 clear_bit(HNAE3_VF_FULL_RESET, addr); 1938 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1939 } else if (test_bit(HNAE3_VF_PF_FUNC_RESET, addr)) { 1940 rst_level = HNAE3_VF_PF_FUNC_RESET; 1941 clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1942 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1943 } else if (test_bit(HNAE3_VF_FUNC_RESET, addr)) { 1944 rst_level = HNAE3_VF_FUNC_RESET; 1945 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1946 } else if (test_bit(HNAE3_FLR_RESET, addr)) { 1947 rst_level = HNAE3_FLR_RESET; 1948 clear_bit(HNAE3_FLR_RESET, addr); 1949 } 1950 1951 return rst_level; 1952 } 1953 1954 static void hclgevf_reset_event(struct pci_dev *pdev, 1955 struct hnae3_handle *handle) 1956 { 1957 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 1958 struct hclgevf_dev *hdev = ae_dev->priv; 1959 1960 dev_info(&hdev->pdev->dev, "received reset request from VF enet\n"); 1961 1962 if (hdev->default_reset_request) 1963 hdev->reset_level = 1964 hclgevf_get_reset_level(hdev, 1965 &hdev->default_reset_request); 1966 else 1967 hdev->reset_level = HNAE3_VF_FUNC_RESET; 1968 1969 /* reset of this VF requested */ 1970 set_bit(HCLGEVF_RESET_REQUESTED, &hdev->reset_state); 1971 hclgevf_reset_task_schedule(hdev); 1972 1973 hdev->last_reset_time = jiffies; 1974 } 1975 1976 static void hclgevf_set_def_reset_request(struct hnae3_ae_dev *ae_dev, 1977 enum hnae3_reset_type rst_type) 1978 { 1979 struct hclgevf_dev *hdev = ae_dev->priv; 1980 1981 set_bit(rst_type, &hdev->default_reset_request); 1982 } 1983 1984 static void hclgevf_enable_vector(struct hclgevf_misc_vector *vector, bool en) 1985 { 1986 writel(en ? 1 : 0, vector->addr); 1987 } 1988 1989 static void hclgevf_flr_prepare(struct hnae3_ae_dev *ae_dev) 1990 { 1991 #define HCLGEVF_FLR_RETRY_WAIT_MS 500 1992 #define HCLGEVF_FLR_RETRY_CNT 5 1993 1994 struct hclgevf_dev *hdev = ae_dev->priv; 1995 int retry_cnt = 0; 1996 int ret; 1997 1998 retry: 1999 down(&hdev->reset_sem); 2000 set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 2001 hdev->reset_type = HNAE3_FLR_RESET; 2002 ret = hclgevf_reset_prepare(hdev); 2003 if (ret) { 2004 dev_err(&hdev->pdev->dev, "fail to prepare FLR, ret=%d\n", 2005 ret); 2006 if (hdev->reset_pending || 2007 retry_cnt++ < HCLGEVF_FLR_RETRY_CNT) { 2008 dev_err(&hdev->pdev->dev, 2009 "reset_pending:0x%lx, retry_cnt:%d\n", 2010 hdev->reset_pending, retry_cnt); 2011 clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 2012 up(&hdev->reset_sem); 2013 msleep(HCLGEVF_FLR_RETRY_WAIT_MS); 2014 goto retry; 2015 } 2016 } 2017 2018 /* disable misc vector before FLR done */ 2019 hclgevf_enable_vector(&hdev->misc_vector, false); 2020 hdev->rst_stats.flr_rst_cnt++; 2021 } 2022 2023 static void hclgevf_flr_done(struct hnae3_ae_dev *ae_dev) 2024 { 2025 struct hclgevf_dev *hdev = ae_dev->priv; 2026 int ret; 2027 2028 hclgevf_enable_vector(&hdev->misc_vector, true); 2029 2030 ret = hclgevf_reset_rebuild(hdev); 2031 if (ret) 2032 dev_warn(&hdev->pdev->dev, "fail to rebuild, ret=%d\n", 2033 ret); 2034 2035 hdev->reset_type = HNAE3_NONE_RESET; 2036 clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 2037 up(&hdev->reset_sem); 2038 } 2039 2040 static u32 hclgevf_get_fw_version(struct hnae3_handle *handle) 2041 { 2042 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2043 2044 return hdev->fw_version; 2045 } 2046 2047 static void hclgevf_get_misc_vector(struct hclgevf_dev *hdev) 2048 { 2049 struct hclgevf_misc_vector *vector = &hdev->misc_vector; 2050 2051 vector->vector_irq = pci_irq_vector(hdev->pdev, 2052 HCLGEVF_MISC_VECTOR_NUM); 2053 vector->addr = hdev->hw.io_base + HCLGEVF_MISC_VECTOR_REG_BASE; 2054 /* vector status always valid for Vector 0 */ 2055 hdev->vector_status[HCLGEVF_MISC_VECTOR_NUM] = 0; 2056 hdev->vector_irq[HCLGEVF_MISC_VECTOR_NUM] = vector->vector_irq; 2057 2058 hdev->num_msi_left -= 1; 2059 hdev->num_msi_used += 1; 2060 } 2061 2062 void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev) 2063 { 2064 if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) && 2065 !test_and_set_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, 2066 &hdev->state)) 2067 mod_delayed_work(hclgevf_wq, &hdev->service_task, 0); 2068 } 2069 2070 void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev) 2071 { 2072 if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) && 2073 !test_and_set_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, 2074 &hdev->state)) 2075 mod_delayed_work(hclgevf_wq, &hdev->service_task, 0); 2076 } 2077 2078 static void hclgevf_task_schedule(struct hclgevf_dev *hdev, 2079 unsigned long delay) 2080 { 2081 if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) && 2082 !test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) 2083 mod_delayed_work(hclgevf_wq, &hdev->service_task, delay); 2084 } 2085 2086 static void hclgevf_reset_service_task(struct hclgevf_dev *hdev) 2087 { 2088 #define HCLGEVF_MAX_RESET_ATTEMPTS_CNT 3 2089 2090 if (!test_and_clear_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state)) 2091 return; 2092 2093 down(&hdev->reset_sem); 2094 set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 2095 2096 if (test_and_clear_bit(HCLGEVF_RESET_PENDING, 2097 &hdev->reset_state)) { 2098 /* PF has initmated that it is about to reset the hardware. 2099 * We now have to poll & check if hardware has actually 2100 * completed the reset sequence. On hardware reset completion, 2101 * VF needs to reset the client and ae device. 2102 */ 2103 hdev->reset_attempts = 0; 2104 2105 hdev->last_reset_time = jiffies; 2106 while ((hdev->reset_type = 2107 hclgevf_get_reset_level(hdev, &hdev->reset_pending)) 2108 != HNAE3_NONE_RESET) 2109 hclgevf_reset(hdev); 2110 } else if (test_and_clear_bit(HCLGEVF_RESET_REQUESTED, 2111 &hdev->reset_state)) { 2112 /* we could be here when either of below happens: 2113 * 1. reset was initiated due to watchdog timeout caused by 2114 * a. IMP was earlier reset and our TX got choked down and 2115 * which resulted in watchdog reacting and inducing VF 2116 * reset. This also means our cmdq would be unreliable. 2117 * b. problem in TX due to other lower layer(example link 2118 * layer not functioning properly etc.) 2119 * 2. VF reset might have been initiated due to some config 2120 * change. 2121 * 2122 * NOTE: Theres no clear way to detect above cases than to react 2123 * to the response of PF for this reset request. PF will ack the 2124 * 1b and 2. cases but we will not get any intimation about 1a 2125 * from PF as cmdq would be in unreliable state i.e. mailbox 2126 * communication between PF and VF would be broken. 2127 * 2128 * if we are never geting into pending state it means either: 2129 * 1. PF is not receiving our request which could be due to IMP 2130 * reset 2131 * 2. PF is screwed 2132 * We cannot do much for 2. but to check first we can try reset 2133 * our PCIe + stack and see if it alleviates the problem. 2134 */ 2135 if (hdev->reset_attempts > HCLGEVF_MAX_RESET_ATTEMPTS_CNT) { 2136 /* prepare for full reset of stack + pcie interface */ 2137 set_bit(HNAE3_VF_FULL_RESET, &hdev->reset_pending); 2138 2139 /* "defer" schedule the reset task again */ 2140 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 2141 } else { 2142 hdev->reset_attempts++; 2143 2144 set_bit(hdev->reset_level, &hdev->reset_pending); 2145 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 2146 } 2147 hclgevf_reset_task_schedule(hdev); 2148 } 2149 2150 hdev->reset_type = HNAE3_NONE_RESET; 2151 clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 2152 up(&hdev->reset_sem); 2153 } 2154 2155 static void hclgevf_mailbox_service_task(struct hclgevf_dev *hdev) 2156 { 2157 if (!test_and_clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state)) 2158 return; 2159 2160 if (test_and_set_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) 2161 return; 2162 2163 hclgevf_mbx_async_handler(hdev); 2164 2165 clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 2166 } 2167 2168 static void hclgevf_keep_alive(struct hclgevf_dev *hdev) 2169 { 2170 struct hclge_vf_to_pf_msg send_msg; 2171 int ret; 2172 2173 if (test_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state)) 2174 return; 2175 2176 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_KEEP_ALIVE, 0); 2177 ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 2178 if (ret) 2179 dev_err(&hdev->pdev->dev, 2180 "VF sends keep alive cmd failed(=%d)\n", ret); 2181 } 2182 2183 static void hclgevf_periodic_service_task(struct hclgevf_dev *hdev) 2184 { 2185 unsigned long delta = round_jiffies_relative(HZ); 2186 struct hnae3_handle *handle = &hdev->nic; 2187 2188 if (time_is_after_jiffies(hdev->last_serv_processed + HZ)) { 2189 delta = jiffies - hdev->last_serv_processed; 2190 2191 if (delta < round_jiffies_relative(HZ)) { 2192 delta = round_jiffies_relative(HZ) - delta; 2193 goto out; 2194 } 2195 } 2196 2197 hdev->serv_processed_cnt++; 2198 if (!(hdev->serv_processed_cnt % HCLGEVF_KEEP_ALIVE_TASK_INTERVAL)) 2199 hclgevf_keep_alive(hdev); 2200 2201 if (test_bit(HCLGEVF_STATE_DOWN, &hdev->state)) { 2202 hdev->last_serv_processed = jiffies; 2203 goto out; 2204 } 2205 2206 if (!(hdev->serv_processed_cnt % HCLGEVF_STATS_TIMER_INTERVAL)) 2207 hclgevf_tqps_update_stats(handle); 2208 2209 /* request the link status from the PF. PF would be able to tell VF 2210 * about such updates in future so we might remove this later 2211 */ 2212 hclgevf_request_link_info(hdev); 2213 2214 hclgevf_update_link_mode(hdev); 2215 2216 hclgevf_sync_vlan_filter(hdev); 2217 2218 hclgevf_sync_mac_table(hdev); 2219 2220 hclgevf_sync_promisc_mode(hdev); 2221 2222 hdev->last_serv_processed = jiffies; 2223 2224 out: 2225 hclgevf_task_schedule(hdev, delta); 2226 } 2227 2228 static void hclgevf_service_task(struct work_struct *work) 2229 { 2230 struct hclgevf_dev *hdev = container_of(work, struct hclgevf_dev, 2231 service_task.work); 2232 2233 hclgevf_reset_service_task(hdev); 2234 hclgevf_mailbox_service_task(hdev); 2235 hclgevf_periodic_service_task(hdev); 2236 2237 /* Handle reset and mbx again in case periodical task delays the 2238 * handling by calling hclgevf_task_schedule() in 2239 * hclgevf_periodic_service_task() 2240 */ 2241 hclgevf_reset_service_task(hdev); 2242 hclgevf_mailbox_service_task(hdev); 2243 } 2244 2245 static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regclr) 2246 { 2247 hclgevf_write_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_SRC_REG, regclr); 2248 } 2249 2250 static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev, 2251 u32 *clearval) 2252 { 2253 u32 val, cmdq_stat_reg, rst_ing_reg; 2254 2255 /* fetch the events from their corresponding regs */ 2256 cmdq_stat_reg = hclgevf_read_dev(&hdev->hw, 2257 HCLGEVF_VECTOR0_CMDQ_STATE_REG); 2258 2259 if (BIT(HCLGEVF_VECTOR0_RST_INT_B) & cmdq_stat_reg) { 2260 rst_ing_reg = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 2261 dev_info(&hdev->pdev->dev, 2262 "receive reset interrupt 0x%x!\n", rst_ing_reg); 2263 set_bit(HNAE3_VF_RESET, &hdev->reset_pending); 2264 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 2265 set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 2266 *clearval = ~(1U << HCLGEVF_VECTOR0_RST_INT_B); 2267 hdev->rst_stats.vf_rst_cnt++; 2268 /* set up VF hardware reset status, its PF will clear 2269 * this status when PF has initialized done. 2270 */ 2271 val = hclgevf_read_dev(&hdev->hw, HCLGEVF_VF_RST_ING); 2272 hclgevf_write_dev(&hdev->hw, HCLGEVF_VF_RST_ING, 2273 val | HCLGEVF_VF_RST_ING_BIT); 2274 return HCLGEVF_VECTOR0_EVENT_RST; 2275 } 2276 2277 /* check for vector0 mailbox(=CMDQ RX) event source */ 2278 if (BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) { 2279 /* for revision 0x21, clearing interrupt is writing bit 0 2280 * to the clear register, writing bit 1 means to keep the 2281 * old value. 2282 * for revision 0x20, the clear register is a read & write 2283 * register, so we should just write 0 to the bit we are 2284 * handling, and keep other bits as cmdq_stat_reg. 2285 */ 2286 if (hdev->pdev->revision >= 0x21) 2287 *clearval = ~(1U << HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 2288 else 2289 *clearval = cmdq_stat_reg & 2290 ~BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 2291 2292 return HCLGEVF_VECTOR0_EVENT_MBX; 2293 } 2294 2295 /* print other vector0 event source */ 2296 dev_info(&hdev->pdev->dev, 2297 "vector 0 interrupt from unknown source, cmdq_src = %#x\n", 2298 cmdq_stat_reg); 2299 2300 return HCLGEVF_VECTOR0_EVENT_OTHER; 2301 } 2302 2303 static irqreturn_t hclgevf_misc_irq_handle(int irq, void *data) 2304 { 2305 enum hclgevf_evt_cause event_cause; 2306 struct hclgevf_dev *hdev = data; 2307 u32 clearval; 2308 2309 hclgevf_enable_vector(&hdev->misc_vector, false); 2310 event_cause = hclgevf_check_evt_cause(hdev, &clearval); 2311 2312 switch (event_cause) { 2313 case HCLGEVF_VECTOR0_EVENT_RST: 2314 hclgevf_reset_task_schedule(hdev); 2315 break; 2316 case HCLGEVF_VECTOR0_EVENT_MBX: 2317 hclgevf_mbx_handler(hdev); 2318 break; 2319 default: 2320 break; 2321 } 2322 2323 if (event_cause != HCLGEVF_VECTOR0_EVENT_OTHER) { 2324 hclgevf_clear_event_cause(hdev, clearval); 2325 hclgevf_enable_vector(&hdev->misc_vector, true); 2326 } 2327 2328 return IRQ_HANDLED; 2329 } 2330 2331 static int hclgevf_configure(struct hclgevf_dev *hdev) 2332 { 2333 int ret; 2334 2335 /* get current port based vlan state from PF */ 2336 ret = hclgevf_get_port_base_vlan_filter_state(hdev); 2337 if (ret) 2338 return ret; 2339 2340 /* get queue configuration from PF */ 2341 ret = hclgevf_get_queue_info(hdev); 2342 if (ret) 2343 return ret; 2344 2345 /* get queue depth info from PF */ 2346 ret = hclgevf_get_queue_depth(hdev); 2347 if (ret) 2348 return ret; 2349 2350 ret = hclgevf_get_pf_media_type(hdev); 2351 if (ret) 2352 return ret; 2353 2354 /* get tc configuration from PF */ 2355 return hclgevf_get_tc_info(hdev); 2356 } 2357 2358 static int hclgevf_alloc_hdev(struct hnae3_ae_dev *ae_dev) 2359 { 2360 struct pci_dev *pdev = ae_dev->pdev; 2361 struct hclgevf_dev *hdev; 2362 2363 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 2364 if (!hdev) 2365 return -ENOMEM; 2366 2367 hdev->pdev = pdev; 2368 hdev->ae_dev = ae_dev; 2369 ae_dev->priv = hdev; 2370 2371 return 0; 2372 } 2373 2374 static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev) 2375 { 2376 struct hnae3_handle *roce = &hdev->roce; 2377 struct hnae3_handle *nic = &hdev->nic; 2378 2379 roce->rinfo.num_vectors = hdev->num_roce_msix; 2380 2381 if (hdev->num_msi_left < roce->rinfo.num_vectors || 2382 hdev->num_msi_left == 0) 2383 return -EINVAL; 2384 2385 roce->rinfo.base_vector = hdev->roce_base_vector; 2386 2387 roce->rinfo.netdev = nic->kinfo.netdev; 2388 roce->rinfo.roce_io_base = hdev->hw.io_base; 2389 2390 roce->pdev = nic->pdev; 2391 roce->ae_algo = nic->ae_algo; 2392 roce->numa_node_mask = nic->numa_node_mask; 2393 2394 return 0; 2395 } 2396 2397 static int hclgevf_config_gro(struct hclgevf_dev *hdev, bool en) 2398 { 2399 struct hclgevf_cfg_gro_status_cmd *req; 2400 struct hclgevf_desc desc; 2401 int ret; 2402 2403 if (!hnae3_dev_gro_supported(hdev)) 2404 return 0; 2405 2406 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_GRO_GENERIC_CONFIG, 2407 false); 2408 req = (struct hclgevf_cfg_gro_status_cmd *)desc.data; 2409 2410 req->gro_en = en ? 1 : 0; 2411 2412 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 2413 if (ret) 2414 dev_err(&hdev->pdev->dev, 2415 "VF GRO hardware config cmd failed, ret = %d.\n", ret); 2416 2417 return ret; 2418 } 2419 2420 static void hclgevf_rss_init_cfg(struct hclgevf_dev *hdev) 2421 { 2422 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 2423 struct hclgevf_rss_tuple_cfg *tuple_sets; 2424 u32 i; 2425 2426 rss_cfg->hash_algo = HCLGEVF_RSS_HASH_ALGO_TOEPLITZ; 2427 rss_cfg->rss_size = hdev->nic.kinfo.rss_size; 2428 tuple_sets = &rss_cfg->rss_tuple_sets; 2429 if (hdev->pdev->revision >= 0x21) { 2430 rss_cfg->hash_algo = HCLGEVF_RSS_HASH_ALGO_SIMPLE; 2431 memcpy(rss_cfg->rss_hash_key, hclgevf_hash_key, 2432 HCLGEVF_RSS_KEY_SIZE); 2433 2434 tuple_sets->ipv4_tcp_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2435 tuple_sets->ipv4_udp_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2436 tuple_sets->ipv4_sctp_en = HCLGEVF_RSS_INPUT_TUPLE_SCTP; 2437 tuple_sets->ipv4_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2438 tuple_sets->ipv6_tcp_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2439 tuple_sets->ipv6_udp_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2440 tuple_sets->ipv6_sctp_en = HCLGEVF_RSS_INPUT_TUPLE_SCTP; 2441 tuple_sets->ipv6_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2442 } 2443 2444 /* Initialize RSS indirect table */ 2445 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 2446 rss_cfg->rss_indirection_tbl[i] = i % rss_cfg->rss_size; 2447 } 2448 2449 static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev) 2450 { 2451 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 2452 int ret; 2453 2454 if (hdev->pdev->revision >= 0x21) { 2455 ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 2456 rss_cfg->rss_hash_key); 2457 if (ret) 2458 return ret; 2459 2460 ret = hclgevf_set_rss_input_tuple(hdev, rss_cfg); 2461 if (ret) 2462 return ret; 2463 } 2464 2465 ret = hclgevf_set_rss_indir_table(hdev); 2466 if (ret) 2467 return ret; 2468 2469 return hclgevf_set_rss_tc_mode(hdev, rss_cfg->rss_size); 2470 } 2471 2472 static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev) 2473 { 2474 return hclgevf_set_vlan_filter(&hdev->nic, htons(ETH_P_8021Q), 0, 2475 false); 2476 } 2477 2478 static void hclgevf_flush_link_update(struct hclgevf_dev *hdev) 2479 { 2480 #define HCLGEVF_FLUSH_LINK_TIMEOUT 100000 2481 2482 unsigned long last = hdev->serv_processed_cnt; 2483 int i = 0; 2484 2485 while (test_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state) && 2486 i++ < HCLGEVF_FLUSH_LINK_TIMEOUT && 2487 last == hdev->serv_processed_cnt) 2488 usleep_range(1, 1); 2489 } 2490 2491 static void hclgevf_set_timer_task(struct hnae3_handle *handle, bool enable) 2492 { 2493 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2494 2495 if (enable) { 2496 hclgevf_task_schedule(hdev, 0); 2497 } else { 2498 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2499 2500 /* flush memory to make sure DOWN is seen by service task */ 2501 smp_mb__before_atomic(); 2502 hclgevf_flush_link_update(hdev); 2503 } 2504 } 2505 2506 static int hclgevf_ae_start(struct hnae3_handle *handle) 2507 { 2508 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2509 2510 hclgevf_reset_tqp_stats(handle); 2511 2512 hclgevf_request_link_info(hdev); 2513 2514 hclgevf_update_link_mode(hdev); 2515 2516 clear_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2517 2518 return 0; 2519 } 2520 2521 static void hclgevf_ae_stop(struct hnae3_handle *handle) 2522 { 2523 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2524 int i; 2525 2526 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2527 2528 if (hdev->reset_type != HNAE3_VF_RESET) 2529 for (i = 0; i < handle->kinfo.num_tqps; i++) 2530 if (hclgevf_reset_tqp(handle, i)) 2531 break; 2532 2533 hclgevf_reset_tqp_stats(handle); 2534 hclgevf_update_link_status(hdev, 0); 2535 } 2536 2537 static int hclgevf_set_alive(struct hnae3_handle *handle, bool alive) 2538 { 2539 #define HCLGEVF_STATE_ALIVE 1 2540 #define HCLGEVF_STATE_NOT_ALIVE 0 2541 2542 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2543 struct hclge_vf_to_pf_msg send_msg; 2544 2545 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_ALIVE, 0); 2546 send_msg.data[0] = alive ? HCLGEVF_STATE_ALIVE : 2547 HCLGEVF_STATE_NOT_ALIVE; 2548 return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 2549 } 2550 2551 static int hclgevf_client_start(struct hnae3_handle *handle) 2552 { 2553 int ret; 2554 2555 ret = hclgevf_set_alive(handle, true); 2556 if (ret) 2557 return ret; 2558 2559 return 0; 2560 } 2561 2562 static void hclgevf_client_stop(struct hnae3_handle *handle) 2563 { 2564 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2565 int ret; 2566 2567 ret = hclgevf_set_alive(handle, false); 2568 if (ret) 2569 dev_warn(&hdev->pdev->dev, 2570 "%s failed %d\n", __func__, ret); 2571 } 2572 2573 static void hclgevf_state_init(struct hclgevf_dev *hdev) 2574 { 2575 clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 2576 clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 2577 clear_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state); 2578 2579 INIT_DELAYED_WORK(&hdev->service_task, hclgevf_service_task); 2580 2581 mutex_init(&hdev->mbx_resp.mbx_mutex); 2582 sema_init(&hdev->reset_sem, 1); 2583 2584 spin_lock_init(&hdev->mac_table.mac_list_lock); 2585 INIT_LIST_HEAD(&hdev->mac_table.uc_mac_list); 2586 INIT_LIST_HEAD(&hdev->mac_table.mc_mac_list); 2587 2588 /* bring the device down */ 2589 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2590 } 2591 2592 static void hclgevf_state_uninit(struct hclgevf_dev *hdev) 2593 { 2594 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2595 set_bit(HCLGEVF_STATE_REMOVING, &hdev->state); 2596 2597 if (hdev->service_task.work.func) 2598 cancel_delayed_work_sync(&hdev->service_task); 2599 2600 mutex_destroy(&hdev->mbx_resp.mbx_mutex); 2601 } 2602 2603 static int hclgevf_init_msi(struct hclgevf_dev *hdev) 2604 { 2605 struct pci_dev *pdev = hdev->pdev; 2606 int vectors; 2607 int i; 2608 2609 if (hnae3_dev_roce_supported(hdev)) 2610 vectors = pci_alloc_irq_vectors(pdev, 2611 hdev->roce_base_msix_offset + 1, 2612 hdev->num_msi, 2613 PCI_IRQ_MSIX); 2614 else 2615 vectors = pci_alloc_irq_vectors(pdev, HNAE3_MIN_VECTOR_NUM, 2616 hdev->num_msi, 2617 PCI_IRQ_MSI | PCI_IRQ_MSIX); 2618 2619 if (vectors < 0) { 2620 dev_err(&pdev->dev, 2621 "failed(%d) to allocate MSI/MSI-X vectors\n", 2622 vectors); 2623 return vectors; 2624 } 2625 if (vectors < hdev->num_msi) 2626 dev_warn(&hdev->pdev->dev, 2627 "requested %u MSI/MSI-X, but allocated %d MSI/MSI-X\n", 2628 hdev->num_msi, vectors); 2629 2630 hdev->num_msi = vectors; 2631 hdev->num_msi_left = vectors; 2632 2633 hdev->base_msi_vector = pdev->irq; 2634 hdev->roce_base_vector = pdev->irq + hdev->roce_base_msix_offset; 2635 2636 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 2637 sizeof(u16), GFP_KERNEL); 2638 if (!hdev->vector_status) { 2639 pci_free_irq_vectors(pdev); 2640 return -ENOMEM; 2641 } 2642 2643 for (i = 0; i < hdev->num_msi; i++) 2644 hdev->vector_status[i] = HCLGEVF_INVALID_VPORT; 2645 2646 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 2647 sizeof(int), GFP_KERNEL); 2648 if (!hdev->vector_irq) { 2649 devm_kfree(&pdev->dev, hdev->vector_status); 2650 pci_free_irq_vectors(pdev); 2651 return -ENOMEM; 2652 } 2653 2654 return 0; 2655 } 2656 2657 static void hclgevf_uninit_msi(struct hclgevf_dev *hdev) 2658 { 2659 struct pci_dev *pdev = hdev->pdev; 2660 2661 devm_kfree(&pdev->dev, hdev->vector_status); 2662 devm_kfree(&pdev->dev, hdev->vector_irq); 2663 pci_free_irq_vectors(pdev); 2664 } 2665 2666 static int hclgevf_misc_irq_init(struct hclgevf_dev *hdev) 2667 { 2668 int ret; 2669 2670 hclgevf_get_misc_vector(hdev); 2671 2672 snprintf(hdev->misc_vector.name, HNAE3_INT_NAME_LEN, "%s-misc-%s", 2673 HCLGEVF_NAME, pci_name(hdev->pdev)); 2674 ret = request_irq(hdev->misc_vector.vector_irq, hclgevf_misc_irq_handle, 2675 0, hdev->misc_vector.name, hdev); 2676 if (ret) { 2677 dev_err(&hdev->pdev->dev, "VF failed to request misc irq(%d)\n", 2678 hdev->misc_vector.vector_irq); 2679 return ret; 2680 } 2681 2682 hclgevf_clear_event_cause(hdev, 0); 2683 2684 /* enable misc. vector(vector 0) */ 2685 hclgevf_enable_vector(&hdev->misc_vector, true); 2686 2687 return ret; 2688 } 2689 2690 static void hclgevf_misc_irq_uninit(struct hclgevf_dev *hdev) 2691 { 2692 /* disable misc vector(vector 0) */ 2693 hclgevf_enable_vector(&hdev->misc_vector, false); 2694 synchronize_irq(hdev->misc_vector.vector_irq); 2695 free_irq(hdev->misc_vector.vector_irq, hdev); 2696 hclgevf_free_vector(hdev, 0); 2697 } 2698 2699 static void hclgevf_info_show(struct hclgevf_dev *hdev) 2700 { 2701 struct device *dev = &hdev->pdev->dev; 2702 2703 dev_info(dev, "VF info begin:\n"); 2704 2705 dev_info(dev, "Task queue pairs numbers: %u\n", hdev->num_tqps); 2706 dev_info(dev, "Desc num per TX queue: %u\n", hdev->num_tx_desc); 2707 dev_info(dev, "Desc num per RX queue: %u\n", hdev->num_rx_desc); 2708 dev_info(dev, "Numbers of vports: %u\n", hdev->num_alloc_vport); 2709 dev_info(dev, "HW tc map: 0x%x\n", hdev->hw_tc_map); 2710 dev_info(dev, "PF media type of this VF: %u\n", 2711 hdev->hw.mac.media_type); 2712 2713 dev_info(dev, "VF info end.\n"); 2714 } 2715 2716 static int hclgevf_init_nic_client_instance(struct hnae3_ae_dev *ae_dev, 2717 struct hnae3_client *client) 2718 { 2719 struct hclgevf_dev *hdev = ae_dev->priv; 2720 int rst_cnt = hdev->rst_stats.rst_cnt; 2721 int ret; 2722 2723 ret = client->ops->init_instance(&hdev->nic); 2724 if (ret) 2725 return ret; 2726 2727 set_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 2728 if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) || 2729 rst_cnt != hdev->rst_stats.rst_cnt) { 2730 clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 2731 2732 client->ops->uninit_instance(&hdev->nic, 0); 2733 return -EBUSY; 2734 } 2735 2736 hnae3_set_client_init_flag(client, ae_dev, 1); 2737 2738 if (netif_msg_drv(&hdev->nic)) 2739 hclgevf_info_show(hdev); 2740 2741 return 0; 2742 } 2743 2744 static int hclgevf_init_roce_client_instance(struct hnae3_ae_dev *ae_dev, 2745 struct hnae3_client *client) 2746 { 2747 struct hclgevf_dev *hdev = ae_dev->priv; 2748 int ret; 2749 2750 if (!hnae3_dev_roce_supported(hdev) || !hdev->roce_client || 2751 !hdev->nic_client) 2752 return 0; 2753 2754 ret = hclgevf_init_roce_base_info(hdev); 2755 if (ret) 2756 return ret; 2757 2758 ret = client->ops->init_instance(&hdev->roce); 2759 if (ret) 2760 return ret; 2761 2762 hnae3_set_client_init_flag(client, ae_dev, 1); 2763 2764 return 0; 2765 } 2766 2767 static int hclgevf_init_client_instance(struct hnae3_client *client, 2768 struct hnae3_ae_dev *ae_dev) 2769 { 2770 struct hclgevf_dev *hdev = ae_dev->priv; 2771 int ret; 2772 2773 switch (client->type) { 2774 case HNAE3_CLIENT_KNIC: 2775 hdev->nic_client = client; 2776 hdev->nic.client = client; 2777 2778 ret = hclgevf_init_nic_client_instance(ae_dev, client); 2779 if (ret) 2780 goto clear_nic; 2781 2782 ret = hclgevf_init_roce_client_instance(ae_dev, 2783 hdev->roce_client); 2784 if (ret) 2785 goto clear_roce; 2786 2787 break; 2788 case HNAE3_CLIENT_ROCE: 2789 if (hnae3_dev_roce_supported(hdev)) { 2790 hdev->roce_client = client; 2791 hdev->roce.client = client; 2792 } 2793 2794 ret = hclgevf_init_roce_client_instance(ae_dev, client); 2795 if (ret) 2796 goto clear_roce; 2797 2798 break; 2799 default: 2800 return -EINVAL; 2801 } 2802 2803 return 0; 2804 2805 clear_nic: 2806 hdev->nic_client = NULL; 2807 hdev->nic.client = NULL; 2808 return ret; 2809 clear_roce: 2810 hdev->roce_client = NULL; 2811 hdev->roce.client = NULL; 2812 return ret; 2813 } 2814 2815 static void hclgevf_uninit_client_instance(struct hnae3_client *client, 2816 struct hnae3_ae_dev *ae_dev) 2817 { 2818 struct hclgevf_dev *hdev = ae_dev->priv; 2819 2820 /* un-init roce, if it exists */ 2821 if (hdev->roce_client) { 2822 hdev->roce_client->ops->uninit_instance(&hdev->roce, 0); 2823 hdev->roce_client = NULL; 2824 hdev->roce.client = NULL; 2825 } 2826 2827 /* un-init nic/unic, if this was not called by roce client */ 2828 if (client->ops->uninit_instance && hdev->nic_client && 2829 client->type != HNAE3_CLIENT_ROCE) { 2830 clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 2831 2832 client->ops->uninit_instance(&hdev->nic, 0); 2833 hdev->nic_client = NULL; 2834 hdev->nic.client = NULL; 2835 } 2836 } 2837 2838 static int hclgevf_pci_init(struct hclgevf_dev *hdev) 2839 { 2840 struct pci_dev *pdev = hdev->pdev; 2841 struct hclgevf_hw *hw; 2842 int ret; 2843 2844 ret = pci_enable_device(pdev); 2845 if (ret) { 2846 dev_err(&pdev->dev, "failed to enable PCI device\n"); 2847 return ret; 2848 } 2849 2850 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 2851 if (ret) { 2852 dev_err(&pdev->dev, "can't set consistent PCI DMA, exiting"); 2853 goto err_disable_device; 2854 } 2855 2856 ret = pci_request_regions(pdev, HCLGEVF_DRIVER_NAME); 2857 if (ret) { 2858 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 2859 goto err_disable_device; 2860 } 2861 2862 pci_set_master(pdev); 2863 hw = &hdev->hw; 2864 hw->hdev = hdev; 2865 hw->io_base = pci_iomap(pdev, 2, 0); 2866 if (!hw->io_base) { 2867 dev_err(&pdev->dev, "can't map configuration register space\n"); 2868 ret = -ENOMEM; 2869 goto err_clr_master; 2870 } 2871 2872 return 0; 2873 2874 err_clr_master: 2875 pci_clear_master(pdev); 2876 pci_release_regions(pdev); 2877 err_disable_device: 2878 pci_disable_device(pdev); 2879 2880 return ret; 2881 } 2882 2883 static void hclgevf_pci_uninit(struct hclgevf_dev *hdev) 2884 { 2885 struct pci_dev *pdev = hdev->pdev; 2886 2887 pci_iounmap(pdev, hdev->hw.io_base); 2888 pci_clear_master(pdev); 2889 pci_release_regions(pdev); 2890 pci_disable_device(pdev); 2891 } 2892 2893 static int hclgevf_query_vf_resource(struct hclgevf_dev *hdev) 2894 { 2895 struct hclgevf_query_res_cmd *req; 2896 struct hclgevf_desc desc; 2897 int ret; 2898 2899 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_VF_RSRC, true); 2900 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 2901 if (ret) { 2902 dev_err(&hdev->pdev->dev, 2903 "query vf resource failed, ret = %d.\n", ret); 2904 return ret; 2905 } 2906 2907 req = (struct hclgevf_query_res_cmd *)desc.data; 2908 2909 if (hnae3_dev_roce_supported(hdev)) { 2910 hdev->roce_base_msix_offset = 2911 hnae3_get_field(le16_to_cpu(req->msixcap_localid_ba_rocee), 2912 HCLGEVF_MSIX_OFT_ROCEE_M, 2913 HCLGEVF_MSIX_OFT_ROCEE_S); 2914 hdev->num_roce_msix = 2915 hnae3_get_field(le16_to_cpu(req->vf_intr_vector_number), 2916 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 2917 2918 /* nic's msix numbers is always equals to the roce's. */ 2919 hdev->num_nic_msix = hdev->num_roce_msix; 2920 2921 /* VF should have NIC vectors and Roce vectors, NIC vectors 2922 * are queued before Roce vectors. The offset is fixed to 64. 2923 */ 2924 hdev->num_msi = hdev->num_roce_msix + 2925 hdev->roce_base_msix_offset; 2926 } else { 2927 hdev->num_msi = 2928 hnae3_get_field(le16_to_cpu(req->vf_intr_vector_number), 2929 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 2930 2931 hdev->num_nic_msix = hdev->num_msi; 2932 } 2933 2934 if (hdev->num_nic_msix < HNAE3_MIN_VECTOR_NUM) { 2935 dev_err(&hdev->pdev->dev, 2936 "Just %u msi resources, not enough for vf(min:2).\n", 2937 hdev->num_nic_msix); 2938 return -EINVAL; 2939 } 2940 2941 return 0; 2942 } 2943 2944 static int hclgevf_pci_reset(struct hclgevf_dev *hdev) 2945 { 2946 struct pci_dev *pdev = hdev->pdev; 2947 int ret = 0; 2948 2949 if (hdev->reset_type == HNAE3_VF_FULL_RESET && 2950 test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2951 hclgevf_misc_irq_uninit(hdev); 2952 hclgevf_uninit_msi(hdev); 2953 clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2954 } 2955 2956 if (!test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2957 pci_set_master(pdev); 2958 ret = hclgevf_init_msi(hdev); 2959 if (ret) { 2960 dev_err(&pdev->dev, 2961 "failed(%d) to init MSI/MSI-X\n", ret); 2962 return ret; 2963 } 2964 2965 ret = hclgevf_misc_irq_init(hdev); 2966 if (ret) { 2967 hclgevf_uninit_msi(hdev); 2968 dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 2969 ret); 2970 return ret; 2971 } 2972 2973 set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2974 } 2975 2976 return ret; 2977 } 2978 2979 static int hclgevf_clear_vport_list(struct hclgevf_dev *hdev) 2980 { 2981 struct hclge_vf_to_pf_msg send_msg; 2982 2983 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_HANDLE_VF_TBL, 2984 HCLGE_MBX_VPORT_LIST_CLEAR); 2985 return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 2986 } 2987 2988 static int hclgevf_reset_hdev(struct hclgevf_dev *hdev) 2989 { 2990 struct pci_dev *pdev = hdev->pdev; 2991 int ret; 2992 2993 ret = hclgevf_pci_reset(hdev); 2994 if (ret) { 2995 dev_err(&pdev->dev, "pci reset failed %d\n", ret); 2996 return ret; 2997 } 2998 2999 ret = hclgevf_cmd_init(hdev); 3000 if (ret) { 3001 dev_err(&pdev->dev, "cmd failed %d\n", ret); 3002 return ret; 3003 } 3004 3005 ret = hclgevf_rss_init_hw(hdev); 3006 if (ret) { 3007 dev_err(&hdev->pdev->dev, 3008 "failed(%d) to initialize RSS\n", ret); 3009 return ret; 3010 } 3011 3012 ret = hclgevf_config_gro(hdev, true); 3013 if (ret) 3014 return ret; 3015 3016 ret = hclgevf_init_vlan_config(hdev); 3017 if (ret) { 3018 dev_err(&hdev->pdev->dev, 3019 "failed(%d) to initialize VLAN config\n", ret); 3020 return ret; 3021 } 3022 3023 set_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state); 3024 3025 dev_info(&hdev->pdev->dev, "Reset done\n"); 3026 3027 return 0; 3028 } 3029 3030 static int hclgevf_init_hdev(struct hclgevf_dev *hdev) 3031 { 3032 struct pci_dev *pdev = hdev->pdev; 3033 int ret; 3034 3035 ret = hclgevf_pci_init(hdev); 3036 if (ret) 3037 return ret; 3038 3039 ret = hclgevf_cmd_queue_init(hdev); 3040 if (ret) 3041 goto err_cmd_queue_init; 3042 3043 ret = hclgevf_cmd_init(hdev); 3044 if (ret) 3045 goto err_cmd_init; 3046 3047 /* Get vf resource */ 3048 ret = hclgevf_query_vf_resource(hdev); 3049 if (ret) 3050 goto err_cmd_init; 3051 3052 ret = hclgevf_init_msi(hdev); 3053 if (ret) { 3054 dev_err(&pdev->dev, "failed(%d) to init MSI/MSI-X\n", ret); 3055 goto err_cmd_init; 3056 } 3057 3058 hclgevf_state_init(hdev); 3059 hdev->reset_level = HNAE3_VF_FUNC_RESET; 3060 hdev->reset_type = HNAE3_NONE_RESET; 3061 3062 ret = hclgevf_misc_irq_init(hdev); 3063 if (ret) 3064 goto err_misc_irq_init; 3065 3066 set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 3067 3068 ret = hclgevf_configure(hdev); 3069 if (ret) { 3070 dev_err(&pdev->dev, "failed(%d) to fetch configuration\n", ret); 3071 goto err_config; 3072 } 3073 3074 ret = hclgevf_alloc_tqps(hdev); 3075 if (ret) { 3076 dev_err(&pdev->dev, "failed(%d) to allocate TQPs\n", ret); 3077 goto err_config; 3078 } 3079 3080 ret = hclgevf_set_handle_info(hdev); 3081 if (ret) 3082 goto err_config; 3083 3084 ret = hclgevf_config_gro(hdev, true); 3085 if (ret) 3086 goto err_config; 3087 3088 /* Initialize RSS for this VF */ 3089 hclgevf_rss_init_cfg(hdev); 3090 ret = hclgevf_rss_init_hw(hdev); 3091 if (ret) { 3092 dev_err(&hdev->pdev->dev, 3093 "failed(%d) to initialize RSS\n", ret); 3094 goto err_config; 3095 } 3096 3097 /* ensure vf tbl list as empty before init*/ 3098 ret = hclgevf_clear_vport_list(hdev); 3099 if (ret) { 3100 dev_err(&pdev->dev, 3101 "failed to clear tbl list configuration, ret = %d.\n", 3102 ret); 3103 goto err_config; 3104 } 3105 3106 ret = hclgevf_init_vlan_config(hdev); 3107 if (ret) { 3108 dev_err(&hdev->pdev->dev, 3109 "failed(%d) to initialize VLAN config\n", ret); 3110 goto err_config; 3111 } 3112 3113 hdev->last_reset_time = jiffies; 3114 dev_info(&hdev->pdev->dev, "finished initializing %s driver\n", 3115 HCLGEVF_DRIVER_NAME); 3116 3117 hclgevf_task_schedule(hdev, round_jiffies_relative(HZ)); 3118 3119 return 0; 3120 3121 err_config: 3122 hclgevf_misc_irq_uninit(hdev); 3123 err_misc_irq_init: 3124 hclgevf_state_uninit(hdev); 3125 hclgevf_uninit_msi(hdev); 3126 err_cmd_init: 3127 hclgevf_cmd_uninit(hdev); 3128 err_cmd_queue_init: 3129 hclgevf_pci_uninit(hdev); 3130 clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 3131 return ret; 3132 } 3133 3134 static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev) 3135 { 3136 struct hclge_vf_to_pf_msg send_msg; 3137 3138 hclgevf_state_uninit(hdev); 3139 3140 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_VF_UNINIT, 0); 3141 hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 3142 3143 if (test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 3144 hclgevf_misc_irq_uninit(hdev); 3145 hclgevf_uninit_msi(hdev); 3146 } 3147 3148 hclgevf_pci_uninit(hdev); 3149 hclgevf_cmd_uninit(hdev); 3150 hclgevf_uninit_mac_list(hdev); 3151 } 3152 3153 static int hclgevf_init_ae_dev(struct hnae3_ae_dev *ae_dev) 3154 { 3155 struct pci_dev *pdev = ae_dev->pdev; 3156 int ret; 3157 3158 ret = hclgevf_alloc_hdev(ae_dev); 3159 if (ret) { 3160 dev_err(&pdev->dev, "hclge device allocation failed\n"); 3161 return ret; 3162 } 3163 3164 ret = hclgevf_init_hdev(ae_dev->priv); 3165 if (ret) { 3166 dev_err(&pdev->dev, "hclge device initialization failed\n"); 3167 return ret; 3168 } 3169 3170 return 0; 3171 } 3172 3173 static void hclgevf_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 3174 { 3175 struct hclgevf_dev *hdev = ae_dev->priv; 3176 3177 hclgevf_uninit_hdev(hdev); 3178 ae_dev->priv = NULL; 3179 } 3180 3181 static u32 hclgevf_get_max_channels(struct hclgevf_dev *hdev) 3182 { 3183 struct hnae3_handle *nic = &hdev->nic; 3184 struct hnae3_knic_private_info *kinfo = &nic->kinfo; 3185 3186 return min_t(u32, hdev->rss_size_max, 3187 hdev->num_tqps / kinfo->num_tc); 3188 } 3189 3190 /** 3191 * hclgevf_get_channels - Get the current channels enabled and max supported. 3192 * @handle: hardware information for network interface 3193 * @ch: ethtool channels structure 3194 * 3195 * We don't support separate tx and rx queues as channels. The other count 3196 * represents how many queues are being used for control. max_combined counts 3197 * how many queue pairs we can support. They may not be mapped 1 to 1 with 3198 * q_vectors since we support a lot more queue pairs than q_vectors. 3199 **/ 3200 static void hclgevf_get_channels(struct hnae3_handle *handle, 3201 struct ethtool_channels *ch) 3202 { 3203 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3204 3205 ch->max_combined = hclgevf_get_max_channels(hdev); 3206 ch->other_count = 0; 3207 ch->max_other = 0; 3208 ch->combined_count = handle->kinfo.rss_size; 3209 } 3210 3211 static void hclgevf_get_tqps_and_rss_info(struct hnae3_handle *handle, 3212 u16 *alloc_tqps, u16 *max_rss_size) 3213 { 3214 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3215 3216 *alloc_tqps = hdev->num_tqps; 3217 *max_rss_size = hdev->rss_size_max; 3218 } 3219 3220 static void hclgevf_update_rss_size(struct hnae3_handle *handle, 3221 u32 new_tqps_num) 3222 { 3223 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 3224 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3225 u16 max_rss_size; 3226 3227 kinfo->req_rss_size = new_tqps_num; 3228 3229 max_rss_size = min_t(u16, hdev->rss_size_max, 3230 hdev->num_tqps / kinfo->num_tc); 3231 3232 /* Use the user's configuration when it is not larger than 3233 * max_rss_size, otherwise, use the maximum specification value. 3234 */ 3235 if (kinfo->req_rss_size != kinfo->rss_size && kinfo->req_rss_size && 3236 kinfo->req_rss_size <= max_rss_size) 3237 kinfo->rss_size = kinfo->req_rss_size; 3238 else if (kinfo->rss_size > max_rss_size || 3239 (!kinfo->req_rss_size && kinfo->rss_size < max_rss_size)) 3240 kinfo->rss_size = max_rss_size; 3241 3242 kinfo->num_tqps = kinfo->num_tc * kinfo->rss_size; 3243 } 3244 3245 static int hclgevf_set_channels(struct hnae3_handle *handle, u32 new_tqps_num, 3246 bool rxfh_configured) 3247 { 3248 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3249 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 3250 u16 cur_rss_size = kinfo->rss_size; 3251 u16 cur_tqps = kinfo->num_tqps; 3252 u32 *rss_indir; 3253 unsigned int i; 3254 int ret; 3255 3256 hclgevf_update_rss_size(handle, new_tqps_num); 3257 3258 ret = hclgevf_set_rss_tc_mode(hdev, kinfo->rss_size); 3259 if (ret) 3260 return ret; 3261 3262 /* RSS indirection table has been configuared by user */ 3263 if (rxfh_configured) 3264 goto out; 3265 3266 /* Reinitializes the rss indirect table according to the new RSS size */ 3267 rss_indir = kcalloc(HCLGEVF_RSS_IND_TBL_SIZE, sizeof(u32), GFP_KERNEL); 3268 if (!rss_indir) 3269 return -ENOMEM; 3270 3271 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 3272 rss_indir[i] = i % kinfo->rss_size; 3273 3274 hdev->rss_cfg.rss_size = kinfo->rss_size; 3275 3276 ret = hclgevf_set_rss(handle, rss_indir, NULL, 0); 3277 if (ret) 3278 dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n", 3279 ret); 3280 3281 kfree(rss_indir); 3282 3283 out: 3284 if (!ret) 3285 dev_info(&hdev->pdev->dev, 3286 "Channels changed, rss_size from %u to %u, tqps from %u to %u", 3287 cur_rss_size, kinfo->rss_size, 3288 cur_tqps, kinfo->rss_size * kinfo->num_tc); 3289 3290 return ret; 3291 } 3292 3293 static int hclgevf_get_status(struct hnae3_handle *handle) 3294 { 3295 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3296 3297 return hdev->hw.mac.link; 3298 } 3299 3300 static void hclgevf_get_ksettings_an_result(struct hnae3_handle *handle, 3301 u8 *auto_neg, u32 *speed, 3302 u8 *duplex) 3303 { 3304 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3305 3306 if (speed) 3307 *speed = hdev->hw.mac.speed; 3308 if (duplex) 3309 *duplex = hdev->hw.mac.duplex; 3310 if (auto_neg) 3311 *auto_neg = AUTONEG_DISABLE; 3312 } 3313 3314 void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed, 3315 u8 duplex) 3316 { 3317 hdev->hw.mac.speed = speed; 3318 hdev->hw.mac.duplex = duplex; 3319 } 3320 3321 static int hclgevf_gro_en(struct hnae3_handle *handle, bool enable) 3322 { 3323 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3324 3325 return hclgevf_config_gro(hdev, enable); 3326 } 3327 3328 static void hclgevf_get_media_type(struct hnae3_handle *handle, u8 *media_type, 3329 u8 *module_type) 3330 { 3331 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3332 3333 if (media_type) 3334 *media_type = hdev->hw.mac.media_type; 3335 3336 if (module_type) 3337 *module_type = hdev->hw.mac.module_type; 3338 } 3339 3340 static bool hclgevf_get_hw_reset_stat(struct hnae3_handle *handle) 3341 { 3342 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3343 3344 return !!hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 3345 } 3346 3347 static bool hclgevf_ae_dev_resetting(struct hnae3_handle *handle) 3348 { 3349 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3350 3351 return test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 3352 } 3353 3354 static unsigned long hclgevf_ae_dev_reset_cnt(struct hnae3_handle *handle) 3355 { 3356 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3357 3358 return hdev->rst_stats.hw_rst_done_cnt; 3359 } 3360 3361 static void hclgevf_get_link_mode(struct hnae3_handle *handle, 3362 unsigned long *supported, 3363 unsigned long *advertising) 3364 { 3365 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3366 3367 *supported = hdev->hw.mac.supported; 3368 *advertising = hdev->hw.mac.advertising; 3369 } 3370 3371 #define MAX_SEPARATE_NUM 4 3372 #define SEPARATOR_VALUE 0xFFFFFFFF 3373 #define REG_NUM_PER_LINE 4 3374 #define REG_LEN_PER_LINE (REG_NUM_PER_LINE * sizeof(u32)) 3375 3376 static int hclgevf_get_regs_len(struct hnae3_handle *handle) 3377 { 3378 int cmdq_lines, common_lines, ring_lines, tqp_intr_lines; 3379 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3380 3381 cmdq_lines = sizeof(cmdq_reg_addr_list) / REG_LEN_PER_LINE + 1; 3382 common_lines = sizeof(common_reg_addr_list) / REG_LEN_PER_LINE + 1; 3383 ring_lines = sizeof(ring_reg_addr_list) / REG_LEN_PER_LINE + 1; 3384 tqp_intr_lines = sizeof(tqp_intr_reg_addr_list) / REG_LEN_PER_LINE + 1; 3385 3386 return (cmdq_lines + common_lines + ring_lines * hdev->num_tqps + 3387 tqp_intr_lines * (hdev->num_msi_used - 1)) * REG_LEN_PER_LINE; 3388 } 3389 3390 static void hclgevf_get_regs(struct hnae3_handle *handle, u32 *version, 3391 void *data) 3392 { 3393 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3394 int i, j, reg_um, separator_num; 3395 u32 *reg = data; 3396 3397 *version = hdev->fw_version; 3398 3399 /* fetching per-VF registers values from VF PCIe register space */ 3400 reg_um = sizeof(cmdq_reg_addr_list) / sizeof(u32); 3401 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 3402 for (i = 0; i < reg_um; i++) 3403 *reg++ = hclgevf_read_dev(&hdev->hw, cmdq_reg_addr_list[i]); 3404 for (i = 0; i < separator_num; i++) 3405 *reg++ = SEPARATOR_VALUE; 3406 3407 reg_um = sizeof(common_reg_addr_list) / sizeof(u32); 3408 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 3409 for (i = 0; i < reg_um; i++) 3410 *reg++ = hclgevf_read_dev(&hdev->hw, common_reg_addr_list[i]); 3411 for (i = 0; i < separator_num; i++) 3412 *reg++ = SEPARATOR_VALUE; 3413 3414 reg_um = sizeof(ring_reg_addr_list) / sizeof(u32); 3415 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 3416 for (j = 0; j < hdev->num_tqps; j++) { 3417 for (i = 0; i < reg_um; i++) 3418 *reg++ = hclgevf_read_dev(&hdev->hw, 3419 ring_reg_addr_list[i] + 3420 0x200 * j); 3421 for (i = 0; i < separator_num; i++) 3422 *reg++ = SEPARATOR_VALUE; 3423 } 3424 3425 reg_um = sizeof(tqp_intr_reg_addr_list) / sizeof(u32); 3426 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 3427 for (j = 0; j < hdev->num_msi_used - 1; j++) { 3428 for (i = 0; i < reg_um; i++) 3429 *reg++ = hclgevf_read_dev(&hdev->hw, 3430 tqp_intr_reg_addr_list[i] + 3431 4 * j); 3432 for (i = 0; i < separator_num; i++) 3433 *reg++ = SEPARATOR_VALUE; 3434 } 3435 } 3436 3437 void hclgevf_update_port_base_vlan_info(struct hclgevf_dev *hdev, u16 state, 3438 u8 *port_base_vlan_info, u8 data_size) 3439 { 3440 struct hnae3_handle *nic = &hdev->nic; 3441 struct hclge_vf_to_pf_msg send_msg; 3442 int ret; 3443 3444 rtnl_lock(); 3445 3446 if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) { 3447 dev_warn(&hdev->pdev->dev, 3448 "is resetting when updating port based vlan info\n"); 3449 rtnl_unlock(); 3450 return; 3451 } 3452 3453 ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 3454 if (ret) { 3455 rtnl_unlock(); 3456 return; 3457 } 3458 3459 /* send msg to PF and wait update port based vlan info */ 3460 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 3461 HCLGE_MBX_PORT_BASE_VLAN_CFG); 3462 memcpy(send_msg.data, port_base_vlan_info, data_size); 3463 ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 3464 if (!ret) { 3465 if (state == HNAE3_PORT_BASE_VLAN_DISABLE) 3466 nic->port_base_vlan_state = state; 3467 else 3468 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_ENABLE; 3469 } 3470 3471 hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 3472 rtnl_unlock(); 3473 } 3474 3475 static const struct hnae3_ae_ops hclgevf_ops = { 3476 .init_ae_dev = hclgevf_init_ae_dev, 3477 .uninit_ae_dev = hclgevf_uninit_ae_dev, 3478 .flr_prepare = hclgevf_flr_prepare, 3479 .flr_done = hclgevf_flr_done, 3480 .init_client_instance = hclgevf_init_client_instance, 3481 .uninit_client_instance = hclgevf_uninit_client_instance, 3482 .start = hclgevf_ae_start, 3483 .stop = hclgevf_ae_stop, 3484 .client_start = hclgevf_client_start, 3485 .client_stop = hclgevf_client_stop, 3486 .map_ring_to_vector = hclgevf_map_ring_to_vector, 3487 .unmap_ring_from_vector = hclgevf_unmap_ring_from_vector, 3488 .get_vector = hclgevf_get_vector, 3489 .put_vector = hclgevf_put_vector, 3490 .reset_queue = hclgevf_reset_tqp, 3491 .get_mac_addr = hclgevf_get_mac_addr, 3492 .set_mac_addr = hclgevf_set_mac_addr, 3493 .add_uc_addr = hclgevf_add_uc_addr, 3494 .rm_uc_addr = hclgevf_rm_uc_addr, 3495 .add_mc_addr = hclgevf_add_mc_addr, 3496 .rm_mc_addr = hclgevf_rm_mc_addr, 3497 .get_stats = hclgevf_get_stats, 3498 .update_stats = hclgevf_update_stats, 3499 .get_strings = hclgevf_get_strings, 3500 .get_sset_count = hclgevf_get_sset_count, 3501 .get_rss_key_size = hclgevf_get_rss_key_size, 3502 .get_rss_indir_size = hclgevf_get_rss_indir_size, 3503 .get_rss = hclgevf_get_rss, 3504 .set_rss = hclgevf_set_rss, 3505 .get_rss_tuple = hclgevf_get_rss_tuple, 3506 .set_rss_tuple = hclgevf_set_rss_tuple, 3507 .get_tc_size = hclgevf_get_tc_size, 3508 .get_fw_version = hclgevf_get_fw_version, 3509 .set_vlan_filter = hclgevf_set_vlan_filter, 3510 .enable_hw_strip_rxvtag = hclgevf_en_hw_strip_rxvtag, 3511 .reset_event = hclgevf_reset_event, 3512 .set_default_reset_request = hclgevf_set_def_reset_request, 3513 .set_channels = hclgevf_set_channels, 3514 .get_channels = hclgevf_get_channels, 3515 .get_tqps_and_rss_info = hclgevf_get_tqps_and_rss_info, 3516 .get_regs_len = hclgevf_get_regs_len, 3517 .get_regs = hclgevf_get_regs, 3518 .get_status = hclgevf_get_status, 3519 .get_ksettings_an_result = hclgevf_get_ksettings_an_result, 3520 .get_media_type = hclgevf_get_media_type, 3521 .get_hw_reset_stat = hclgevf_get_hw_reset_stat, 3522 .ae_dev_resetting = hclgevf_ae_dev_resetting, 3523 .ae_dev_reset_cnt = hclgevf_ae_dev_reset_cnt, 3524 .set_gro_en = hclgevf_gro_en, 3525 .set_mtu = hclgevf_set_mtu, 3526 .get_global_queue_id = hclgevf_get_qid_global, 3527 .set_timer_task = hclgevf_set_timer_task, 3528 .get_link_mode = hclgevf_get_link_mode, 3529 .set_promisc_mode = hclgevf_set_promisc_mode, 3530 .request_update_promisc_mode = hclgevf_request_update_promisc_mode, 3531 }; 3532 3533 static struct hnae3_ae_algo ae_algovf = { 3534 .ops = &hclgevf_ops, 3535 .pdev_id_table = ae_algovf_pci_tbl, 3536 }; 3537 3538 static int hclgevf_init(void) 3539 { 3540 pr_info("%s is initializing\n", HCLGEVF_NAME); 3541 3542 hclgevf_wq = alloc_workqueue("%s", 0, 0, HCLGEVF_NAME); 3543 if (!hclgevf_wq) { 3544 pr_err("%s: failed to create workqueue\n", HCLGEVF_NAME); 3545 return -ENOMEM; 3546 } 3547 3548 hnae3_register_ae_algo(&ae_algovf); 3549 3550 return 0; 3551 } 3552 3553 static void hclgevf_exit(void) 3554 { 3555 hnae3_unregister_ae_algo(&ae_algovf); 3556 destroy_workqueue(hclgevf_wq); 3557 } 3558 module_init(hclgevf_init); 3559 module_exit(hclgevf_exit); 3560 3561 MODULE_LICENSE("GPL"); 3562 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 3563 MODULE_DESCRIPTION("HCLGEVF Driver"); 3564 MODULE_VERSION(HCLGEVF_MOD_VERSION); 3565