1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/etherdevice.h> 5 #include <linux/iopoll.h> 6 #include <net/rtnetlink.h> 7 #include "hclgevf_cmd.h" 8 #include "hclgevf_main.h" 9 #include "hclge_mbx.h" 10 #include "hnae3.h" 11 12 #define HCLGEVF_NAME "hclgevf" 13 14 static int hclgevf_reset_hdev(struct hclgevf_dev *hdev); 15 static struct hnae3_ae_algo ae_algovf; 16 17 static const struct pci_device_id ae_algovf_pci_tbl[] = { 18 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0}, 19 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF), 0}, 20 /* required last entry */ 21 {0, } 22 }; 23 24 static const u8 hclgevf_hash_key[] = { 25 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2, 26 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0, 27 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4, 28 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C, 29 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA 30 }; 31 32 MODULE_DEVICE_TABLE(pci, ae_algovf_pci_tbl); 33 34 static const u32 cmdq_reg_addr_list[] = {HCLGEVF_CMDQ_TX_ADDR_L_REG, 35 HCLGEVF_CMDQ_TX_ADDR_H_REG, 36 HCLGEVF_CMDQ_TX_DEPTH_REG, 37 HCLGEVF_CMDQ_TX_TAIL_REG, 38 HCLGEVF_CMDQ_TX_HEAD_REG, 39 HCLGEVF_CMDQ_RX_ADDR_L_REG, 40 HCLGEVF_CMDQ_RX_ADDR_H_REG, 41 HCLGEVF_CMDQ_RX_DEPTH_REG, 42 HCLGEVF_CMDQ_RX_TAIL_REG, 43 HCLGEVF_CMDQ_RX_HEAD_REG, 44 HCLGEVF_VECTOR0_CMDQ_SRC_REG, 45 HCLGEVF_CMDQ_INTR_STS_REG, 46 HCLGEVF_CMDQ_INTR_EN_REG, 47 HCLGEVF_CMDQ_INTR_GEN_REG}; 48 49 static const u32 common_reg_addr_list[] = {HCLGEVF_MISC_VECTOR_REG_BASE, 50 HCLGEVF_RST_ING, 51 HCLGEVF_GRO_EN_REG}; 52 53 static const u32 ring_reg_addr_list[] = {HCLGEVF_RING_RX_ADDR_L_REG, 54 HCLGEVF_RING_RX_ADDR_H_REG, 55 HCLGEVF_RING_RX_BD_NUM_REG, 56 HCLGEVF_RING_RX_BD_LENGTH_REG, 57 HCLGEVF_RING_RX_MERGE_EN_REG, 58 HCLGEVF_RING_RX_TAIL_REG, 59 HCLGEVF_RING_RX_HEAD_REG, 60 HCLGEVF_RING_RX_FBD_NUM_REG, 61 HCLGEVF_RING_RX_OFFSET_REG, 62 HCLGEVF_RING_RX_FBD_OFFSET_REG, 63 HCLGEVF_RING_RX_STASH_REG, 64 HCLGEVF_RING_RX_BD_ERR_REG, 65 HCLGEVF_RING_TX_ADDR_L_REG, 66 HCLGEVF_RING_TX_ADDR_H_REG, 67 HCLGEVF_RING_TX_BD_NUM_REG, 68 HCLGEVF_RING_TX_PRIORITY_REG, 69 HCLGEVF_RING_TX_TC_REG, 70 HCLGEVF_RING_TX_MERGE_EN_REG, 71 HCLGEVF_RING_TX_TAIL_REG, 72 HCLGEVF_RING_TX_HEAD_REG, 73 HCLGEVF_RING_TX_FBD_NUM_REG, 74 HCLGEVF_RING_TX_OFFSET_REG, 75 HCLGEVF_RING_TX_EBD_NUM_REG, 76 HCLGEVF_RING_TX_EBD_OFFSET_REG, 77 HCLGEVF_RING_TX_BD_ERR_REG, 78 HCLGEVF_RING_EN_REG}; 79 80 static const u32 tqp_intr_reg_addr_list[] = {HCLGEVF_TQP_INTR_CTRL_REG, 81 HCLGEVF_TQP_INTR_GL0_REG, 82 HCLGEVF_TQP_INTR_GL1_REG, 83 HCLGEVF_TQP_INTR_GL2_REG, 84 HCLGEVF_TQP_INTR_RL_REG}; 85 86 static struct hclgevf_dev *hclgevf_ae_get_hdev(struct hnae3_handle *handle) 87 { 88 if (!handle->client) 89 return container_of(handle, struct hclgevf_dev, nic); 90 else if (handle->client->type == HNAE3_CLIENT_ROCE) 91 return container_of(handle, struct hclgevf_dev, roce); 92 else 93 return container_of(handle, struct hclgevf_dev, nic); 94 } 95 96 static int hclgevf_tqps_update_stats(struct hnae3_handle *handle) 97 { 98 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 99 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 100 struct hclgevf_desc desc; 101 struct hclgevf_tqp *tqp; 102 int status; 103 int i; 104 105 for (i = 0; i < kinfo->num_tqps; i++) { 106 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 107 hclgevf_cmd_setup_basic_desc(&desc, 108 HCLGEVF_OPC_QUERY_RX_STATUS, 109 true); 110 111 desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 112 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 113 if (status) { 114 dev_err(&hdev->pdev->dev, 115 "Query tqp stat fail, status = %d,queue = %d\n", 116 status, i); 117 return status; 118 } 119 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd += 120 le32_to_cpu(desc.data[1]); 121 122 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_TX_STATUS, 123 true); 124 125 desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 126 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 127 if (status) { 128 dev_err(&hdev->pdev->dev, 129 "Query tqp stat fail, status = %d,queue = %d\n", 130 status, i); 131 return status; 132 } 133 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd += 134 le32_to_cpu(desc.data[1]); 135 } 136 137 return 0; 138 } 139 140 static u64 *hclgevf_tqps_get_stats(struct hnae3_handle *handle, u64 *data) 141 { 142 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 143 struct hclgevf_tqp *tqp; 144 u64 *buff = data; 145 int i; 146 147 for (i = 0; i < kinfo->num_tqps; i++) { 148 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 149 *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd; 150 } 151 for (i = 0; i < kinfo->num_tqps; i++) { 152 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 153 *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd; 154 } 155 156 return buff; 157 } 158 159 static int hclgevf_tqps_get_sset_count(struct hnae3_handle *handle, int strset) 160 { 161 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 162 163 return kinfo->num_tqps * 2; 164 } 165 166 static u8 *hclgevf_tqps_get_strings(struct hnae3_handle *handle, u8 *data) 167 { 168 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 169 u8 *buff = data; 170 int i = 0; 171 172 for (i = 0; i < kinfo->num_tqps; i++) { 173 struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 174 struct hclgevf_tqp, q); 175 snprintf(buff, ETH_GSTRING_LEN, "txq%d_pktnum_rcd", 176 tqp->index); 177 buff += ETH_GSTRING_LEN; 178 } 179 180 for (i = 0; i < kinfo->num_tqps; i++) { 181 struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 182 struct hclgevf_tqp, q); 183 snprintf(buff, ETH_GSTRING_LEN, "rxq%d_pktnum_rcd", 184 tqp->index); 185 buff += ETH_GSTRING_LEN; 186 } 187 188 return buff; 189 } 190 191 static void hclgevf_update_stats(struct hnae3_handle *handle, 192 struct net_device_stats *net_stats) 193 { 194 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 195 int status; 196 197 status = hclgevf_tqps_update_stats(handle); 198 if (status) 199 dev_err(&hdev->pdev->dev, 200 "VF update of TQPS stats fail, status = %d.\n", 201 status); 202 } 203 204 static int hclgevf_get_sset_count(struct hnae3_handle *handle, int strset) 205 { 206 if (strset == ETH_SS_TEST) 207 return -EOPNOTSUPP; 208 else if (strset == ETH_SS_STATS) 209 return hclgevf_tqps_get_sset_count(handle, strset); 210 211 return 0; 212 } 213 214 static void hclgevf_get_strings(struct hnae3_handle *handle, u32 strset, 215 u8 *data) 216 { 217 u8 *p = (char *)data; 218 219 if (strset == ETH_SS_STATS) 220 p = hclgevf_tqps_get_strings(handle, p); 221 } 222 223 static void hclgevf_get_stats(struct hnae3_handle *handle, u64 *data) 224 { 225 hclgevf_tqps_get_stats(handle, data); 226 } 227 228 static int hclgevf_get_tc_info(struct hclgevf_dev *hdev) 229 { 230 u8 resp_msg; 231 int status; 232 233 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_TCINFO, 0, NULL, 0, 234 true, &resp_msg, sizeof(resp_msg)); 235 if (status) { 236 dev_err(&hdev->pdev->dev, 237 "VF request to get TC info from PF failed %d", 238 status); 239 return status; 240 } 241 242 hdev->hw_tc_map = resp_msg; 243 244 return 0; 245 } 246 247 static int hclgevf_get_port_base_vlan_filter_state(struct hclgevf_dev *hdev) 248 { 249 struct hnae3_handle *nic = &hdev->nic; 250 u8 resp_msg; 251 int ret; 252 253 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 254 HCLGE_MBX_GET_PORT_BASE_VLAN_STATE, 255 NULL, 0, true, &resp_msg, sizeof(u8)); 256 if (ret) { 257 dev_err(&hdev->pdev->dev, 258 "VF request to get port based vlan state failed %d", 259 ret); 260 return ret; 261 } 262 263 nic->port_base_vlan_state = resp_msg; 264 265 return 0; 266 } 267 268 static int hclgevf_get_queue_info(struct hclgevf_dev *hdev) 269 { 270 #define HCLGEVF_TQPS_RSS_INFO_LEN 6 271 u8 resp_msg[HCLGEVF_TQPS_RSS_INFO_LEN]; 272 int status; 273 274 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QINFO, 0, NULL, 0, 275 true, resp_msg, 276 HCLGEVF_TQPS_RSS_INFO_LEN); 277 if (status) { 278 dev_err(&hdev->pdev->dev, 279 "VF request to get tqp info from PF failed %d", 280 status); 281 return status; 282 } 283 284 memcpy(&hdev->num_tqps, &resp_msg[0], sizeof(u16)); 285 memcpy(&hdev->rss_size_max, &resp_msg[2], sizeof(u16)); 286 memcpy(&hdev->rx_buf_len, &resp_msg[4], sizeof(u16)); 287 288 return 0; 289 } 290 291 static int hclgevf_get_queue_depth(struct hclgevf_dev *hdev) 292 { 293 #define HCLGEVF_TQPS_DEPTH_INFO_LEN 4 294 u8 resp_msg[HCLGEVF_TQPS_DEPTH_INFO_LEN]; 295 int ret; 296 297 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QDEPTH, 0, NULL, 0, 298 true, resp_msg, 299 HCLGEVF_TQPS_DEPTH_INFO_LEN); 300 if (ret) { 301 dev_err(&hdev->pdev->dev, 302 "VF request to get tqp depth info from PF failed %d", 303 ret); 304 return ret; 305 } 306 307 memcpy(&hdev->num_tx_desc, &resp_msg[0], sizeof(u16)); 308 memcpy(&hdev->num_rx_desc, &resp_msg[2], sizeof(u16)); 309 310 return 0; 311 } 312 313 static u16 hclgevf_get_qid_global(struct hnae3_handle *handle, u16 queue_id) 314 { 315 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 316 u8 msg_data[2], resp_data[2]; 317 u16 qid_in_pf = 0; 318 int ret; 319 320 memcpy(&msg_data[0], &queue_id, sizeof(queue_id)); 321 322 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QID_IN_PF, 0, msg_data, 323 sizeof(msg_data), true, resp_data, 324 sizeof(resp_data)); 325 if (!ret) 326 qid_in_pf = *(u16 *)resp_data; 327 328 return qid_in_pf; 329 } 330 331 static int hclgevf_get_pf_media_type(struct hclgevf_dev *hdev) 332 { 333 u8 resp_msg[2]; 334 int ret; 335 336 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_MEDIA_TYPE, 0, NULL, 0, 337 true, resp_msg, sizeof(resp_msg)); 338 if (ret) { 339 dev_err(&hdev->pdev->dev, 340 "VF request to get the pf port media type failed %d", 341 ret); 342 return ret; 343 } 344 345 hdev->hw.mac.media_type = resp_msg[0]; 346 hdev->hw.mac.module_type = resp_msg[1]; 347 348 return 0; 349 } 350 351 static int hclgevf_alloc_tqps(struct hclgevf_dev *hdev) 352 { 353 struct hclgevf_tqp *tqp; 354 int i; 355 356 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 357 sizeof(struct hclgevf_tqp), GFP_KERNEL); 358 if (!hdev->htqp) 359 return -ENOMEM; 360 361 tqp = hdev->htqp; 362 363 for (i = 0; i < hdev->num_tqps; i++) { 364 tqp->dev = &hdev->pdev->dev; 365 tqp->index = i; 366 367 tqp->q.ae_algo = &ae_algovf; 368 tqp->q.buf_size = hdev->rx_buf_len; 369 tqp->q.tx_desc_num = hdev->num_tx_desc; 370 tqp->q.rx_desc_num = hdev->num_rx_desc; 371 tqp->q.io_base = hdev->hw.io_base + HCLGEVF_TQP_REG_OFFSET + 372 i * HCLGEVF_TQP_REG_SIZE; 373 374 tqp++; 375 } 376 377 return 0; 378 } 379 380 static int hclgevf_knic_setup(struct hclgevf_dev *hdev) 381 { 382 struct hnae3_handle *nic = &hdev->nic; 383 struct hnae3_knic_private_info *kinfo; 384 u16 new_tqps = hdev->num_tqps; 385 int i; 386 387 kinfo = &nic->kinfo; 388 kinfo->num_tc = 0; 389 kinfo->num_tx_desc = hdev->num_tx_desc; 390 kinfo->num_rx_desc = hdev->num_rx_desc; 391 kinfo->rx_buf_len = hdev->rx_buf_len; 392 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) 393 if (hdev->hw_tc_map & BIT(i)) 394 kinfo->num_tc++; 395 396 kinfo->rss_size 397 = min_t(u16, hdev->rss_size_max, new_tqps / kinfo->num_tc); 398 new_tqps = kinfo->rss_size * kinfo->num_tc; 399 kinfo->num_tqps = min(new_tqps, hdev->num_tqps); 400 401 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps, 402 sizeof(struct hnae3_queue *), GFP_KERNEL); 403 if (!kinfo->tqp) 404 return -ENOMEM; 405 406 for (i = 0; i < kinfo->num_tqps; i++) { 407 hdev->htqp[i].q.handle = &hdev->nic; 408 hdev->htqp[i].q.tqp_index = i; 409 kinfo->tqp[i] = &hdev->htqp[i].q; 410 } 411 412 return 0; 413 } 414 415 static void hclgevf_request_link_info(struct hclgevf_dev *hdev) 416 { 417 int status; 418 u8 resp_msg; 419 420 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_STATUS, 0, NULL, 421 0, false, &resp_msg, sizeof(resp_msg)); 422 if (status) 423 dev_err(&hdev->pdev->dev, 424 "VF failed to fetch link status(%d) from PF", status); 425 } 426 427 void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state) 428 { 429 struct hnae3_handle *rhandle = &hdev->roce; 430 struct hnae3_handle *handle = &hdev->nic; 431 struct hnae3_client *rclient; 432 struct hnae3_client *client; 433 434 client = handle->client; 435 rclient = hdev->roce_client; 436 437 link_state = 438 test_bit(HCLGEVF_STATE_DOWN, &hdev->state) ? 0 : link_state; 439 440 if (link_state != hdev->hw.mac.link) { 441 client->ops->link_status_change(handle, !!link_state); 442 if (rclient && rclient->ops->link_status_change) 443 rclient->ops->link_status_change(rhandle, !!link_state); 444 hdev->hw.mac.link = link_state; 445 } 446 } 447 448 static void hclgevf_update_link_mode(struct hclgevf_dev *hdev) 449 { 450 #define HCLGEVF_ADVERTISING 0 451 #define HCLGEVF_SUPPORTED 1 452 u8 send_msg; 453 u8 resp_msg; 454 455 send_msg = HCLGEVF_ADVERTISING; 456 hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_MODE, 0, 457 &send_msg, sizeof(send_msg), false, 458 &resp_msg, sizeof(resp_msg)); 459 send_msg = HCLGEVF_SUPPORTED; 460 hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_MODE, 0, 461 &send_msg, sizeof(send_msg), false, 462 &resp_msg, sizeof(resp_msg)); 463 } 464 465 static int hclgevf_set_handle_info(struct hclgevf_dev *hdev) 466 { 467 struct hnae3_handle *nic = &hdev->nic; 468 int ret; 469 470 nic->ae_algo = &ae_algovf; 471 nic->pdev = hdev->pdev; 472 nic->numa_node_mask = hdev->numa_node_mask; 473 nic->flags |= HNAE3_SUPPORT_VF; 474 475 ret = hclgevf_knic_setup(hdev); 476 if (ret) 477 dev_err(&hdev->pdev->dev, "VF knic setup failed %d\n", 478 ret); 479 return ret; 480 } 481 482 static void hclgevf_free_vector(struct hclgevf_dev *hdev, int vector_id) 483 { 484 if (hdev->vector_status[vector_id] == HCLGEVF_INVALID_VPORT) { 485 dev_warn(&hdev->pdev->dev, 486 "vector(vector_id %d) has been freed.\n", vector_id); 487 return; 488 } 489 490 hdev->vector_status[vector_id] = HCLGEVF_INVALID_VPORT; 491 hdev->num_msi_left += 1; 492 hdev->num_msi_used -= 1; 493 } 494 495 static int hclgevf_get_vector(struct hnae3_handle *handle, u16 vector_num, 496 struct hnae3_vector_info *vector_info) 497 { 498 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 499 struct hnae3_vector_info *vector = vector_info; 500 int alloc = 0; 501 int i, j; 502 503 vector_num = min(hdev->num_msi_left, vector_num); 504 505 for (j = 0; j < vector_num; j++) { 506 for (i = HCLGEVF_MISC_VECTOR_NUM + 1; i < hdev->num_msi; i++) { 507 if (hdev->vector_status[i] == HCLGEVF_INVALID_VPORT) { 508 vector->vector = pci_irq_vector(hdev->pdev, i); 509 vector->io_addr = hdev->hw.io_base + 510 HCLGEVF_VECTOR_REG_BASE + 511 (i - 1) * HCLGEVF_VECTOR_REG_OFFSET; 512 hdev->vector_status[i] = 0; 513 hdev->vector_irq[i] = vector->vector; 514 515 vector++; 516 alloc++; 517 518 break; 519 } 520 } 521 } 522 hdev->num_msi_left -= alloc; 523 hdev->num_msi_used += alloc; 524 525 return alloc; 526 } 527 528 static int hclgevf_get_vector_index(struct hclgevf_dev *hdev, int vector) 529 { 530 int i; 531 532 for (i = 0; i < hdev->num_msi; i++) 533 if (vector == hdev->vector_irq[i]) 534 return i; 535 536 return -EINVAL; 537 } 538 539 static int hclgevf_set_rss_algo_key(struct hclgevf_dev *hdev, 540 const u8 hfunc, const u8 *key) 541 { 542 struct hclgevf_rss_config_cmd *req; 543 struct hclgevf_desc desc; 544 int key_offset = 0; 545 int key_counts; 546 int key_size; 547 int ret; 548 549 key_counts = HCLGEVF_RSS_KEY_SIZE; 550 req = (struct hclgevf_rss_config_cmd *)desc.data; 551 552 while (key_counts) { 553 hclgevf_cmd_setup_basic_desc(&desc, 554 HCLGEVF_OPC_RSS_GENERIC_CONFIG, 555 false); 556 557 req->hash_config |= (hfunc & HCLGEVF_RSS_HASH_ALGO_MASK); 558 req->hash_config |= 559 (key_offset << HCLGEVF_RSS_HASH_KEY_OFFSET_B); 560 561 key_size = min(HCLGEVF_RSS_HASH_KEY_NUM, key_counts); 562 memcpy(req->hash_key, 563 key + key_offset * HCLGEVF_RSS_HASH_KEY_NUM, key_size); 564 565 key_counts -= key_size; 566 key_offset++; 567 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 568 if (ret) { 569 dev_err(&hdev->pdev->dev, 570 "Configure RSS config fail, status = %d\n", 571 ret); 572 return ret; 573 } 574 } 575 576 return 0; 577 } 578 579 static u32 hclgevf_get_rss_key_size(struct hnae3_handle *handle) 580 { 581 return HCLGEVF_RSS_KEY_SIZE; 582 } 583 584 static u32 hclgevf_get_rss_indir_size(struct hnae3_handle *handle) 585 { 586 return HCLGEVF_RSS_IND_TBL_SIZE; 587 } 588 589 static int hclgevf_set_rss_indir_table(struct hclgevf_dev *hdev) 590 { 591 const u8 *indir = hdev->rss_cfg.rss_indirection_tbl; 592 struct hclgevf_rss_indirection_table_cmd *req; 593 struct hclgevf_desc desc; 594 int status; 595 int i, j; 596 597 req = (struct hclgevf_rss_indirection_table_cmd *)desc.data; 598 599 for (i = 0; i < HCLGEVF_RSS_CFG_TBL_NUM; i++) { 600 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INDIR_TABLE, 601 false); 602 req->start_table_index = i * HCLGEVF_RSS_CFG_TBL_SIZE; 603 req->rss_set_bitmap = HCLGEVF_RSS_SET_BITMAP_MSK; 604 for (j = 0; j < HCLGEVF_RSS_CFG_TBL_SIZE; j++) 605 req->rss_result[j] = 606 indir[i * HCLGEVF_RSS_CFG_TBL_SIZE + j]; 607 608 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 609 if (status) { 610 dev_err(&hdev->pdev->dev, 611 "VF failed(=%d) to set RSS indirection table\n", 612 status); 613 return status; 614 } 615 } 616 617 return 0; 618 } 619 620 static int hclgevf_set_rss_tc_mode(struct hclgevf_dev *hdev, u16 rss_size) 621 { 622 struct hclgevf_rss_tc_mode_cmd *req; 623 u16 tc_offset[HCLGEVF_MAX_TC_NUM]; 624 u16 tc_valid[HCLGEVF_MAX_TC_NUM]; 625 u16 tc_size[HCLGEVF_MAX_TC_NUM]; 626 struct hclgevf_desc desc; 627 u16 roundup_size; 628 int status; 629 int i; 630 631 req = (struct hclgevf_rss_tc_mode_cmd *)desc.data; 632 633 roundup_size = roundup_pow_of_two(rss_size); 634 roundup_size = ilog2(roundup_size); 635 636 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 637 tc_valid[i] = !!(hdev->hw_tc_map & BIT(i)); 638 tc_size[i] = roundup_size; 639 tc_offset[i] = rss_size * i; 640 } 641 642 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_TC_MODE, false); 643 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 644 hnae3_set_bit(req->rss_tc_mode[i], HCLGEVF_RSS_TC_VALID_B, 645 (tc_valid[i] & 0x1)); 646 hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_SIZE_M, 647 HCLGEVF_RSS_TC_SIZE_S, tc_size[i]); 648 hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_OFFSET_M, 649 HCLGEVF_RSS_TC_OFFSET_S, tc_offset[i]); 650 } 651 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 652 if (status) 653 dev_err(&hdev->pdev->dev, 654 "VF failed(=%d) to set rss tc mode\n", status); 655 656 return status; 657 } 658 659 /* for revision 0x20, vf shared the same rss config with pf */ 660 static int hclgevf_get_rss_hash_key(struct hclgevf_dev *hdev) 661 { 662 #define HCLGEVF_RSS_MBX_RESP_LEN 8 663 664 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 665 u8 resp_msg[HCLGEVF_RSS_MBX_RESP_LEN]; 666 u16 msg_num, hash_key_index; 667 u8 index; 668 int ret; 669 670 msg_num = (HCLGEVF_RSS_KEY_SIZE + HCLGEVF_RSS_MBX_RESP_LEN - 1) / 671 HCLGEVF_RSS_MBX_RESP_LEN; 672 for (index = 0; index < msg_num; index++) { 673 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_RSS_KEY, 0, 674 &index, sizeof(index), 675 true, resp_msg, 676 HCLGEVF_RSS_MBX_RESP_LEN); 677 if (ret) { 678 dev_err(&hdev->pdev->dev, 679 "VF get rss hash key from PF failed, ret=%d", 680 ret); 681 return ret; 682 } 683 684 hash_key_index = HCLGEVF_RSS_MBX_RESP_LEN * index; 685 if (index == msg_num - 1) 686 memcpy(&rss_cfg->rss_hash_key[hash_key_index], 687 &resp_msg[0], 688 HCLGEVF_RSS_KEY_SIZE - hash_key_index); 689 else 690 memcpy(&rss_cfg->rss_hash_key[hash_key_index], 691 &resp_msg[0], HCLGEVF_RSS_MBX_RESP_LEN); 692 } 693 694 return 0; 695 } 696 697 static int hclgevf_get_rss(struct hnae3_handle *handle, u32 *indir, u8 *key, 698 u8 *hfunc) 699 { 700 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 701 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 702 int i, ret; 703 704 if (handle->pdev->revision >= 0x21) { 705 /* Get hash algorithm */ 706 if (hfunc) { 707 switch (rss_cfg->hash_algo) { 708 case HCLGEVF_RSS_HASH_ALGO_TOEPLITZ: 709 *hfunc = ETH_RSS_HASH_TOP; 710 break; 711 case HCLGEVF_RSS_HASH_ALGO_SIMPLE: 712 *hfunc = ETH_RSS_HASH_XOR; 713 break; 714 default: 715 *hfunc = ETH_RSS_HASH_UNKNOWN; 716 break; 717 } 718 } 719 720 /* Get the RSS Key required by the user */ 721 if (key) 722 memcpy(key, rss_cfg->rss_hash_key, 723 HCLGEVF_RSS_KEY_SIZE); 724 } else { 725 if (hfunc) 726 *hfunc = ETH_RSS_HASH_TOP; 727 if (key) { 728 ret = hclgevf_get_rss_hash_key(hdev); 729 if (ret) 730 return ret; 731 memcpy(key, rss_cfg->rss_hash_key, 732 HCLGEVF_RSS_KEY_SIZE); 733 } 734 } 735 736 if (indir) 737 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 738 indir[i] = rss_cfg->rss_indirection_tbl[i]; 739 740 return 0; 741 } 742 743 static int hclgevf_set_rss(struct hnae3_handle *handle, const u32 *indir, 744 const u8 *key, const u8 hfunc) 745 { 746 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 747 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 748 int ret, i; 749 750 if (handle->pdev->revision >= 0x21) { 751 /* Set the RSS Hash Key if specififed by the user */ 752 if (key) { 753 switch (hfunc) { 754 case ETH_RSS_HASH_TOP: 755 rss_cfg->hash_algo = 756 HCLGEVF_RSS_HASH_ALGO_TOEPLITZ; 757 break; 758 case ETH_RSS_HASH_XOR: 759 rss_cfg->hash_algo = 760 HCLGEVF_RSS_HASH_ALGO_SIMPLE; 761 break; 762 case ETH_RSS_HASH_NO_CHANGE: 763 break; 764 default: 765 return -EINVAL; 766 } 767 768 ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 769 key); 770 if (ret) 771 return ret; 772 773 /* Update the shadow RSS key with user specified qids */ 774 memcpy(rss_cfg->rss_hash_key, key, 775 HCLGEVF_RSS_KEY_SIZE); 776 } 777 } 778 779 /* update the shadow RSS table with user specified qids */ 780 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 781 rss_cfg->rss_indirection_tbl[i] = indir[i]; 782 783 /* update the hardware */ 784 return hclgevf_set_rss_indir_table(hdev); 785 } 786 787 static u8 hclgevf_get_rss_hash_bits(struct ethtool_rxnfc *nfc) 788 { 789 u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGEVF_S_PORT_BIT : 0; 790 791 if (nfc->data & RXH_L4_B_2_3) 792 hash_sets |= HCLGEVF_D_PORT_BIT; 793 else 794 hash_sets &= ~HCLGEVF_D_PORT_BIT; 795 796 if (nfc->data & RXH_IP_SRC) 797 hash_sets |= HCLGEVF_S_IP_BIT; 798 else 799 hash_sets &= ~HCLGEVF_S_IP_BIT; 800 801 if (nfc->data & RXH_IP_DST) 802 hash_sets |= HCLGEVF_D_IP_BIT; 803 else 804 hash_sets &= ~HCLGEVF_D_IP_BIT; 805 806 if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW) 807 hash_sets |= HCLGEVF_V_TAG_BIT; 808 809 return hash_sets; 810 } 811 812 static int hclgevf_set_rss_tuple(struct hnae3_handle *handle, 813 struct ethtool_rxnfc *nfc) 814 { 815 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 816 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 817 struct hclgevf_rss_input_tuple_cmd *req; 818 struct hclgevf_desc desc; 819 u8 tuple_sets; 820 int ret; 821 822 if (handle->pdev->revision == 0x20) 823 return -EOPNOTSUPP; 824 825 if (nfc->data & 826 ~(RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3)) 827 return -EINVAL; 828 829 req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 830 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 831 832 req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 833 req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 834 req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 835 req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 836 req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 837 req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 838 req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 839 req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 840 841 tuple_sets = hclgevf_get_rss_hash_bits(nfc); 842 switch (nfc->flow_type) { 843 case TCP_V4_FLOW: 844 req->ipv4_tcp_en = tuple_sets; 845 break; 846 case TCP_V6_FLOW: 847 req->ipv6_tcp_en = tuple_sets; 848 break; 849 case UDP_V4_FLOW: 850 req->ipv4_udp_en = tuple_sets; 851 break; 852 case UDP_V6_FLOW: 853 req->ipv6_udp_en = tuple_sets; 854 break; 855 case SCTP_V4_FLOW: 856 req->ipv4_sctp_en = tuple_sets; 857 break; 858 case SCTP_V6_FLOW: 859 if ((nfc->data & RXH_L4_B_0_1) || 860 (nfc->data & RXH_L4_B_2_3)) 861 return -EINVAL; 862 863 req->ipv6_sctp_en = tuple_sets; 864 break; 865 case IPV4_FLOW: 866 req->ipv4_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 867 break; 868 case IPV6_FLOW: 869 req->ipv6_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 870 break; 871 default: 872 return -EINVAL; 873 } 874 875 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 876 if (ret) { 877 dev_err(&hdev->pdev->dev, 878 "Set rss tuple fail, status = %d\n", ret); 879 return ret; 880 } 881 882 rss_cfg->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en; 883 rss_cfg->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en; 884 rss_cfg->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en; 885 rss_cfg->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en; 886 rss_cfg->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en; 887 rss_cfg->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en; 888 rss_cfg->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en; 889 rss_cfg->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en; 890 return 0; 891 } 892 893 static int hclgevf_get_rss_tuple(struct hnae3_handle *handle, 894 struct ethtool_rxnfc *nfc) 895 { 896 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 897 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 898 u8 tuple_sets; 899 900 if (handle->pdev->revision == 0x20) 901 return -EOPNOTSUPP; 902 903 nfc->data = 0; 904 905 switch (nfc->flow_type) { 906 case TCP_V4_FLOW: 907 tuple_sets = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 908 break; 909 case UDP_V4_FLOW: 910 tuple_sets = rss_cfg->rss_tuple_sets.ipv4_udp_en; 911 break; 912 case TCP_V6_FLOW: 913 tuple_sets = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 914 break; 915 case UDP_V6_FLOW: 916 tuple_sets = rss_cfg->rss_tuple_sets.ipv6_udp_en; 917 break; 918 case SCTP_V4_FLOW: 919 tuple_sets = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 920 break; 921 case SCTP_V6_FLOW: 922 tuple_sets = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 923 break; 924 case IPV4_FLOW: 925 case IPV6_FLOW: 926 tuple_sets = HCLGEVF_S_IP_BIT | HCLGEVF_D_IP_BIT; 927 break; 928 default: 929 return -EINVAL; 930 } 931 932 if (!tuple_sets) 933 return 0; 934 935 if (tuple_sets & HCLGEVF_D_PORT_BIT) 936 nfc->data |= RXH_L4_B_2_3; 937 if (tuple_sets & HCLGEVF_S_PORT_BIT) 938 nfc->data |= RXH_L4_B_0_1; 939 if (tuple_sets & HCLGEVF_D_IP_BIT) 940 nfc->data |= RXH_IP_DST; 941 if (tuple_sets & HCLGEVF_S_IP_BIT) 942 nfc->data |= RXH_IP_SRC; 943 944 return 0; 945 } 946 947 static int hclgevf_set_rss_input_tuple(struct hclgevf_dev *hdev, 948 struct hclgevf_rss_cfg *rss_cfg) 949 { 950 struct hclgevf_rss_input_tuple_cmd *req; 951 struct hclgevf_desc desc; 952 int ret; 953 954 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 955 956 req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 957 958 req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 959 req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 960 req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 961 req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 962 req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 963 req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 964 req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 965 req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 966 967 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 968 if (ret) 969 dev_err(&hdev->pdev->dev, 970 "Configure rss input fail, status = %d\n", ret); 971 return ret; 972 } 973 974 static int hclgevf_get_tc_size(struct hnae3_handle *handle) 975 { 976 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 977 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 978 979 return rss_cfg->rss_size; 980 } 981 982 static int hclgevf_bind_ring_to_vector(struct hnae3_handle *handle, bool en, 983 int vector_id, 984 struct hnae3_ring_chain_node *ring_chain) 985 { 986 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 987 struct hnae3_ring_chain_node *node; 988 struct hclge_mbx_vf_to_pf_cmd *req; 989 struct hclgevf_desc desc; 990 int i = 0; 991 int status; 992 u8 type; 993 994 req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data; 995 996 for (node = ring_chain; node; node = node->next) { 997 int idx_offset = HCLGE_MBX_RING_MAP_BASIC_MSG_NUM + 998 HCLGE_MBX_RING_NODE_VARIABLE_NUM * i; 999 1000 if (i == 0) { 1001 hclgevf_cmd_setup_basic_desc(&desc, 1002 HCLGEVF_OPC_MBX_VF_TO_PF, 1003 false); 1004 type = en ? 1005 HCLGE_MBX_MAP_RING_TO_VECTOR : 1006 HCLGE_MBX_UNMAP_RING_TO_VECTOR; 1007 req->msg[0] = type; 1008 req->msg[1] = vector_id; 1009 } 1010 1011 req->msg[idx_offset] = 1012 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B); 1013 req->msg[idx_offset + 1] = node->tqp_index; 1014 req->msg[idx_offset + 2] = hnae3_get_field(node->int_gl_idx, 1015 HNAE3_RING_GL_IDX_M, 1016 HNAE3_RING_GL_IDX_S); 1017 1018 i++; 1019 if ((i == (HCLGE_MBX_VF_MSG_DATA_NUM - 1020 HCLGE_MBX_RING_MAP_BASIC_MSG_NUM) / 1021 HCLGE_MBX_RING_NODE_VARIABLE_NUM) || 1022 !node->next) { 1023 req->msg[2] = i; 1024 1025 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1026 if (status) { 1027 dev_err(&hdev->pdev->dev, 1028 "Map TQP fail, status is %d.\n", 1029 status); 1030 return status; 1031 } 1032 i = 0; 1033 hclgevf_cmd_setup_basic_desc(&desc, 1034 HCLGEVF_OPC_MBX_VF_TO_PF, 1035 false); 1036 req->msg[0] = type; 1037 req->msg[1] = vector_id; 1038 } 1039 } 1040 1041 return 0; 1042 } 1043 1044 static int hclgevf_map_ring_to_vector(struct hnae3_handle *handle, int vector, 1045 struct hnae3_ring_chain_node *ring_chain) 1046 { 1047 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1048 int vector_id; 1049 1050 vector_id = hclgevf_get_vector_index(hdev, vector); 1051 if (vector_id < 0) { 1052 dev_err(&handle->pdev->dev, 1053 "Get vector index fail. ret =%d\n", vector_id); 1054 return vector_id; 1055 } 1056 1057 return hclgevf_bind_ring_to_vector(handle, true, vector_id, ring_chain); 1058 } 1059 1060 static int hclgevf_unmap_ring_from_vector( 1061 struct hnae3_handle *handle, 1062 int vector, 1063 struct hnae3_ring_chain_node *ring_chain) 1064 { 1065 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1066 int ret, vector_id; 1067 1068 if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 1069 return 0; 1070 1071 vector_id = hclgevf_get_vector_index(hdev, vector); 1072 if (vector_id < 0) { 1073 dev_err(&handle->pdev->dev, 1074 "Get vector index fail. ret =%d\n", vector_id); 1075 return vector_id; 1076 } 1077 1078 ret = hclgevf_bind_ring_to_vector(handle, false, vector_id, ring_chain); 1079 if (ret) 1080 dev_err(&handle->pdev->dev, 1081 "Unmap ring from vector fail. vector=%d, ret =%d\n", 1082 vector_id, 1083 ret); 1084 1085 return ret; 1086 } 1087 1088 static int hclgevf_put_vector(struct hnae3_handle *handle, int vector) 1089 { 1090 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1091 int vector_id; 1092 1093 vector_id = hclgevf_get_vector_index(hdev, vector); 1094 if (vector_id < 0) { 1095 dev_err(&handle->pdev->dev, 1096 "hclgevf_put_vector get vector index fail. ret =%d\n", 1097 vector_id); 1098 return vector_id; 1099 } 1100 1101 hclgevf_free_vector(hdev, vector_id); 1102 1103 return 0; 1104 } 1105 1106 static int hclgevf_cmd_set_promisc_mode(struct hclgevf_dev *hdev, 1107 bool en_bc_pmc) 1108 { 1109 struct hclge_mbx_vf_to_pf_cmd *req; 1110 struct hclgevf_desc desc; 1111 int ret; 1112 1113 req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data; 1114 1115 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_MBX_VF_TO_PF, false); 1116 req->msg[0] = HCLGE_MBX_SET_PROMISC_MODE; 1117 req->msg[1] = en_bc_pmc ? 1 : 0; 1118 1119 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1120 if (ret) 1121 dev_err(&hdev->pdev->dev, 1122 "Set promisc mode fail, status is %d.\n", ret); 1123 1124 return ret; 1125 } 1126 1127 static int hclgevf_set_promisc_mode(struct hclgevf_dev *hdev, bool en_bc_pmc) 1128 { 1129 return hclgevf_cmd_set_promisc_mode(hdev, en_bc_pmc); 1130 } 1131 1132 static int hclgevf_tqp_enable(struct hclgevf_dev *hdev, int tqp_id, 1133 int stream_id, bool enable) 1134 { 1135 struct hclgevf_cfg_com_tqp_queue_cmd *req; 1136 struct hclgevf_desc desc; 1137 int status; 1138 1139 req = (struct hclgevf_cfg_com_tqp_queue_cmd *)desc.data; 1140 1141 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_CFG_COM_TQP_QUEUE, 1142 false); 1143 req->tqp_id = cpu_to_le16(tqp_id & HCLGEVF_RING_ID_MASK); 1144 req->stream_id = cpu_to_le16(stream_id); 1145 req->enable |= enable << HCLGEVF_TQP_ENABLE_B; 1146 1147 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1148 if (status) 1149 dev_err(&hdev->pdev->dev, 1150 "TQP enable fail, status =%d.\n", status); 1151 1152 return status; 1153 } 1154 1155 static void hclgevf_reset_tqp_stats(struct hnae3_handle *handle) 1156 { 1157 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 1158 struct hclgevf_tqp *tqp; 1159 int i; 1160 1161 for (i = 0; i < kinfo->num_tqps; i++) { 1162 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 1163 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats)); 1164 } 1165 } 1166 1167 static void hclgevf_get_mac_addr(struct hnae3_handle *handle, u8 *p) 1168 { 1169 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1170 1171 ether_addr_copy(p, hdev->hw.mac.mac_addr); 1172 } 1173 1174 static int hclgevf_set_mac_addr(struct hnae3_handle *handle, void *p, 1175 bool is_first) 1176 { 1177 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1178 u8 *old_mac_addr = (u8 *)hdev->hw.mac.mac_addr; 1179 u8 *new_mac_addr = (u8 *)p; 1180 u8 msg_data[ETH_ALEN * 2]; 1181 u16 subcode; 1182 int status; 1183 1184 ether_addr_copy(msg_data, new_mac_addr); 1185 ether_addr_copy(&msg_data[ETH_ALEN], old_mac_addr); 1186 1187 subcode = is_first ? HCLGE_MBX_MAC_VLAN_UC_ADD : 1188 HCLGE_MBX_MAC_VLAN_UC_MODIFY; 1189 1190 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 1191 subcode, msg_data, sizeof(msg_data), 1192 true, NULL, 0); 1193 if (!status) 1194 ether_addr_copy(hdev->hw.mac.mac_addr, new_mac_addr); 1195 1196 return status; 1197 } 1198 1199 static int hclgevf_add_uc_addr(struct hnae3_handle *handle, 1200 const unsigned char *addr) 1201 { 1202 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1203 1204 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 1205 HCLGE_MBX_MAC_VLAN_UC_ADD, 1206 addr, ETH_ALEN, false, NULL, 0); 1207 } 1208 1209 static int hclgevf_rm_uc_addr(struct hnae3_handle *handle, 1210 const unsigned char *addr) 1211 { 1212 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1213 1214 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 1215 HCLGE_MBX_MAC_VLAN_UC_REMOVE, 1216 addr, ETH_ALEN, false, NULL, 0); 1217 } 1218 1219 static int hclgevf_add_mc_addr(struct hnae3_handle *handle, 1220 const unsigned char *addr) 1221 { 1222 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1223 1224 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 1225 HCLGE_MBX_MAC_VLAN_MC_ADD, 1226 addr, ETH_ALEN, false, NULL, 0); 1227 } 1228 1229 static int hclgevf_rm_mc_addr(struct hnae3_handle *handle, 1230 const unsigned char *addr) 1231 { 1232 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1233 1234 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 1235 HCLGE_MBX_MAC_VLAN_MC_REMOVE, 1236 addr, ETH_ALEN, false, NULL, 0); 1237 } 1238 1239 static int hclgevf_set_vlan_filter(struct hnae3_handle *handle, 1240 __be16 proto, u16 vlan_id, 1241 bool is_kill) 1242 { 1243 #define HCLGEVF_VLAN_MBX_MSG_LEN 5 1244 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1245 u8 msg_data[HCLGEVF_VLAN_MBX_MSG_LEN]; 1246 1247 if (vlan_id > HCLGEVF_MAX_VLAN_ID) 1248 return -EINVAL; 1249 1250 if (proto != htons(ETH_P_8021Q)) 1251 return -EPROTONOSUPPORT; 1252 1253 msg_data[0] = is_kill; 1254 memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id)); 1255 memcpy(&msg_data[3], &proto, sizeof(proto)); 1256 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 1257 HCLGE_MBX_VLAN_FILTER, msg_data, 1258 HCLGEVF_VLAN_MBX_MSG_LEN, false, NULL, 0); 1259 } 1260 1261 static int hclgevf_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) 1262 { 1263 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1264 u8 msg_data; 1265 1266 msg_data = enable ? 1 : 0; 1267 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 1268 HCLGE_MBX_VLAN_RX_OFF_CFG, &msg_data, 1269 1, false, NULL, 0); 1270 } 1271 1272 static int hclgevf_reset_tqp(struct hnae3_handle *handle, u16 queue_id) 1273 { 1274 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1275 u8 msg_data[2]; 1276 int ret; 1277 1278 memcpy(msg_data, &queue_id, sizeof(queue_id)); 1279 1280 /* disable vf queue before send queue reset msg to PF */ 1281 ret = hclgevf_tqp_enable(hdev, queue_id, 0, false); 1282 if (ret) 1283 return ret; 1284 1285 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_QUEUE_RESET, 0, msg_data, 1286 sizeof(msg_data), true, NULL, 0); 1287 } 1288 1289 static int hclgevf_set_mtu(struct hnae3_handle *handle, int new_mtu) 1290 { 1291 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1292 1293 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MTU, 0, (u8 *)&new_mtu, 1294 sizeof(new_mtu), true, NULL, 0); 1295 } 1296 1297 static int hclgevf_notify_client(struct hclgevf_dev *hdev, 1298 enum hnae3_reset_notify_type type) 1299 { 1300 struct hnae3_client *client = hdev->nic_client; 1301 struct hnae3_handle *handle = &hdev->nic; 1302 int ret; 1303 1304 if (!test_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state) || 1305 !client) 1306 return 0; 1307 1308 if (!client->ops->reset_notify) 1309 return -EOPNOTSUPP; 1310 1311 ret = client->ops->reset_notify(handle, type); 1312 if (ret) 1313 dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n", 1314 type, ret); 1315 1316 return ret; 1317 } 1318 1319 static void hclgevf_flr_done(struct hnae3_ae_dev *ae_dev) 1320 { 1321 struct hclgevf_dev *hdev = ae_dev->priv; 1322 1323 set_bit(HNAE3_FLR_DONE, &hdev->flr_state); 1324 } 1325 1326 static int hclgevf_flr_poll_timeout(struct hclgevf_dev *hdev, 1327 unsigned long delay_us, 1328 unsigned long wait_cnt) 1329 { 1330 unsigned long cnt = 0; 1331 1332 while (!test_bit(HNAE3_FLR_DONE, &hdev->flr_state) && 1333 cnt++ < wait_cnt) 1334 usleep_range(delay_us, delay_us * 2); 1335 1336 if (!test_bit(HNAE3_FLR_DONE, &hdev->flr_state)) { 1337 dev_err(&hdev->pdev->dev, 1338 "flr wait timeout\n"); 1339 return -ETIMEDOUT; 1340 } 1341 1342 return 0; 1343 } 1344 1345 static int hclgevf_reset_wait(struct hclgevf_dev *hdev) 1346 { 1347 #define HCLGEVF_RESET_WAIT_US 20000 1348 #define HCLGEVF_RESET_WAIT_CNT 2000 1349 #define HCLGEVF_RESET_WAIT_TIMEOUT_US \ 1350 (HCLGEVF_RESET_WAIT_US * HCLGEVF_RESET_WAIT_CNT) 1351 1352 u32 val; 1353 int ret; 1354 1355 /* wait to check the hardware reset completion status */ 1356 val = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 1357 dev_info(&hdev->pdev->dev, "checking vf resetting status: %x\n", val); 1358 1359 if (hdev->reset_type == HNAE3_FLR_RESET) 1360 return hclgevf_flr_poll_timeout(hdev, 1361 HCLGEVF_RESET_WAIT_US, 1362 HCLGEVF_RESET_WAIT_CNT); 1363 1364 ret = readl_poll_timeout(hdev->hw.io_base + HCLGEVF_RST_ING, val, 1365 !(val & HCLGEVF_RST_ING_BITS), 1366 HCLGEVF_RESET_WAIT_US, 1367 HCLGEVF_RESET_WAIT_TIMEOUT_US); 1368 1369 /* hardware completion status should be available by this time */ 1370 if (ret) { 1371 dev_err(&hdev->pdev->dev, 1372 "could'nt get reset done status from h/w, timeout!\n"); 1373 return ret; 1374 } 1375 1376 /* we will wait a bit more to let reset of the stack to complete. This 1377 * might happen in case reset assertion was made by PF. Yes, this also 1378 * means we might end up waiting bit more even for VF reset. 1379 */ 1380 msleep(5000); 1381 1382 return 0; 1383 } 1384 1385 static int hclgevf_reset_stack(struct hclgevf_dev *hdev) 1386 { 1387 int ret; 1388 1389 /* uninitialize the nic client */ 1390 ret = hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT); 1391 if (ret) 1392 return ret; 1393 1394 /* re-initialize the hclge device */ 1395 ret = hclgevf_reset_hdev(hdev); 1396 if (ret) { 1397 dev_err(&hdev->pdev->dev, 1398 "hclge device re-init failed, VF is disabled!\n"); 1399 return ret; 1400 } 1401 1402 /* bring up the nic client again */ 1403 ret = hclgevf_notify_client(hdev, HNAE3_INIT_CLIENT); 1404 if (ret) 1405 return ret; 1406 1407 return hclgevf_notify_client(hdev, HNAE3_RESTORE_CLIENT); 1408 } 1409 1410 static int hclgevf_reset_prepare_wait(struct hclgevf_dev *hdev) 1411 { 1412 #define HCLGEVF_RESET_SYNC_TIME 100 1413 1414 int ret = 0; 1415 1416 switch (hdev->reset_type) { 1417 case HNAE3_VF_FUNC_RESET: 1418 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_RESET, 0, NULL, 1419 0, true, NULL, sizeof(u8)); 1420 hdev->rst_stats.vf_func_rst_cnt++; 1421 break; 1422 case HNAE3_FLR_RESET: 1423 set_bit(HNAE3_FLR_DOWN, &hdev->flr_state); 1424 hdev->rst_stats.flr_rst_cnt++; 1425 break; 1426 default: 1427 break; 1428 } 1429 1430 set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 1431 /* inform hardware that preparatory work is done */ 1432 msleep(HCLGEVF_RESET_SYNC_TIME); 1433 hclgevf_write_dev(&hdev->hw, HCLGEVF_NIC_CSQ_DEPTH_REG, 1434 HCLGEVF_NIC_CMQ_ENABLE); 1435 dev_info(&hdev->pdev->dev, "prepare reset(%d) wait done, ret:%d\n", 1436 hdev->reset_type, ret); 1437 1438 return ret; 1439 } 1440 1441 static int hclgevf_reset(struct hclgevf_dev *hdev) 1442 { 1443 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1444 int ret; 1445 1446 /* Initialize ae_dev reset status as well, in case enet layer wants to 1447 * know if device is undergoing reset 1448 */ 1449 ae_dev->reset_type = hdev->reset_type; 1450 hdev->rst_stats.rst_cnt++; 1451 rtnl_lock(); 1452 1453 /* bring down the nic to stop any ongoing TX/RX */ 1454 ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 1455 if (ret) 1456 goto err_reset_lock; 1457 1458 rtnl_unlock(); 1459 1460 ret = hclgevf_reset_prepare_wait(hdev); 1461 if (ret) 1462 goto err_reset; 1463 1464 /* check if VF could successfully fetch the hardware reset completion 1465 * status from the hardware 1466 */ 1467 ret = hclgevf_reset_wait(hdev); 1468 if (ret) { 1469 /* can't do much in this situation, will disable VF */ 1470 dev_err(&hdev->pdev->dev, 1471 "VF failed(=%d) to fetch H/W reset completion status\n", 1472 ret); 1473 goto err_reset; 1474 } 1475 1476 hdev->rst_stats.hw_rst_done_cnt++; 1477 1478 rtnl_lock(); 1479 1480 /* now, re-initialize the nic client and ae device*/ 1481 ret = hclgevf_reset_stack(hdev); 1482 if (ret) { 1483 dev_err(&hdev->pdev->dev, "failed to reset VF stack\n"); 1484 goto err_reset_lock; 1485 } 1486 1487 /* bring up the nic to enable TX/RX again */ 1488 ret = hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 1489 if (ret) 1490 goto err_reset_lock; 1491 1492 rtnl_unlock(); 1493 1494 hdev->last_reset_time = jiffies; 1495 ae_dev->reset_type = HNAE3_NONE_RESET; 1496 hdev->rst_stats.rst_done_cnt++; 1497 1498 return ret; 1499 err_reset_lock: 1500 rtnl_unlock(); 1501 err_reset: 1502 /* When VF reset failed, only the higher level reset asserted by PF 1503 * can restore it, so re-initialize the command queue to receive 1504 * this higher reset event. 1505 */ 1506 hclgevf_cmd_init(hdev); 1507 dev_err(&hdev->pdev->dev, "failed to reset VF\n"); 1508 if (hclgevf_is_reset_pending(hdev)) 1509 hclgevf_reset_task_schedule(hdev); 1510 1511 return ret; 1512 } 1513 1514 static enum hnae3_reset_type hclgevf_get_reset_level(struct hclgevf_dev *hdev, 1515 unsigned long *addr) 1516 { 1517 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; 1518 1519 /* return the highest priority reset level amongst all */ 1520 if (test_bit(HNAE3_VF_RESET, addr)) { 1521 rst_level = HNAE3_VF_RESET; 1522 clear_bit(HNAE3_VF_RESET, addr); 1523 clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1524 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1525 } else if (test_bit(HNAE3_VF_FULL_RESET, addr)) { 1526 rst_level = HNAE3_VF_FULL_RESET; 1527 clear_bit(HNAE3_VF_FULL_RESET, addr); 1528 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1529 } else if (test_bit(HNAE3_VF_PF_FUNC_RESET, addr)) { 1530 rst_level = HNAE3_VF_PF_FUNC_RESET; 1531 clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1532 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1533 } else if (test_bit(HNAE3_VF_FUNC_RESET, addr)) { 1534 rst_level = HNAE3_VF_FUNC_RESET; 1535 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1536 } else if (test_bit(HNAE3_FLR_RESET, addr)) { 1537 rst_level = HNAE3_FLR_RESET; 1538 clear_bit(HNAE3_FLR_RESET, addr); 1539 } 1540 1541 return rst_level; 1542 } 1543 1544 static void hclgevf_reset_event(struct pci_dev *pdev, 1545 struct hnae3_handle *handle) 1546 { 1547 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 1548 struct hclgevf_dev *hdev = ae_dev->priv; 1549 1550 dev_info(&hdev->pdev->dev, "received reset request from VF enet\n"); 1551 1552 if (hdev->default_reset_request) 1553 hdev->reset_level = 1554 hclgevf_get_reset_level(hdev, 1555 &hdev->default_reset_request); 1556 else 1557 hdev->reset_level = HNAE3_VF_FUNC_RESET; 1558 1559 /* reset of this VF requested */ 1560 set_bit(HCLGEVF_RESET_REQUESTED, &hdev->reset_state); 1561 hclgevf_reset_task_schedule(hdev); 1562 1563 hdev->last_reset_time = jiffies; 1564 } 1565 1566 static void hclgevf_set_def_reset_request(struct hnae3_ae_dev *ae_dev, 1567 enum hnae3_reset_type rst_type) 1568 { 1569 struct hclgevf_dev *hdev = ae_dev->priv; 1570 1571 set_bit(rst_type, &hdev->default_reset_request); 1572 } 1573 1574 static void hclgevf_flr_prepare(struct hnae3_ae_dev *ae_dev) 1575 { 1576 #define HCLGEVF_FLR_WAIT_MS 100 1577 #define HCLGEVF_FLR_WAIT_CNT 50 1578 struct hclgevf_dev *hdev = ae_dev->priv; 1579 int cnt = 0; 1580 1581 clear_bit(HNAE3_FLR_DOWN, &hdev->flr_state); 1582 clear_bit(HNAE3_FLR_DONE, &hdev->flr_state); 1583 set_bit(HNAE3_FLR_RESET, &hdev->default_reset_request); 1584 hclgevf_reset_event(hdev->pdev, NULL); 1585 1586 while (!test_bit(HNAE3_FLR_DOWN, &hdev->flr_state) && 1587 cnt++ < HCLGEVF_FLR_WAIT_CNT) 1588 msleep(HCLGEVF_FLR_WAIT_MS); 1589 1590 if (!test_bit(HNAE3_FLR_DOWN, &hdev->flr_state)) 1591 dev_err(&hdev->pdev->dev, 1592 "flr wait down timeout: %d\n", cnt); 1593 } 1594 1595 static u32 hclgevf_get_fw_version(struct hnae3_handle *handle) 1596 { 1597 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1598 1599 return hdev->fw_version; 1600 } 1601 1602 static void hclgevf_get_misc_vector(struct hclgevf_dev *hdev) 1603 { 1604 struct hclgevf_misc_vector *vector = &hdev->misc_vector; 1605 1606 vector->vector_irq = pci_irq_vector(hdev->pdev, 1607 HCLGEVF_MISC_VECTOR_NUM); 1608 vector->addr = hdev->hw.io_base + HCLGEVF_MISC_VECTOR_REG_BASE; 1609 /* vector status always valid for Vector 0 */ 1610 hdev->vector_status[HCLGEVF_MISC_VECTOR_NUM] = 0; 1611 hdev->vector_irq[HCLGEVF_MISC_VECTOR_NUM] = vector->vector_irq; 1612 1613 hdev->num_msi_left -= 1; 1614 hdev->num_msi_used += 1; 1615 } 1616 1617 void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev) 1618 { 1619 if (!test_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state) && 1620 !test_bit(HCLGEVF_STATE_REMOVING, &hdev->state)) { 1621 set_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state); 1622 schedule_work(&hdev->rst_service_task); 1623 } 1624 } 1625 1626 void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev) 1627 { 1628 if (!test_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state) && 1629 !test_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) { 1630 set_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 1631 schedule_work(&hdev->mbx_service_task); 1632 } 1633 } 1634 1635 static void hclgevf_task_schedule(struct hclgevf_dev *hdev) 1636 { 1637 if (!test_bit(HCLGEVF_STATE_DOWN, &hdev->state) && 1638 !test_and_set_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state)) 1639 schedule_work(&hdev->service_task); 1640 } 1641 1642 static void hclgevf_deferred_task_schedule(struct hclgevf_dev *hdev) 1643 { 1644 /* if we have any pending mailbox event then schedule the mbx task */ 1645 if (hdev->mbx_event_pending) 1646 hclgevf_mbx_task_schedule(hdev); 1647 1648 if (test_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state)) 1649 hclgevf_reset_task_schedule(hdev); 1650 } 1651 1652 static void hclgevf_service_timer(struct timer_list *t) 1653 { 1654 struct hclgevf_dev *hdev = from_timer(hdev, t, service_timer); 1655 1656 mod_timer(&hdev->service_timer, jiffies + 1657 HCLGEVF_GENERAL_TASK_INTERVAL * HZ); 1658 1659 hdev->stats_timer++; 1660 hclgevf_task_schedule(hdev); 1661 } 1662 1663 static void hclgevf_reset_service_task(struct work_struct *work) 1664 { 1665 struct hclgevf_dev *hdev = 1666 container_of(work, struct hclgevf_dev, rst_service_task); 1667 int ret; 1668 1669 if (test_and_set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 1670 return; 1671 1672 clear_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state); 1673 1674 if (test_and_clear_bit(HCLGEVF_RESET_PENDING, 1675 &hdev->reset_state)) { 1676 /* PF has initmated that it is about to reset the hardware. 1677 * We now have to poll & check if hardware has actually 1678 * completed the reset sequence. On hardware reset completion, 1679 * VF needs to reset the client and ae device. 1680 */ 1681 hdev->reset_attempts = 0; 1682 1683 hdev->last_reset_time = jiffies; 1684 while ((hdev->reset_type = 1685 hclgevf_get_reset_level(hdev, &hdev->reset_pending)) 1686 != HNAE3_NONE_RESET) { 1687 ret = hclgevf_reset(hdev); 1688 if (ret) 1689 dev_err(&hdev->pdev->dev, 1690 "VF stack reset failed %d.\n", ret); 1691 } 1692 } else if (test_and_clear_bit(HCLGEVF_RESET_REQUESTED, 1693 &hdev->reset_state)) { 1694 /* we could be here when either of below happens: 1695 * 1. reset was initiated due to watchdog timeout caused by 1696 * a. IMP was earlier reset and our TX got choked down and 1697 * which resulted in watchdog reacting and inducing VF 1698 * reset. This also means our cmdq would be unreliable. 1699 * b. problem in TX due to other lower layer(example link 1700 * layer not functioning properly etc.) 1701 * 2. VF reset might have been initiated due to some config 1702 * change. 1703 * 1704 * NOTE: Theres no clear way to detect above cases than to react 1705 * to the response of PF for this reset request. PF will ack the 1706 * 1b and 2. cases but we will not get any intimation about 1a 1707 * from PF as cmdq would be in unreliable state i.e. mailbox 1708 * communication between PF and VF would be broken. 1709 */ 1710 1711 /* if we are never geting into pending state it means either: 1712 * 1. PF is not receiving our request which could be due to IMP 1713 * reset 1714 * 2. PF is screwed 1715 * We cannot do much for 2. but to check first we can try reset 1716 * our PCIe + stack and see if it alleviates the problem. 1717 */ 1718 if (hdev->reset_attempts > 3) { 1719 /* prepare for full reset of stack + pcie interface */ 1720 set_bit(HNAE3_VF_FULL_RESET, &hdev->reset_pending); 1721 1722 /* "defer" schedule the reset task again */ 1723 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1724 } else { 1725 hdev->reset_attempts++; 1726 1727 set_bit(hdev->reset_level, &hdev->reset_pending); 1728 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1729 } 1730 hclgevf_reset_task_schedule(hdev); 1731 } 1732 1733 clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 1734 } 1735 1736 static void hclgevf_mailbox_service_task(struct work_struct *work) 1737 { 1738 struct hclgevf_dev *hdev; 1739 1740 hdev = container_of(work, struct hclgevf_dev, mbx_service_task); 1741 1742 if (test_and_set_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) 1743 return; 1744 1745 clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 1746 1747 hclgevf_mbx_async_handler(hdev); 1748 1749 clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 1750 } 1751 1752 static void hclgevf_keep_alive_timer(struct timer_list *t) 1753 { 1754 struct hclgevf_dev *hdev = from_timer(hdev, t, keep_alive_timer); 1755 1756 schedule_work(&hdev->keep_alive_task); 1757 mod_timer(&hdev->keep_alive_timer, jiffies + 1758 HCLGEVF_KEEP_ALIVE_TASK_INTERVAL * HZ); 1759 } 1760 1761 static void hclgevf_keep_alive_task(struct work_struct *work) 1762 { 1763 struct hclgevf_dev *hdev; 1764 u8 respmsg; 1765 int ret; 1766 1767 hdev = container_of(work, struct hclgevf_dev, keep_alive_task); 1768 1769 if (test_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state)) 1770 return; 1771 1772 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_KEEP_ALIVE, 0, NULL, 1773 0, false, &respmsg, sizeof(respmsg)); 1774 if (ret) 1775 dev_err(&hdev->pdev->dev, 1776 "VF sends keep alive cmd failed(=%d)\n", ret); 1777 } 1778 1779 static void hclgevf_service_task(struct work_struct *work) 1780 { 1781 struct hnae3_handle *handle; 1782 struct hclgevf_dev *hdev; 1783 1784 hdev = container_of(work, struct hclgevf_dev, service_task); 1785 handle = &hdev->nic; 1786 1787 if (hdev->stats_timer >= HCLGEVF_STATS_TIMER_INTERVAL) { 1788 hclgevf_tqps_update_stats(handle); 1789 hdev->stats_timer = 0; 1790 } 1791 1792 /* request the link status from the PF. PF would be able to tell VF 1793 * about such updates in future so we might remove this later 1794 */ 1795 hclgevf_request_link_info(hdev); 1796 1797 hclgevf_update_link_mode(hdev); 1798 1799 hclgevf_deferred_task_schedule(hdev); 1800 1801 clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 1802 } 1803 1804 static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regclr) 1805 { 1806 hclgevf_write_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_SRC_REG, regclr); 1807 } 1808 1809 static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev, 1810 u32 *clearval) 1811 { 1812 u32 cmdq_src_reg, rst_ing_reg; 1813 1814 /* fetch the events from their corresponding regs */ 1815 cmdq_src_reg = hclgevf_read_dev(&hdev->hw, 1816 HCLGEVF_VECTOR0_CMDQ_SRC_REG); 1817 1818 if (BIT(HCLGEVF_VECTOR0_RST_INT_B) & cmdq_src_reg) { 1819 rst_ing_reg = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 1820 dev_info(&hdev->pdev->dev, 1821 "receive reset interrupt 0x%x!\n", rst_ing_reg); 1822 set_bit(HNAE3_VF_RESET, &hdev->reset_pending); 1823 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1824 set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 1825 cmdq_src_reg &= ~BIT(HCLGEVF_VECTOR0_RST_INT_B); 1826 *clearval = cmdq_src_reg; 1827 hdev->rst_stats.vf_rst_cnt++; 1828 return HCLGEVF_VECTOR0_EVENT_RST; 1829 } 1830 1831 /* check for vector0 mailbox(=CMDQ RX) event source */ 1832 if (BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) { 1833 cmdq_src_reg &= ~BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 1834 *clearval = cmdq_src_reg; 1835 return HCLGEVF_VECTOR0_EVENT_MBX; 1836 } 1837 1838 dev_dbg(&hdev->pdev->dev, "vector 0 interrupt from unknown source\n"); 1839 1840 return HCLGEVF_VECTOR0_EVENT_OTHER; 1841 } 1842 1843 static void hclgevf_enable_vector(struct hclgevf_misc_vector *vector, bool en) 1844 { 1845 writel(en ? 1 : 0, vector->addr); 1846 } 1847 1848 static irqreturn_t hclgevf_misc_irq_handle(int irq, void *data) 1849 { 1850 enum hclgevf_evt_cause event_cause; 1851 struct hclgevf_dev *hdev = data; 1852 u32 clearval; 1853 1854 hclgevf_enable_vector(&hdev->misc_vector, false); 1855 event_cause = hclgevf_check_evt_cause(hdev, &clearval); 1856 1857 switch (event_cause) { 1858 case HCLGEVF_VECTOR0_EVENT_RST: 1859 hclgevf_reset_task_schedule(hdev); 1860 break; 1861 case HCLGEVF_VECTOR0_EVENT_MBX: 1862 hclgevf_mbx_handler(hdev); 1863 break; 1864 default: 1865 break; 1866 } 1867 1868 if (event_cause != HCLGEVF_VECTOR0_EVENT_OTHER) { 1869 hclgevf_clear_event_cause(hdev, clearval); 1870 hclgevf_enable_vector(&hdev->misc_vector, true); 1871 } 1872 1873 return IRQ_HANDLED; 1874 } 1875 1876 static int hclgevf_configure(struct hclgevf_dev *hdev) 1877 { 1878 int ret; 1879 1880 /* get current port based vlan state from PF */ 1881 ret = hclgevf_get_port_base_vlan_filter_state(hdev); 1882 if (ret) 1883 return ret; 1884 1885 /* get queue configuration from PF */ 1886 ret = hclgevf_get_queue_info(hdev); 1887 if (ret) 1888 return ret; 1889 1890 /* get queue depth info from PF */ 1891 ret = hclgevf_get_queue_depth(hdev); 1892 if (ret) 1893 return ret; 1894 1895 ret = hclgevf_get_pf_media_type(hdev); 1896 if (ret) 1897 return ret; 1898 1899 /* get tc configuration from PF */ 1900 return hclgevf_get_tc_info(hdev); 1901 } 1902 1903 static int hclgevf_alloc_hdev(struct hnae3_ae_dev *ae_dev) 1904 { 1905 struct pci_dev *pdev = ae_dev->pdev; 1906 struct hclgevf_dev *hdev; 1907 1908 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 1909 if (!hdev) 1910 return -ENOMEM; 1911 1912 hdev->pdev = pdev; 1913 hdev->ae_dev = ae_dev; 1914 ae_dev->priv = hdev; 1915 1916 return 0; 1917 } 1918 1919 static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev) 1920 { 1921 struct hnae3_handle *roce = &hdev->roce; 1922 struct hnae3_handle *nic = &hdev->nic; 1923 1924 roce->rinfo.num_vectors = hdev->num_roce_msix; 1925 1926 if (hdev->num_msi_left < roce->rinfo.num_vectors || 1927 hdev->num_msi_left == 0) 1928 return -EINVAL; 1929 1930 roce->rinfo.base_vector = hdev->roce_base_vector; 1931 1932 roce->rinfo.netdev = nic->kinfo.netdev; 1933 roce->rinfo.roce_io_base = hdev->hw.io_base; 1934 1935 roce->pdev = nic->pdev; 1936 roce->ae_algo = nic->ae_algo; 1937 roce->numa_node_mask = nic->numa_node_mask; 1938 1939 return 0; 1940 } 1941 1942 static int hclgevf_config_gro(struct hclgevf_dev *hdev, bool en) 1943 { 1944 struct hclgevf_cfg_gro_status_cmd *req; 1945 struct hclgevf_desc desc; 1946 int ret; 1947 1948 if (!hnae3_dev_gro_supported(hdev)) 1949 return 0; 1950 1951 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_GRO_GENERIC_CONFIG, 1952 false); 1953 req = (struct hclgevf_cfg_gro_status_cmd *)desc.data; 1954 1955 req->gro_en = cpu_to_le16(en ? 1 : 0); 1956 1957 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1958 if (ret) 1959 dev_err(&hdev->pdev->dev, 1960 "VF GRO hardware config cmd failed, ret = %d.\n", ret); 1961 1962 return ret; 1963 } 1964 1965 static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev) 1966 { 1967 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 1968 int i, ret; 1969 1970 rss_cfg->rss_size = hdev->rss_size_max; 1971 1972 if (hdev->pdev->revision >= 0x21) { 1973 rss_cfg->hash_algo = HCLGEVF_RSS_HASH_ALGO_SIMPLE; 1974 memcpy(rss_cfg->rss_hash_key, hclgevf_hash_key, 1975 HCLGEVF_RSS_KEY_SIZE); 1976 1977 ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 1978 rss_cfg->rss_hash_key); 1979 if (ret) 1980 return ret; 1981 1982 rss_cfg->rss_tuple_sets.ipv4_tcp_en = 1983 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1984 rss_cfg->rss_tuple_sets.ipv4_udp_en = 1985 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1986 rss_cfg->rss_tuple_sets.ipv4_sctp_en = 1987 HCLGEVF_RSS_INPUT_TUPLE_SCTP; 1988 rss_cfg->rss_tuple_sets.ipv4_fragment_en = 1989 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1990 rss_cfg->rss_tuple_sets.ipv6_tcp_en = 1991 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1992 rss_cfg->rss_tuple_sets.ipv6_udp_en = 1993 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1994 rss_cfg->rss_tuple_sets.ipv6_sctp_en = 1995 HCLGEVF_RSS_INPUT_TUPLE_SCTP; 1996 rss_cfg->rss_tuple_sets.ipv6_fragment_en = 1997 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 1998 1999 ret = hclgevf_set_rss_input_tuple(hdev, rss_cfg); 2000 if (ret) 2001 return ret; 2002 2003 } 2004 2005 /* Initialize RSS indirect table */ 2006 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 2007 rss_cfg->rss_indirection_tbl[i] = i % hdev->rss_size_max; 2008 2009 ret = hclgevf_set_rss_indir_table(hdev); 2010 if (ret) 2011 return ret; 2012 2013 return hclgevf_set_rss_tc_mode(hdev, hdev->rss_size_max); 2014 } 2015 2016 static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev) 2017 { 2018 return hclgevf_set_vlan_filter(&hdev->nic, htons(ETH_P_8021Q), 0, 2019 false); 2020 } 2021 2022 static void hclgevf_set_timer_task(struct hnae3_handle *handle, bool enable) 2023 { 2024 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2025 2026 if (enable) { 2027 mod_timer(&hdev->service_timer, jiffies + HZ); 2028 } else { 2029 del_timer_sync(&hdev->service_timer); 2030 cancel_work_sync(&hdev->service_task); 2031 clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 2032 } 2033 } 2034 2035 static int hclgevf_ae_start(struct hnae3_handle *handle) 2036 { 2037 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2038 2039 hclgevf_reset_tqp_stats(handle); 2040 2041 hclgevf_request_link_info(hdev); 2042 2043 hclgevf_update_link_mode(hdev); 2044 2045 clear_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2046 2047 return 0; 2048 } 2049 2050 static void hclgevf_ae_stop(struct hnae3_handle *handle) 2051 { 2052 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2053 int i; 2054 2055 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2056 2057 if (hdev->reset_type != HNAE3_VF_RESET) 2058 for (i = 0; i < handle->kinfo.num_tqps; i++) 2059 if (hclgevf_reset_tqp(handle, i)) 2060 break; 2061 2062 hclgevf_reset_tqp_stats(handle); 2063 hclgevf_update_link_status(hdev, 0); 2064 } 2065 2066 static int hclgevf_set_alive(struct hnae3_handle *handle, bool alive) 2067 { 2068 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2069 u8 msg_data; 2070 2071 msg_data = alive ? 1 : 0; 2072 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_ALIVE, 2073 0, &msg_data, 1, false, NULL, 0); 2074 } 2075 2076 static int hclgevf_client_start(struct hnae3_handle *handle) 2077 { 2078 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2079 int ret; 2080 2081 ret = hclgevf_set_alive(handle, true); 2082 if (ret) 2083 return ret; 2084 2085 mod_timer(&hdev->keep_alive_timer, jiffies + 2086 HCLGEVF_KEEP_ALIVE_TASK_INTERVAL * HZ); 2087 2088 return 0; 2089 } 2090 2091 static void hclgevf_client_stop(struct hnae3_handle *handle) 2092 { 2093 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2094 int ret; 2095 2096 ret = hclgevf_set_alive(handle, false); 2097 if (ret) 2098 dev_warn(&hdev->pdev->dev, 2099 "%s failed %d\n", __func__, ret); 2100 2101 del_timer_sync(&hdev->keep_alive_timer); 2102 cancel_work_sync(&hdev->keep_alive_task); 2103 } 2104 2105 static void hclgevf_state_init(struct hclgevf_dev *hdev) 2106 { 2107 /* setup tasks for the MBX */ 2108 INIT_WORK(&hdev->mbx_service_task, hclgevf_mailbox_service_task); 2109 clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 2110 clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 2111 2112 /* setup tasks for service timer */ 2113 timer_setup(&hdev->service_timer, hclgevf_service_timer, 0); 2114 2115 INIT_WORK(&hdev->service_task, hclgevf_service_task); 2116 clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 2117 2118 INIT_WORK(&hdev->rst_service_task, hclgevf_reset_service_task); 2119 2120 mutex_init(&hdev->mbx_resp.mbx_mutex); 2121 2122 /* bring the device down */ 2123 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2124 } 2125 2126 static void hclgevf_state_uninit(struct hclgevf_dev *hdev) 2127 { 2128 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2129 set_bit(HCLGEVF_STATE_REMOVING, &hdev->state); 2130 2131 if (hdev->keep_alive_timer.function) 2132 del_timer_sync(&hdev->keep_alive_timer); 2133 if (hdev->keep_alive_task.func) 2134 cancel_work_sync(&hdev->keep_alive_task); 2135 if (hdev->service_timer.function) 2136 del_timer_sync(&hdev->service_timer); 2137 if (hdev->service_task.func) 2138 cancel_work_sync(&hdev->service_task); 2139 if (hdev->mbx_service_task.func) 2140 cancel_work_sync(&hdev->mbx_service_task); 2141 if (hdev->rst_service_task.func) 2142 cancel_work_sync(&hdev->rst_service_task); 2143 2144 mutex_destroy(&hdev->mbx_resp.mbx_mutex); 2145 } 2146 2147 static int hclgevf_init_msi(struct hclgevf_dev *hdev) 2148 { 2149 struct pci_dev *pdev = hdev->pdev; 2150 int vectors; 2151 int i; 2152 2153 if (hnae3_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B)) 2154 vectors = pci_alloc_irq_vectors(pdev, 2155 hdev->roce_base_msix_offset + 1, 2156 hdev->num_msi, 2157 PCI_IRQ_MSIX); 2158 else 2159 vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi, 2160 PCI_IRQ_MSI | PCI_IRQ_MSIX); 2161 2162 if (vectors < 0) { 2163 dev_err(&pdev->dev, 2164 "failed(%d) to allocate MSI/MSI-X vectors\n", 2165 vectors); 2166 return vectors; 2167 } 2168 if (vectors < hdev->num_msi) 2169 dev_warn(&hdev->pdev->dev, 2170 "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n", 2171 hdev->num_msi, vectors); 2172 2173 hdev->num_msi = vectors; 2174 hdev->num_msi_left = vectors; 2175 hdev->base_msi_vector = pdev->irq; 2176 hdev->roce_base_vector = pdev->irq + hdev->roce_base_msix_offset; 2177 2178 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 2179 sizeof(u16), GFP_KERNEL); 2180 if (!hdev->vector_status) { 2181 pci_free_irq_vectors(pdev); 2182 return -ENOMEM; 2183 } 2184 2185 for (i = 0; i < hdev->num_msi; i++) 2186 hdev->vector_status[i] = HCLGEVF_INVALID_VPORT; 2187 2188 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 2189 sizeof(int), GFP_KERNEL); 2190 if (!hdev->vector_irq) { 2191 devm_kfree(&pdev->dev, hdev->vector_status); 2192 pci_free_irq_vectors(pdev); 2193 return -ENOMEM; 2194 } 2195 2196 return 0; 2197 } 2198 2199 static void hclgevf_uninit_msi(struct hclgevf_dev *hdev) 2200 { 2201 struct pci_dev *pdev = hdev->pdev; 2202 2203 devm_kfree(&pdev->dev, hdev->vector_status); 2204 devm_kfree(&pdev->dev, hdev->vector_irq); 2205 pci_free_irq_vectors(pdev); 2206 } 2207 2208 static int hclgevf_misc_irq_init(struct hclgevf_dev *hdev) 2209 { 2210 int ret = 0; 2211 2212 hclgevf_get_misc_vector(hdev); 2213 2214 ret = request_irq(hdev->misc_vector.vector_irq, hclgevf_misc_irq_handle, 2215 0, "hclgevf_cmd", hdev); 2216 if (ret) { 2217 dev_err(&hdev->pdev->dev, "VF failed to request misc irq(%d)\n", 2218 hdev->misc_vector.vector_irq); 2219 return ret; 2220 } 2221 2222 hclgevf_clear_event_cause(hdev, 0); 2223 2224 /* enable misc. vector(vector 0) */ 2225 hclgevf_enable_vector(&hdev->misc_vector, true); 2226 2227 return ret; 2228 } 2229 2230 static void hclgevf_misc_irq_uninit(struct hclgevf_dev *hdev) 2231 { 2232 /* disable misc vector(vector 0) */ 2233 hclgevf_enable_vector(&hdev->misc_vector, false); 2234 synchronize_irq(hdev->misc_vector.vector_irq); 2235 free_irq(hdev->misc_vector.vector_irq, hdev); 2236 hclgevf_free_vector(hdev, 0); 2237 } 2238 2239 static void hclgevf_info_show(struct hclgevf_dev *hdev) 2240 { 2241 struct device *dev = &hdev->pdev->dev; 2242 2243 dev_info(dev, "VF info begin:\n"); 2244 2245 dev_info(dev, "Task queue pairs numbers: %d\n", hdev->num_tqps); 2246 dev_info(dev, "Desc num per TX queue: %d\n", hdev->num_tx_desc); 2247 dev_info(dev, "Desc num per RX queue: %d\n", hdev->num_rx_desc); 2248 dev_info(dev, "Numbers of vports: %d\n", hdev->num_alloc_vport); 2249 dev_info(dev, "HW tc map: %d\n", hdev->hw_tc_map); 2250 dev_info(dev, "PF media type of this VF: %d\n", 2251 hdev->hw.mac.media_type); 2252 2253 dev_info(dev, "VF info end.\n"); 2254 } 2255 2256 static int hclgevf_init_nic_client_instance(struct hnae3_ae_dev *ae_dev, 2257 struct hnae3_client *client) 2258 { 2259 struct hclgevf_dev *hdev = ae_dev->priv; 2260 int ret; 2261 2262 ret = client->ops->init_instance(&hdev->nic); 2263 if (ret) 2264 return ret; 2265 2266 set_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 2267 hnae3_set_client_init_flag(client, ae_dev, 1); 2268 2269 if (netif_msg_drv(&hdev->nic)) 2270 hclgevf_info_show(hdev); 2271 2272 return 0; 2273 } 2274 2275 static int hclgevf_init_roce_client_instance(struct hnae3_ae_dev *ae_dev, 2276 struct hnae3_client *client) 2277 { 2278 struct hclgevf_dev *hdev = ae_dev->priv; 2279 int ret; 2280 2281 if (!hnae3_dev_roce_supported(hdev) || !hdev->roce_client || 2282 !hdev->nic_client) 2283 return 0; 2284 2285 ret = hclgevf_init_roce_base_info(hdev); 2286 if (ret) 2287 return ret; 2288 2289 ret = client->ops->init_instance(&hdev->roce); 2290 if (ret) 2291 return ret; 2292 2293 hnae3_set_client_init_flag(client, ae_dev, 1); 2294 2295 return 0; 2296 } 2297 2298 static int hclgevf_init_client_instance(struct hnae3_client *client, 2299 struct hnae3_ae_dev *ae_dev) 2300 { 2301 struct hclgevf_dev *hdev = ae_dev->priv; 2302 int ret; 2303 2304 switch (client->type) { 2305 case HNAE3_CLIENT_KNIC: 2306 hdev->nic_client = client; 2307 hdev->nic.client = client; 2308 2309 ret = hclgevf_init_nic_client_instance(ae_dev, client); 2310 if (ret) 2311 goto clear_nic; 2312 2313 ret = hclgevf_init_roce_client_instance(ae_dev, 2314 hdev->roce_client); 2315 if (ret) 2316 goto clear_roce; 2317 2318 break; 2319 case HNAE3_CLIENT_ROCE: 2320 if (hnae3_dev_roce_supported(hdev)) { 2321 hdev->roce_client = client; 2322 hdev->roce.client = client; 2323 } 2324 2325 ret = hclgevf_init_roce_client_instance(ae_dev, client); 2326 if (ret) 2327 goto clear_roce; 2328 2329 break; 2330 default: 2331 return -EINVAL; 2332 } 2333 2334 return 0; 2335 2336 clear_nic: 2337 hdev->nic_client = NULL; 2338 hdev->nic.client = NULL; 2339 return ret; 2340 clear_roce: 2341 hdev->roce_client = NULL; 2342 hdev->roce.client = NULL; 2343 return ret; 2344 } 2345 2346 static void hclgevf_uninit_client_instance(struct hnae3_client *client, 2347 struct hnae3_ae_dev *ae_dev) 2348 { 2349 struct hclgevf_dev *hdev = ae_dev->priv; 2350 2351 /* un-init roce, if it exists */ 2352 if (hdev->roce_client) { 2353 hdev->roce_client->ops->uninit_instance(&hdev->roce, 0); 2354 hdev->roce_client = NULL; 2355 hdev->roce.client = NULL; 2356 } 2357 2358 /* un-init nic/unic, if this was not called by roce client */ 2359 if (client->ops->uninit_instance && hdev->nic_client && 2360 client->type != HNAE3_CLIENT_ROCE) { 2361 clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 2362 2363 client->ops->uninit_instance(&hdev->nic, 0); 2364 hdev->nic_client = NULL; 2365 hdev->nic.client = NULL; 2366 } 2367 } 2368 2369 static int hclgevf_pci_init(struct hclgevf_dev *hdev) 2370 { 2371 struct pci_dev *pdev = hdev->pdev; 2372 struct hclgevf_hw *hw; 2373 int ret; 2374 2375 ret = pci_enable_device(pdev); 2376 if (ret) { 2377 dev_err(&pdev->dev, "failed to enable PCI device\n"); 2378 return ret; 2379 } 2380 2381 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 2382 if (ret) { 2383 dev_err(&pdev->dev, "can't set consistent PCI DMA, exiting"); 2384 goto err_disable_device; 2385 } 2386 2387 ret = pci_request_regions(pdev, HCLGEVF_DRIVER_NAME); 2388 if (ret) { 2389 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 2390 goto err_disable_device; 2391 } 2392 2393 pci_set_master(pdev); 2394 hw = &hdev->hw; 2395 hw->hdev = hdev; 2396 hw->io_base = pci_iomap(pdev, 2, 0); 2397 if (!hw->io_base) { 2398 dev_err(&pdev->dev, "can't map configuration register space\n"); 2399 ret = -ENOMEM; 2400 goto err_clr_master; 2401 } 2402 2403 return 0; 2404 2405 err_clr_master: 2406 pci_clear_master(pdev); 2407 pci_release_regions(pdev); 2408 err_disable_device: 2409 pci_disable_device(pdev); 2410 2411 return ret; 2412 } 2413 2414 static void hclgevf_pci_uninit(struct hclgevf_dev *hdev) 2415 { 2416 struct pci_dev *pdev = hdev->pdev; 2417 2418 pci_iounmap(pdev, hdev->hw.io_base); 2419 pci_clear_master(pdev); 2420 pci_release_regions(pdev); 2421 pci_disable_device(pdev); 2422 } 2423 2424 static int hclgevf_query_vf_resource(struct hclgevf_dev *hdev) 2425 { 2426 struct hclgevf_query_res_cmd *req; 2427 struct hclgevf_desc desc; 2428 int ret; 2429 2430 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_VF_RSRC, true); 2431 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 2432 if (ret) { 2433 dev_err(&hdev->pdev->dev, 2434 "query vf resource failed, ret = %d.\n", ret); 2435 return ret; 2436 } 2437 2438 req = (struct hclgevf_query_res_cmd *)desc.data; 2439 2440 if (hnae3_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B)) { 2441 hdev->roce_base_msix_offset = 2442 hnae3_get_field(__le16_to_cpu(req->msixcap_localid_ba_rocee), 2443 HCLGEVF_MSIX_OFT_ROCEE_M, 2444 HCLGEVF_MSIX_OFT_ROCEE_S); 2445 hdev->num_roce_msix = 2446 hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number), 2447 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 2448 2449 /* VF should have NIC vectors and Roce vectors, NIC vectors 2450 * are queued before Roce vectors. The offset is fixed to 64. 2451 */ 2452 hdev->num_msi = hdev->num_roce_msix + 2453 hdev->roce_base_msix_offset; 2454 } else { 2455 hdev->num_msi = 2456 hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number), 2457 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 2458 } 2459 2460 return 0; 2461 } 2462 2463 static int hclgevf_pci_reset(struct hclgevf_dev *hdev) 2464 { 2465 struct pci_dev *pdev = hdev->pdev; 2466 int ret = 0; 2467 2468 if (hdev->reset_type == HNAE3_VF_FULL_RESET && 2469 test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2470 hclgevf_misc_irq_uninit(hdev); 2471 hclgevf_uninit_msi(hdev); 2472 clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2473 } 2474 2475 if (!test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2476 pci_set_master(pdev); 2477 ret = hclgevf_init_msi(hdev); 2478 if (ret) { 2479 dev_err(&pdev->dev, 2480 "failed(%d) to init MSI/MSI-X\n", ret); 2481 return ret; 2482 } 2483 2484 ret = hclgevf_misc_irq_init(hdev); 2485 if (ret) { 2486 hclgevf_uninit_msi(hdev); 2487 dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 2488 ret); 2489 return ret; 2490 } 2491 2492 set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2493 } 2494 2495 return ret; 2496 } 2497 2498 static int hclgevf_reset_hdev(struct hclgevf_dev *hdev) 2499 { 2500 struct pci_dev *pdev = hdev->pdev; 2501 int ret; 2502 2503 ret = hclgevf_pci_reset(hdev); 2504 if (ret) { 2505 dev_err(&pdev->dev, "pci reset failed %d\n", ret); 2506 return ret; 2507 } 2508 2509 ret = hclgevf_cmd_init(hdev); 2510 if (ret) { 2511 dev_err(&pdev->dev, "cmd failed %d\n", ret); 2512 return ret; 2513 } 2514 2515 ret = hclgevf_rss_init_hw(hdev); 2516 if (ret) { 2517 dev_err(&hdev->pdev->dev, 2518 "failed(%d) to initialize RSS\n", ret); 2519 return ret; 2520 } 2521 2522 ret = hclgevf_config_gro(hdev, true); 2523 if (ret) 2524 return ret; 2525 2526 ret = hclgevf_init_vlan_config(hdev); 2527 if (ret) { 2528 dev_err(&hdev->pdev->dev, 2529 "failed(%d) to initialize VLAN config\n", ret); 2530 return ret; 2531 } 2532 2533 dev_info(&hdev->pdev->dev, "Reset done\n"); 2534 2535 return 0; 2536 } 2537 2538 static int hclgevf_init_hdev(struct hclgevf_dev *hdev) 2539 { 2540 struct pci_dev *pdev = hdev->pdev; 2541 int ret; 2542 2543 ret = hclgevf_pci_init(hdev); 2544 if (ret) { 2545 dev_err(&pdev->dev, "PCI initialization failed\n"); 2546 return ret; 2547 } 2548 2549 ret = hclgevf_cmd_queue_init(hdev); 2550 if (ret) { 2551 dev_err(&pdev->dev, "Cmd queue init failed: %d\n", ret); 2552 goto err_cmd_queue_init; 2553 } 2554 2555 ret = hclgevf_cmd_init(hdev); 2556 if (ret) 2557 goto err_cmd_init; 2558 2559 /* Get vf resource */ 2560 ret = hclgevf_query_vf_resource(hdev); 2561 if (ret) { 2562 dev_err(&hdev->pdev->dev, 2563 "Query vf status error, ret = %d.\n", ret); 2564 goto err_cmd_init; 2565 } 2566 2567 ret = hclgevf_init_msi(hdev); 2568 if (ret) { 2569 dev_err(&pdev->dev, "failed(%d) to init MSI/MSI-X\n", ret); 2570 goto err_cmd_init; 2571 } 2572 2573 hclgevf_state_init(hdev); 2574 hdev->reset_level = HNAE3_VF_FUNC_RESET; 2575 2576 ret = hclgevf_misc_irq_init(hdev); 2577 if (ret) { 2578 dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 2579 ret); 2580 goto err_misc_irq_init; 2581 } 2582 2583 set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2584 2585 ret = hclgevf_configure(hdev); 2586 if (ret) { 2587 dev_err(&pdev->dev, "failed(%d) to fetch configuration\n", ret); 2588 goto err_config; 2589 } 2590 2591 ret = hclgevf_alloc_tqps(hdev); 2592 if (ret) { 2593 dev_err(&pdev->dev, "failed(%d) to allocate TQPs\n", ret); 2594 goto err_config; 2595 } 2596 2597 ret = hclgevf_set_handle_info(hdev); 2598 if (ret) { 2599 dev_err(&pdev->dev, "failed(%d) to set handle info\n", ret); 2600 goto err_config; 2601 } 2602 2603 ret = hclgevf_config_gro(hdev, true); 2604 if (ret) 2605 goto err_config; 2606 2607 /* vf is not allowed to enable unicast/multicast promisc mode. 2608 * For revision 0x20, default to disable broadcast promisc mode, 2609 * firmware makes sure broadcast packets can be accepted. 2610 * For revision 0x21, default to enable broadcast promisc mode. 2611 */ 2612 ret = hclgevf_set_promisc_mode(hdev, true); 2613 if (ret) 2614 goto err_config; 2615 2616 /* Initialize RSS for this VF */ 2617 ret = hclgevf_rss_init_hw(hdev); 2618 if (ret) { 2619 dev_err(&hdev->pdev->dev, 2620 "failed(%d) to initialize RSS\n", ret); 2621 goto err_config; 2622 } 2623 2624 ret = hclgevf_init_vlan_config(hdev); 2625 if (ret) { 2626 dev_err(&hdev->pdev->dev, 2627 "failed(%d) to initialize VLAN config\n", ret); 2628 goto err_config; 2629 } 2630 2631 hdev->last_reset_time = jiffies; 2632 pr_info("finished initializing %s driver\n", HCLGEVF_DRIVER_NAME); 2633 2634 return 0; 2635 2636 err_config: 2637 hclgevf_misc_irq_uninit(hdev); 2638 err_misc_irq_init: 2639 hclgevf_state_uninit(hdev); 2640 hclgevf_uninit_msi(hdev); 2641 err_cmd_init: 2642 hclgevf_cmd_uninit(hdev); 2643 err_cmd_queue_init: 2644 hclgevf_pci_uninit(hdev); 2645 clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2646 return ret; 2647 } 2648 2649 static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev) 2650 { 2651 hclgevf_state_uninit(hdev); 2652 2653 if (test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2654 hclgevf_misc_irq_uninit(hdev); 2655 hclgevf_uninit_msi(hdev); 2656 } 2657 2658 hclgevf_pci_uninit(hdev); 2659 hclgevf_cmd_uninit(hdev); 2660 } 2661 2662 static int hclgevf_init_ae_dev(struct hnae3_ae_dev *ae_dev) 2663 { 2664 struct pci_dev *pdev = ae_dev->pdev; 2665 struct hclgevf_dev *hdev; 2666 int ret; 2667 2668 ret = hclgevf_alloc_hdev(ae_dev); 2669 if (ret) { 2670 dev_err(&pdev->dev, "hclge device allocation failed\n"); 2671 return ret; 2672 } 2673 2674 ret = hclgevf_init_hdev(ae_dev->priv); 2675 if (ret) { 2676 dev_err(&pdev->dev, "hclge device initialization failed\n"); 2677 return ret; 2678 } 2679 2680 hdev = ae_dev->priv; 2681 timer_setup(&hdev->keep_alive_timer, hclgevf_keep_alive_timer, 0); 2682 INIT_WORK(&hdev->keep_alive_task, hclgevf_keep_alive_task); 2683 2684 return 0; 2685 } 2686 2687 static void hclgevf_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 2688 { 2689 struct hclgevf_dev *hdev = ae_dev->priv; 2690 2691 hclgevf_uninit_hdev(hdev); 2692 ae_dev->priv = NULL; 2693 } 2694 2695 static u32 hclgevf_get_max_channels(struct hclgevf_dev *hdev) 2696 { 2697 struct hnae3_handle *nic = &hdev->nic; 2698 struct hnae3_knic_private_info *kinfo = &nic->kinfo; 2699 2700 return min_t(u32, hdev->rss_size_max, 2701 hdev->num_tqps / kinfo->num_tc); 2702 } 2703 2704 /** 2705 * hclgevf_get_channels - Get the current channels enabled and max supported. 2706 * @handle: hardware information for network interface 2707 * @ch: ethtool channels structure 2708 * 2709 * We don't support separate tx and rx queues as channels. The other count 2710 * represents how many queues are being used for control. max_combined counts 2711 * how many queue pairs we can support. They may not be mapped 1 to 1 with 2712 * q_vectors since we support a lot more queue pairs than q_vectors. 2713 **/ 2714 static void hclgevf_get_channels(struct hnae3_handle *handle, 2715 struct ethtool_channels *ch) 2716 { 2717 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2718 2719 ch->max_combined = hclgevf_get_max_channels(hdev); 2720 ch->other_count = 0; 2721 ch->max_other = 0; 2722 ch->combined_count = handle->kinfo.rss_size; 2723 } 2724 2725 static void hclgevf_get_tqps_and_rss_info(struct hnae3_handle *handle, 2726 u16 *alloc_tqps, u16 *max_rss_size) 2727 { 2728 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2729 2730 *alloc_tqps = hdev->num_tqps; 2731 *max_rss_size = hdev->rss_size_max; 2732 } 2733 2734 static int hclgevf_get_status(struct hnae3_handle *handle) 2735 { 2736 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2737 2738 return hdev->hw.mac.link; 2739 } 2740 2741 static void hclgevf_get_ksettings_an_result(struct hnae3_handle *handle, 2742 u8 *auto_neg, u32 *speed, 2743 u8 *duplex) 2744 { 2745 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2746 2747 if (speed) 2748 *speed = hdev->hw.mac.speed; 2749 if (duplex) 2750 *duplex = hdev->hw.mac.duplex; 2751 if (auto_neg) 2752 *auto_neg = AUTONEG_DISABLE; 2753 } 2754 2755 void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed, 2756 u8 duplex) 2757 { 2758 hdev->hw.mac.speed = speed; 2759 hdev->hw.mac.duplex = duplex; 2760 } 2761 2762 static int hclgevf_gro_en(struct hnae3_handle *handle, bool enable) 2763 { 2764 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2765 2766 return hclgevf_config_gro(hdev, enable); 2767 } 2768 2769 static void hclgevf_get_media_type(struct hnae3_handle *handle, u8 *media_type, 2770 u8 *module_type) 2771 { 2772 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2773 2774 if (media_type) 2775 *media_type = hdev->hw.mac.media_type; 2776 2777 if (module_type) 2778 *module_type = hdev->hw.mac.module_type; 2779 } 2780 2781 static bool hclgevf_get_hw_reset_stat(struct hnae3_handle *handle) 2782 { 2783 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2784 2785 return !!hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 2786 } 2787 2788 static bool hclgevf_ae_dev_resetting(struct hnae3_handle *handle) 2789 { 2790 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2791 2792 return test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 2793 } 2794 2795 static unsigned long hclgevf_ae_dev_reset_cnt(struct hnae3_handle *handle) 2796 { 2797 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2798 2799 return hdev->rst_stats.hw_rst_done_cnt; 2800 } 2801 2802 static void hclgevf_get_link_mode(struct hnae3_handle *handle, 2803 unsigned long *supported, 2804 unsigned long *advertising) 2805 { 2806 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2807 2808 *supported = hdev->hw.mac.supported; 2809 *advertising = hdev->hw.mac.advertising; 2810 } 2811 2812 #define MAX_SEPARATE_NUM 4 2813 #define SEPARATOR_VALUE 0xFFFFFFFF 2814 #define REG_NUM_PER_LINE 4 2815 #define REG_LEN_PER_LINE (REG_NUM_PER_LINE * sizeof(u32)) 2816 2817 static int hclgevf_get_regs_len(struct hnae3_handle *handle) 2818 { 2819 int cmdq_lines, common_lines, ring_lines, tqp_intr_lines; 2820 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2821 2822 cmdq_lines = sizeof(cmdq_reg_addr_list) / REG_LEN_PER_LINE + 1; 2823 common_lines = sizeof(common_reg_addr_list) / REG_LEN_PER_LINE + 1; 2824 ring_lines = sizeof(ring_reg_addr_list) / REG_LEN_PER_LINE + 1; 2825 tqp_intr_lines = sizeof(tqp_intr_reg_addr_list) / REG_LEN_PER_LINE + 1; 2826 2827 return (cmdq_lines + common_lines + ring_lines * hdev->num_tqps + 2828 tqp_intr_lines * (hdev->num_msi_used - 1)) * REG_LEN_PER_LINE; 2829 } 2830 2831 static void hclgevf_get_regs(struct hnae3_handle *handle, u32 *version, 2832 void *data) 2833 { 2834 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2835 int i, j, reg_um, separator_num; 2836 u32 *reg = data; 2837 2838 *version = hdev->fw_version; 2839 2840 /* fetching per-VF registers values from VF PCIe register space */ 2841 reg_um = sizeof(cmdq_reg_addr_list) / sizeof(u32); 2842 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 2843 for (i = 0; i < reg_um; i++) 2844 *reg++ = hclgevf_read_dev(&hdev->hw, cmdq_reg_addr_list[i]); 2845 for (i = 0; i < separator_num; i++) 2846 *reg++ = SEPARATOR_VALUE; 2847 2848 reg_um = sizeof(common_reg_addr_list) / sizeof(u32); 2849 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 2850 for (i = 0; i < reg_um; i++) 2851 *reg++ = hclgevf_read_dev(&hdev->hw, common_reg_addr_list[i]); 2852 for (i = 0; i < separator_num; i++) 2853 *reg++ = SEPARATOR_VALUE; 2854 2855 reg_um = sizeof(ring_reg_addr_list) / sizeof(u32); 2856 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 2857 for (j = 0; j < hdev->num_tqps; j++) { 2858 for (i = 0; i < reg_um; i++) 2859 *reg++ = hclgevf_read_dev(&hdev->hw, 2860 ring_reg_addr_list[i] + 2861 0x200 * j); 2862 for (i = 0; i < separator_num; i++) 2863 *reg++ = SEPARATOR_VALUE; 2864 } 2865 2866 reg_um = sizeof(tqp_intr_reg_addr_list) / sizeof(u32); 2867 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 2868 for (j = 0; j < hdev->num_msi_used - 1; j++) { 2869 for (i = 0; i < reg_um; i++) 2870 *reg++ = hclgevf_read_dev(&hdev->hw, 2871 tqp_intr_reg_addr_list[i] + 2872 4 * j); 2873 for (i = 0; i < separator_num; i++) 2874 *reg++ = SEPARATOR_VALUE; 2875 } 2876 } 2877 2878 void hclgevf_update_port_base_vlan_info(struct hclgevf_dev *hdev, u16 state, 2879 u8 *port_base_vlan_info, u8 data_size) 2880 { 2881 struct hnae3_handle *nic = &hdev->nic; 2882 2883 rtnl_lock(); 2884 hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 2885 rtnl_unlock(); 2886 2887 /* send msg to PF and wait update port based vlan info */ 2888 hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 2889 HCLGE_MBX_PORT_BASE_VLAN_CFG, 2890 port_base_vlan_info, data_size, 2891 false, NULL, 0); 2892 2893 if (state == HNAE3_PORT_BASE_VLAN_DISABLE) 2894 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_DISABLE; 2895 else 2896 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_ENABLE; 2897 2898 rtnl_lock(); 2899 hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 2900 rtnl_unlock(); 2901 } 2902 2903 static const struct hnae3_ae_ops hclgevf_ops = { 2904 .init_ae_dev = hclgevf_init_ae_dev, 2905 .uninit_ae_dev = hclgevf_uninit_ae_dev, 2906 .flr_prepare = hclgevf_flr_prepare, 2907 .flr_done = hclgevf_flr_done, 2908 .init_client_instance = hclgevf_init_client_instance, 2909 .uninit_client_instance = hclgevf_uninit_client_instance, 2910 .start = hclgevf_ae_start, 2911 .stop = hclgevf_ae_stop, 2912 .client_start = hclgevf_client_start, 2913 .client_stop = hclgevf_client_stop, 2914 .map_ring_to_vector = hclgevf_map_ring_to_vector, 2915 .unmap_ring_from_vector = hclgevf_unmap_ring_from_vector, 2916 .get_vector = hclgevf_get_vector, 2917 .put_vector = hclgevf_put_vector, 2918 .reset_queue = hclgevf_reset_tqp, 2919 .get_mac_addr = hclgevf_get_mac_addr, 2920 .set_mac_addr = hclgevf_set_mac_addr, 2921 .add_uc_addr = hclgevf_add_uc_addr, 2922 .rm_uc_addr = hclgevf_rm_uc_addr, 2923 .add_mc_addr = hclgevf_add_mc_addr, 2924 .rm_mc_addr = hclgevf_rm_mc_addr, 2925 .get_stats = hclgevf_get_stats, 2926 .update_stats = hclgevf_update_stats, 2927 .get_strings = hclgevf_get_strings, 2928 .get_sset_count = hclgevf_get_sset_count, 2929 .get_rss_key_size = hclgevf_get_rss_key_size, 2930 .get_rss_indir_size = hclgevf_get_rss_indir_size, 2931 .get_rss = hclgevf_get_rss, 2932 .set_rss = hclgevf_set_rss, 2933 .get_rss_tuple = hclgevf_get_rss_tuple, 2934 .set_rss_tuple = hclgevf_set_rss_tuple, 2935 .get_tc_size = hclgevf_get_tc_size, 2936 .get_fw_version = hclgevf_get_fw_version, 2937 .set_vlan_filter = hclgevf_set_vlan_filter, 2938 .enable_hw_strip_rxvtag = hclgevf_en_hw_strip_rxvtag, 2939 .reset_event = hclgevf_reset_event, 2940 .set_default_reset_request = hclgevf_set_def_reset_request, 2941 .get_channels = hclgevf_get_channels, 2942 .get_tqps_and_rss_info = hclgevf_get_tqps_and_rss_info, 2943 .get_regs_len = hclgevf_get_regs_len, 2944 .get_regs = hclgevf_get_regs, 2945 .get_status = hclgevf_get_status, 2946 .get_ksettings_an_result = hclgevf_get_ksettings_an_result, 2947 .get_media_type = hclgevf_get_media_type, 2948 .get_hw_reset_stat = hclgevf_get_hw_reset_stat, 2949 .ae_dev_resetting = hclgevf_ae_dev_resetting, 2950 .ae_dev_reset_cnt = hclgevf_ae_dev_reset_cnt, 2951 .set_gro_en = hclgevf_gro_en, 2952 .set_mtu = hclgevf_set_mtu, 2953 .get_global_queue_id = hclgevf_get_qid_global, 2954 .set_timer_task = hclgevf_set_timer_task, 2955 .get_link_mode = hclgevf_get_link_mode, 2956 }; 2957 2958 static struct hnae3_ae_algo ae_algovf = { 2959 .ops = &hclgevf_ops, 2960 .pdev_id_table = ae_algovf_pci_tbl, 2961 }; 2962 2963 static int hclgevf_init(void) 2964 { 2965 pr_info("%s is initializing\n", HCLGEVF_NAME); 2966 2967 hnae3_register_ae_algo(&ae_algovf); 2968 2969 return 0; 2970 } 2971 2972 static void hclgevf_exit(void) 2973 { 2974 hnae3_unregister_ae_algo(&ae_algovf); 2975 } 2976 module_init(hclgevf_init); 2977 module_exit(hclgevf_exit); 2978 2979 MODULE_LICENSE("GPL"); 2980 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 2981 MODULE_DESCRIPTION("HCLGEVF Driver"); 2982 MODULE_VERSION(HCLGEVF_MOD_VERSION); 2983