1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/etherdevice.h> 5 #include <linux/iopoll.h> 6 #include <net/rtnetlink.h> 7 #include "hclgevf_cmd.h" 8 #include "hclgevf_main.h" 9 #include "hclge_mbx.h" 10 #include "hnae3.h" 11 #include "hclgevf_devlink.h" 12 #include "hclge_comm_rss.h" 13 14 #define HCLGEVF_NAME "hclgevf" 15 16 #define HCLGEVF_RESET_MAX_FAIL_CNT 5 17 18 static int hclgevf_reset_hdev(struct hclgevf_dev *hdev); 19 static void hclgevf_task_schedule(struct hclgevf_dev *hdev, 20 unsigned long delay); 21 22 static struct hnae3_ae_algo ae_algovf; 23 24 static struct workqueue_struct *hclgevf_wq; 25 26 static const struct pci_device_id ae_algovf_pci_tbl[] = { 27 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_VF), 0}, 28 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF), 29 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 30 /* required last entry */ 31 {0, } 32 }; 33 34 MODULE_DEVICE_TABLE(pci, ae_algovf_pci_tbl); 35 36 static const u32 cmdq_reg_addr_list[] = {HCLGE_COMM_NIC_CSQ_BASEADDR_L_REG, 37 HCLGE_COMM_NIC_CSQ_BASEADDR_H_REG, 38 HCLGE_COMM_NIC_CSQ_DEPTH_REG, 39 HCLGE_COMM_NIC_CSQ_TAIL_REG, 40 HCLGE_COMM_NIC_CSQ_HEAD_REG, 41 HCLGE_COMM_NIC_CRQ_BASEADDR_L_REG, 42 HCLGE_COMM_NIC_CRQ_BASEADDR_H_REG, 43 HCLGE_COMM_NIC_CRQ_DEPTH_REG, 44 HCLGE_COMM_NIC_CRQ_TAIL_REG, 45 HCLGE_COMM_NIC_CRQ_HEAD_REG, 46 HCLGE_COMM_VECTOR0_CMDQ_SRC_REG, 47 HCLGE_COMM_VECTOR0_CMDQ_STATE_REG, 48 HCLGE_COMM_CMDQ_INTR_EN_REG, 49 HCLGE_COMM_CMDQ_INTR_GEN_REG}; 50 51 static const u32 common_reg_addr_list[] = {HCLGEVF_MISC_VECTOR_REG_BASE, 52 HCLGEVF_RST_ING, 53 HCLGEVF_GRO_EN_REG}; 54 55 static const u32 ring_reg_addr_list[] = {HCLGEVF_RING_RX_ADDR_L_REG, 56 HCLGEVF_RING_RX_ADDR_H_REG, 57 HCLGEVF_RING_RX_BD_NUM_REG, 58 HCLGEVF_RING_RX_BD_LENGTH_REG, 59 HCLGEVF_RING_RX_MERGE_EN_REG, 60 HCLGEVF_RING_RX_TAIL_REG, 61 HCLGEVF_RING_RX_HEAD_REG, 62 HCLGEVF_RING_RX_FBD_NUM_REG, 63 HCLGEVF_RING_RX_OFFSET_REG, 64 HCLGEVF_RING_RX_FBD_OFFSET_REG, 65 HCLGEVF_RING_RX_STASH_REG, 66 HCLGEVF_RING_RX_BD_ERR_REG, 67 HCLGEVF_RING_TX_ADDR_L_REG, 68 HCLGEVF_RING_TX_ADDR_H_REG, 69 HCLGEVF_RING_TX_BD_NUM_REG, 70 HCLGEVF_RING_TX_PRIORITY_REG, 71 HCLGEVF_RING_TX_TC_REG, 72 HCLGEVF_RING_TX_MERGE_EN_REG, 73 HCLGEVF_RING_TX_TAIL_REG, 74 HCLGEVF_RING_TX_HEAD_REG, 75 HCLGEVF_RING_TX_FBD_NUM_REG, 76 HCLGEVF_RING_TX_OFFSET_REG, 77 HCLGEVF_RING_TX_EBD_NUM_REG, 78 HCLGEVF_RING_TX_EBD_OFFSET_REG, 79 HCLGEVF_RING_TX_BD_ERR_REG, 80 HCLGEVF_RING_EN_REG}; 81 82 static const u32 tqp_intr_reg_addr_list[] = {HCLGEVF_TQP_INTR_CTRL_REG, 83 HCLGEVF_TQP_INTR_GL0_REG, 84 HCLGEVF_TQP_INTR_GL1_REG, 85 HCLGEVF_TQP_INTR_GL2_REG, 86 HCLGEVF_TQP_INTR_RL_REG}; 87 88 /* hclgevf_cmd_send - send command to command queue 89 * @hw: pointer to the hw struct 90 * @desc: prefilled descriptor for describing the command 91 * @num : the number of descriptors to be sent 92 * 93 * This is the main send command for command queue, it 94 * sends the queue, cleans the queue, etc 95 */ 96 int hclgevf_cmd_send(struct hclgevf_hw *hw, struct hclge_desc *desc, int num) 97 { 98 return hclge_comm_cmd_send(&hw->hw, desc, num); 99 } 100 101 void hclgevf_arq_init(struct hclgevf_dev *hdev) 102 { 103 struct hclge_comm_cmq *cmdq = &hdev->hw.hw.cmq; 104 105 spin_lock(&cmdq->crq.lock); 106 /* initialize the pointers of async rx queue of mailbox */ 107 hdev->arq.hdev = hdev; 108 hdev->arq.head = 0; 109 hdev->arq.tail = 0; 110 atomic_set(&hdev->arq.count, 0); 111 spin_unlock(&cmdq->crq.lock); 112 } 113 114 static struct hclgevf_dev *hclgevf_ae_get_hdev(struct hnae3_handle *handle) 115 { 116 if (!handle->client) 117 return container_of(handle, struct hclgevf_dev, nic); 118 else if (handle->client->type == HNAE3_CLIENT_ROCE) 119 return container_of(handle, struct hclgevf_dev, roce); 120 else 121 return container_of(handle, struct hclgevf_dev, nic); 122 } 123 124 static int hclgevf_tqps_update_stats(struct hnae3_handle *handle) 125 { 126 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 127 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 128 struct hclge_desc desc; 129 struct hclgevf_tqp *tqp; 130 int status; 131 int i; 132 133 for (i = 0; i < kinfo->num_tqps; i++) { 134 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 135 hclgevf_cmd_setup_basic_desc(&desc, 136 HCLGEVF_OPC_QUERY_RX_STATUS, 137 true); 138 139 desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 140 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 141 if (status) { 142 dev_err(&hdev->pdev->dev, 143 "Query tqp stat fail, status = %d,queue = %d\n", 144 status, i); 145 return status; 146 } 147 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd += 148 le32_to_cpu(desc.data[1]); 149 150 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_TX_STATUS, 151 true); 152 153 desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 154 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 155 if (status) { 156 dev_err(&hdev->pdev->dev, 157 "Query tqp stat fail, status = %d,queue = %d\n", 158 status, i); 159 return status; 160 } 161 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd += 162 le32_to_cpu(desc.data[1]); 163 } 164 165 return 0; 166 } 167 168 static u64 *hclgevf_tqps_get_stats(struct hnae3_handle *handle, u64 *data) 169 { 170 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 171 struct hclgevf_tqp *tqp; 172 u64 *buff = data; 173 int i; 174 175 for (i = 0; i < kinfo->num_tqps; i++) { 176 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 177 *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd; 178 } 179 for (i = 0; i < kinfo->num_tqps; i++) { 180 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 181 *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd; 182 } 183 184 return buff; 185 } 186 187 static int hclgevf_tqps_get_sset_count(struct hnae3_handle *handle, int strset) 188 { 189 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 190 191 return kinfo->num_tqps * 2; 192 } 193 194 static u8 *hclgevf_tqps_get_strings(struct hnae3_handle *handle, u8 *data) 195 { 196 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 197 u8 *buff = data; 198 int i; 199 200 for (i = 0; i < kinfo->num_tqps; i++) { 201 struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 202 struct hclgevf_tqp, q); 203 snprintf(buff, ETH_GSTRING_LEN, "txq%u_pktnum_rcd", 204 tqp->index); 205 buff += ETH_GSTRING_LEN; 206 } 207 208 for (i = 0; i < kinfo->num_tqps; i++) { 209 struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 210 struct hclgevf_tqp, q); 211 snprintf(buff, ETH_GSTRING_LEN, "rxq%u_pktnum_rcd", 212 tqp->index); 213 buff += ETH_GSTRING_LEN; 214 } 215 216 return buff; 217 } 218 219 static void hclgevf_update_stats(struct hnae3_handle *handle, 220 struct net_device_stats *net_stats) 221 { 222 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 223 int status; 224 225 status = hclgevf_tqps_update_stats(handle); 226 if (status) 227 dev_err(&hdev->pdev->dev, 228 "VF update of TQPS stats fail, status = %d.\n", 229 status); 230 } 231 232 static int hclgevf_get_sset_count(struct hnae3_handle *handle, int strset) 233 { 234 if (strset == ETH_SS_TEST) 235 return -EOPNOTSUPP; 236 else if (strset == ETH_SS_STATS) 237 return hclgevf_tqps_get_sset_count(handle, strset); 238 239 return 0; 240 } 241 242 static void hclgevf_get_strings(struct hnae3_handle *handle, u32 strset, 243 u8 *data) 244 { 245 u8 *p = (char *)data; 246 247 if (strset == ETH_SS_STATS) 248 p = hclgevf_tqps_get_strings(handle, p); 249 } 250 251 static void hclgevf_get_stats(struct hnae3_handle *handle, u64 *data) 252 { 253 hclgevf_tqps_get_stats(handle, data); 254 } 255 256 static void hclgevf_build_send_msg(struct hclge_vf_to_pf_msg *msg, u8 code, 257 u8 subcode) 258 { 259 if (msg) { 260 memset(msg, 0, sizeof(struct hclge_vf_to_pf_msg)); 261 msg->code = code; 262 msg->subcode = subcode; 263 } 264 } 265 266 static int hclgevf_get_basic_info(struct hclgevf_dev *hdev) 267 { 268 struct hnae3_ae_dev *ae_dev = hdev->ae_dev; 269 u8 resp_msg[HCLGE_MBX_MAX_RESP_DATA_SIZE]; 270 struct hclge_basic_info *basic_info; 271 struct hclge_vf_to_pf_msg send_msg; 272 unsigned long caps; 273 int status; 274 275 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_BASIC_INFO, 0); 276 status = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 277 sizeof(resp_msg)); 278 if (status) { 279 dev_err(&hdev->pdev->dev, 280 "failed to get basic info from pf, ret = %d", status); 281 return status; 282 } 283 284 basic_info = (struct hclge_basic_info *)resp_msg; 285 286 hdev->hw_tc_map = basic_info->hw_tc_map; 287 hdev->mbx_api_version = basic_info->mbx_api_version; 288 caps = basic_info->pf_caps; 289 if (test_bit(HNAE3_PF_SUPPORT_VLAN_FLTR_MDF_B, &caps)) 290 set_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps); 291 292 return 0; 293 } 294 295 static int hclgevf_get_port_base_vlan_filter_state(struct hclgevf_dev *hdev) 296 { 297 struct hnae3_handle *nic = &hdev->nic; 298 struct hclge_vf_to_pf_msg send_msg; 299 u8 resp_msg; 300 int ret; 301 302 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 303 HCLGE_MBX_GET_PORT_BASE_VLAN_STATE); 304 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, &resp_msg, 305 sizeof(u8)); 306 if (ret) { 307 dev_err(&hdev->pdev->dev, 308 "VF request to get port based vlan state failed %d", 309 ret); 310 return ret; 311 } 312 313 nic->port_base_vlan_state = resp_msg; 314 315 return 0; 316 } 317 318 static int hclgevf_get_queue_info(struct hclgevf_dev *hdev) 319 { 320 #define HCLGEVF_TQPS_RSS_INFO_LEN 6 321 #define HCLGEVF_TQPS_ALLOC_OFFSET 0 322 #define HCLGEVF_TQPS_RSS_SIZE_OFFSET 2 323 #define HCLGEVF_TQPS_RX_BUFFER_LEN_OFFSET 4 324 325 u8 resp_msg[HCLGEVF_TQPS_RSS_INFO_LEN]; 326 struct hclge_vf_to_pf_msg send_msg; 327 int status; 328 329 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QINFO, 0); 330 status = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 331 HCLGEVF_TQPS_RSS_INFO_LEN); 332 if (status) { 333 dev_err(&hdev->pdev->dev, 334 "VF request to get tqp info from PF failed %d", 335 status); 336 return status; 337 } 338 339 memcpy(&hdev->num_tqps, &resp_msg[HCLGEVF_TQPS_ALLOC_OFFSET], 340 sizeof(u16)); 341 memcpy(&hdev->rss_size_max, &resp_msg[HCLGEVF_TQPS_RSS_SIZE_OFFSET], 342 sizeof(u16)); 343 memcpy(&hdev->rx_buf_len, &resp_msg[HCLGEVF_TQPS_RX_BUFFER_LEN_OFFSET], 344 sizeof(u16)); 345 346 return 0; 347 } 348 349 static int hclgevf_get_queue_depth(struct hclgevf_dev *hdev) 350 { 351 #define HCLGEVF_TQPS_DEPTH_INFO_LEN 4 352 #define HCLGEVF_TQPS_NUM_TX_DESC_OFFSET 0 353 #define HCLGEVF_TQPS_NUM_RX_DESC_OFFSET 2 354 355 u8 resp_msg[HCLGEVF_TQPS_DEPTH_INFO_LEN]; 356 struct hclge_vf_to_pf_msg send_msg; 357 int ret; 358 359 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QDEPTH, 0); 360 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 361 HCLGEVF_TQPS_DEPTH_INFO_LEN); 362 if (ret) { 363 dev_err(&hdev->pdev->dev, 364 "VF request to get tqp depth info from PF failed %d", 365 ret); 366 return ret; 367 } 368 369 memcpy(&hdev->num_tx_desc, &resp_msg[HCLGEVF_TQPS_NUM_TX_DESC_OFFSET], 370 sizeof(u16)); 371 memcpy(&hdev->num_rx_desc, &resp_msg[HCLGEVF_TQPS_NUM_RX_DESC_OFFSET], 372 sizeof(u16)); 373 374 return 0; 375 } 376 377 static u16 hclgevf_get_qid_global(struct hnae3_handle *handle, u16 queue_id) 378 { 379 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 380 struct hclge_vf_to_pf_msg send_msg; 381 u16 qid_in_pf = 0; 382 u8 resp_data[2]; 383 int ret; 384 385 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QID_IN_PF, 0); 386 memcpy(send_msg.data, &queue_id, sizeof(queue_id)); 387 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_data, 388 sizeof(resp_data)); 389 if (!ret) 390 qid_in_pf = *(u16 *)resp_data; 391 392 return qid_in_pf; 393 } 394 395 static int hclgevf_get_pf_media_type(struct hclgevf_dev *hdev) 396 { 397 struct hclge_vf_to_pf_msg send_msg; 398 u8 resp_msg[2]; 399 int ret; 400 401 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_MEDIA_TYPE, 0); 402 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 403 sizeof(resp_msg)); 404 if (ret) { 405 dev_err(&hdev->pdev->dev, 406 "VF request to get the pf port media type failed %d", 407 ret); 408 return ret; 409 } 410 411 hdev->hw.mac.media_type = resp_msg[0]; 412 hdev->hw.mac.module_type = resp_msg[1]; 413 414 return 0; 415 } 416 417 static int hclgevf_alloc_tqps(struct hclgevf_dev *hdev) 418 { 419 struct hclgevf_tqp *tqp; 420 int i; 421 422 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 423 sizeof(struct hclgevf_tqp), GFP_KERNEL); 424 if (!hdev->htqp) 425 return -ENOMEM; 426 427 tqp = hdev->htqp; 428 429 for (i = 0; i < hdev->num_tqps; i++) { 430 tqp->dev = &hdev->pdev->dev; 431 tqp->index = i; 432 433 tqp->q.ae_algo = &ae_algovf; 434 tqp->q.buf_size = hdev->rx_buf_len; 435 tqp->q.tx_desc_num = hdev->num_tx_desc; 436 tqp->q.rx_desc_num = hdev->num_rx_desc; 437 438 /* need an extended offset to configure queues >= 439 * HCLGEVF_TQP_MAX_SIZE_DEV_V2. 440 */ 441 if (i < HCLGEVF_TQP_MAX_SIZE_DEV_V2) 442 tqp->q.io_base = hdev->hw.hw.io_base + 443 HCLGEVF_TQP_REG_OFFSET + 444 i * HCLGEVF_TQP_REG_SIZE; 445 else 446 tqp->q.io_base = hdev->hw.hw.io_base + 447 HCLGEVF_TQP_REG_OFFSET + 448 HCLGEVF_TQP_EXT_REG_OFFSET + 449 (i - HCLGEVF_TQP_MAX_SIZE_DEV_V2) * 450 HCLGEVF_TQP_REG_SIZE; 451 452 tqp++; 453 } 454 455 return 0; 456 } 457 458 static int hclgevf_knic_setup(struct hclgevf_dev *hdev) 459 { 460 struct hnae3_handle *nic = &hdev->nic; 461 struct hnae3_knic_private_info *kinfo; 462 u16 new_tqps = hdev->num_tqps; 463 unsigned int i; 464 u8 num_tc = 0; 465 466 kinfo = &nic->kinfo; 467 kinfo->num_tx_desc = hdev->num_tx_desc; 468 kinfo->num_rx_desc = hdev->num_rx_desc; 469 kinfo->rx_buf_len = hdev->rx_buf_len; 470 for (i = 0; i < HCLGE_COMM_MAX_TC_NUM; i++) 471 if (hdev->hw_tc_map & BIT(i)) 472 num_tc++; 473 474 num_tc = num_tc ? num_tc : 1; 475 kinfo->tc_info.num_tc = num_tc; 476 kinfo->rss_size = min_t(u16, hdev->rss_size_max, new_tqps / num_tc); 477 new_tqps = kinfo->rss_size * num_tc; 478 kinfo->num_tqps = min(new_tqps, hdev->num_tqps); 479 480 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps, 481 sizeof(struct hnae3_queue *), GFP_KERNEL); 482 if (!kinfo->tqp) 483 return -ENOMEM; 484 485 for (i = 0; i < kinfo->num_tqps; i++) { 486 hdev->htqp[i].q.handle = &hdev->nic; 487 hdev->htqp[i].q.tqp_index = i; 488 kinfo->tqp[i] = &hdev->htqp[i].q; 489 } 490 491 /* after init the max rss_size and tqps, adjust the default tqp numbers 492 * and rss size with the actual vector numbers 493 */ 494 kinfo->num_tqps = min_t(u16, hdev->num_nic_msix - 1, kinfo->num_tqps); 495 kinfo->rss_size = min_t(u16, kinfo->num_tqps / num_tc, 496 kinfo->rss_size); 497 498 return 0; 499 } 500 501 static void hclgevf_request_link_info(struct hclgevf_dev *hdev) 502 { 503 struct hclge_vf_to_pf_msg send_msg; 504 int status; 505 506 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_LINK_STATUS, 0); 507 status = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 508 if (status) 509 dev_err(&hdev->pdev->dev, 510 "VF failed to fetch link status(%d) from PF", status); 511 } 512 513 void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state) 514 { 515 struct hnae3_handle *rhandle = &hdev->roce; 516 struct hnae3_handle *handle = &hdev->nic; 517 struct hnae3_client *rclient; 518 struct hnae3_client *client; 519 520 if (test_and_set_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state)) 521 return; 522 523 client = handle->client; 524 rclient = hdev->roce_client; 525 526 link_state = 527 test_bit(HCLGEVF_STATE_DOWN, &hdev->state) ? 0 : link_state; 528 if (link_state != hdev->hw.mac.link) { 529 hdev->hw.mac.link = link_state; 530 client->ops->link_status_change(handle, !!link_state); 531 if (rclient && rclient->ops->link_status_change) 532 rclient->ops->link_status_change(rhandle, !!link_state); 533 } 534 535 clear_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state); 536 } 537 538 static void hclgevf_update_link_mode(struct hclgevf_dev *hdev) 539 { 540 #define HCLGEVF_ADVERTISING 0 541 #define HCLGEVF_SUPPORTED 1 542 543 struct hclge_vf_to_pf_msg send_msg; 544 545 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_LINK_MODE, 0); 546 send_msg.data[0] = HCLGEVF_ADVERTISING; 547 hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 548 send_msg.data[0] = HCLGEVF_SUPPORTED; 549 hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 550 } 551 552 static int hclgevf_set_handle_info(struct hclgevf_dev *hdev) 553 { 554 struct hnae3_handle *nic = &hdev->nic; 555 int ret; 556 557 nic->ae_algo = &ae_algovf; 558 nic->pdev = hdev->pdev; 559 nic->numa_node_mask = hdev->numa_node_mask; 560 nic->flags |= HNAE3_SUPPORT_VF; 561 nic->kinfo.io_base = hdev->hw.hw.io_base; 562 563 ret = hclgevf_knic_setup(hdev); 564 if (ret) 565 dev_err(&hdev->pdev->dev, "VF knic setup failed %d\n", 566 ret); 567 return ret; 568 } 569 570 static void hclgevf_free_vector(struct hclgevf_dev *hdev, int vector_id) 571 { 572 if (hdev->vector_status[vector_id] == HCLGEVF_INVALID_VPORT) { 573 dev_warn(&hdev->pdev->dev, 574 "vector(vector_id %d) has been freed.\n", vector_id); 575 return; 576 } 577 578 hdev->vector_status[vector_id] = HCLGEVF_INVALID_VPORT; 579 hdev->num_msi_left += 1; 580 hdev->num_msi_used -= 1; 581 } 582 583 static int hclgevf_get_vector(struct hnae3_handle *handle, u16 vector_num, 584 struct hnae3_vector_info *vector_info) 585 { 586 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 587 struct hnae3_vector_info *vector = vector_info; 588 int alloc = 0; 589 int i, j; 590 591 vector_num = min_t(u16, hdev->num_nic_msix - 1, vector_num); 592 vector_num = min(hdev->num_msi_left, vector_num); 593 594 for (j = 0; j < vector_num; j++) { 595 for (i = HCLGEVF_MISC_VECTOR_NUM + 1; i < hdev->num_msi; i++) { 596 if (hdev->vector_status[i] == HCLGEVF_INVALID_VPORT) { 597 vector->vector = pci_irq_vector(hdev->pdev, i); 598 vector->io_addr = hdev->hw.hw.io_base + 599 HCLGEVF_VECTOR_REG_BASE + 600 (i - 1) * HCLGEVF_VECTOR_REG_OFFSET; 601 hdev->vector_status[i] = 0; 602 hdev->vector_irq[i] = vector->vector; 603 604 vector++; 605 alloc++; 606 607 break; 608 } 609 } 610 } 611 hdev->num_msi_left -= alloc; 612 hdev->num_msi_used += alloc; 613 614 return alloc; 615 } 616 617 static int hclgevf_get_vector_index(struct hclgevf_dev *hdev, int vector) 618 { 619 int i; 620 621 for (i = 0; i < hdev->num_msi; i++) 622 if (vector == hdev->vector_irq[i]) 623 return i; 624 625 return -EINVAL; 626 } 627 628 /* for revision 0x20, vf shared the same rss config with pf */ 629 static int hclgevf_get_rss_hash_key(struct hclgevf_dev *hdev) 630 { 631 #define HCLGEVF_RSS_MBX_RESP_LEN 8 632 struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg; 633 u8 resp_msg[HCLGEVF_RSS_MBX_RESP_LEN]; 634 struct hclge_vf_to_pf_msg send_msg; 635 u16 msg_num, hash_key_index; 636 u8 index; 637 int ret; 638 639 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_RSS_KEY, 0); 640 msg_num = (HCLGE_COMM_RSS_KEY_SIZE + HCLGEVF_RSS_MBX_RESP_LEN - 1) / 641 HCLGEVF_RSS_MBX_RESP_LEN; 642 for (index = 0; index < msg_num; index++) { 643 send_msg.data[0] = index; 644 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 645 HCLGEVF_RSS_MBX_RESP_LEN); 646 if (ret) { 647 dev_err(&hdev->pdev->dev, 648 "VF get rss hash key from PF failed, ret=%d", 649 ret); 650 return ret; 651 } 652 653 hash_key_index = HCLGEVF_RSS_MBX_RESP_LEN * index; 654 if (index == msg_num - 1) 655 memcpy(&rss_cfg->rss_hash_key[hash_key_index], 656 &resp_msg[0], 657 HCLGE_COMM_RSS_KEY_SIZE - hash_key_index); 658 else 659 memcpy(&rss_cfg->rss_hash_key[hash_key_index], 660 &resp_msg[0], HCLGEVF_RSS_MBX_RESP_LEN); 661 } 662 663 return 0; 664 } 665 666 static int hclgevf_get_rss(struct hnae3_handle *handle, u32 *indir, u8 *key, 667 u8 *hfunc) 668 { 669 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 670 struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg; 671 int ret; 672 673 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 674 hclge_comm_get_rss_hash_info(rss_cfg, key, hfunc); 675 } else { 676 if (hfunc) 677 *hfunc = ETH_RSS_HASH_TOP; 678 if (key) { 679 ret = hclgevf_get_rss_hash_key(hdev); 680 if (ret) 681 return ret; 682 memcpy(key, rss_cfg->rss_hash_key, 683 HCLGE_COMM_RSS_KEY_SIZE); 684 } 685 } 686 687 hclge_comm_get_rss_indir_tbl(rss_cfg, indir, 688 hdev->ae_dev->dev_specs.rss_ind_tbl_size); 689 690 return 0; 691 } 692 693 static int hclgevf_set_rss(struct hnae3_handle *handle, const u32 *indir, 694 const u8 *key, const u8 hfunc) 695 { 696 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 697 struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg; 698 int ret, i; 699 700 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 701 ret = hclge_comm_set_rss_hash_key(rss_cfg, &hdev->hw.hw, key, 702 hfunc); 703 if (ret) 704 return ret; 705 } 706 707 /* update the shadow RSS table with user specified qids */ 708 for (i = 0; i < hdev->ae_dev->dev_specs.rss_ind_tbl_size; i++) 709 rss_cfg->rss_indirection_tbl[i] = indir[i]; 710 711 /* update the hardware */ 712 return hclge_comm_set_rss_indir_table(hdev->ae_dev, &hdev->hw.hw, 713 rss_cfg->rss_indirection_tbl); 714 } 715 716 static int hclgevf_set_rss_tuple(struct hnae3_handle *handle, 717 struct ethtool_rxnfc *nfc) 718 { 719 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 720 int ret; 721 722 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 723 return -EOPNOTSUPP; 724 725 ret = hclge_comm_set_rss_tuple(hdev->ae_dev, &hdev->hw.hw, 726 &hdev->rss_cfg, nfc); 727 if (ret) 728 dev_err(&hdev->pdev->dev, 729 "failed to set rss tuple, ret = %d.\n", ret); 730 731 return ret; 732 } 733 734 static int hclgevf_get_rss_tuple(struct hnae3_handle *handle, 735 struct ethtool_rxnfc *nfc) 736 { 737 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 738 u8 tuple_sets; 739 int ret; 740 741 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 742 return -EOPNOTSUPP; 743 744 nfc->data = 0; 745 746 ret = hclge_comm_get_rss_tuple(&hdev->rss_cfg, nfc->flow_type, 747 &tuple_sets); 748 if (ret || !tuple_sets) 749 return ret; 750 751 nfc->data = hclge_comm_convert_rss_tuple(tuple_sets); 752 753 return 0; 754 } 755 756 static int hclgevf_get_tc_size(struct hnae3_handle *handle) 757 { 758 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 759 struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg; 760 761 return rss_cfg->rss_size; 762 } 763 764 static int hclgevf_bind_ring_to_vector(struct hnae3_handle *handle, bool en, 765 int vector_id, 766 struct hnae3_ring_chain_node *ring_chain) 767 { 768 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 769 struct hclge_vf_to_pf_msg send_msg; 770 struct hnae3_ring_chain_node *node; 771 int status; 772 int i = 0; 773 774 memset(&send_msg, 0, sizeof(send_msg)); 775 send_msg.code = en ? HCLGE_MBX_MAP_RING_TO_VECTOR : 776 HCLGE_MBX_UNMAP_RING_TO_VECTOR; 777 send_msg.vector_id = vector_id; 778 779 for (node = ring_chain; node; node = node->next) { 780 send_msg.param[i].ring_type = 781 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B); 782 783 send_msg.param[i].tqp_index = node->tqp_index; 784 send_msg.param[i].int_gl_index = 785 hnae3_get_field(node->int_gl_idx, 786 HNAE3_RING_GL_IDX_M, 787 HNAE3_RING_GL_IDX_S); 788 789 i++; 790 if (i == HCLGE_MBX_MAX_RING_CHAIN_PARAM_NUM || !node->next) { 791 send_msg.ring_num = i; 792 793 status = hclgevf_send_mbx_msg(hdev, &send_msg, false, 794 NULL, 0); 795 if (status) { 796 dev_err(&hdev->pdev->dev, 797 "Map TQP fail, status is %d.\n", 798 status); 799 return status; 800 } 801 i = 0; 802 } 803 } 804 805 return 0; 806 } 807 808 static int hclgevf_map_ring_to_vector(struct hnae3_handle *handle, int vector, 809 struct hnae3_ring_chain_node *ring_chain) 810 { 811 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 812 int vector_id; 813 814 vector_id = hclgevf_get_vector_index(hdev, vector); 815 if (vector_id < 0) { 816 dev_err(&handle->pdev->dev, 817 "Get vector index fail. ret =%d\n", vector_id); 818 return vector_id; 819 } 820 821 return hclgevf_bind_ring_to_vector(handle, true, vector_id, ring_chain); 822 } 823 824 static int hclgevf_unmap_ring_from_vector( 825 struct hnae3_handle *handle, 826 int vector, 827 struct hnae3_ring_chain_node *ring_chain) 828 { 829 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 830 int ret, vector_id; 831 832 if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 833 return 0; 834 835 vector_id = hclgevf_get_vector_index(hdev, vector); 836 if (vector_id < 0) { 837 dev_err(&handle->pdev->dev, 838 "Get vector index fail. ret =%d\n", vector_id); 839 return vector_id; 840 } 841 842 ret = hclgevf_bind_ring_to_vector(handle, false, vector_id, ring_chain); 843 if (ret) 844 dev_err(&handle->pdev->dev, 845 "Unmap ring from vector fail. vector=%d, ret =%d\n", 846 vector_id, 847 ret); 848 849 return ret; 850 } 851 852 static int hclgevf_put_vector(struct hnae3_handle *handle, int vector) 853 { 854 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 855 int vector_id; 856 857 vector_id = hclgevf_get_vector_index(hdev, vector); 858 if (vector_id < 0) { 859 dev_err(&handle->pdev->dev, 860 "hclgevf_put_vector get vector index fail. ret =%d\n", 861 vector_id); 862 return vector_id; 863 } 864 865 hclgevf_free_vector(hdev, vector_id); 866 867 return 0; 868 } 869 870 static int hclgevf_cmd_set_promisc_mode(struct hclgevf_dev *hdev, 871 bool en_uc_pmc, bool en_mc_pmc, 872 bool en_bc_pmc) 873 { 874 struct hnae3_handle *handle = &hdev->nic; 875 struct hclge_vf_to_pf_msg send_msg; 876 int ret; 877 878 memset(&send_msg, 0, sizeof(send_msg)); 879 send_msg.code = HCLGE_MBX_SET_PROMISC_MODE; 880 send_msg.en_bc = en_bc_pmc ? 1 : 0; 881 send_msg.en_uc = en_uc_pmc ? 1 : 0; 882 send_msg.en_mc = en_mc_pmc ? 1 : 0; 883 send_msg.en_limit_promisc = test_bit(HNAE3_PFLAG_LIMIT_PROMISC, 884 &handle->priv_flags) ? 1 : 0; 885 886 ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 887 if (ret) 888 dev_err(&hdev->pdev->dev, 889 "Set promisc mode fail, status is %d.\n", ret); 890 891 return ret; 892 } 893 894 static int hclgevf_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc, 895 bool en_mc_pmc) 896 { 897 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 898 bool en_bc_pmc; 899 900 en_bc_pmc = hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2; 901 902 return hclgevf_cmd_set_promisc_mode(hdev, en_uc_pmc, en_mc_pmc, 903 en_bc_pmc); 904 } 905 906 static void hclgevf_request_update_promisc_mode(struct hnae3_handle *handle) 907 { 908 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 909 910 set_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state); 911 hclgevf_task_schedule(hdev, 0); 912 } 913 914 static void hclgevf_sync_promisc_mode(struct hclgevf_dev *hdev) 915 { 916 struct hnae3_handle *handle = &hdev->nic; 917 bool en_uc_pmc = handle->netdev_flags & HNAE3_UPE; 918 bool en_mc_pmc = handle->netdev_flags & HNAE3_MPE; 919 int ret; 920 921 if (test_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state)) { 922 ret = hclgevf_set_promisc_mode(handle, en_uc_pmc, en_mc_pmc); 923 if (!ret) 924 clear_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state); 925 } 926 } 927 928 static int hclgevf_tqp_enable_cmd_send(struct hclgevf_dev *hdev, u16 tqp_id, 929 u16 stream_id, bool enable) 930 { 931 struct hclgevf_cfg_com_tqp_queue_cmd *req; 932 struct hclge_desc desc; 933 934 req = (struct hclgevf_cfg_com_tqp_queue_cmd *)desc.data; 935 936 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_CFG_COM_TQP_QUEUE, 937 false); 938 req->tqp_id = cpu_to_le16(tqp_id & HCLGEVF_RING_ID_MASK); 939 req->stream_id = cpu_to_le16(stream_id); 940 if (enable) 941 req->enable |= 1U << HCLGEVF_TQP_ENABLE_B; 942 943 return hclgevf_cmd_send(&hdev->hw, &desc, 1); 944 } 945 946 static int hclgevf_tqp_enable(struct hnae3_handle *handle, bool enable) 947 { 948 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 949 int ret; 950 u16 i; 951 952 for (i = 0; i < handle->kinfo.num_tqps; i++) { 953 ret = hclgevf_tqp_enable_cmd_send(hdev, i, 0, enable); 954 if (ret) 955 return ret; 956 } 957 958 return 0; 959 } 960 961 static void hclgevf_reset_tqp_stats(struct hnae3_handle *handle) 962 { 963 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 964 struct hclgevf_tqp *tqp; 965 int i; 966 967 for (i = 0; i < kinfo->num_tqps; i++) { 968 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 969 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats)); 970 } 971 } 972 973 static int hclgevf_get_host_mac_addr(struct hclgevf_dev *hdev, u8 *p) 974 { 975 struct hclge_vf_to_pf_msg send_msg; 976 u8 host_mac[ETH_ALEN]; 977 int status; 978 979 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_MAC_ADDR, 0); 980 status = hclgevf_send_mbx_msg(hdev, &send_msg, true, host_mac, 981 ETH_ALEN); 982 if (status) { 983 dev_err(&hdev->pdev->dev, 984 "fail to get VF MAC from host %d", status); 985 return status; 986 } 987 988 ether_addr_copy(p, host_mac); 989 990 return 0; 991 } 992 993 static void hclgevf_get_mac_addr(struct hnae3_handle *handle, u8 *p) 994 { 995 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 996 u8 host_mac_addr[ETH_ALEN]; 997 998 if (hclgevf_get_host_mac_addr(hdev, host_mac_addr)) 999 return; 1000 1001 hdev->has_pf_mac = !is_zero_ether_addr(host_mac_addr); 1002 if (hdev->has_pf_mac) 1003 ether_addr_copy(p, host_mac_addr); 1004 else 1005 ether_addr_copy(p, hdev->hw.mac.mac_addr); 1006 } 1007 1008 static int hclgevf_set_mac_addr(struct hnae3_handle *handle, const void *p, 1009 bool is_first) 1010 { 1011 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1012 u8 *old_mac_addr = (u8 *)hdev->hw.mac.mac_addr; 1013 struct hclge_vf_to_pf_msg send_msg; 1014 u8 *new_mac_addr = (u8 *)p; 1015 int status; 1016 1017 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_UNICAST, 0); 1018 send_msg.subcode = HCLGE_MBX_MAC_VLAN_UC_MODIFY; 1019 ether_addr_copy(send_msg.data, new_mac_addr); 1020 if (is_first && !hdev->has_pf_mac) 1021 eth_zero_addr(&send_msg.data[ETH_ALEN]); 1022 else 1023 ether_addr_copy(&send_msg.data[ETH_ALEN], old_mac_addr); 1024 status = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1025 if (!status) 1026 ether_addr_copy(hdev->hw.mac.mac_addr, new_mac_addr); 1027 1028 return status; 1029 } 1030 1031 static struct hclgevf_mac_addr_node * 1032 hclgevf_find_mac_node(struct list_head *list, const u8 *mac_addr) 1033 { 1034 struct hclgevf_mac_addr_node *mac_node, *tmp; 1035 1036 list_for_each_entry_safe(mac_node, tmp, list, node) 1037 if (ether_addr_equal(mac_addr, mac_node->mac_addr)) 1038 return mac_node; 1039 1040 return NULL; 1041 } 1042 1043 static void hclgevf_update_mac_node(struct hclgevf_mac_addr_node *mac_node, 1044 enum HCLGEVF_MAC_NODE_STATE state) 1045 { 1046 switch (state) { 1047 /* from set_rx_mode or tmp_add_list */ 1048 case HCLGEVF_MAC_TO_ADD: 1049 if (mac_node->state == HCLGEVF_MAC_TO_DEL) 1050 mac_node->state = HCLGEVF_MAC_ACTIVE; 1051 break; 1052 /* only from set_rx_mode */ 1053 case HCLGEVF_MAC_TO_DEL: 1054 if (mac_node->state == HCLGEVF_MAC_TO_ADD) { 1055 list_del(&mac_node->node); 1056 kfree(mac_node); 1057 } else { 1058 mac_node->state = HCLGEVF_MAC_TO_DEL; 1059 } 1060 break; 1061 /* only from tmp_add_list, the mac_node->state won't be 1062 * HCLGEVF_MAC_ACTIVE 1063 */ 1064 case HCLGEVF_MAC_ACTIVE: 1065 if (mac_node->state == HCLGEVF_MAC_TO_ADD) 1066 mac_node->state = HCLGEVF_MAC_ACTIVE; 1067 break; 1068 } 1069 } 1070 1071 static int hclgevf_update_mac_list(struct hnae3_handle *handle, 1072 enum HCLGEVF_MAC_NODE_STATE state, 1073 enum HCLGEVF_MAC_ADDR_TYPE mac_type, 1074 const unsigned char *addr) 1075 { 1076 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1077 struct hclgevf_mac_addr_node *mac_node; 1078 struct list_head *list; 1079 1080 list = (mac_type == HCLGEVF_MAC_ADDR_UC) ? 1081 &hdev->mac_table.uc_mac_list : &hdev->mac_table.mc_mac_list; 1082 1083 spin_lock_bh(&hdev->mac_table.mac_list_lock); 1084 1085 /* if the mac addr is already in the mac list, no need to add a new 1086 * one into it, just check the mac addr state, convert it to a new 1087 * new state, or just remove it, or do nothing. 1088 */ 1089 mac_node = hclgevf_find_mac_node(list, addr); 1090 if (mac_node) { 1091 hclgevf_update_mac_node(mac_node, state); 1092 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1093 return 0; 1094 } 1095 /* if this address is never added, unnecessary to delete */ 1096 if (state == HCLGEVF_MAC_TO_DEL) { 1097 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1098 return -ENOENT; 1099 } 1100 1101 mac_node = kzalloc(sizeof(*mac_node), GFP_ATOMIC); 1102 if (!mac_node) { 1103 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1104 return -ENOMEM; 1105 } 1106 1107 mac_node->state = state; 1108 ether_addr_copy(mac_node->mac_addr, addr); 1109 list_add_tail(&mac_node->node, list); 1110 1111 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1112 return 0; 1113 } 1114 1115 static int hclgevf_add_uc_addr(struct hnae3_handle *handle, 1116 const unsigned char *addr) 1117 { 1118 return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_ADD, 1119 HCLGEVF_MAC_ADDR_UC, addr); 1120 } 1121 1122 static int hclgevf_rm_uc_addr(struct hnae3_handle *handle, 1123 const unsigned char *addr) 1124 { 1125 return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_DEL, 1126 HCLGEVF_MAC_ADDR_UC, addr); 1127 } 1128 1129 static int hclgevf_add_mc_addr(struct hnae3_handle *handle, 1130 const unsigned char *addr) 1131 { 1132 return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_ADD, 1133 HCLGEVF_MAC_ADDR_MC, addr); 1134 } 1135 1136 static int hclgevf_rm_mc_addr(struct hnae3_handle *handle, 1137 const unsigned char *addr) 1138 { 1139 return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_DEL, 1140 HCLGEVF_MAC_ADDR_MC, addr); 1141 } 1142 1143 static int hclgevf_add_del_mac_addr(struct hclgevf_dev *hdev, 1144 struct hclgevf_mac_addr_node *mac_node, 1145 enum HCLGEVF_MAC_ADDR_TYPE mac_type) 1146 { 1147 struct hclge_vf_to_pf_msg send_msg; 1148 u8 code, subcode; 1149 1150 if (mac_type == HCLGEVF_MAC_ADDR_UC) { 1151 code = HCLGE_MBX_SET_UNICAST; 1152 if (mac_node->state == HCLGEVF_MAC_TO_ADD) 1153 subcode = HCLGE_MBX_MAC_VLAN_UC_ADD; 1154 else 1155 subcode = HCLGE_MBX_MAC_VLAN_UC_REMOVE; 1156 } else { 1157 code = HCLGE_MBX_SET_MULTICAST; 1158 if (mac_node->state == HCLGEVF_MAC_TO_ADD) 1159 subcode = HCLGE_MBX_MAC_VLAN_MC_ADD; 1160 else 1161 subcode = HCLGE_MBX_MAC_VLAN_MC_REMOVE; 1162 } 1163 1164 hclgevf_build_send_msg(&send_msg, code, subcode); 1165 ether_addr_copy(send_msg.data, mac_node->mac_addr); 1166 return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 1167 } 1168 1169 static void hclgevf_config_mac_list(struct hclgevf_dev *hdev, 1170 struct list_head *list, 1171 enum HCLGEVF_MAC_ADDR_TYPE mac_type) 1172 { 1173 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 1174 struct hclgevf_mac_addr_node *mac_node, *tmp; 1175 int ret; 1176 1177 list_for_each_entry_safe(mac_node, tmp, list, node) { 1178 ret = hclgevf_add_del_mac_addr(hdev, mac_node, mac_type); 1179 if (ret) { 1180 hnae3_format_mac_addr(format_mac_addr, 1181 mac_node->mac_addr); 1182 dev_err(&hdev->pdev->dev, 1183 "failed to configure mac %s, state = %d, ret = %d\n", 1184 format_mac_addr, mac_node->state, ret); 1185 return; 1186 } 1187 if (mac_node->state == HCLGEVF_MAC_TO_ADD) { 1188 mac_node->state = HCLGEVF_MAC_ACTIVE; 1189 } else { 1190 list_del(&mac_node->node); 1191 kfree(mac_node); 1192 } 1193 } 1194 } 1195 1196 static void hclgevf_sync_from_add_list(struct list_head *add_list, 1197 struct list_head *mac_list) 1198 { 1199 struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node; 1200 1201 list_for_each_entry_safe(mac_node, tmp, add_list, node) { 1202 /* if the mac address from tmp_add_list is not in the 1203 * uc/mc_mac_list, it means have received a TO_DEL request 1204 * during the time window of sending mac config request to PF 1205 * If mac_node state is ACTIVE, then change its state to TO_DEL, 1206 * then it will be removed at next time. If is TO_ADD, it means 1207 * send TO_ADD request failed, so just remove the mac node. 1208 */ 1209 new_node = hclgevf_find_mac_node(mac_list, mac_node->mac_addr); 1210 if (new_node) { 1211 hclgevf_update_mac_node(new_node, mac_node->state); 1212 list_del(&mac_node->node); 1213 kfree(mac_node); 1214 } else if (mac_node->state == HCLGEVF_MAC_ACTIVE) { 1215 mac_node->state = HCLGEVF_MAC_TO_DEL; 1216 list_move_tail(&mac_node->node, mac_list); 1217 } else { 1218 list_del(&mac_node->node); 1219 kfree(mac_node); 1220 } 1221 } 1222 } 1223 1224 static void hclgevf_sync_from_del_list(struct list_head *del_list, 1225 struct list_head *mac_list) 1226 { 1227 struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node; 1228 1229 list_for_each_entry_safe(mac_node, tmp, del_list, node) { 1230 new_node = hclgevf_find_mac_node(mac_list, mac_node->mac_addr); 1231 if (new_node) { 1232 /* If the mac addr is exist in the mac list, it means 1233 * received a new request TO_ADD during the time window 1234 * of sending mac addr configurrequest to PF, so just 1235 * change the mac state to ACTIVE. 1236 */ 1237 new_node->state = HCLGEVF_MAC_ACTIVE; 1238 list_del(&mac_node->node); 1239 kfree(mac_node); 1240 } else { 1241 list_move_tail(&mac_node->node, mac_list); 1242 } 1243 } 1244 } 1245 1246 static void hclgevf_clear_list(struct list_head *list) 1247 { 1248 struct hclgevf_mac_addr_node *mac_node, *tmp; 1249 1250 list_for_each_entry_safe(mac_node, tmp, list, node) { 1251 list_del(&mac_node->node); 1252 kfree(mac_node); 1253 } 1254 } 1255 1256 static void hclgevf_sync_mac_list(struct hclgevf_dev *hdev, 1257 enum HCLGEVF_MAC_ADDR_TYPE mac_type) 1258 { 1259 struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node; 1260 struct list_head tmp_add_list, tmp_del_list; 1261 struct list_head *list; 1262 1263 INIT_LIST_HEAD(&tmp_add_list); 1264 INIT_LIST_HEAD(&tmp_del_list); 1265 1266 /* move the mac addr to the tmp_add_list and tmp_del_list, then 1267 * we can add/delete these mac addr outside the spin lock 1268 */ 1269 list = (mac_type == HCLGEVF_MAC_ADDR_UC) ? 1270 &hdev->mac_table.uc_mac_list : &hdev->mac_table.mc_mac_list; 1271 1272 spin_lock_bh(&hdev->mac_table.mac_list_lock); 1273 1274 list_for_each_entry_safe(mac_node, tmp, list, node) { 1275 switch (mac_node->state) { 1276 case HCLGEVF_MAC_TO_DEL: 1277 list_move_tail(&mac_node->node, &tmp_del_list); 1278 break; 1279 case HCLGEVF_MAC_TO_ADD: 1280 new_node = kzalloc(sizeof(*new_node), GFP_ATOMIC); 1281 if (!new_node) 1282 goto stop_traverse; 1283 1284 ether_addr_copy(new_node->mac_addr, mac_node->mac_addr); 1285 new_node->state = mac_node->state; 1286 list_add_tail(&new_node->node, &tmp_add_list); 1287 break; 1288 default: 1289 break; 1290 } 1291 } 1292 1293 stop_traverse: 1294 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1295 1296 /* delete first, in order to get max mac table space for adding */ 1297 hclgevf_config_mac_list(hdev, &tmp_del_list, mac_type); 1298 hclgevf_config_mac_list(hdev, &tmp_add_list, mac_type); 1299 1300 /* if some mac addresses were added/deleted fail, move back to the 1301 * mac_list, and retry at next time. 1302 */ 1303 spin_lock_bh(&hdev->mac_table.mac_list_lock); 1304 1305 hclgevf_sync_from_del_list(&tmp_del_list, list); 1306 hclgevf_sync_from_add_list(&tmp_add_list, list); 1307 1308 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1309 } 1310 1311 static void hclgevf_sync_mac_table(struct hclgevf_dev *hdev) 1312 { 1313 hclgevf_sync_mac_list(hdev, HCLGEVF_MAC_ADDR_UC); 1314 hclgevf_sync_mac_list(hdev, HCLGEVF_MAC_ADDR_MC); 1315 } 1316 1317 static void hclgevf_uninit_mac_list(struct hclgevf_dev *hdev) 1318 { 1319 spin_lock_bh(&hdev->mac_table.mac_list_lock); 1320 1321 hclgevf_clear_list(&hdev->mac_table.uc_mac_list); 1322 hclgevf_clear_list(&hdev->mac_table.mc_mac_list); 1323 1324 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1325 } 1326 1327 static int hclgevf_enable_vlan_filter(struct hnae3_handle *handle, bool enable) 1328 { 1329 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1330 struct hnae3_ae_dev *ae_dev = hdev->ae_dev; 1331 struct hclge_vf_to_pf_msg send_msg; 1332 1333 if (!test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps)) 1334 return -EOPNOTSUPP; 1335 1336 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 1337 HCLGE_MBX_ENABLE_VLAN_FILTER); 1338 send_msg.data[0] = enable ? 1 : 0; 1339 1340 return hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1341 } 1342 1343 static int hclgevf_set_vlan_filter(struct hnae3_handle *handle, 1344 __be16 proto, u16 vlan_id, 1345 bool is_kill) 1346 { 1347 #define HCLGEVF_VLAN_MBX_IS_KILL_OFFSET 0 1348 #define HCLGEVF_VLAN_MBX_VLAN_ID_OFFSET 1 1349 #define HCLGEVF_VLAN_MBX_PROTO_OFFSET 3 1350 1351 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1352 struct hclge_vf_to_pf_msg send_msg; 1353 int ret; 1354 1355 if (vlan_id > HCLGEVF_MAX_VLAN_ID) 1356 return -EINVAL; 1357 1358 if (proto != htons(ETH_P_8021Q)) 1359 return -EPROTONOSUPPORT; 1360 1361 /* When device is resetting or reset failed, firmware is unable to 1362 * handle mailbox. Just record the vlan id, and remove it after 1363 * reset finished. 1364 */ 1365 if ((test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) || 1366 test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) && is_kill) { 1367 set_bit(vlan_id, hdev->vlan_del_fail_bmap); 1368 return -EBUSY; 1369 } 1370 1371 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 1372 HCLGE_MBX_VLAN_FILTER); 1373 send_msg.data[HCLGEVF_VLAN_MBX_IS_KILL_OFFSET] = is_kill; 1374 memcpy(&send_msg.data[HCLGEVF_VLAN_MBX_VLAN_ID_OFFSET], &vlan_id, 1375 sizeof(vlan_id)); 1376 memcpy(&send_msg.data[HCLGEVF_VLAN_MBX_PROTO_OFFSET], &proto, 1377 sizeof(proto)); 1378 /* when remove hw vlan filter failed, record the vlan id, 1379 * and try to remove it from hw later, to be consistence 1380 * with stack. 1381 */ 1382 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1383 if (is_kill && ret) 1384 set_bit(vlan_id, hdev->vlan_del_fail_bmap); 1385 1386 return ret; 1387 } 1388 1389 static void hclgevf_sync_vlan_filter(struct hclgevf_dev *hdev) 1390 { 1391 #define HCLGEVF_MAX_SYNC_COUNT 60 1392 struct hnae3_handle *handle = &hdev->nic; 1393 int ret, sync_cnt = 0; 1394 u16 vlan_id; 1395 1396 vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID); 1397 while (vlan_id != VLAN_N_VID) { 1398 ret = hclgevf_set_vlan_filter(handle, htons(ETH_P_8021Q), 1399 vlan_id, true); 1400 if (ret) 1401 return; 1402 1403 clear_bit(vlan_id, hdev->vlan_del_fail_bmap); 1404 sync_cnt++; 1405 if (sync_cnt >= HCLGEVF_MAX_SYNC_COUNT) 1406 return; 1407 1408 vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID); 1409 } 1410 } 1411 1412 static int hclgevf_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) 1413 { 1414 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1415 struct hclge_vf_to_pf_msg send_msg; 1416 1417 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 1418 HCLGE_MBX_VLAN_RX_OFF_CFG); 1419 send_msg.data[0] = enable ? 1 : 0; 1420 return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 1421 } 1422 1423 static int hclgevf_reset_tqp(struct hnae3_handle *handle) 1424 { 1425 #define HCLGEVF_RESET_ALL_QUEUE_DONE 1U 1426 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1427 struct hclge_vf_to_pf_msg send_msg; 1428 u8 return_status = 0; 1429 int ret; 1430 u16 i; 1431 1432 /* disable vf queue before send queue reset msg to PF */ 1433 ret = hclgevf_tqp_enable(handle, false); 1434 if (ret) { 1435 dev_err(&hdev->pdev->dev, "failed to disable tqp, ret = %d\n", 1436 ret); 1437 return ret; 1438 } 1439 1440 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_QUEUE_RESET, 0); 1441 1442 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, &return_status, 1443 sizeof(return_status)); 1444 if (ret || return_status == HCLGEVF_RESET_ALL_QUEUE_DONE) 1445 return ret; 1446 1447 for (i = 1; i < handle->kinfo.num_tqps; i++) { 1448 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_QUEUE_RESET, 0); 1449 memcpy(send_msg.data, &i, sizeof(i)); 1450 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1451 if (ret) 1452 return ret; 1453 } 1454 1455 return 0; 1456 } 1457 1458 static int hclgevf_set_mtu(struct hnae3_handle *handle, int new_mtu) 1459 { 1460 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1461 struct hclge_vf_to_pf_msg send_msg; 1462 1463 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_MTU, 0); 1464 memcpy(send_msg.data, &new_mtu, sizeof(new_mtu)); 1465 return hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1466 } 1467 1468 static int hclgevf_notify_client(struct hclgevf_dev *hdev, 1469 enum hnae3_reset_notify_type type) 1470 { 1471 struct hnae3_client *client = hdev->nic_client; 1472 struct hnae3_handle *handle = &hdev->nic; 1473 int ret; 1474 1475 if (!test_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state) || 1476 !client) 1477 return 0; 1478 1479 if (!client->ops->reset_notify) 1480 return -EOPNOTSUPP; 1481 1482 ret = client->ops->reset_notify(handle, type); 1483 if (ret) 1484 dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n", 1485 type, ret); 1486 1487 return ret; 1488 } 1489 1490 static int hclgevf_notify_roce_client(struct hclgevf_dev *hdev, 1491 enum hnae3_reset_notify_type type) 1492 { 1493 struct hnae3_client *client = hdev->roce_client; 1494 struct hnae3_handle *handle = &hdev->roce; 1495 int ret; 1496 1497 if (!test_bit(HCLGEVF_STATE_ROCE_REGISTERED, &hdev->state) || !client) 1498 return 0; 1499 1500 if (!client->ops->reset_notify) 1501 return -EOPNOTSUPP; 1502 1503 ret = client->ops->reset_notify(handle, type); 1504 if (ret) 1505 dev_err(&hdev->pdev->dev, "notify roce client failed %d(%d)", 1506 type, ret); 1507 return ret; 1508 } 1509 1510 static int hclgevf_reset_wait(struct hclgevf_dev *hdev) 1511 { 1512 #define HCLGEVF_RESET_WAIT_US 20000 1513 #define HCLGEVF_RESET_WAIT_CNT 2000 1514 #define HCLGEVF_RESET_WAIT_TIMEOUT_US \ 1515 (HCLGEVF_RESET_WAIT_US * HCLGEVF_RESET_WAIT_CNT) 1516 1517 u32 val; 1518 int ret; 1519 1520 if (hdev->reset_type == HNAE3_VF_RESET) 1521 ret = readl_poll_timeout(hdev->hw.hw.io_base + 1522 HCLGEVF_VF_RST_ING, val, 1523 !(val & HCLGEVF_VF_RST_ING_BIT), 1524 HCLGEVF_RESET_WAIT_US, 1525 HCLGEVF_RESET_WAIT_TIMEOUT_US); 1526 else 1527 ret = readl_poll_timeout(hdev->hw.hw.io_base + 1528 HCLGEVF_RST_ING, val, 1529 !(val & HCLGEVF_RST_ING_BITS), 1530 HCLGEVF_RESET_WAIT_US, 1531 HCLGEVF_RESET_WAIT_TIMEOUT_US); 1532 1533 /* hardware completion status should be available by this time */ 1534 if (ret) { 1535 dev_err(&hdev->pdev->dev, 1536 "couldn't get reset done status from h/w, timeout!\n"); 1537 return ret; 1538 } 1539 1540 /* we will wait a bit more to let reset of the stack to complete. This 1541 * might happen in case reset assertion was made by PF. Yes, this also 1542 * means we might end up waiting bit more even for VF reset. 1543 */ 1544 msleep(5000); 1545 1546 return 0; 1547 } 1548 1549 static void hclgevf_reset_handshake(struct hclgevf_dev *hdev, bool enable) 1550 { 1551 u32 reg_val; 1552 1553 reg_val = hclgevf_read_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG); 1554 if (enable) 1555 reg_val |= HCLGEVF_NIC_SW_RST_RDY; 1556 else 1557 reg_val &= ~HCLGEVF_NIC_SW_RST_RDY; 1558 1559 hclgevf_write_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG, 1560 reg_val); 1561 } 1562 1563 static int hclgevf_reset_stack(struct hclgevf_dev *hdev) 1564 { 1565 int ret; 1566 1567 /* uninitialize the nic client */ 1568 ret = hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT); 1569 if (ret) 1570 return ret; 1571 1572 /* re-initialize the hclge device */ 1573 ret = hclgevf_reset_hdev(hdev); 1574 if (ret) { 1575 dev_err(&hdev->pdev->dev, 1576 "hclge device re-init failed, VF is disabled!\n"); 1577 return ret; 1578 } 1579 1580 /* bring up the nic client again */ 1581 ret = hclgevf_notify_client(hdev, HNAE3_INIT_CLIENT); 1582 if (ret) 1583 return ret; 1584 1585 /* clear handshake status with IMP */ 1586 hclgevf_reset_handshake(hdev, false); 1587 1588 /* bring up the nic to enable TX/RX again */ 1589 return hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 1590 } 1591 1592 static int hclgevf_reset_prepare_wait(struct hclgevf_dev *hdev) 1593 { 1594 #define HCLGEVF_RESET_SYNC_TIME 100 1595 1596 if (hdev->reset_type == HNAE3_VF_FUNC_RESET) { 1597 struct hclge_vf_to_pf_msg send_msg; 1598 int ret; 1599 1600 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_RESET, 0); 1601 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1602 if (ret) { 1603 dev_err(&hdev->pdev->dev, 1604 "failed to assert VF reset, ret = %d\n", ret); 1605 return ret; 1606 } 1607 hdev->rst_stats.vf_func_rst_cnt++; 1608 } 1609 1610 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 1611 /* inform hardware that preparatory work is done */ 1612 msleep(HCLGEVF_RESET_SYNC_TIME); 1613 hclgevf_reset_handshake(hdev, true); 1614 dev_info(&hdev->pdev->dev, "prepare reset(%d) wait done\n", 1615 hdev->reset_type); 1616 1617 return 0; 1618 } 1619 1620 static void hclgevf_dump_rst_info(struct hclgevf_dev *hdev) 1621 { 1622 dev_info(&hdev->pdev->dev, "VF function reset count: %u\n", 1623 hdev->rst_stats.vf_func_rst_cnt); 1624 dev_info(&hdev->pdev->dev, "FLR reset count: %u\n", 1625 hdev->rst_stats.flr_rst_cnt); 1626 dev_info(&hdev->pdev->dev, "VF reset count: %u\n", 1627 hdev->rst_stats.vf_rst_cnt); 1628 dev_info(&hdev->pdev->dev, "reset done count: %u\n", 1629 hdev->rst_stats.rst_done_cnt); 1630 dev_info(&hdev->pdev->dev, "HW reset done count: %u\n", 1631 hdev->rst_stats.hw_rst_done_cnt); 1632 dev_info(&hdev->pdev->dev, "reset count: %u\n", 1633 hdev->rst_stats.rst_cnt); 1634 dev_info(&hdev->pdev->dev, "reset fail count: %u\n", 1635 hdev->rst_stats.rst_fail_cnt); 1636 dev_info(&hdev->pdev->dev, "vector0 interrupt enable status: 0x%x\n", 1637 hclgevf_read_dev(&hdev->hw, HCLGEVF_MISC_VECTOR_REG_BASE)); 1638 dev_info(&hdev->pdev->dev, "vector0 interrupt status: 0x%x\n", 1639 hclgevf_read_dev(&hdev->hw, HCLGE_COMM_VECTOR0_CMDQ_STATE_REG)); 1640 dev_info(&hdev->pdev->dev, "handshake status: 0x%x\n", 1641 hclgevf_read_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG)); 1642 dev_info(&hdev->pdev->dev, "function reset status: 0x%x\n", 1643 hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING)); 1644 dev_info(&hdev->pdev->dev, "hdev state: 0x%lx\n", hdev->state); 1645 } 1646 1647 static void hclgevf_reset_err_handle(struct hclgevf_dev *hdev) 1648 { 1649 /* recover handshake status with IMP when reset fail */ 1650 hclgevf_reset_handshake(hdev, true); 1651 hdev->rst_stats.rst_fail_cnt++; 1652 dev_err(&hdev->pdev->dev, "failed to reset VF(%u)\n", 1653 hdev->rst_stats.rst_fail_cnt); 1654 1655 if (hdev->rst_stats.rst_fail_cnt < HCLGEVF_RESET_MAX_FAIL_CNT) 1656 set_bit(hdev->reset_type, &hdev->reset_pending); 1657 1658 if (hclgevf_is_reset_pending(hdev)) { 1659 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1660 hclgevf_reset_task_schedule(hdev); 1661 } else { 1662 set_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state); 1663 hclgevf_dump_rst_info(hdev); 1664 } 1665 } 1666 1667 static int hclgevf_reset_prepare(struct hclgevf_dev *hdev) 1668 { 1669 int ret; 1670 1671 hdev->rst_stats.rst_cnt++; 1672 1673 /* perform reset of the stack & ae device for a client */ 1674 ret = hclgevf_notify_roce_client(hdev, HNAE3_DOWN_CLIENT); 1675 if (ret) 1676 return ret; 1677 1678 rtnl_lock(); 1679 /* bring down the nic to stop any ongoing TX/RX */ 1680 ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 1681 rtnl_unlock(); 1682 if (ret) 1683 return ret; 1684 1685 return hclgevf_reset_prepare_wait(hdev); 1686 } 1687 1688 static int hclgevf_reset_rebuild(struct hclgevf_dev *hdev) 1689 { 1690 int ret; 1691 1692 hdev->rst_stats.hw_rst_done_cnt++; 1693 ret = hclgevf_notify_roce_client(hdev, HNAE3_UNINIT_CLIENT); 1694 if (ret) 1695 return ret; 1696 1697 rtnl_lock(); 1698 /* now, re-initialize the nic client and ae device */ 1699 ret = hclgevf_reset_stack(hdev); 1700 rtnl_unlock(); 1701 if (ret) { 1702 dev_err(&hdev->pdev->dev, "failed to reset VF stack\n"); 1703 return ret; 1704 } 1705 1706 ret = hclgevf_notify_roce_client(hdev, HNAE3_INIT_CLIENT); 1707 /* ignore RoCE notify error if it fails HCLGEVF_RESET_MAX_FAIL_CNT - 1 1708 * times 1709 */ 1710 if (ret && 1711 hdev->rst_stats.rst_fail_cnt < HCLGEVF_RESET_MAX_FAIL_CNT - 1) 1712 return ret; 1713 1714 ret = hclgevf_notify_roce_client(hdev, HNAE3_UP_CLIENT); 1715 if (ret) 1716 return ret; 1717 1718 hdev->last_reset_time = jiffies; 1719 hdev->rst_stats.rst_done_cnt++; 1720 hdev->rst_stats.rst_fail_cnt = 0; 1721 clear_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state); 1722 1723 return 0; 1724 } 1725 1726 static void hclgevf_reset(struct hclgevf_dev *hdev) 1727 { 1728 if (hclgevf_reset_prepare(hdev)) 1729 goto err_reset; 1730 1731 /* check if VF could successfully fetch the hardware reset completion 1732 * status from the hardware 1733 */ 1734 if (hclgevf_reset_wait(hdev)) { 1735 /* can't do much in this situation, will disable VF */ 1736 dev_err(&hdev->pdev->dev, 1737 "failed to fetch H/W reset completion status\n"); 1738 goto err_reset; 1739 } 1740 1741 if (hclgevf_reset_rebuild(hdev)) 1742 goto err_reset; 1743 1744 return; 1745 1746 err_reset: 1747 hclgevf_reset_err_handle(hdev); 1748 } 1749 1750 static enum hnae3_reset_type hclgevf_get_reset_level(struct hclgevf_dev *hdev, 1751 unsigned long *addr) 1752 { 1753 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; 1754 1755 /* return the highest priority reset level amongst all */ 1756 if (test_bit(HNAE3_VF_RESET, addr)) { 1757 rst_level = HNAE3_VF_RESET; 1758 clear_bit(HNAE3_VF_RESET, addr); 1759 clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1760 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1761 } else if (test_bit(HNAE3_VF_FULL_RESET, addr)) { 1762 rst_level = HNAE3_VF_FULL_RESET; 1763 clear_bit(HNAE3_VF_FULL_RESET, addr); 1764 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1765 } else if (test_bit(HNAE3_VF_PF_FUNC_RESET, addr)) { 1766 rst_level = HNAE3_VF_PF_FUNC_RESET; 1767 clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1768 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1769 } else if (test_bit(HNAE3_VF_FUNC_RESET, addr)) { 1770 rst_level = HNAE3_VF_FUNC_RESET; 1771 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1772 } else if (test_bit(HNAE3_FLR_RESET, addr)) { 1773 rst_level = HNAE3_FLR_RESET; 1774 clear_bit(HNAE3_FLR_RESET, addr); 1775 } 1776 1777 return rst_level; 1778 } 1779 1780 static void hclgevf_reset_event(struct pci_dev *pdev, 1781 struct hnae3_handle *handle) 1782 { 1783 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 1784 struct hclgevf_dev *hdev = ae_dev->priv; 1785 1786 dev_info(&hdev->pdev->dev, "received reset request from VF enet\n"); 1787 1788 if (hdev->default_reset_request) 1789 hdev->reset_level = 1790 hclgevf_get_reset_level(hdev, 1791 &hdev->default_reset_request); 1792 else 1793 hdev->reset_level = HNAE3_VF_FUNC_RESET; 1794 1795 /* reset of this VF requested */ 1796 set_bit(HCLGEVF_RESET_REQUESTED, &hdev->reset_state); 1797 hclgevf_reset_task_schedule(hdev); 1798 1799 hdev->last_reset_time = jiffies; 1800 } 1801 1802 static void hclgevf_set_def_reset_request(struct hnae3_ae_dev *ae_dev, 1803 enum hnae3_reset_type rst_type) 1804 { 1805 struct hclgevf_dev *hdev = ae_dev->priv; 1806 1807 set_bit(rst_type, &hdev->default_reset_request); 1808 } 1809 1810 static void hclgevf_enable_vector(struct hclgevf_misc_vector *vector, bool en) 1811 { 1812 writel(en ? 1 : 0, vector->addr); 1813 } 1814 1815 static void hclgevf_reset_prepare_general(struct hnae3_ae_dev *ae_dev, 1816 enum hnae3_reset_type rst_type) 1817 { 1818 #define HCLGEVF_RESET_RETRY_WAIT_MS 500 1819 #define HCLGEVF_RESET_RETRY_CNT 5 1820 1821 struct hclgevf_dev *hdev = ae_dev->priv; 1822 int retry_cnt = 0; 1823 int ret; 1824 1825 while (retry_cnt++ < HCLGEVF_RESET_RETRY_CNT) { 1826 down(&hdev->reset_sem); 1827 set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 1828 hdev->reset_type = rst_type; 1829 ret = hclgevf_reset_prepare(hdev); 1830 if (!ret && !hdev->reset_pending) 1831 break; 1832 1833 dev_err(&hdev->pdev->dev, 1834 "failed to prepare to reset, ret=%d, reset_pending:0x%lx, retry_cnt:%d\n", 1835 ret, hdev->reset_pending, retry_cnt); 1836 clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 1837 up(&hdev->reset_sem); 1838 msleep(HCLGEVF_RESET_RETRY_WAIT_MS); 1839 } 1840 1841 /* disable misc vector before reset done */ 1842 hclgevf_enable_vector(&hdev->misc_vector, false); 1843 1844 if (hdev->reset_type == HNAE3_FLR_RESET) 1845 hdev->rst_stats.flr_rst_cnt++; 1846 } 1847 1848 static void hclgevf_reset_done(struct hnae3_ae_dev *ae_dev) 1849 { 1850 struct hclgevf_dev *hdev = ae_dev->priv; 1851 int ret; 1852 1853 hclgevf_enable_vector(&hdev->misc_vector, true); 1854 1855 ret = hclgevf_reset_rebuild(hdev); 1856 if (ret) 1857 dev_warn(&hdev->pdev->dev, "fail to rebuild, ret=%d\n", 1858 ret); 1859 1860 hdev->reset_type = HNAE3_NONE_RESET; 1861 clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 1862 up(&hdev->reset_sem); 1863 } 1864 1865 static u32 hclgevf_get_fw_version(struct hnae3_handle *handle) 1866 { 1867 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1868 1869 return hdev->fw_version; 1870 } 1871 1872 static void hclgevf_get_misc_vector(struct hclgevf_dev *hdev) 1873 { 1874 struct hclgevf_misc_vector *vector = &hdev->misc_vector; 1875 1876 vector->vector_irq = pci_irq_vector(hdev->pdev, 1877 HCLGEVF_MISC_VECTOR_NUM); 1878 vector->addr = hdev->hw.hw.io_base + HCLGEVF_MISC_VECTOR_REG_BASE; 1879 /* vector status always valid for Vector 0 */ 1880 hdev->vector_status[HCLGEVF_MISC_VECTOR_NUM] = 0; 1881 hdev->vector_irq[HCLGEVF_MISC_VECTOR_NUM] = vector->vector_irq; 1882 1883 hdev->num_msi_left -= 1; 1884 hdev->num_msi_used += 1; 1885 } 1886 1887 void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev) 1888 { 1889 if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) && 1890 test_bit(HCLGEVF_STATE_SERVICE_INITED, &hdev->state) && 1891 !test_and_set_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, 1892 &hdev->state)) 1893 mod_delayed_work(hclgevf_wq, &hdev->service_task, 0); 1894 } 1895 1896 void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev) 1897 { 1898 if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) && 1899 !test_and_set_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, 1900 &hdev->state)) 1901 mod_delayed_work(hclgevf_wq, &hdev->service_task, 0); 1902 } 1903 1904 static void hclgevf_task_schedule(struct hclgevf_dev *hdev, 1905 unsigned long delay) 1906 { 1907 if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) && 1908 !test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) 1909 mod_delayed_work(hclgevf_wq, &hdev->service_task, delay); 1910 } 1911 1912 static void hclgevf_reset_service_task(struct hclgevf_dev *hdev) 1913 { 1914 #define HCLGEVF_MAX_RESET_ATTEMPTS_CNT 3 1915 1916 if (!test_and_clear_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state)) 1917 return; 1918 1919 down(&hdev->reset_sem); 1920 set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 1921 1922 if (test_and_clear_bit(HCLGEVF_RESET_PENDING, 1923 &hdev->reset_state)) { 1924 /* PF has intimated that it is about to reset the hardware. 1925 * We now have to poll & check if hardware has actually 1926 * completed the reset sequence. On hardware reset completion, 1927 * VF needs to reset the client and ae device. 1928 */ 1929 hdev->reset_attempts = 0; 1930 1931 hdev->last_reset_time = jiffies; 1932 hdev->reset_type = 1933 hclgevf_get_reset_level(hdev, &hdev->reset_pending); 1934 if (hdev->reset_type != HNAE3_NONE_RESET) 1935 hclgevf_reset(hdev); 1936 } else if (test_and_clear_bit(HCLGEVF_RESET_REQUESTED, 1937 &hdev->reset_state)) { 1938 /* we could be here when either of below happens: 1939 * 1. reset was initiated due to watchdog timeout caused by 1940 * a. IMP was earlier reset and our TX got choked down and 1941 * which resulted in watchdog reacting and inducing VF 1942 * reset. This also means our cmdq would be unreliable. 1943 * b. problem in TX due to other lower layer(example link 1944 * layer not functioning properly etc.) 1945 * 2. VF reset might have been initiated due to some config 1946 * change. 1947 * 1948 * NOTE: Theres no clear way to detect above cases than to react 1949 * to the response of PF for this reset request. PF will ack the 1950 * 1b and 2. cases but we will not get any intimation about 1a 1951 * from PF as cmdq would be in unreliable state i.e. mailbox 1952 * communication between PF and VF would be broken. 1953 * 1954 * if we are never geting into pending state it means either: 1955 * 1. PF is not receiving our request which could be due to IMP 1956 * reset 1957 * 2. PF is screwed 1958 * We cannot do much for 2. but to check first we can try reset 1959 * our PCIe + stack and see if it alleviates the problem. 1960 */ 1961 if (hdev->reset_attempts > HCLGEVF_MAX_RESET_ATTEMPTS_CNT) { 1962 /* prepare for full reset of stack + pcie interface */ 1963 set_bit(HNAE3_VF_FULL_RESET, &hdev->reset_pending); 1964 1965 /* "defer" schedule the reset task again */ 1966 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1967 } else { 1968 hdev->reset_attempts++; 1969 1970 set_bit(hdev->reset_level, &hdev->reset_pending); 1971 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1972 } 1973 hclgevf_reset_task_schedule(hdev); 1974 } 1975 1976 hdev->reset_type = HNAE3_NONE_RESET; 1977 clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 1978 up(&hdev->reset_sem); 1979 } 1980 1981 static void hclgevf_mailbox_service_task(struct hclgevf_dev *hdev) 1982 { 1983 if (!test_and_clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state)) 1984 return; 1985 1986 if (test_and_set_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) 1987 return; 1988 1989 hclgevf_mbx_async_handler(hdev); 1990 1991 clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 1992 } 1993 1994 static void hclgevf_keep_alive(struct hclgevf_dev *hdev) 1995 { 1996 struct hclge_vf_to_pf_msg send_msg; 1997 int ret; 1998 1999 if (test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state)) 2000 return; 2001 2002 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_KEEP_ALIVE, 0); 2003 ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 2004 if (ret) 2005 dev_err(&hdev->pdev->dev, 2006 "VF sends keep alive cmd failed(=%d)\n", ret); 2007 } 2008 2009 static void hclgevf_periodic_service_task(struct hclgevf_dev *hdev) 2010 { 2011 unsigned long delta = round_jiffies_relative(HZ); 2012 struct hnae3_handle *handle = &hdev->nic; 2013 2014 if (test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) 2015 return; 2016 2017 if (time_is_after_jiffies(hdev->last_serv_processed + HZ)) { 2018 delta = jiffies - hdev->last_serv_processed; 2019 2020 if (delta < round_jiffies_relative(HZ)) { 2021 delta = round_jiffies_relative(HZ) - delta; 2022 goto out; 2023 } 2024 } 2025 2026 hdev->serv_processed_cnt++; 2027 if (!(hdev->serv_processed_cnt % HCLGEVF_KEEP_ALIVE_TASK_INTERVAL)) 2028 hclgevf_keep_alive(hdev); 2029 2030 if (test_bit(HCLGEVF_STATE_DOWN, &hdev->state)) { 2031 hdev->last_serv_processed = jiffies; 2032 goto out; 2033 } 2034 2035 if (!(hdev->serv_processed_cnt % HCLGEVF_STATS_TIMER_INTERVAL)) 2036 hclgevf_tqps_update_stats(handle); 2037 2038 /* VF does not need to request link status when this bit is set, because 2039 * PF will push its link status to VFs when link status changed. 2040 */ 2041 if (!test_bit(HCLGEVF_STATE_PF_PUSH_LINK_STATUS, &hdev->state)) 2042 hclgevf_request_link_info(hdev); 2043 2044 hclgevf_update_link_mode(hdev); 2045 2046 hclgevf_sync_vlan_filter(hdev); 2047 2048 hclgevf_sync_mac_table(hdev); 2049 2050 hclgevf_sync_promisc_mode(hdev); 2051 2052 hdev->last_serv_processed = jiffies; 2053 2054 out: 2055 hclgevf_task_schedule(hdev, delta); 2056 } 2057 2058 static void hclgevf_service_task(struct work_struct *work) 2059 { 2060 struct hclgevf_dev *hdev = container_of(work, struct hclgevf_dev, 2061 service_task.work); 2062 2063 hclgevf_reset_service_task(hdev); 2064 hclgevf_mailbox_service_task(hdev); 2065 hclgevf_periodic_service_task(hdev); 2066 2067 /* Handle reset and mbx again in case periodical task delays the 2068 * handling by calling hclgevf_task_schedule() in 2069 * hclgevf_periodic_service_task() 2070 */ 2071 hclgevf_reset_service_task(hdev); 2072 hclgevf_mailbox_service_task(hdev); 2073 } 2074 2075 static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regclr) 2076 { 2077 hclgevf_write_dev(&hdev->hw, HCLGE_COMM_VECTOR0_CMDQ_SRC_REG, regclr); 2078 } 2079 2080 static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev, 2081 u32 *clearval) 2082 { 2083 u32 val, cmdq_stat_reg, rst_ing_reg; 2084 2085 /* fetch the events from their corresponding regs */ 2086 cmdq_stat_reg = hclgevf_read_dev(&hdev->hw, 2087 HCLGE_COMM_VECTOR0_CMDQ_STATE_REG); 2088 if (BIT(HCLGEVF_VECTOR0_RST_INT_B) & cmdq_stat_reg) { 2089 rst_ing_reg = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 2090 dev_info(&hdev->pdev->dev, 2091 "receive reset interrupt 0x%x!\n", rst_ing_reg); 2092 set_bit(HNAE3_VF_RESET, &hdev->reset_pending); 2093 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 2094 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 2095 *clearval = ~(1U << HCLGEVF_VECTOR0_RST_INT_B); 2096 hdev->rst_stats.vf_rst_cnt++; 2097 /* set up VF hardware reset status, its PF will clear 2098 * this status when PF has initialized done. 2099 */ 2100 val = hclgevf_read_dev(&hdev->hw, HCLGEVF_VF_RST_ING); 2101 hclgevf_write_dev(&hdev->hw, HCLGEVF_VF_RST_ING, 2102 val | HCLGEVF_VF_RST_ING_BIT); 2103 return HCLGEVF_VECTOR0_EVENT_RST; 2104 } 2105 2106 /* check for vector0 mailbox(=CMDQ RX) event source */ 2107 if (BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) { 2108 /* for revision 0x21, clearing interrupt is writing bit 0 2109 * to the clear register, writing bit 1 means to keep the 2110 * old value. 2111 * for revision 0x20, the clear register is a read & write 2112 * register, so we should just write 0 to the bit we are 2113 * handling, and keep other bits as cmdq_stat_reg. 2114 */ 2115 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) 2116 *clearval = ~(1U << HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 2117 else 2118 *clearval = cmdq_stat_reg & 2119 ~BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 2120 2121 return HCLGEVF_VECTOR0_EVENT_MBX; 2122 } 2123 2124 /* print other vector0 event source */ 2125 dev_info(&hdev->pdev->dev, 2126 "vector 0 interrupt from unknown source, cmdq_src = %#x\n", 2127 cmdq_stat_reg); 2128 2129 return HCLGEVF_VECTOR0_EVENT_OTHER; 2130 } 2131 2132 static irqreturn_t hclgevf_misc_irq_handle(int irq, void *data) 2133 { 2134 enum hclgevf_evt_cause event_cause; 2135 struct hclgevf_dev *hdev = data; 2136 u32 clearval; 2137 2138 hclgevf_enable_vector(&hdev->misc_vector, false); 2139 event_cause = hclgevf_check_evt_cause(hdev, &clearval); 2140 if (event_cause != HCLGEVF_VECTOR0_EVENT_OTHER) 2141 hclgevf_clear_event_cause(hdev, clearval); 2142 2143 switch (event_cause) { 2144 case HCLGEVF_VECTOR0_EVENT_RST: 2145 hclgevf_reset_task_schedule(hdev); 2146 break; 2147 case HCLGEVF_VECTOR0_EVENT_MBX: 2148 hclgevf_mbx_handler(hdev); 2149 break; 2150 default: 2151 break; 2152 } 2153 2154 if (event_cause != HCLGEVF_VECTOR0_EVENT_OTHER) 2155 hclgevf_enable_vector(&hdev->misc_vector, true); 2156 2157 return IRQ_HANDLED; 2158 } 2159 2160 static int hclgevf_configure(struct hclgevf_dev *hdev) 2161 { 2162 int ret; 2163 2164 hdev->gro_en = true; 2165 2166 ret = hclgevf_get_basic_info(hdev); 2167 if (ret) 2168 return ret; 2169 2170 /* get current port based vlan state from PF */ 2171 ret = hclgevf_get_port_base_vlan_filter_state(hdev); 2172 if (ret) 2173 return ret; 2174 2175 /* get queue configuration from PF */ 2176 ret = hclgevf_get_queue_info(hdev); 2177 if (ret) 2178 return ret; 2179 2180 /* get queue depth info from PF */ 2181 ret = hclgevf_get_queue_depth(hdev); 2182 if (ret) 2183 return ret; 2184 2185 return hclgevf_get_pf_media_type(hdev); 2186 } 2187 2188 static int hclgevf_alloc_hdev(struct hnae3_ae_dev *ae_dev) 2189 { 2190 struct pci_dev *pdev = ae_dev->pdev; 2191 struct hclgevf_dev *hdev; 2192 2193 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 2194 if (!hdev) 2195 return -ENOMEM; 2196 2197 hdev->pdev = pdev; 2198 hdev->ae_dev = ae_dev; 2199 ae_dev->priv = hdev; 2200 2201 return 0; 2202 } 2203 2204 static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev) 2205 { 2206 struct hnae3_handle *roce = &hdev->roce; 2207 struct hnae3_handle *nic = &hdev->nic; 2208 2209 roce->rinfo.num_vectors = hdev->num_roce_msix; 2210 2211 if (hdev->num_msi_left < roce->rinfo.num_vectors || 2212 hdev->num_msi_left == 0) 2213 return -EINVAL; 2214 2215 roce->rinfo.base_vector = hdev->roce_base_msix_offset; 2216 2217 roce->rinfo.netdev = nic->kinfo.netdev; 2218 roce->rinfo.roce_io_base = hdev->hw.hw.io_base; 2219 roce->rinfo.roce_mem_base = hdev->hw.hw.mem_base; 2220 2221 roce->pdev = nic->pdev; 2222 roce->ae_algo = nic->ae_algo; 2223 roce->numa_node_mask = nic->numa_node_mask; 2224 2225 return 0; 2226 } 2227 2228 static int hclgevf_config_gro(struct hclgevf_dev *hdev) 2229 { 2230 struct hclgevf_cfg_gro_status_cmd *req; 2231 struct hclge_desc desc; 2232 int ret; 2233 2234 if (!hnae3_dev_gro_supported(hdev)) 2235 return 0; 2236 2237 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_GRO_GENERIC_CONFIG, 2238 false); 2239 req = (struct hclgevf_cfg_gro_status_cmd *)desc.data; 2240 2241 req->gro_en = hdev->gro_en ? 1 : 0; 2242 2243 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 2244 if (ret) 2245 dev_err(&hdev->pdev->dev, 2246 "VF GRO hardware config cmd failed, ret = %d.\n", ret); 2247 2248 return ret; 2249 } 2250 2251 static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev) 2252 { 2253 struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg; 2254 u16 tc_offset[HCLGE_COMM_MAX_TC_NUM]; 2255 u16 tc_valid[HCLGE_COMM_MAX_TC_NUM]; 2256 u16 tc_size[HCLGE_COMM_MAX_TC_NUM]; 2257 int ret; 2258 2259 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 2260 ret = hclge_comm_set_rss_algo_key(&hdev->hw.hw, 2261 rss_cfg->rss_algo, 2262 rss_cfg->rss_hash_key); 2263 if (ret) 2264 return ret; 2265 2266 ret = hclge_comm_set_rss_input_tuple(&hdev->nic, &hdev->hw.hw, 2267 false, rss_cfg); 2268 if (ret) 2269 return ret; 2270 } 2271 2272 ret = hclge_comm_set_rss_indir_table(hdev->ae_dev, &hdev->hw.hw, 2273 rss_cfg->rss_indirection_tbl); 2274 if (ret) 2275 return ret; 2276 2277 hclge_comm_get_rss_tc_info(rss_cfg->rss_size, hdev->hw_tc_map, 2278 tc_offset, tc_valid, tc_size); 2279 2280 return hclge_comm_set_rss_tc_mode(&hdev->hw.hw, tc_offset, 2281 tc_valid, tc_size); 2282 } 2283 2284 static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev) 2285 { 2286 struct hnae3_handle *nic = &hdev->nic; 2287 int ret; 2288 2289 ret = hclgevf_en_hw_strip_rxvtag(nic, true); 2290 if (ret) { 2291 dev_err(&hdev->pdev->dev, 2292 "failed to enable rx vlan offload, ret = %d\n", ret); 2293 return ret; 2294 } 2295 2296 return hclgevf_set_vlan_filter(&hdev->nic, htons(ETH_P_8021Q), 0, 2297 false); 2298 } 2299 2300 static void hclgevf_flush_link_update(struct hclgevf_dev *hdev) 2301 { 2302 #define HCLGEVF_FLUSH_LINK_TIMEOUT 100000 2303 2304 unsigned long last = hdev->serv_processed_cnt; 2305 int i = 0; 2306 2307 while (test_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state) && 2308 i++ < HCLGEVF_FLUSH_LINK_TIMEOUT && 2309 last == hdev->serv_processed_cnt) 2310 usleep_range(1, 1); 2311 } 2312 2313 static void hclgevf_set_timer_task(struct hnae3_handle *handle, bool enable) 2314 { 2315 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2316 2317 if (enable) { 2318 hclgevf_task_schedule(hdev, 0); 2319 } else { 2320 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2321 2322 /* flush memory to make sure DOWN is seen by service task */ 2323 smp_mb__before_atomic(); 2324 hclgevf_flush_link_update(hdev); 2325 } 2326 } 2327 2328 static int hclgevf_ae_start(struct hnae3_handle *handle) 2329 { 2330 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2331 2332 clear_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2333 clear_bit(HCLGEVF_STATE_PF_PUSH_LINK_STATUS, &hdev->state); 2334 2335 hclgevf_reset_tqp_stats(handle); 2336 2337 hclgevf_request_link_info(hdev); 2338 2339 hclgevf_update_link_mode(hdev); 2340 2341 return 0; 2342 } 2343 2344 static void hclgevf_ae_stop(struct hnae3_handle *handle) 2345 { 2346 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2347 2348 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2349 2350 if (hdev->reset_type != HNAE3_VF_RESET) 2351 hclgevf_reset_tqp(handle); 2352 2353 hclgevf_reset_tqp_stats(handle); 2354 hclgevf_update_link_status(hdev, 0); 2355 } 2356 2357 static int hclgevf_set_alive(struct hnae3_handle *handle, bool alive) 2358 { 2359 #define HCLGEVF_STATE_ALIVE 1 2360 #define HCLGEVF_STATE_NOT_ALIVE 0 2361 2362 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2363 struct hclge_vf_to_pf_msg send_msg; 2364 2365 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_ALIVE, 0); 2366 send_msg.data[0] = alive ? HCLGEVF_STATE_ALIVE : 2367 HCLGEVF_STATE_NOT_ALIVE; 2368 return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 2369 } 2370 2371 static int hclgevf_client_start(struct hnae3_handle *handle) 2372 { 2373 return hclgevf_set_alive(handle, true); 2374 } 2375 2376 static void hclgevf_client_stop(struct hnae3_handle *handle) 2377 { 2378 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2379 int ret; 2380 2381 ret = hclgevf_set_alive(handle, false); 2382 if (ret) 2383 dev_warn(&hdev->pdev->dev, 2384 "%s failed %d\n", __func__, ret); 2385 } 2386 2387 static void hclgevf_state_init(struct hclgevf_dev *hdev) 2388 { 2389 clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 2390 clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 2391 clear_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state); 2392 2393 INIT_DELAYED_WORK(&hdev->service_task, hclgevf_service_task); 2394 2395 mutex_init(&hdev->mbx_resp.mbx_mutex); 2396 sema_init(&hdev->reset_sem, 1); 2397 2398 spin_lock_init(&hdev->mac_table.mac_list_lock); 2399 INIT_LIST_HEAD(&hdev->mac_table.uc_mac_list); 2400 INIT_LIST_HEAD(&hdev->mac_table.mc_mac_list); 2401 2402 /* bring the device down */ 2403 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2404 } 2405 2406 static void hclgevf_state_uninit(struct hclgevf_dev *hdev) 2407 { 2408 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2409 set_bit(HCLGEVF_STATE_REMOVING, &hdev->state); 2410 2411 if (hdev->service_task.work.func) 2412 cancel_delayed_work_sync(&hdev->service_task); 2413 2414 mutex_destroy(&hdev->mbx_resp.mbx_mutex); 2415 } 2416 2417 static int hclgevf_init_msi(struct hclgevf_dev *hdev) 2418 { 2419 struct pci_dev *pdev = hdev->pdev; 2420 int vectors; 2421 int i; 2422 2423 if (hnae3_dev_roce_supported(hdev)) 2424 vectors = pci_alloc_irq_vectors(pdev, 2425 hdev->roce_base_msix_offset + 1, 2426 hdev->num_msi, 2427 PCI_IRQ_MSIX); 2428 else 2429 vectors = pci_alloc_irq_vectors(pdev, HNAE3_MIN_VECTOR_NUM, 2430 hdev->num_msi, 2431 PCI_IRQ_MSI | PCI_IRQ_MSIX); 2432 2433 if (vectors < 0) { 2434 dev_err(&pdev->dev, 2435 "failed(%d) to allocate MSI/MSI-X vectors\n", 2436 vectors); 2437 return vectors; 2438 } 2439 if (vectors < hdev->num_msi) 2440 dev_warn(&hdev->pdev->dev, 2441 "requested %u MSI/MSI-X, but allocated %d MSI/MSI-X\n", 2442 hdev->num_msi, vectors); 2443 2444 hdev->num_msi = vectors; 2445 hdev->num_msi_left = vectors; 2446 2447 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 2448 sizeof(u16), GFP_KERNEL); 2449 if (!hdev->vector_status) { 2450 pci_free_irq_vectors(pdev); 2451 return -ENOMEM; 2452 } 2453 2454 for (i = 0; i < hdev->num_msi; i++) 2455 hdev->vector_status[i] = HCLGEVF_INVALID_VPORT; 2456 2457 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 2458 sizeof(int), GFP_KERNEL); 2459 if (!hdev->vector_irq) { 2460 devm_kfree(&pdev->dev, hdev->vector_status); 2461 pci_free_irq_vectors(pdev); 2462 return -ENOMEM; 2463 } 2464 2465 return 0; 2466 } 2467 2468 static void hclgevf_uninit_msi(struct hclgevf_dev *hdev) 2469 { 2470 struct pci_dev *pdev = hdev->pdev; 2471 2472 devm_kfree(&pdev->dev, hdev->vector_status); 2473 devm_kfree(&pdev->dev, hdev->vector_irq); 2474 pci_free_irq_vectors(pdev); 2475 } 2476 2477 static int hclgevf_misc_irq_init(struct hclgevf_dev *hdev) 2478 { 2479 int ret; 2480 2481 hclgevf_get_misc_vector(hdev); 2482 2483 snprintf(hdev->misc_vector.name, HNAE3_INT_NAME_LEN, "%s-misc-%s", 2484 HCLGEVF_NAME, pci_name(hdev->pdev)); 2485 ret = request_irq(hdev->misc_vector.vector_irq, hclgevf_misc_irq_handle, 2486 0, hdev->misc_vector.name, hdev); 2487 if (ret) { 2488 dev_err(&hdev->pdev->dev, "VF failed to request misc irq(%d)\n", 2489 hdev->misc_vector.vector_irq); 2490 return ret; 2491 } 2492 2493 hclgevf_clear_event_cause(hdev, 0); 2494 2495 /* enable misc. vector(vector 0) */ 2496 hclgevf_enable_vector(&hdev->misc_vector, true); 2497 2498 return ret; 2499 } 2500 2501 static void hclgevf_misc_irq_uninit(struct hclgevf_dev *hdev) 2502 { 2503 /* disable misc vector(vector 0) */ 2504 hclgevf_enable_vector(&hdev->misc_vector, false); 2505 synchronize_irq(hdev->misc_vector.vector_irq); 2506 free_irq(hdev->misc_vector.vector_irq, hdev); 2507 hclgevf_free_vector(hdev, 0); 2508 } 2509 2510 static void hclgevf_info_show(struct hclgevf_dev *hdev) 2511 { 2512 struct device *dev = &hdev->pdev->dev; 2513 2514 dev_info(dev, "VF info begin:\n"); 2515 2516 dev_info(dev, "Task queue pairs numbers: %u\n", hdev->num_tqps); 2517 dev_info(dev, "Desc num per TX queue: %u\n", hdev->num_tx_desc); 2518 dev_info(dev, "Desc num per RX queue: %u\n", hdev->num_rx_desc); 2519 dev_info(dev, "Numbers of vports: %u\n", hdev->num_alloc_vport); 2520 dev_info(dev, "HW tc map: 0x%x\n", hdev->hw_tc_map); 2521 dev_info(dev, "PF media type of this VF: %u\n", 2522 hdev->hw.mac.media_type); 2523 2524 dev_info(dev, "VF info end.\n"); 2525 } 2526 2527 static int hclgevf_init_nic_client_instance(struct hnae3_ae_dev *ae_dev, 2528 struct hnae3_client *client) 2529 { 2530 struct hclgevf_dev *hdev = ae_dev->priv; 2531 int rst_cnt = hdev->rst_stats.rst_cnt; 2532 int ret; 2533 2534 ret = client->ops->init_instance(&hdev->nic); 2535 if (ret) 2536 return ret; 2537 2538 set_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 2539 if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) || 2540 rst_cnt != hdev->rst_stats.rst_cnt) { 2541 clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 2542 2543 client->ops->uninit_instance(&hdev->nic, 0); 2544 return -EBUSY; 2545 } 2546 2547 hnae3_set_client_init_flag(client, ae_dev, 1); 2548 2549 if (netif_msg_drv(&hdev->nic)) 2550 hclgevf_info_show(hdev); 2551 2552 return 0; 2553 } 2554 2555 static int hclgevf_init_roce_client_instance(struct hnae3_ae_dev *ae_dev, 2556 struct hnae3_client *client) 2557 { 2558 struct hclgevf_dev *hdev = ae_dev->priv; 2559 int ret; 2560 2561 if (!hnae3_dev_roce_supported(hdev) || !hdev->roce_client || 2562 !hdev->nic_client) 2563 return 0; 2564 2565 ret = hclgevf_init_roce_base_info(hdev); 2566 if (ret) 2567 return ret; 2568 2569 ret = client->ops->init_instance(&hdev->roce); 2570 if (ret) 2571 return ret; 2572 2573 set_bit(HCLGEVF_STATE_ROCE_REGISTERED, &hdev->state); 2574 hnae3_set_client_init_flag(client, ae_dev, 1); 2575 2576 return 0; 2577 } 2578 2579 static int hclgevf_init_client_instance(struct hnae3_client *client, 2580 struct hnae3_ae_dev *ae_dev) 2581 { 2582 struct hclgevf_dev *hdev = ae_dev->priv; 2583 int ret; 2584 2585 switch (client->type) { 2586 case HNAE3_CLIENT_KNIC: 2587 hdev->nic_client = client; 2588 hdev->nic.client = client; 2589 2590 ret = hclgevf_init_nic_client_instance(ae_dev, client); 2591 if (ret) 2592 goto clear_nic; 2593 2594 ret = hclgevf_init_roce_client_instance(ae_dev, 2595 hdev->roce_client); 2596 if (ret) 2597 goto clear_roce; 2598 2599 break; 2600 case HNAE3_CLIENT_ROCE: 2601 if (hnae3_dev_roce_supported(hdev)) { 2602 hdev->roce_client = client; 2603 hdev->roce.client = client; 2604 } 2605 2606 ret = hclgevf_init_roce_client_instance(ae_dev, client); 2607 if (ret) 2608 goto clear_roce; 2609 2610 break; 2611 default: 2612 return -EINVAL; 2613 } 2614 2615 return 0; 2616 2617 clear_nic: 2618 hdev->nic_client = NULL; 2619 hdev->nic.client = NULL; 2620 return ret; 2621 clear_roce: 2622 hdev->roce_client = NULL; 2623 hdev->roce.client = NULL; 2624 return ret; 2625 } 2626 2627 static void hclgevf_uninit_client_instance(struct hnae3_client *client, 2628 struct hnae3_ae_dev *ae_dev) 2629 { 2630 struct hclgevf_dev *hdev = ae_dev->priv; 2631 2632 /* un-init roce, if it exists */ 2633 if (hdev->roce_client) { 2634 while (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 2635 msleep(HCLGEVF_WAIT_RESET_DONE); 2636 clear_bit(HCLGEVF_STATE_ROCE_REGISTERED, &hdev->state); 2637 2638 hdev->roce_client->ops->uninit_instance(&hdev->roce, 0); 2639 hdev->roce_client = NULL; 2640 hdev->roce.client = NULL; 2641 } 2642 2643 /* un-init nic/unic, if this was not called by roce client */ 2644 if (client->ops->uninit_instance && hdev->nic_client && 2645 client->type != HNAE3_CLIENT_ROCE) { 2646 while (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 2647 msleep(HCLGEVF_WAIT_RESET_DONE); 2648 clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 2649 2650 client->ops->uninit_instance(&hdev->nic, 0); 2651 hdev->nic_client = NULL; 2652 hdev->nic.client = NULL; 2653 } 2654 } 2655 2656 static int hclgevf_dev_mem_map(struct hclgevf_dev *hdev) 2657 { 2658 #define HCLGEVF_MEM_BAR 4 2659 2660 struct pci_dev *pdev = hdev->pdev; 2661 struct hclgevf_hw *hw = &hdev->hw; 2662 2663 /* for device does not have device memory, return directly */ 2664 if (!(pci_select_bars(pdev, IORESOURCE_MEM) & BIT(HCLGEVF_MEM_BAR))) 2665 return 0; 2666 2667 hw->hw.mem_base = 2668 devm_ioremap_wc(&pdev->dev, 2669 pci_resource_start(pdev, HCLGEVF_MEM_BAR), 2670 pci_resource_len(pdev, HCLGEVF_MEM_BAR)); 2671 if (!hw->hw.mem_base) { 2672 dev_err(&pdev->dev, "failed to map device memory\n"); 2673 return -EFAULT; 2674 } 2675 2676 return 0; 2677 } 2678 2679 static int hclgevf_pci_init(struct hclgevf_dev *hdev) 2680 { 2681 struct pci_dev *pdev = hdev->pdev; 2682 struct hclgevf_hw *hw; 2683 int ret; 2684 2685 ret = pci_enable_device(pdev); 2686 if (ret) { 2687 dev_err(&pdev->dev, "failed to enable PCI device\n"); 2688 return ret; 2689 } 2690 2691 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 2692 if (ret) { 2693 dev_err(&pdev->dev, "can't set consistent PCI DMA, exiting"); 2694 goto err_disable_device; 2695 } 2696 2697 ret = pci_request_regions(pdev, HCLGEVF_DRIVER_NAME); 2698 if (ret) { 2699 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 2700 goto err_disable_device; 2701 } 2702 2703 pci_set_master(pdev); 2704 hw = &hdev->hw; 2705 hw->hw.io_base = pci_iomap(pdev, 2, 0); 2706 if (!hw->hw.io_base) { 2707 dev_err(&pdev->dev, "can't map configuration register space\n"); 2708 ret = -ENOMEM; 2709 goto err_clr_master; 2710 } 2711 2712 ret = hclgevf_dev_mem_map(hdev); 2713 if (ret) 2714 goto err_unmap_io_base; 2715 2716 return 0; 2717 2718 err_unmap_io_base: 2719 pci_iounmap(pdev, hdev->hw.hw.io_base); 2720 err_clr_master: 2721 pci_clear_master(pdev); 2722 pci_release_regions(pdev); 2723 err_disable_device: 2724 pci_disable_device(pdev); 2725 2726 return ret; 2727 } 2728 2729 static void hclgevf_pci_uninit(struct hclgevf_dev *hdev) 2730 { 2731 struct pci_dev *pdev = hdev->pdev; 2732 2733 if (hdev->hw.hw.mem_base) 2734 devm_iounmap(&pdev->dev, hdev->hw.hw.mem_base); 2735 2736 pci_iounmap(pdev, hdev->hw.hw.io_base); 2737 pci_clear_master(pdev); 2738 pci_release_regions(pdev); 2739 pci_disable_device(pdev); 2740 } 2741 2742 static int hclgevf_query_vf_resource(struct hclgevf_dev *hdev) 2743 { 2744 struct hclgevf_query_res_cmd *req; 2745 struct hclge_desc desc; 2746 int ret; 2747 2748 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_VF_RSRC, true); 2749 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 2750 if (ret) { 2751 dev_err(&hdev->pdev->dev, 2752 "query vf resource failed, ret = %d.\n", ret); 2753 return ret; 2754 } 2755 2756 req = (struct hclgevf_query_res_cmd *)desc.data; 2757 2758 if (hnae3_dev_roce_supported(hdev)) { 2759 hdev->roce_base_msix_offset = 2760 hnae3_get_field(le16_to_cpu(req->msixcap_localid_ba_rocee), 2761 HCLGEVF_MSIX_OFT_ROCEE_M, 2762 HCLGEVF_MSIX_OFT_ROCEE_S); 2763 hdev->num_roce_msix = 2764 hnae3_get_field(le16_to_cpu(req->vf_intr_vector_number), 2765 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 2766 2767 /* nic's msix numbers is always equals to the roce's. */ 2768 hdev->num_nic_msix = hdev->num_roce_msix; 2769 2770 /* VF should have NIC vectors and Roce vectors, NIC vectors 2771 * are queued before Roce vectors. The offset is fixed to 64. 2772 */ 2773 hdev->num_msi = hdev->num_roce_msix + 2774 hdev->roce_base_msix_offset; 2775 } else { 2776 hdev->num_msi = 2777 hnae3_get_field(le16_to_cpu(req->vf_intr_vector_number), 2778 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 2779 2780 hdev->num_nic_msix = hdev->num_msi; 2781 } 2782 2783 if (hdev->num_nic_msix < HNAE3_MIN_VECTOR_NUM) { 2784 dev_err(&hdev->pdev->dev, 2785 "Just %u msi resources, not enough for vf(min:2).\n", 2786 hdev->num_nic_msix); 2787 return -EINVAL; 2788 } 2789 2790 return 0; 2791 } 2792 2793 static void hclgevf_set_default_dev_specs(struct hclgevf_dev *hdev) 2794 { 2795 #define HCLGEVF_MAX_NON_TSO_BD_NUM 8U 2796 2797 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 2798 2799 ae_dev->dev_specs.max_non_tso_bd_num = 2800 HCLGEVF_MAX_NON_TSO_BD_NUM; 2801 ae_dev->dev_specs.rss_ind_tbl_size = HCLGEVF_RSS_IND_TBL_SIZE; 2802 ae_dev->dev_specs.rss_key_size = HCLGE_COMM_RSS_KEY_SIZE; 2803 ae_dev->dev_specs.max_int_gl = HCLGEVF_DEF_MAX_INT_GL; 2804 ae_dev->dev_specs.max_frm_size = HCLGEVF_MAC_MAX_FRAME; 2805 } 2806 2807 static void hclgevf_parse_dev_specs(struct hclgevf_dev *hdev, 2808 struct hclge_desc *desc) 2809 { 2810 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 2811 struct hclgevf_dev_specs_0_cmd *req0; 2812 struct hclgevf_dev_specs_1_cmd *req1; 2813 2814 req0 = (struct hclgevf_dev_specs_0_cmd *)desc[0].data; 2815 req1 = (struct hclgevf_dev_specs_1_cmd *)desc[1].data; 2816 2817 ae_dev->dev_specs.max_non_tso_bd_num = req0->max_non_tso_bd_num; 2818 ae_dev->dev_specs.rss_ind_tbl_size = 2819 le16_to_cpu(req0->rss_ind_tbl_size); 2820 ae_dev->dev_specs.int_ql_max = le16_to_cpu(req0->int_ql_max); 2821 ae_dev->dev_specs.rss_key_size = le16_to_cpu(req0->rss_key_size); 2822 ae_dev->dev_specs.max_int_gl = le16_to_cpu(req1->max_int_gl); 2823 ae_dev->dev_specs.max_frm_size = le16_to_cpu(req1->max_frm_size); 2824 } 2825 2826 static void hclgevf_check_dev_specs(struct hclgevf_dev *hdev) 2827 { 2828 struct hnae3_dev_specs *dev_specs = &hdev->ae_dev->dev_specs; 2829 2830 if (!dev_specs->max_non_tso_bd_num) 2831 dev_specs->max_non_tso_bd_num = HCLGEVF_MAX_NON_TSO_BD_NUM; 2832 if (!dev_specs->rss_ind_tbl_size) 2833 dev_specs->rss_ind_tbl_size = HCLGEVF_RSS_IND_TBL_SIZE; 2834 if (!dev_specs->rss_key_size) 2835 dev_specs->rss_key_size = HCLGE_COMM_RSS_KEY_SIZE; 2836 if (!dev_specs->max_int_gl) 2837 dev_specs->max_int_gl = HCLGEVF_DEF_MAX_INT_GL; 2838 if (!dev_specs->max_frm_size) 2839 dev_specs->max_frm_size = HCLGEVF_MAC_MAX_FRAME; 2840 } 2841 2842 static int hclgevf_query_dev_specs(struct hclgevf_dev *hdev) 2843 { 2844 struct hclge_desc desc[HCLGEVF_QUERY_DEV_SPECS_BD_NUM]; 2845 int ret; 2846 int i; 2847 2848 /* set default specifications as devices lower than version V3 do not 2849 * support querying specifications from firmware. 2850 */ 2851 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3) { 2852 hclgevf_set_default_dev_specs(hdev); 2853 return 0; 2854 } 2855 2856 for (i = 0; i < HCLGEVF_QUERY_DEV_SPECS_BD_NUM - 1; i++) { 2857 hclgevf_cmd_setup_basic_desc(&desc[i], 2858 HCLGEVF_OPC_QUERY_DEV_SPECS, true); 2859 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2860 } 2861 hclgevf_cmd_setup_basic_desc(&desc[i], HCLGEVF_OPC_QUERY_DEV_SPECS, 2862 true); 2863 2864 ret = hclgevf_cmd_send(&hdev->hw, desc, HCLGEVF_QUERY_DEV_SPECS_BD_NUM); 2865 if (ret) 2866 return ret; 2867 2868 hclgevf_parse_dev_specs(hdev, desc); 2869 hclgevf_check_dev_specs(hdev); 2870 2871 return 0; 2872 } 2873 2874 static int hclgevf_pci_reset(struct hclgevf_dev *hdev) 2875 { 2876 struct pci_dev *pdev = hdev->pdev; 2877 int ret = 0; 2878 2879 if (hdev->reset_type == HNAE3_VF_FULL_RESET && 2880 test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2881 hclgevf_misc_irq_uninit(hdev); 2882 hclgevf_uninit_msi(hdev); 2883 clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2884 } 2885 2886 if (!test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2887 pci_set_master(pdev); 2888 ret = hclgevf_init_msi(hdev); 2889 if (ret) { 2890 dev_err(&pdev->dev, 2891 "failed(%d) to init MSI/MSI-X\n", ret); 2892 return ret; 2893 } 2894 2895 ret = hclgevf_misc_irq_init(hdev); 2896 if (ret) { 2897 hclgevf_uninit_msi(hdev); 2898 dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 2899 ret); 2900 return ret; 2901 } 2902 2903 set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2904 } 2905 2906 return ret; 2907 } 2908 2909 static int hclgevf_clear_vport_list(struct hclgevf_dev *hdev) 2910 { 2911 struct hclge_vf_to_pf_msg send_msg; 2912 2913 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_HANDLE_VF_TBL, 2914 HCLGE_MBX_VPORT_LIST_CLEAR); 2915 return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 2916 } 2917 2918 static void hclgevf_init_rxd_adv_layout(struct hclgevf_dev *hdev) 2919 { 2920 if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev)) 2921 hclgevf_write_dev(&hdev->hw, HCLGEVF_RXD_ADV_LAYOUT_EN_REG, 1); 2922 } 2923 2924 static void hclgevf_uninit_rxd_adv_layout(struct hclgevf_dev *hdev) 2925 { 2926 if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev)) 2927 hclgevf_write_dev(&hdev->hw, HCLGEVF_RXD_ADV_LAYOUT_EN_REG, 0); 2928 } 2929 2930 static int hclgevf_reset_hdev(struct hclgevf_dev *hdev) 2931 { 2932 struct pci_dev *pdev = hdev->pdev; 2933 int ret; 2934 2935 ret = hclgevf_pci_reset(hdev); 2936 if (ret) { 2937 dev_err(&pdev->dev, "pci reset failed %d\n", ret); 2938 return ret; 2939 } 2940 2941 hclgevf_arq_init(hdev); 2942 ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw, 2943 &hdev->fw_version, false, 2944 hdev->reset_pending); 2945 if (ret) { 2946 dev_err(&pdev->dev, "cmd failed %d\n", ret); 2947 return ret; 2948 } 2949 2950 ret = hclgevf_rss_init_hw(hdev); 2951 if (ret) { 2952 dev_err(&hdev->pdev->dev, 2953 "failed(%d) to initialize RSS\n", ret); 2954 return ret; 2955 } 2956 2957 ret = hclgevf_config_gro(hdev); 2958 if (ret) 2959 return ret; 2960 2961 ret = hclgevf_init_vlan_config(hdev); 2962 if (ret) { 2963 dev_err(&hdev->pdev->dev, 2964 "failed(%d) to initialize VLAN config\n", ret); 2965 return ret; 2966 } 2967 2968 set_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state); 2969 2970 hclgevf_init_rxd_adv_layout(hdev); 2971 2972 dev_info(&hdev->pdev->dev, "Reset done\n"); 2973 2974 return 0; 2975 } 2976 2977 static int hclgevf_init_hdev(struct hclgevf_dev *hdev) 2978 { 2979 struct pci_dev *pdev = hdev->pdev; 2980 int ret; 2981 2982 ret = hclgevf_pci_init(hdev); 2983 if (ret) 2984 return ret; 2985 2986 ret = hclgevf_devlink_init(hdev); 2987 if (ret) 2988 goto err_devlink_init; 2989 2990 ret = hclge_comm_cmd_queue_init(hdev->pdev, &hdev->hw.hw); 2991 if (ret) 2992 goto err_cmd_queue_init; 2993 2994 hclgevf_arq_init(hdev); 2995 ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw, 2996 &hdev->fw_version, false, 2997 hdev->reset_pending); 2998 if (ret) 2999 goto err_cmd_init; 3000 3001 /* Get vf resource */ 3002 ret = hclgevf_query_vf_resource(hdev); 3003 if (ret) 3004 goto err_cmd_init; 3005 3006 ret = hclgevf_query_dev_specs(hdev); 3007 if (ret) { 3008 dev_err(&pdev->dev, 3009 "failed to query dev specifications, ret = %d\n", ret); 3010 goto err_cmd_init; 3011 } 3012 3013 ret = hclgevf_init_msi(hdev); 3014 if (ret) { 3015 dev_err(&pdev->dev, "failed(%d) to init MSI/MSI-X\n", ret); 3016 goto err_cmd_init; 3017 } 3018 3019 hclgevf_state_init(hdev); 3020 hdev->reset_level = HNAE3_VF_FUNC_RESET; 3021 hdev->reset_type = HNAE3_NONE_RESET; 3022 3023 ret = hclgevf_misc_irq_init(hdev); 3024 if (ret) 3025 goto err_misc_irq_init; 3026 3027 set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 3028 3029 ret = hclgevf_configure(hdev); 3030 if (ret) { 3031 dev_err(&pdev->dev, "failed(%d) to fetch configuration\n", ret); 3032 goto err_config; 3033 } 3034 3035 ret = hclgevf_alloc_tqps(hdev); 3036 if (ret) { 3037 dev_err(&pdev->dev, "failed(%d) to allocate TQPs\n", ret); 3038 goto err_config; 3039 } 3040 3041 ret = hclgevf_set_handle_info(hdev); 3042 if (ret) 3043 goto err_config; 3044 3045 ret = hclgevf_config_gro(hdev); 3046 if (ret) 3047 goto err_config; 3048 3049 /* Initialize RSS for this VF */ 3050 ret = hclge_comm_rss_init_cfg(&hdev->nic, hdev->ae_dev, 3051 &hdev->rss_cfg); 3052 if (ret) { 3053 dev_err(&pdev->dev, "failed to init rss cfg, ret = %d\n", ret); 3054 goto err_config; 3055 } 3056 3057 ret = hclgevf_rss_init_hw(hdev); 3058 if (ret) { 3059 dev_err(&hdev->pdev->dev, 3060 "failed(%d) to initialize RSS\n", ret); 3061 goto err_config; 3062 } 3063 3064 /* ensure vf tbl list as empty before init*/ 3065 ret = hclgevf_clear_vport_list(hdev); 3066 if (ret) { 3067 dev_err(&pdev->dev, 3068 "failed to clear tbl list configuration, ret = %d.\n", 3069 ret); 3070 goto err_config; 3071 } 3072 3073 ret = hclgevf_init_vlan_config(hdev); 3074 if (ret) { 3075 dev_err(&hdev->pdev->dev, 3076 "failed(%d) to initialize VLAN config\n", ret); 3077 goto err_config; 3078 } 3079 3080 hclgevf_init_rxd_adv_layout(hdev); 3081 3082 set_bit(HCLGEVF_STATE_SERVICE_INITED, &hdev->state); 3083 3084 hdev->last_reset_time = jiffies; 3085 dev_info(&hdev->pdev->dev, "finished initializing %s driver\n", 3086 HCLGEVF_DRIVER_NAME); 3087 3088 hclgevf_task_schedule(hdev, round_jiffies_relative(HZ)); 3089 3090 return 0; 3091 3092 err_config: 3093 hclgevf_misc_irq_uninit(hdev); 3094 err_misc_irq_init: 3095 hclgevf_state_uninit(hdev); 3096 hclgevf_uninit_msi(hdev); 3097 err_cmd_init: 3098 hclge_comm_cmd_uninit(hdev->ae_dev, &hdev->hw.hw); 3099 err_cmd_queue_init: 3100 hclgevf_devlink_uninit(hdev); 3101 err_devlink_init: 3102 hclgevf_pci_uninit(hdev); 3103 clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 3104 return ret; 3105 } 3106 3107 static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev) 3108 { 3109 struct hclge_vf_to_pf_msg send_msg; 3110 3111 hclgevf_state_uninit(hdev); 3112 hclgevf_uninit_rxd_adv_layout(hdev); 3113 3114 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_VF_UNINIT, 0); 3115 hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 3116 3117 if (test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 3118 hclgevf_misc_irq_uninit(hdev); 3119 hclgevf_uninit_msi(hdev); 3120 } 3121 3122 hclge_comm_cmd_uninit(hdev->ae_dev, &hdev->hw.hw); 3123 hclgevf_devlink_uninit(hdev); 3124 hclgevf_pci_uninit(hdev); 3125 hclgevf_uninit_mac_list(hdev); 3126 } 3127 3128 static int hclgevf_init_ae_dev(struct hnae3_ae_dev *ae_dev) 3129 { 3130 struct pci_dev *pdev = ae_dev->pdev; 3131 int ret; 3132 3133 ret = hclgevf_alloc_hdev(ae_dev); 3134 if (ret) { 3135 dev_err(&pdev->dev, "hclge device allocation failed\n"); 3136 return ret; 3137 } 3138 3139 ret = hclgevf_init_hdev(ae_dev->priv); 3140 if (ret) { 3141 dev_err(&pdev->dev, "hclge device initialization failed\n"); 3142 return ret; 3143 } 3144 3145 return 0; 3146 } 3147 3148 static void hclgevf_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 3149 { 3150 struct hclgevf_dev *hdev = ae_dev->priv; 3151 3152 hclgevf_uninit_hdev(hdev); 3153 ae_dev->priv = NULL; 3154 } 3155 3156 static u32 hclgevf_get_max_channels(struct hclgevf_dev *hdev) 3157 { 3158 struct hnae3_handle *nic = &hdev->nic; 3159 struct hnae3_knic_private_info *kinfo = &nic->kinfo; 3160 3161 return min_t(u32, hdev->rss_size_max, 3162 hdev->num_tqps / kinfo->tc_info.num_tc); 3163 } 3164 3165 /** 3166 * hclgevf_get_channels - Get the current channels enabled and max supported. 3167 * @handle: hardware information for network interface 3168 * @ch: ethtool channels structure 3169 * 3170 * We don't support separate tx and rx queues as channels. The other count 3171 * represents how many queues are being used for control. max_combined counts 3172 * how many queue pairs we can support. They may not be mapped 1 to 1 with 3173 * q_vectors since we support a lot more queue pairs than q_vectors. 3174 **/ 3175 static void hclgevf_get_channels(struct hnae3_handle *handle, 3176 struct ethtool_channels *ch) 3177 { 3178 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3179 3180 ch->max_combined = hclgevf_get_max_channels(hdev); 3181 ch->other_count = 0; 3182 ch->max_other = 0; 3183 ch->combined_count = handle->kinfo.rss_size; 3184 } 3185 3186 static void hclgevf_get_tqps_and_rss_info(struct hnae3_handle *handle, 3187 u16 *alloc_tqps, u16 *max_rss_size) 3188 { 3189 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3190 3191 *alloc_tqps = hdev->num_tqps; 3192 *max_rss_size = hdev->rss_size_max; 3193 } 3194 3195 static void hclgevf_update_rss_size(struct hnae3_handle *handle, 3196 u32 new_tqps_num) 3197 { 3198 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 3199 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3200 u16 max_rss_size; 3201 3202 kinfo->req_rss_size = new_tqps_num; 3203 3204 max_rss_size = min_t(u16, hdev->rss_size_max, 3205 hdev->num_tqps / kinfo->tc_info.num_tc); 3206 3207 /* Use the user's configuration when it is not larger than 3208 * max_rss_size, otherwise, use the maximum specification value. 3209 */ 3210 if (kinfo->req_rss_size != kinfo->rss_size && kinfo->req_rss_size && 3211 kinfo->req_rss_size <= max_rss_size) 3212 kinfo->rss_size = kinfo->req_rss_size; 3213 else if (kinfo->rss_size > max_rss_size || 3214 (!kinfo->req_rss_size && kinfo->rss_size < max_rss_size)) 3215 kinfo->rss_size = max_rss_size; 3216 3217 kinfo->num_tqps = kinfo->tc_info.num_tc * kinfo->rss_size; 3218 } 3219 3220 static int hclgevf_set_channels(struct hnae3_handle *handle, u32 new_tqps_num, 3221 bool rxfh_configured) 3222 { 3223 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3224 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 3225 u16 tc_offset[HCLGE_COMM_MAX_TC_NUM]; 3226 u16 tc_valid[HCLGE_COMM_MAX_TC_NUM]; 3227 u16 tc_size[HCLGE_COMM_MAX_TC_NUM]; 3228 u16 cur_rss_size = kinfo->rss_size; 3229 u16 cur_tqps = kinfo->num_tqps; 3230 u32 *rss_indir; 3231 unsigned int i; 3232 int ret; 3233 3234 hclgevf_update_rss_size(handle, new_tqps_num); 3235 3236 hclge_comm_get_rss_tc_info(cur_rss_size, hdev->hw_tc_map, 3237 tc_offset, tc_valid, tc_size); 3238 ret = hclge_comm_set_rss_tc_mode(&hdev->hw.hw, tc_offset, 3239 tc_valid, tc_size); 3240 if (ret) 3241 return ret; 3242 3243 /* RSS indirection table has been configured by user */ 3244 if (rxfh_configured) 3245 goto out; 3246 3247 /* Reinitializes the rss indirect table according to the new RSS size */ 3248 rss_indir = kcalloc(hdev->ae_dev->dev_specs.rss_ind_tbl_size, 3249 sizeof(u32), GFP_KERNEL); 3250 if (!rss_indir) 3251 return -ENOMEM; 3252 3253 for (i = 0; i < hdev->ae_dev->dev_specs.rss_ind_tbl_size; i++) 3254 rss_indir[i] = i % kinfo->rss_size; 3255 3256 hdev->rss_cfg.rss_size = kinfo->rss_size; 3257 3258 ret = hclgevf_set_rss(handle, rss_indir, NULL, 0); 3259 if (ret) 3260 dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n", 3261 ret); 3262 3263 kfree(rss_indir); 3264 3265 out: 3266 if (!ret) 3267 dev_info(&hdev->pdev->dev, 3268 "Channels changed, rss_size from %u to %u, tqps from %u to %u", 3269 cur_rss_size, kinfo->rss_size, 3270 cur_tqps, kinfo->rss_size * kinfo->tc_info.num_tc); 3271 3272 return ret; 3273 } 3274 3275 static int hclgevf_get_status(struct hnae3_handle *handle) 3276 { 3277 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3278 3279 return hdev->hw.mac.link; 3280 } 3281 3282 static void hclgevf_get_ksettings_an_result(struct hnae3_handle *handle, 3283 u8 *auto_neg, u32 *speed, 3284 u8 *duplex) 3285 { 3286 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3287 3288 if (speed) 3289 *speed = hdev->hw.mac.speed; 3290 if (duplex) 3291 *duplex = hdev->hw.mac.duplex; 3292 if (auto_neg) 3293 *auto_neg = AUTONEG_DISABLE; 3294 } 3295 3296 void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed, 3297 u8 duplex) 3298 { 3299 hdev->hw.mac.speed = speed; 3300 hdev->hw.mac.duplex = duplex; 3301 } 3302 3303 static int hclgevf_gro_en(struct hnae3_handle *handle, bool enable) 3304 { 3305 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3306 bool gro_en_old = hdev->gro_en; 3307 int ret; 3308 3309 hdev->gro_en = enable; 3310 ret = hclgevf_config_gro(hdev); 3311 if (ret) 3312 hdev->gro_en = gro_en_old; 3313 3314 return ret; 3315 } 3316 3317 static void hclgevf_get_media_type(struct hnae3_handle *handle, u8 *media_type, 3318 u8 *module_type) 3319 { 3320 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3321 3322 if (media_type) 3323 *media_type = hdev->hw.mac.media_type; 3324 3325 if (module_type) 3326 *module_type = hdev->hw.mac.module_type; 3327 } 3328 3329 static bool hclgevf_get_hw_reset_stat(struct hnae3_handle *handle) 3330 { 3331 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3332 3333 return !!hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 3334 } 3335 3336 static bool hclgevf_get_cmdq_stat(struct hnae3_handle *handle) 3337 { 3338 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3339 3340 return test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 3341 } 3342 3343 static bool hclgevf_ae_dev_resetting(struct hnae3_handle *handle) 3344 { 3345 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3346 3347 return test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 3348 } 3349 3350 static unsigned long hclgevf_ae_dev_reset_cnt(struct hnae3_handle *handle) 3351 { 3352 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3353 3354 return hdev->rst_stats.hw_rst_done_cnt; 3355 } 3356 3357 static void hclgevf_get_link_mode(struct hnae3_handle *handle, 3358 unsigned long *supported, 3359 unsigned long *advertising) 3360 { 3361 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3362 3363 *supported = hdev->hw.mac.supported; 3364 *advertising = hdev->hw.mac.advertising; 3365 } 3366 3367 #define MAX_SEPARATE_NUM 4 3368 #define SEPARATOR_VALUE 0xFDFCFBFA 3369 #define REG_NUM_PER_LINE 4 3370 #define REG_LEN_PER_LINE (REG_NUM_PER_LINE * sizeof(u32)) 3371 3372 static int hclgevf_get_regs_len(struct hnae3_handle *handle) 3373 { 3374 int cmdq_lines, common_lines, ring_lines, tqp_intr_lines; 3375 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3376 3377 cmdq_lines = sizeof(cmdq_reg_addr_list) / REG_LEN_PER_LINE + 1; 3378 common_lines = sizeof(common_reg_addr_list) / REG_LEN_PER_LINE + 1; 3379 ring_lines = sizeof(ring_reg_addr_list) / REG_LEN_PER_LINE + 1; 3380 tqp_intr_lines = sizeof(tqp_intr_reg_addr_list) / REG_LEN_PER_LINE + 1; 3381 3382 return (cmdq_lines + common_lines + ring_lines * hdev->num_tqps + 3383 tqp_intr_lines * (hdev->num_msi_used - 1)) * REG_LEN_PER_LINE; 3384 } 3385 3386 static void hclgevf_get_regs(struct hnae3_handle *handle, u32 *version, 3387 void *data) 3388 { 3389 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3390 int i, j, reg_um, separator_num; 3391 u32 *reg = data; 3392 3393 *version = hdev->fw_version; 3394 3395 /* fetching per-VF registers values from VF PCIe register space */ 3396 reg_um = sizeof(cmdq_reg_addr_list) / sizeof(u32); 3397 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 3398 for (i = 0; i < reg_um; i++) 3399 *reg++ = hclgevf_read_dev(&hdev->hw, cmdq_reg_addr_list[i]); 3400 for (i = 0; i < separator_num; i++) 3401 *reg++ = SEPARATOR_VALUE; 3402 3403 reg_um = sizeof(common_reg_addr_list) / sizeof(u32); 3404 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 3405 for (i = 0; i < reg_um; i++) 3406 *reg++ = hclgevf_read_dev(&hdev->hw, common_reg_addr_list[i]); 3407 for (i = 0; i < separator_num; i++) 3408 *reg++ = SEPARATOR_VALUE; 3409 3410 reg_um = sizeof(ring_reg_addr_list) / sizeof(u32); 3411 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 3412 for (j = 0; j < hdev->num_tqps; j++) { 3413 for (i = 0; i < reg_um; i++) 3414 *reg++ = hclgevf_read_dev(&hdev->hw, 3415 ring_reg_addr_list[i] + 3416 0x200 * j); 3417 for (i = 0; i < separator_num; i++) 3418 *reg++ = SEPARATOR_VALUE; 3419 } 3420 3421 reg_um = sizeof(tqp_intr_reg_addr_list) / sizeof(u32); 3422 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 3423 for (j = 0; j < hdev->num_msi_used - 1; j++) { 3424 for (i = 0; i < reg_um; i++) 3425 *reg++ = hclgevf_read_dev(&hdev->hw, 3426 tqp_intr_reg_addr_list[i] + 3427 4 * j); 3428 for (i = 0; i < separator_num; i++) 3429 *reg++ = SEPARATOR_VALUE; 3430 } 3431 } 3432 3433 void hclgevf_update_port_base_vlan_info(struct hclgevf_dev *hdev, u16 state, 3434 u8 *port_base_vlan_info, u8 data_size) 3435 { 3436 struct hnae3_handle *nic = &hdev->nic; 3437 struct hclge_vf_to_pf_msg send_msg; 3438 int ret; 3439 3440 rtnl_lock(); 3441 3442 if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) || 3443 test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) { 3444 dev_warn(&hdev->pdev->dev, 3445 "is resetting when updating port based vlan info\n"); 3446 rtnl_unlock(); 3447 return; 3448 } 3449 3450 ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 3451 if (ret) { 3452 rtnl_unlock(); 3453 return; 3454 } 3455 3456 /* send msg to PF and wait update port based vlan info */ 3457 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 3458 HCLGE_MBX_PORT_BASE_VLAN_CFG); 3459 memcpy(send_msg.data, port_base_vlan_info, data_size); 3460 ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 3461 if (!ret) { 3462 if (state == HNAE3_PORT_BASE_VLAN_DISABLE) 3463 nic->port_base_vlan_state = state; 3464 else 3465 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_ENABLE; 3466 } 3467 3468 hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 3469 rtnl_unlock(); 3470 } 3471 3472 static const struct hnae3_ae_ops hclgevf_ops = { 3473 .init_ae_dev = hclgevf_init_ae_dev, 3474 .uninit_ae_dev = hclgevf_uninit_ae_dev, 3475 .reset_prepare = hclgevf_reset_prepare_general, 3476 .reset_done = hclgevf_reset_done, 3477 .init_client_instance = hclgevf_init_client_instance, 3478 .uninit_client_instance = hclgevf_uninit_client_instance, 3479 .start = hclgevf_ae_start, 3480 .stop = hclgevf_ae_stop, 3481 .client_start = hclgevf_client_start, 3482 .client_stop = hclgevf_client_stop, 3483 .map_ring_to_vector = hclgevf_map_ring_to_vector, 3484 .unmap_ring_from_vector = hclgevf_unmap_ring_from_vector, 3485 .get_vector = hclgevf_get_vector, 3486 .put_vector = hclgevf_put_vector, 3487 .reset_queue = hclgevf_reset_tqp, 3488 .get_mac_addr = hclgevf_get_mac_addr, 3489 .set_mac_addr = hclgevf_set_mac_addr, 3490 .add_uc_addr = hclgevf_add_uc_addr, 3491 .rm_uc_addr = hclgevf_rm_uc_addr, 3492 .add_mc_addr = hclgevf_add_mc_addr, 3493 .rm_mc_addr = hclgevf_rm_mc_addr, 3494 .get_stats = hclgevf_get_stats, 3495 .update_stats = hclgevf_update_stats, 3496 .get_strings = hclgevf_get_strings, 3497 .get_sset_count = hclgevf_get_sset_count, 3498 .get_rss_key_size = hclge_comm_get_rss_key_size, 3499 .get_rss = hclgevf_get_rss, 3500 .set_rss = hclgevf_set_rss, 3501 .get_rss_tuple = hclgevf_get_rss_tuple, 3502 .set_rss_tuple = hclgevf_set_rss_tuple, 3503 .get_tc_size = hclgevf_get_tc_size, 3504 .get_fw_version = hclgevf_get_fw_version, 3505 .set_vlan_filter = hclgevf_set_vlan_filter, 3506 .enable_vlan_filter = hclgevf_enable_vlan_filter, 3507 .enable_hw_strip_rxvtag = hclgevf_en_hw_strip_rxvtag, 3508 .reset_event = hclgevf_reset_event, 3509 .set_default_reset_request = hclgevf_set_def_reset_request, 3510 .set_channels = hclgevf_set_channels, 3511 .get_channels = hclgevf_get_channels, 3512 .get_tqps_and_rss_info = hclgevf_get_tqps_and_rss_info, 3513 .get_regs_len = hclgevf_get_regs_len, 3514 .get_regs = hclgevf_get_regs, 3515 .get_status = hclgevf_get_status, 3516 .get_ksettings_an_result = hclgevf_get_ksettings_an_result, 3517 .get_media_type = hclgevf_get_media_type, 3518 .get_hw_reset_stat = hclgevf_get_hw_reset_stat, 3519 .ae_dev_resetting = hclgevf_ae_dev_resetting, 3520 .ae_dev_reset_cnt = hclgevf_ae_dev_reset_cnt, 3521 .set_gro_en = hclgevf_gro_en, 3522 .set_mtu = hclgevf_set_mtu, 3523 .get_global_queue_id = hclgevf_get_qid_global, 3524 .set_timer_task = hclgevf_set_timer_task, 3525 .get_link_mode = hclgevf_get_link_mode, 3526 .set_promisc_mode = hclgevf_set_promisc_mode, 3527 .request_update_promisc_mode = hclgevf_request_update_promisc_mode, 3528 .get_cmdq_stat = hclgevf_get_cmdq_stat, 3529 }; 3530 3531 static struct hnae3_ae_algo ae_algovf = { 3532 .ops = &hclgevf_ops, 3533 .pdev_id_table = ae_algovf_pci_tbl, 3534 }; 3535 3536 static int hclgevf_init(void) 3537 { 3538 pr_info("%s is initializing\n", HCLGEVF_NAME); 3539 3540 hclgevf_wq = alloc_workqueue("%s", WQ_UNBOUND, 0, HCLGEVF_NAME); 3541 if (!hclgevf_wq) { 3542 pr_err("%s: failed to create workqueue\n", HCLGEVF_NAME); 3543 return -ENOMEM; 3544 } 3545 3546 hnae3_register_ae_algo(&ae_algovf); 3547 3548 return 0; 3549 } 3550 3551 static void hclgevf_exit(void) 3552 { 3553 hnae3_unregister_ae_algo(&ae_algovf); 3554 destroy_workqueue(hclgevf_wq); 3555 } 3556 module_init(hclgevf_init); 3557 module_exit(hclgevf_exit); 3558 3559 MODULE_LICENSE("GPL"); 3560 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 3561 MODULE_DESCRIPTION("HCLGEVF Driver"); 3562 MODULE_VERSION(HCLGEVF_MOD_VERSION); 3563