1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/etherdevice.h> 5 #include <linux/iopoll.h> 6 #include <net/rtnetlink.h> 7 #include "hclgevf_cmd.h" 8 #include "hclgevf_main.h" 9 #include "hclgevf_regs.h" 10 #include "hclge_mbx.h" 11 #include "hnae3.h" 12 #include "hclgevf_devlink.h" 13 #include "hclge_comm_rss.h" 14 15 #define HCLGEVF_NAME "hclgevf" 16 17 #define HCLGEVF_RESET_MAX_FAIL_CNT 5 18 19 static int hclgevf_reset_hdev(struct hclgevf_dev *hdev); 20 static void hclgevf_task_schedule(struct hclgevf_dev *hdev, 21 unsigned long delay); 22 23 static struct hnae3_ae_algo ae_algovf; 24 25 static struct workqueue_struct *hclgevf_wq; 26 27 static const struct pci_device_id ae_algovf_pci_tbl[] = { 28 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_VF), 0}, 29 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF), 30 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 31 /* required last entry */ 32 {0, } 33 }; 34 35 MODULE_DEVICE_TABLE(pci, ae_algovf_pci_tbl); 36 37 /* hclgevf_cmd_send - send command to command queue 38 * @hw: pointer to the hw struct 39 * @desc: prefilled descriptor for describing the command 40 * @num : the number of descriptors to be sent 41 * 42 * This is the main send command for command queue, it 43 * sends the queue, cleans the queue, etc 44 */ 45 int hclgevf_cmd_send(struct hclgevf_hw *hw, struct hclge_desc *desc, int num) 46 { 47 return hclge_comm_cmd_send(&hw->hw, desc, num); 48 } 49 50 void hclgevf_arq_init(struct hclgevf_dev *hdev) 51 { 52 struct hclge_comm_cmq *cmdq = &hdev->hw.hw.cmq; 53 54 spin_lock(&cmdq->crq.lock); 55 /* initialize the pointers of async rx queue of mailbox */ 56 hdev->arq.hdev = hdev; 57 hdev->arq.head = 0; 58 hdev->arq.tail = 0; 59 atomic_set(&hdev->arq.count, 0); 60 spin_unlock(&cmdq->crq.lock); 61 } 62 63 struct hclgevf_dev *hclgevf_ae_get_hdev(struct hnae3_handle *handle) 64 { 65 if (!handle->client) 66 return container_of(handle, struct hclgevf_dev, nic); 67 else if (handle->client->type == HNAE3_CLIENT_ROCE) 68 return container_of(handle, struct hclgevf_dev, roce); 69 else 70 return container_of(handle, struct hclgevf_dev, nic); 71 } 72 73 static void hclgevf_update_stats(struct hnae3_handle *handle) 74 { 75 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 76 int status; 77 78 status = hclge_comm_tqps_update_stats(handle, &hdev->hw.hw); 79 if (status) 80 dev_err(&hdev->pdev->dev, 81 "VF update of TQPS stats fail, status = %d.\n", 82 status); 83 } 84 85 static int hclgevf_get_sset_count(struct hnae3_handle *handle, int strset) 86 { 87 if (strset == ETH_SS_TEST) 88 return -EOPNOTSUPP; 89 else if (strset == ETH_SS_STATS) 90 return hclge_comm_tqps_get_sset_count(handle); 91 92 return 0; 93 } 94 95 static void hclgevf_get_strings(struct hnae3_handle *handle, u32 strset, 96 u8 *data) 97 { 98 u8 *p = (char *)data; 99 100 if (strset == ETH_SS_STATS) 101 p = hclge_comm_tqps_get_strings(handle, p); 102 } 103 104 static void hclgevf_get_stats(struct hnae3_handle *handle, u64 *data) 105 { 106 hclge_comm_tqps_get_stats(handle, data); 107 } 108 109 static void hclgevf_build_send_msg(struct hclge_vf_to_pf_msg *msg, u8 code, 110 u8 subcode) 111 { 112 if (msg) { 113 memset(msg, 0, sizeof(struct hclge_vf_to_pf_msg)); 114 msg->code = code; 115 msg->subcode = subcode; 116 } 117 } 118 119 static int hclgevf_get_basic_info(struct hclgevf_dev *hdev) 120 { 121 struct hnae3_ae_dev *ae_dev = hdev->ae_dev; 122 u8 resp_msg[HCLGE_MBX_MAX_RESP_DATA_SIZE]; 123 struct hclge_basic_info *basic_info; 124 struct hclge_vf_to_pf_msg send_msg; 125 unsigned long caps; 126 int status; 127 128 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_BASIC_INFO, 0); 129 status = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 130 sizeof(resp_msg)); 131 if (status) { 132 dev_err(&hdev->pdev->dev, 133 "failed to get basic info from pf, ret = %d", status); 134 return status; 135 } 136 137 basic_info = (struct hclge_basic_info *)resp_msg; 138 139 hdev->hw_tc_map = basic_info->hw_tc_map; 140 hdev->mbx_api_version = le16_to_cpu(basic_info->mbx_api_version); 141 caps = le32_to_cpu(basic_info->pf_caps); 142 if (test_bit(HNAE3_PF_SUPPORT_VLAN_FLTR_MDF_B, &caps)) 143 set_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps); 144 145 return 0; 146 } 147 148 static int hclgevf_get_port_base_vlan_filter_state(struct hclgevf_dev *hdev) 149 { 150 struct hnae3_handle *nic = &hdev->nic; 151 struct hclge_vf_to_pf_msg send_msg; 152 u8 resp_msg; 153 int ret; 154 155 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 156 HCLGE_MBX_GET_PORT_BASE_VLAN_STATE); 157 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, &resp_msg, 158 sizeof(u8)); 159 if (ret) { 160 dev_err(&hdev->pdev->dev, 161 "VF request to get port based vlan state failed %d", 162 ret); 163 return ret; 164 } 165 166 nic->port_base_vlan_state = resp_msg; 167 168 return 0; 169 } 170 171 static int hclgevf_get_queue_info(struct hclgevf_dev *hdev) 172 { 173 #define HCLGEVF_TQPS_RSS_INFO_LEN 6 174 175 struct hclge_mbx_vf_queue_info *queue_info; 176 u8 resp_msg[HCLGEVF_TQPS_RSS_INFO_LEN]; 177 struct hclge_vf_to_pf_msg send_msg; 178 int status; 179 180 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QINFO, 0); 181 status = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 182 HCLGEVF_TQPS_RSS_INFO_LEN); 183 if (status) { 184 dev_err(&hdev->pdev->dev, 185 "VF request to get tqp info from PF failed %d", 186 status); 187 return status; 188 } 189 190 queue_info = (struct hclge_mbx_vf_queue_info *)resp_msg; 191 hdev->num_tqps = le16_to_cpu(queue_info->num_tqps); 192 hdev->rss_size_max = le16_to_cpu(queue_info->rss_size); 193 hdev->rx_buf_len = le16_to_cpu(queue_info->rx_buf_len); 194 195 return 0; 196 } 197 198 static int hclgevf_get_queue_depth(struct hclgevf_dev *hdev) 199 { 200 #define HCLGEVF_TQPS_DEPTH_INFO_LEN 4 201 202 struct hclge_mbx_vf_queue_depth *queue_depth; 203 u8 resp_msg[HCLGEVF_TQPS_DEPTH_INFO_LEN]; 204 struct hclge_vf_to_pf_msg send_msg; 205 int ret; 206 207 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QDEPTH, 0); 208 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 209 HCLGEVF_TQPS_DEPTH_INFO_LEN); 210 if (ret) { 211 dev_err(&hdev->pdev->dev, 212 "VF request to get tqp depth info from PF failed %d", 213 ret); 214 return ret; 215 } 216 217 queue_depth = (struct hclge_mbx_vf_queue_depth *)resp_msg; 218 hdev->num_tx_desc = le16_to_cpu(queue_depth->num_tx_desc); 219 hdev->num_rx_desc = le16_to_cpu(queue_depth->num_rx_desc); 220 221 return 0; 222 } 223 224 static u16 hclgevf_get_qid_global(struct hnae3_handle *handle, u16 queue_id) 225 { 226 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 227 struct hclge_vf_to_pf_msg send_msg; 228 u16 qid_in_pf = 0; 229 u8 resp_data[2]; 230 int ret; 231 232 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QID_IN_PF, 0); 233 *(__le16 *)send_msg.data = cpu_to_le16(queue_id); 234 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_data, 235 sizeof(resp_data)); 236 if (!ret) 237 qid_in_pf = le16_to_cpu(*(__le16 *)resp_data); 238 239 return qid_in_pf; 240 } 241 242 static int hclgevf_get_pf_media_type(struct hclgevf_dev *hdev) 243 { 244 struct hclge_vf_to_pf_msg send_msg; 245 u8 resp_msg[2]; 246 int ret; 247 248 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_MEDIA_TYPE, 0); 249 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 250 sizeof(resp_msg)); 251 if (ret) { 252 dev_err(&hdev->pdev->dev, 253 "VF request to get the pf port media type failed %d", 254 ret); 255 return ret; 256 } 257 258 hdev->hw.mac.media_type = resp_msg[0]; 259 hdev->hw.mac.module_type = resp_msg[1]; 260 261 return 0; 262 } 263 264 static int hclgevf_alloc_tqps(struct hclgevf_dev *hdev) 265 { 266 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 267 struct hclge_comm_tqp *tqp; 268 int i; 269 270 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 271 sizeof(struct hclge_comm_tqp), GFP_KERNEL); 272 if (!hdev->htqp) 273 return -ENOMEM; 274 275 tqp = hdev->htqp; 276 277 for (i = 0; i < hdev->num_tqps; i++) { 278 tqp->dev = &hdev->pdev->dev; 279 tqp->index = i; 280 281 tqp->q.ae_algo = &ae_algovf; 282 tqp->q.buf_size = hdev->rx_buf_len; 283 tqp->q.tx_desc_num = hdev->num_tx_desc; 284 tqp->q.rx_desc_num = hdev->num_rx_desc; 285 286 /* need an extended offset to configure queues >= 287 * HCLGEVF_TQP_MAX_SIZE_DEV_V2. 288 */ 289 if (i < HCLGEVF_TQP_MAX_SIZE_DEV_V2) 290 tqp->q.io_base = hdev->hw.hw.io_base + 291 HCLGEVF_TQP_REG_OFFSET + 292 i * HCLGEVF_TQP_REG_SIZE; 293 else 294 tqp->q.io_base = hdev->hw.hw.io_base + 295 HCLGEVF_TQP_REG_OFFSET + 296 HCLGEVF_TQP_EXT_REG_OFFSET + 297 (i - HCLGEVF_TQP_MAX_SIZE_DEV_V2) * 298 HCLGEVF_TQP_REG_SIZE; 299 300 /* when device supports tx push and has device memory, 301 * the queue can execute push mode or doorbell mode on 302 * device memory. 303 */ 304 if (test_bit(HNAE3_DEV_SUPPORT_TX_PUSH_B, ae_dev->caps)) 305 tqp->q.mem_base = hdev->hw.hw.mem_base + 306 HCLGEVF_TQP_MEM_OFFSET(hdev, i); 307 308 tqp++; 309 } 310 311 return 0; 312 } 313 314 static int hclgevf_knic_setup(struct hclgevf_dev *hdev) 315 { 316 struct hnae3_handle *nic = &hdev->nic; 317 struct hnae3_knic_private_info *kinfo; 318 u16 new_tqps = hdev->num_tqps; 319 unsigned int i; 320 u8 num_tc = 0; 321 322 kinfo = &nic->kinfo; 323 kinfo->num_tx_desc = hdev->num_tx_desc; 324 kinfo->num_rx_desc = hdev->num_rx_desc; 325 kinfo->rx_buf_len = hdev->rx_buf_len; 326 for (i = 0; i < HCLGE_COMM_MAX_TC_NUM; i++) 327 if (hdev->hw_tc_map & BIT(i)) 328 num_tc++; 329 330 num_tc = num_tc ? num_tc : 1; 331 kinfo->tc_info.num_tc = num_tc; 332 kinfo->rss_size = min_t(u16, hdev->rss_size_max, new_tqps / num_tc); 333 new_tqps = kinfo->rss_size * num_tc; 334 kinfo->num_tqps = min(new_tqps, hdev->num_tqps); 335 336 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps, 337 sizeof(struct hnae3_queue *), GFP_KERNEL); 338 if (!kinfo->tqp) 339 return -ENOMEM; 340 341 for (i = 0; i < kinfo->num_tqps; i++) { 342 hdev->htqp[i].q.handle = &hdev->nic; 343 hdev->htqp[i].q.tqp_index = i; 344 kinfo->tqp[i] = &hdev->htqp[i].q; 345 } 346 347 /* after init the max rss_size and tqps, adjust the default tqp numbers 348 * and rss size with the actual vector numbers 349 */ 350 kinfo->num_tqps = min_t(u16, hdev->num_nic_msix - 1, kinfo->num_tqps); 351 kinfo->rss_size = min_t(u16, kinfo->num_tqps / num_tc, 352 kinfo->rss_size); 353 354 return 0; 355 } 356 357 static void hclgevf_request_link_info(struct hclgevf_dev *hdev) 358 { 359 struct hclge_vf_to_pf_msg send_msg; 360 int status; 361 362 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_LINK_STATUS, 0); 363 status = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 364 if (status) 365 dev_err(&hdev->pdev->dev, 366 "VF failed to fetch link status(%d) from PF", status); 367 } 368 369 void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state) 370 { 371 struct hnae3_handle *rhandle = &hdev->roce; 372 struct hnae3_handle *handle = &hdev->nic; 373 struct hnae3_client *rclient; 374 struct hnae3_client *client; 375 376 if (test_and_set_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state)) 377 return; 378 379 client = handle->client; 380 rclient = hdev->roce_client; 381 382 link_state = 383 test_bit(HCLGEVF_STATE_DOWN, &hdev->state) ? 0 : link_state; 384 if (link_state != hdev->hw.mac.link) { 385 hdev->hw.mac.link = link_state; 386 client->ops->link_status_change(handle, !!link_state); 387 if (rclient && rclient->ops->link_status_change) 388 rclient->ops->link_status_change(rhandle, !!link_state); 389 } 390 391 clear_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state); 392 } 393 394 static void hclgevf_update_link_mode(struct hclgevf_dev *hdev) 395 { 396 #define HCLGEVF_ADVERTISING 0 397 #define HCLGEVF_SUPPORTED 1 398 399 struct hclge_vf_to_pf_msg send_msg; 400 401 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_LINK_MODE, 0); 402 send_msg.data[0] = HCLGEVF_ADVERTISING; 403 hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 404 send_msg.data[0] = HCLGEVF_SUPPORTED; 405 hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 406 } 407 408 static int hclgevf_set_handle_info(struct hclgevf_dev *hdev) 409 { 410 struct hnae3_handle *nic = &hdev->nic; 411 int ret; 412 413 nic->ae_algo = &ae_algovf; 414 nic->pdev = hdev->pdev; 415 bitmap_copy(nic->numa_node_mask.bits, hdev->numa_node_mask.bits, 416 MAX_NUMNODES); 417 nic->flags |= HNAE3_SUPPORT_VF; 418 nic->kinfo.io_base = hdev->hw.hw.io_base; 419 420 ret = hclgevf_knic_setup(hdev); 421 if (ret) 422 dev_err(&hdev->pdev->dev, "VF knic setup failed %d\n", 423 ret); 424 return ret; 425 } 426 427 static void hclgevf_free_vector(struct hclgevf_dev *hdev, int vector_id) 428 { 429 if (hdev->vector_status[vector_id] == HCLGEVF_INVALID_VPORT) { 430 dev_warn(&hdev->pdev->dev, 431 "vector(vector_id %d) has been freed.\n", vector_id); 432 return; 433 } 434 435 hdev->vector_status[vector_id] = HCLGEVF_INVALID_VPORT; 436 hdev->num_msi_left += 1; 437 hdev->num_msi_used -= 1; 438 } 439 440 static int hclgevf_get_vector(struct hnae3_handle *handle, u16 vector_num, 441 struct hnae3_vector_info *vector_info) 442 { 443 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 444 struct hnae3_vector_info *vector = vector_info; 445 int alloc = 0; 446 int i, j; 447 448 vector_num = min_t(u16, hdev->num_nic_msix - 1, vector_num); 449 vector_num = min(hdev->num_msi_left, vector_num); 450 451 for (j = 0; j < vector_num; j++) { 452 for (i = HCLGEVF_MISC_VECTOR_NUM + 1; i < hdev->num_msi; i++) { 453 if (hdev->vector_status[i] == HCLGEVF_INVALID_VPORT) { 454 vector->vector = pci_irq_vector(hdev->pdev, i); 455 vector->io_addr = hdev->hw.hw.io_base + 456 HCLGEVF_VECTOR_REG_BASE + 457 (i - 1) * HCLGEVF_VECTOR_REG_OFFSET; 458 hdev->vector_status[i] = 0; 459 hdev->vector_irq[i] = vector->vector; 460 461 vector++; 462 alloc++; 463 464 break; 465 } 466 } 467 } 468 hdev->num_msi_left -= alloc; 469 hdev->num_msi_used += alloc; 470 471 return alloc; 472 } 473 474 static int hclgevf_get_vector_index(struct hclgevf_dev *hdev, int vector) 475 { 476 int i; 477 478 for (i = 0; i < hdev->num_msi; i++) 479 if (vector == hdev->vector_irq[i]) 480 return i; 481 482 return -EINVAL; 483 } 484 485 /* for revision 0x20, vf shared the same rss config with pf */ 486 static int hclgevf_get_rss_hash_key(struct hclgevf_dev *hdev) 487 { 488 #define HCLGEVF_RSS_MBX_RESP_LEN 8 489 struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg; 490 u8 resp_msg[HCLGEVF_RSS_MBX_RESP_LEN]; 491 struct hclge_vf_to_pf_msg send_msg; 492 u16 msg_num, hash_key_index; 493 u8 index; 494 int ret; 495 496 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_RSS_KEY, 0); 497 msg_num = (HCLGE_COMM_RSS_KEY_SIZE + HCLGEVF_RSS_MBX_RESP_LEN - 1) / 498 HCLGEVF_RSS_MBX_RESP_LEN; 499 for (index = 0; index < msg_num; index++) { 500 send_msg.data[0] = index; 501 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 502 HCLGEVF_RSS_MBX_RESP_LEN); 503 if (ret) { 504 dev_err(&hdev->pdev->dev, 505 "VF get rss hash key from PF failed, ret=%d", 506 ret); 507 return ret; 508 } 509 510 hash_key_index = HCLGEVF_RSS_MBX_RESP_LEN * index; 511 if (index == msg_num - 1) 512 memcpy(&rss_cfg->rss_hash_key[hash_key_index], 513 &resp_msg[0], 514 HCLGE_COMM_RSS_KEY_SIZE - hash_key_index); 515 else 516 memcpy(&rss_cfg->rss_hash_key[hash_key_index], 517 &resp_msg[0], HCLGEVF_RSS_MBX_RESP_LEN); 518 } 519 520 return 0; 521 } 522 523 static int hclgevf_get_rss(struct hnae3_handle *handle, u32 *indir, u8 *key, 524 u8 *hfunc) 525 { 526 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 527 struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg; 528 int ret; 529 530 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 531 hclge_comm_get_rss_hash_info(rss_cfg, key, hfunc); 532 } else { 533 if (hfunc) 534 *hfunc = ETH_RSS_HASH_TOP; 535 if (key) { 536 ret = hclgevf_get_rss_hash_key(hdev); 537 if (ret) 538 return ret; 539 memcpy(key, rss_cfg->rss_hash_key, 540 HCLGE_COMM_RSS_KEY_SIZE); 541 } 542 } 543 544 hclge_comm_get_rss_indir_tbl(rss_cfg, indir, 545 hdev->ae_dev->dev_specs.rss_ind_tbl_size); 546 547 return 0; 548 } 549 550 static int hclgevf_set_rss(struct hnae3_handle *handle, const u32 *indir, 551 const u8 *key, const u8 hfunc) 552 { 553 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 554 struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg; 555 int ret, i; 556 557 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 558 ret = hclge_comm_set_rss_hash_key(rss_cfg, &hdev->hw.hw, key, 559 hfunc); 560 if (ret) 561 return ret; 562 } 563 564 /* update the shadow RSS table with user specified qids */ 565 for (i = 0; i < hdev->ae_dev->dev_specs.rss_ind_tbl_size; i++) 566 rss_cfg->rss_indirection_tbl[i] = indir[i]; 567 568 /* update the hardware */ 569 return hclge_comm_set_rss_indir_table(hdev->ae_dev, &hdev->hw.hw, 570 rss_cfg->rss_indirection_tbl); 571 } 572 573 static int hclgevf_set_rss_tuple(struct hnae3_handle *handle, 574 struct ethtool_rxnfc *nfc) 575 { 576 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 577 int ret; 578 579 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 580 return -EOPNOTSUPP; 581 582 ret = hclge_comm_set_rss_tuple(hdev->ae_dev, &hdev->hw.hw, 583 &hdev->rss_cfg, nfc); 584 if (ret) 585 dev_err(&hdev->pdev->dev, 586 "failed to set rss tuple, ret = %d.\n", ret); 587 588 return ret; 589 } 590 591 static int hclgevf_get_rss_tuple(struct hnae3_handle *handle, 592 struct ethtool_rxnfc *nfc) 593 { 594 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 595 u8 tuple_sets; 596 int ret; 597 598 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 599 return -EOPNOTSUPP; 600 601 nfc->data = 0; 602 603 ret = hclge_comm_get_rss_tuple(&hdev->rss_cfg, nfc->flow_type, 604 &tuple_sets); 605 if (ret || !tuple_sets) 606 return ret; 607 608 nfc->data = hclge_comm_convert_rss_tuple(tuple_sets); 609 610 return 0; 611 } 612 613 static int hclgevf_get_tc_size(struct hnae3_handle *handle) 614 { 615 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 616 struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg; 617 618 return rss_cfg->rss_size; 619 } 620 621 static int hclgevf_bind_ring_to_vector(struct hnae3_handle *handle, bool en, 622 int vector_id, 623 struct hnae3_ring_chain_node *ring_chain) 624 { 625 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 626 struct hclge_vf_to_pf_msg send_msg; 627 struct hnae3_ring_chain_node *node; 628 int status; 629 int i = 0; 630 631 memset(&send_msg, 0, sizeof(send_msg)); 632 send_msg.code = en ? HCLGE_MBX_MAP_RING_TO_VECTOR : 633 HCLGE_MBX_UNMAP_RING_TO_VECTOR; 634 send_msg.vector_id = vector_id; 635 636 for (node = ring_chain; node; node = node->next) { 637 send_msg.param[i].ring_type = 638 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B); 639 640 send_msg.param[i].tqp_index = node->tqp_index; 641 send_msg.param[i].int_gl_index = 642 hnae3_get_field(node->int_gl_idx, 643 HNAE3_RING_GL_IDX_M, 644 HNAE3_RING_GL_IDX_S); 645 646 i++; 647 if (i == HCLGE_MBX_MAX_RING_CHAIN_PARAM_NUM || !node->next) { 648 send_msg.ring_num = i; 649 650 status = hclgevf_send_mbx_msg(hdev, &send_msg, false, 651 NULL, 0); 652 if (status) { 653 dev_err(&hdev->pdev->dev, 654 "Map TQP fail, status is %d.\n", 655 status); 656 return status; 657 } 658 i = 0; 659 } 660 } 661 662 return 0; 663 } 664 665 static int hclgevf_map_ring_to_vector(struct hnae3_handle *handle, int vector, 666 struct hnae3_ring_chain_node *ring_chain) 667 { 668 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 669 int vector_id; 670 671 vector_id = hclgevf_get_vector_index(hdev, vector); 672 if (vector_id < 0) { 673 dev_err(&handle->pdev->dev, 674 "Get vector index fail. ret =%d\n", vector_id); 675 return vector_id; 676 } 677 678 return hclgevf_bind_ring_to_vector(handle, true, vector_id, ring_chain); 679 } 680 681 static int hclgevf_unmap_ring_from_vector( 682 struct hnae3_handle *handle, 683 int vector, 684 struct hnae3_ring_chain_node *ring_chain) 685 { 686 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 687 int ret, vector_id; 688 689 if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 690 return 0; 691 692 vector_id = hclgevf_get_vector_index(hdev, vector); 693 if (vector_id < 0) { 694 dev_err(&handle->pdev->dev, 695 "Get vector index fail. ret =%d\n", vector_id); 696 return vector_id; 697 } 698 699 ret = hclgevf_bind_ring_to_vector(handle, false, vector_id, ring_chain); 700 if (ret) 701 dev_err(&handle->pdev->dev, 702 "Unmap ring from vector fail. vector=%d, ret =%d\n", 703 vector_id, 704 ret); 705 706 return ret; 707 } 708 709 static int hclgevf_put_vector(struct hnae3_handle *handle, int vector) 710 { 711 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 712 int vector_id; 713 714 vector_id = hclgevf_get_vector_index(hdev, vector); 715 if (vector_id < 0) { 716 dev_err(&handle->pdev->dev, 717 "hclgevf_put_vector get vector index fail. ret =%d\n", 718 vector_id); 719 return vector_id; 720 } 721 722 hclgevf_free_vector(hdev, vector_id); 723 724 return 0; 725 } 726 727 static int hclgevf_cmd_set_promisc_mode(struct hclgevf_dev *hdev, 728 bool en_uc_pmc, bool en_mc_pmc, 729 bool en_bc_pmc) 730 { 731 struct hnae3_handle *handle = &hdev->nic; 732 struct hclge_vf_to_pf_msg send_msg; 733 int ret; 734 735 memset(&send_msg, 0, sizeof(send_msg)); 736 send_msg.code = HCLGE_MBX_SET_PROMISC_MODE; 737 send_msg.en_bc = en_bc_pmc ? 1 : 0; 738 send_msg.en_uc = en_uc_pmc ? 1 : 0; 739 send_msg.en_mc = en_mc_pmc ? 1 : 0; 740 send_msg.en_limit_promisc = test_bit(HNAE3_PFLAG_LIMIT_PROMISC, 741 &handle->priv_flags) ? 1 : 0; 742 743 ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 744 if (ret) 745 dev_err(&hdev->pdev->dev, 746 "Set promisc mode fail, status is %d.\n", ret); 747 748 return ret; 749 } 750 751 static int hclgevf_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc, 752 bool en_mc_pmc) 753 { 754 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 755 bool en_bc_pmc; 756 757 en_bc_pmc = hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2; 758 759 return hclgevf_cmd_set_promisc_mode(hdev, en_uc_pmc, en_mc_pmc, 760 en_bc_pmc); 761 } 762 763 static void hclgevf_request_update_promisc_mode(struct hnae3_handle *handle) 764 { 765 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 766 767 set_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state); 768 hclgevf_task_schedule(hdev, 0); 769 } 770 771 static void hclgevf_sync_promisc_mode(struct hclgevf_dev *hdev) 772 { 773 struct hnae3_handle *handle = &hdev->nic; 774 bool en_uc_pmc = handle->netdev_flags & HNAE3_UPE; 775 bool en_mc_pmc = handle->netdev_flags & HNAE3_MPE; 776 int ret; 777 778 if (test_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state)) { 779 ret = hclgevf_set_promisc_mode(handle, en_uc_pmc, en_mc_pmc); 780 if (!ret) 781 clear_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state); 782 } 783 } 784 785 static int hclgevf_tqp_enable_cmd_send(struct hclgevf_dev *hdev, u16 tqp_id, 786 u16 stream_id, bool enable) 787 { 788 struct hclgevf_cfg_com_tqp_queue_cmd *req; 789 struct hclge_desc desc; 790 791 req = (struct hclgevf_cfg_com_tqp_queue_cmd *)desc.data; 792 793 hclgevf_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false); 794 req->tqp_id = cpu_to_le16(tqp_id & HCLGEVF_RING_ID_MASK); 795 req->stream_id = cpu_to_le16(stream_id); 796 if (enable) 797 req->enable |= 1U << HCLGEVF_TQP_ENABLE_B; 798 799 return hclgevf_cmd_send(&hdev->hw, &desc, 1); 800 } 801 802 static int hclgevf_tqp_enable(struct hnae3_handle *handle, bool enable) 803 { 804 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 805 int ret; 806 u16 i; 807 808 for (i = 0; i < handle->kinfo.num_tqps; i++) { 809 ret = hclgevf_tqp_enable_cmd_send(hdev, i, 0, enable); 810 if (ret) 811 return ret; 812 } 813 814 return 0; 815 } 816 817 static int hclgevf_get_host_mac_addr(struct hclgevf_dev *hdev, u8 *p) 818 { 819 struct hclge_vf_to_pf_msg send_msg; 820 u8 host_mac[ETH_ALEN]; 821 int status; 822 823 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_MAC_ADDR, 0); 824 status = hclgevf_send_mbx_msg(hdev, &send_msg, true, host_mac, 825 ETH_ALEN); 826 if (status) { 827 dev_err(&hdev->pdev->dev, 828 "fail to get VF MAC from host %d", status); 829 return status; 830 } 831 832 ether_addr_copy(p, host_mac); 833 834 return 0; 835 } 836 837 static void hclgevf_get_mac_addr(struct hnae3_handle *handle, u8 *p) 838 { 839 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 840 u8 host_mac_addr[ETH_ALEN]; 841 842 if (hclgevf_get_host_mac_addr(hdev, host_mac_addr)) 843 return; 844 845 hdev->has_pf_mac = !is_zero_ether_addr(host_mac_addr); 846 if (hdev->has_pf_mac) 847 ether_addr_copy(p, host_mac_addr); 848 else 849 ether_addr_copy(p, hdev->hw.mac.mac_addr); 850 } 851 852 static int hclgevf_set_mac_addr(struct hnae3_handle *handle, const void *p, 853 bool is_first) 854 { 855 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 856 u8 *old_mac_addr = (u8 *)hdev->hw.mac.mac_addr; 857 struct hclge_vf_to_pf_msg send_msg; 858 u8 *new_mac_addr = (u8 *)p; 859 int status; 860 861 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_UNICAST, 0); 862 send_msg.subcode = HCLGE_MBX_MAC_VLAN_UC_MODIFY; 863 ether_addr_copy(send_msg.data, new_mac_addr); 864 if (is_first && !hdev->has_pf_mac) 865 eth_zero_addr(&send_msg.data[ETH_ALEN]); 866 else 867 ether_addr_copy(&send_msg.data[ETH_ALEN], old_mac_addr); 868 status = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 869 if (!status) 870 ether_addr_copy(hdev->hw.mac.mac_addr, new_mac_addr); 871 872 return status; 873 } 874 875 static struct hclgevf_mac_addr_node * 876 hclgevf_find_mac_node(struct list_head *list, const u8 *mac_addr) 877 { 878 struct hclgevf_mac_addr_node *mac_node, *tmp; 879 880 list_for_each_entry_safe(mac_node, tmp, list, node) 881 if (ether_addr_equal(mac_addr, mac_node->mac_addr)) 882 return mac_node; 883 884 return NULL; 885 } 886 887 static void hclgevf_update_mac_node(struct hclgevf_mac_addr_node *mac_node, 888 enum HCLGEVF_MAC_NODE_STATE state) 889 { 890 switch (state) { 891 /* from set_rx_mode or tmp_add_list */ 892 case HCLGEVF_MAC_TO_ADD: 893 if (mac_node->state == HCLGEVF_MAC_TO_DEL) 894 mac_node->state = HCLGEVF_MAC_ACTIVE; 895 break; 896 /* only from set_rx_mode */ 897 case HCLGEVF_MAC_TO_DEL: 898 if (mac_node->state == HCLGEVF_MAC_TO_ADD) { 899 list_del(&mac_node->node); 900 kfree(mac_node); 901 } else { 902 mac_node->state = HCLGEVF_MAC_TO_DEL; 903 } 904 break; 905 /* only from tmp_add_list, the mac_node->state won't be 906 * HCLGEVF_MAC_ACTIVE 907 */ 908 case HCLGEVF_MAC_ACTIVE: 909 if (mac_node->state == HCLGEVF_MAC_TO_ADD) 910 mac_node->state = HCLGEVF_MAC_ACTIVE; 911 break; 912 } 913 } 914 915 static int hclgevf_update_mac_list(struct hnae3_handle *handle, 916 enum HCLGEVF_MAC_NODE_STATE state, 917 enum HCLGEVF_MAC_ADDR_TYPE mac_type, 918 const unsigned char *addr) 919 { 920 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 921 struct hclgevf_mac_addr_node *mac_node; 922 struct list_head *list; 923 924 list = (mac_type == HCLGEVF_MAC_ADDR_UC) ? 925 &hdev->mac_table.uc_mac_list : &hdev->mac_table.mc_mac_list; 926 927 spin_lock_bh(&hdev->mac_table.mac_list_lock); 928 929 /* if the mac addr is already in the mac list, no need to add a new 930 * one into it, just check the mac addr state, convert it to a new 931 * state, or just remove it, or do nothing. 932 */ 933 mac_node = hclgevf_find_mac_node(list, addr); 934 if (mac_node) { 935 hclgevf_update_mac_node(mac_node, state); 936 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 937 return 0; 938 } 939 /* if this address is never added, unnecessary to delete */ 940 if (state == HCLGEVF_MAC_TO_DEL) { 941 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 942 return -ENOENT; 943 } 944 945 mac_node = kzalloc(sizeof(*mac_node), GFP_ATOMIC); 946 if (!mac_node) { 947 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 948 return -ENOMEM; 949 } 950 951 mac_node->state = state; 952 ether_addr_copy(mac_node->mac_addr, addr); 953 list_add_tail(&mac_node->node, list); 954 955 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 956 return 0; 957 } 958 959 static int hclgevf_add_uc_addr(struct hnae3_handle *handle, 960 const unsigned char *addr) 961 { 962 return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_ADD, 963 HCLGEVF_MAC_ADDR_UC, addr); 964 } 965 966 static int hclgevf_rm_uc_addr(struct hnae3_handle *handle, 967 const unsigned char *addr) 968 { 969 return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_DEL, 970 HCLGEVF_MAC_ADDR_UC, addr); 971 } 972 973 static int hclgevf_add_mc_addr(struct hnae3_handle *handle, 974 const unsigned char *addr) 975 { 976 return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_ADD, 977 HCLGEVF_MAC_ADDR_MC, addr); 978 } 979 980 static int hclgevf_rm_mc_addr(struct hnae3_handle *handle, 981 const unsigned char *addr) 982 { 983 return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_DEL, 984 HCLGEVF_MAC_ADDR_MC, addr); 985 } 986 987 static int hclgevf_add_del_mac_addr(struct hclgevf_dev *hdev, 988 struct hclgevf_mac_addr_node *mac_node, 989 enum HCLGEVF_MAC_ADDR_TYPE mac_type) 990 { 991 struct hclge_vf_to_pf_msg send_msg; 992 u8 code, subcode; 993 994 if (mac_type == HCLGEVF_MAC_ADDR_UC) { 995 code = HCLGE_MBX_SET_UNICAST; 996 if (mac_node->state == HCLGEVF_MAC_TO_ADD) 997 subcode = HCLGE_MBX_MAC_VLAN_UC_ADD; 998 else 999 subcode = HCLGE_MBX_MAC_VLAN_UC_REMOVE; 1000 } else { 1001 code = HCLGE_MBX_SET_MULTICAST; 1002 if (mac_node->state == HCLGEVF_MAC_TO_ADD) 1003 subcode = HCLGE_MBX_MAC_VLAN_MC_ADD; 1004 else 1005 subcode = HCLGE_MBX_MAC_VLAN_MC_REMOVE; 1006 } 1007 1008 hclgevf_build_send_msg(&send_msg, code, subcode); 1009 ether_addr_copy(send_msg.data, mac_node->mac_addr); 1010 return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 1011 } 1012 1013 static void hclgevf_config_mac_list(struct hclgevf_dev *hdev, 1014 struct list_head *list, 1015 enum HCLGEVF_MAC_ADDR_TYPE mac_type) 1016 { 1017 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 1018 struct hclgevf_mac_addr_node *mac_node, *tmp; 1019 int ret; 1020 1021 list_for_each_entry_safe(mac_node, tmp, list, node) { 1022 ret = hclgevf_add_del_mac_addr(hdev, mac_node, mac_type); 1023 if (ret) { 1024 hnae3_format_mac_addr(format_mac_addr, 1025 mac_node->mac_addr); 1026 dev_err(&hdev->pdev->dev, 1027 "failed to configure mac %s, state = %d, ret = %d\n", 1028 format_mac_addr, mac_node->state, ret); 1029 return; 1030 } 1031 if (mac_node->state == HCLGEVF_MAC_TO_ADD) { 1032 mac_node->state = HCLGEVF_MAC_ACTIVE; 1033 } else { 1034 list_del(&mac_node->node); 1035 kfree(mac_node); 1036 } 1037 } 1038 } 1039 1040 static void hclgevf_sync_from_add_list(struct list_head *add_list, 1041 struct list_head *mac_list) 1042 { 1043 struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node; 1044 1045 list_for_each_entry_safe(mac_node, tmp, add_list, node) { 1046 /* if the mac address from tmp_add_list is not in the 1047 * uc/mc_mac_list, it means have received a TO_DEL request 1048 * during the time window of sending mac config request to PF 1049 * If mac_node state is ACTIVE, then change its state to TO_DEL, 1050 * then it will be removed at next time. If is TO_ADD, it means 1051 * send TO_ADD request failed, so just remove the mac node. 1052 */ 1053 new_node = hclgevf_find_mac_node(mac_list, mac_node->mac_addr); 1054 if (new_node) { 1055 hclgevf_update_mac_node(new_node, mac_node->state); 1056 list_del(&mac_node->node); 1057 kfree(mac_node); 1058 } else if (mac_node->state == HCLGEVF_MAC_ACTIVE) { 1059 mac_node->state = HCLGEVF_MAC_TO_DEL; 1060 list_move_tail(&mac_node->node, mac_list); 1061 } else { 1062 list_del(&mac_node->node); 1063 kfree(mac_node); 1064 } 1065 } 1066 } 1067 1068 static void hclgevf_sync_from_del_list(struct list_head *del_list, 1069 struct list_head *mac_list) 1070 { 1071 struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node; 1072 1073 list_for_each_entry_safe(mac_node, tmp, del_list, node) { 1074 new_node = hclgevf_find_mac_node(mac_list, mac_node->mac_addr); 1075 if (new_node) { 1076 /* If the mac addr is exist in the mac list, it means 1077 * received a new request TO_ADD during the time window 1078 * of sending mac addr configurrequest to PF, so just 1079 * change the mac state to ACTIVE. 1080 */ 1081 new_node->state = HCLGEVF_MAC_ACTIVE; 1082 list_del(&mac_node->node); 1083 kfree(mac_node); 1084 } else { 1085 list_move_tail(&mac_node->node, mac_list); 1086 } 1087 } 1088 } 1089 1090 static void hclgevf_clear_list(struct list_head *list) 1091 { 1092 struct hclgevf_mac_addr_node *mac_node, *tmp; 1093 1094 list_for_each_entry_safe(mac_node, tmp, list, node) { 1095 list_del(&mac_node->node); 1096 kfree(mac_node); 1097 } 1098 } 1099 1100 static void hclgevf_sync_mac_list(struct hclgevf_dev *hdev, 1101 enum HCLGEVF_MAC_ADDR_TYPE mac_type) 1102 { 1103 struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node; 1104 struct list_head tmp_add_list, tmp_del_list; 1105 struct list_head *list; 1106 1107 INIT_LIST_HEAD(&tmp_add_list); 1108 INIT_LIST_HEAD(&tmp_del_list); 1109 1110 /* move the mac addr to the tmp_add_list and tmp_del_list, then 1111 * we can add/delete these mac addr outside the spin lock 1112 */ 1113 list = (mac_type == HCLGEVF_MAC_ADDR_UC) ? 1114 &hdev->mac_table.uc_mac_list : &hdev->mac_table.mc_mac_list; 1115 1116 spin_lock_bh(&hdev->mac_table.mac_list_lock); 1117 1118 list_for_each_entry_safe(mac_node, tmp, list, node) { 1119 switch (mac_node->state) { 1120 case HCLGEVF_MAC_TO_DEL: 1121 list_move_tail(&mac_node->node, &tmp_del_list); 1122 break; 1123 case HCLGEVF_MAC_TO_ADD: 1124 new_node = kzalloc(sizeof(*new_node), GFP_ATOMIC); 1125 if (!new_node) 1126 goto stop_traverse; 1127 1128 ether_addr_copy(new_node->mac_addr, mac_node->mac_addr); 1129 new_node->state = mac_node->state; 1130 list_add_tail(&new_node->node, &tmp_add_list); 1131 break; 1132 default: 1133 break; 1134 } 1135 } 1136 1137 stop_traverse: 1138 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1139 1140 /* delete first, in order to get max mac table space for adding */ 1141 hclgevf_config_mac_list(hdev, &tmp_del_list, mac_type); 1142 hclgevf_config_mac_list(hdev, &tmp_add_list, mac_type); 1143 1144 /* if some mac addresses were added/deleted fail, move back to the 1145 * mac_list, and retry at next time. 1146 */ 1147 spin_lock_bh(&hdev->mac_table.mac_list_lock); 1148 1149 hclgevf_sync_from_del_list(&tmp_del_list, list); 1150 hclgevf_sync_from_add_list(&tmp_add_list, list); 1151 1152 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1153 } 1154 1155 static void hclgevf_sync_mac_table(struct hclgevf_dev *hdev) 1156 { 1157 hclgevf_sync_mac_list(hdev, HCLGEVF_MAC_ADDR_UC); 1158 hclgevf_sync_mac_list(hdev, HCLGEVF_MAC_ADDR_MC); 1159 } 1160 1161 static void hclgevf_uninit_mac_list(struct hclgevf_dev *hdev) 1162 { 1163 spin_lock_bh(&hdev->mac_table.mac_list_lock); 1164 1165 hclgevf_clear_list(&hdev->mac_table.uc_mac_list); 1166 hclgevf_clear_list(&hdev->mac_table.mc_mac_list); 1167 1168 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1169 } 1170 1171 static int hclgevf_enable_vlan_filter(struct hnae3_handle *handle, bool enable) 1172 { 1173 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1174 struct hnae3_ae_dev *ae_dev = hdev->ae_dev; 1175 struct hclge_vf_to_pf_msg send_msg; 1176 1177 if (!test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps)) 1178 return -EOPNOTSUPP; 1179 1180 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 1181 HCLGE_MBX_ENABLE_VLAN_FILTER); 1182 send_msg.data[0] = enable ? 1 : 0; 1183 1184 return hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1185 } 1186 1187 static int hclgevf_set_vlan_filter(struct hnae3_handle *handle, 1188 __be16 proto, u16 vlan_id, 1189 bool is_kill) 1190 { 1191 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1192 struct hclge_mbx_vlan_filter *vlan_filter; 1193 struct hclge_vf_to_pf_msg send_msg; 1194 int ret; 1195 1196 if (vlan_id > HCLGEVF_MAX_VLAN_ID) 1197 return -EINVAL; 1198 1199 if (proto != htons(ETH_P_8021Q)) 1200 return -EPROTONOSUPPORT; 1201 1202 /* When device is resetting or reset failed, firmware is unable to 1203 * handle mailbox. Just record the vlan id, and remove it after 1204 * reset finished. 1205 */ 1206 if ((test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) || 1207 test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) && is_kill) { 1208 set_bit(vlan_id, hdev->vlan_del_fail_bmap); 1209 return -EBUSY; 1210 } else if (!is_kill && test_bit(vlan_id, hdev->vlan_del_fail_bmap)) { 1211 clear_bit(vlan_id, hdev->vlan_del_fail_bmap); 1212 } 1213 1214 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 1215 HCLGE_MBX_VLAN_FILTER); 1216 vlan_filter = (struct hclge_mbx_vlan_filter *)send_msg.data; 1217 vlan_filter->is_kill = is_kill; 1218 vlan_filter->vlan_id = cpu_to_le16(vlan_id); 1219 vlan_filter->proto = cpu_to_le16(be16_to_cpu(proto)); 1220 1221 /* when remove hw vlan filter failed, record the vlan id, 1222 * and try to remove it from hw later, to be consistence 1223 * with stack. 1224 */ 1225 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1226 if (is_kill && ret) 1227 set_bit(vlan_id, hdev->vlan_del_fail_bmap); 1228 1229 return ret; 1230 } 1231 1232 static void hclgevf_sync_vlan_filter(struct hclgevf_dev *hdev) 1233 { 1234 #define HCLGEVF_MAX_SYNC_COUNT 60 1235 struct hnae3_handle *handle = &hdev->nic; 1236 int ret, sync_cnt = 0; 1237 u16 vlan_id; 1238 1239 if (bitmap_empty(hdev->vlan_del_fail_bmap, VLAN_N_VID)) 1240 return; 1241 1242 rtnl_lock(); 1243 vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID); 1244 while (vlan_id != VLAN_N_VID) { 1245 ret = hclgevf_set_vlan_filter(handle, htons(ETH_P_8021Q), 1246 vlan_id, true); 1247 if (ret) 1248 break; 1249 1250 clear_bit(vlan_id, hdev->vlan_del_fail_bmap); 1251 sync_cnt++; 1252 if (sync_cnt >= HCLGEVF_MAX_SYNC_COUNT) 1253 break; 1254 1255 vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID); 1256 } 1257 rtnl_unlock(); 1258 } 1259 1260 static int hclgevf_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) 1261 { 1262 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1263 struct hclge_vf_to_pf_msg send_msg; 1264 1265 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 1266 HCLGE_MBX_VLAN_RX_OFF_CFG); 1267 send_msg.data[0] = enable ? 1 : 0; 1268 return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 1269 } 1270 1271 static int hclgevf_reset_tqp(struct hnae3_handle *handle) 1272 { 1273 #define HCLGEVF_RESET_ALL_QUEUE_DONE 1U 1274 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1275 struct hclge_vf_to_pf_msg send_msg; 1276 u8 return_status = 0; 1277 int ret; 1278 u16 i; 1279 1280 /* disable vf queue before send queue reset msg to PF */ 1281 ret = hclgevf_tqp_enable(handle, false); 1282 if (ret) { 1283 dev_err(&hdev->pdev->dev, "failed to disable tqp, ret = %d\n", 1284 ret); 1285 return ret; 1286 } 1287 1288 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_QUEUE_RESET, 0); 1289 1290 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, &return_status, 1291 sizeof(return_status)); 1292 if (ret || return_status == HCLGEVF_RESET_ALL_QUEUE_DONE) 1293 return ret; 1294 1295 for (i = 1; i < handle->kinfo.num_tqps; i++) { 1296 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_QUEUE_RESET, 0); 1297 *(__le16 *)send_msg.data = cpu_to_le16(i); 1298 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1299 if (ret) 1300 return ret; 1301 } 1302 1303 return 0; 1304 } 1305 1306 static int hclgevf_set_mtu(struct hnae3_handle *handle, int new_mtu) 1307 { 1308 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1309 struct hclge_mbx_mtu_info *mtu_info; 1310 struct hclge_vf_to_pf_msg send_msg; 1311 1312 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_MTU, 0); 1313 mtu_info = (struct hclge_mbx_mtu_info *)send_msg.data; 1314 mtu_info->mtu = cpu_to_le32(new_mtu); 1315 1316 return hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1317 } 1318 1319 static int hclgevf_notify_client(struct hclgevf_dev *hdev, 1320 enum hnae3_reset_notify_type type) 1321 { 1322 struct hnae3_client *client = hdev->nic_client; 1323 struct hnae3_handle *handle = &hdev->nic; 1324 int ret; 1325 1326 if (!test_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state) || 1327 !client) 1328 return 0; 1329 1330 if (!client->ops->reset_notify) 1331 return -EOPNOTSUPP; 1332 1333 ret = client->ops->reset_notify(handle, type); 1334 if (ret) 1335 dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n", 1336 type, ret); 1337 1338 return ret; 1339 } 1340 1341 static int hclgevf_notify_roce_client(struct hclgevf_dev *hdev, 1342 enum hnae3_reset_notify_type type) 1343 { 1344 struct hnae3_client *client = hdev->roce_client; 1345 struct hnae3_handle *handle = &hdev->roce; 1346 int ret; 1347 1348 if (!test_bit(HCLGEVF_STATE_ROCE_REGISTERED, &hdev->state) || !client) 1349 return 0; 1350 1351 if (!client->ops->reset_notify) 1352 return -EOPNOTSUPP; 1353 1354 ret = client->ops->reset_notify(handle, type); 1355 if (ret) 1356 dev_err(&hdev->pdev->dev, "notify roce client failed %d(%d)", 1357 type, ret); 1358 return ret; 1359 } 1360 1361 static int hclgevf_reset_wait(struct hclgevf_dev *hdev) 1362 { 1363 #define HCLGEVF_RESET_WAIT_US 20000 1364 #define HCLGEVF_RESET_WAIT_CNT 2000 1365 #define HCLGEVF_RESET_WAIT_TIMEOUT_US \ 1366 (HCLGEVF_RESET_WAIT_US * HCLGEVF_RESET_WAIT_CNT) 1367 1368 u32 val; 1369 int ret; 1370 1371 if (hdev->reset_type == HNAE3_VF_RESET) 1372 ret = readl_poll_timeout(hdev->hw.hw.io_base + 1373 HCLGEVF_VF_RST_ING, val, 1374 !(val & HCLGEVF_VF_RST_ING_BIT), 1375 HCLGEVF_RESET_WAIT_US, 1376 HCLGEVF_RESET_WAIT_TIMEOUT_US); 1377 else 1378 ret = readl_poll_timeout(hdev->hw.hw.io_base + 1379 HCLGEVF_RST_ING, val, 1380 !(val & HCLGEVF_RST_ING_BITS), 1381 HCLGEVF_RESET_WAIT_US, 1382 HCLGEVF_RESET_WAIT_TIMEOUT_US); 1383 1384 /* hardware completion status should be available by this time */ 1385 if (ret) { 1386 dev_err(&hdev->pdev->dev, 1387 "couldn't get reset done status from h/w, timeout!\n"); 1388 return ret; 1389 } 1390 1391 /* we will wait a bit more to let reset of the stack to complete. This 1392 * might happen in case reset assertion was made by PF. Yes, this also 1393 * means we might end up waiting bit more even for VF reset. 1394 */ 1395 if (hdev->reset_type == HNAE3_VF_FULL_RESET) 1396 msleep(5000); 1397 else 1398 msleep(500); 1399 1400 return 0; 1401 } 1402 1403 static void hclgevf_reset_handshake(struct hclgevf_dev *hdev, bool enable) 1404 { 1405 u32 reg_val; 1406 1407 reg_val = hclgevf_read_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG); 1408 if (enable) 1409 reg_val |= HCLGEVF_NIC_SW_RST_RDY; 1410 else 1411 reg_val &= ~HCLGEVF_NIC_SW_RST_RDY; 1412 1413 hclgevf_write_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG, 1414 reg_val); 1415 } 1416 1417 static int hclgevf_reset_stack(struct hclgevf_dev *hdev) 1418 { 1419 int ret; 1420 1421 /* uninitialize the nic client */ 1422 ret = hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT); 1423 if (ret) 1424 return ret; 1425 1426 /* re-initialize the hclge device */ 1427 ret = hclgevf_reset_hdev(hdev); 1428 if (ret) { 1429 dev_err(&hdev->pdev->dev, 1430 "hclge device re-init failed, VF is disabled!\n"); 1431 return ret; 1432 } 1433 1434 /* bring up the nic client again */ 1435 ret = hclgevf_notify_client(hdev, HNAE3_INIT_CLIENT); 1436 if (ret) 1437 return ret; 1438 1439 /* clear handshake status with IMP */ 1440 hclgevf_reset_handshake(hdev, false); 1441 1442 /* bring up the nic to enable TX/RX again */ 1443 return hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 1444 } 1445 1446 static int hclgevf_reset_prepare_wait(struct hclgevf_dev *hdev) 1447 { 1448 #define HCLGEVF_RESET_SYNC_TIME 100 1449 1450 if (hdev->reset_type == HNAE3_VF_FUNC_RESET) { 1451 struct hclge_vf_to_pf_msg send_msg; 1452 int ret; 1453 1454 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_RESET, 0); 1455 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1456 if (ret) { 1457 dev_err(&hdev->pdev->dev, 1458 "failed to assert VF reset, ret = %d\n", ret); 1459 return ret; 1460 } 1461 hdev->rst_stats.vf_func_rst_cnt++; 1462 } 1463 1464 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 1465 /* inform hardware that preparatory work is done */ 1466 msleep(HCLGEVF_RESET_SYNC_TIME); 1467 hclgevf_reset_handshake(hdev, true); 1468 dev_info(&hdev->pdev->dev, "prepare reset(%d) wait done\n", 1469 hdev->reset_type); 1470 1471 return 0; 1472 } 1473 1474 static void hclgevf_dump_rst_info(struct hclgevf_dev *hdev) 1475 { 1476 dev_info(&hdev->pdev->dev, "VF function reset count: %u\n", 1477 hdev->rst_stats.vf_func_rst_cnt); 1478 dev_info(&hdev->pdev->dev, "FLR reset count: %u\n", 1479 hdev->rst_stats.flr_rst_cnt); 1480 dev_info(&hdev->pdev->dev, "VF reset count: %u\n", 1481 hdev->rst_stats.vf_rst_cnt); 1482 dev_info(&hdev->pdev->dev, "reset done count: %u\n", 1483 hdev->rst_stats.rst_done_cnt); 1484 dev_info(&hdev->pdev->dev, "HW reset done count: %u\n", 1485 hdev->rst_stats.hw_rst_done_cnt); 1486 dev_info(&hdev->pdev->dev, "reset count: %u\n", 1487 hdev->rst_stats.rst_cnt); 1488 dev_info(&hdev->pdev->dev, "reset fail count: %u\n", 1489 hdev->rst_stats.rst_fail_cnt); 1490 dev_info(&hdev->pdev->dev, "vector0 interrupt enable status: 0x%x\n", 1491 hclgevf_read_dev(&hdev->hw, HCLGEVF_MISC_VECTOR_REG_BASE)); 1492 dev_info(&hdev->pdev->dev, "vector0 interrupt status: 0x%x\n", 1493 hclgevf_read_dev(&hdev->hw, HCLGE_COMM_VECTOR0_CMDQ_STATE_REG)); 1494 dev_info(&hdev->pdev->dev, "handshake status: 0x%x\n", 1495 hclgevf_read_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG)); 1496 dev_info(&hdev->pdev->dev, "function reset status: 0x%x\n", 1497 hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING)); 1498 dev_info(&hdev->pdev->dev, "hdev state: 0x%lx\n", hdev->state); 1499 } 1500 1501 static void hclgevf_reset_err_handle(struct hclgevf_dev *hdev) 1502 { 1503 /* recover handshake status with IMP when reset fail */ 1504 hclgevf_reset_handshake(hdev, true); 1505 hdev->rst_stats.rst_fail_cnt++; 1506 dev_err(&hdev->pdev->dev, "failed to reset VF(%u)\n", 1507 hdev->rst_stats.rst_fail_cnt); 1508 1509 if (hdev->rst_stats.rst_fail_cnt < HCLGEVF_RESET_MAX_FAIL_CNT) 1510 set_bit(hdev->reset_type, &hdev->reset_pending); 1511 1512 if (hclgevf_is_reset_pending(hdev)) { 1513 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1514 hclgevf_reset_task_schedule(hdev); 1515 } else { 1516 set_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state); 1517 hclgevf_dump_rst_info(hdev); 1518 } 1519 } 1520 1521 static int hclgevf_reset_prepare(struct hclgevf_dev *hdev) 1522 { 1523 int ret; 1524 1525 hdev->rst_stats.rst_cnt++; 1526 1527 /* perform reset of the stack & ae device for a client */ 1528 ret = hclgevf_notify_roce_client(hdev, HNAE3_DOWN_CLIENT); 1529 if (ret) 1530 return ret; 1531 1532 rtnl_lock(); 1533 /* bring down the nic to stop any ongoing TX/RX */ 1534 ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 1535 rtnl_unlock(); 1536 if (ret) 1537 return ret; 1538 1539 return hclgevf_reset_prepare_wait(hdev); 1540 } 1541 1542 static int hclgevf_reset_rebuild(struct hclgevf_dev *hdev) 1543 { 1544 int ret; 1545 1546 hdev->rst_stats.hw_rst_done_cnt++; 1547 ret = hclgevf_notify_roce_client(hdev, HNAE3_UNINIT_CLIENT); 1548 if (ret) 1549 return ret; 1550 1551 rtnl_lock(); 1552 /* now, re-initialize the nic client and ae device */ 1553 ret = hclgevf_reset_stack(hdev); 1554 rtnl_unlock(); 1555 if (ret) { 1556 dev_err(&hdev->pdev->dev, "failed to reset VF stack\n"); 1557 return ret; 1558 } 1559 1560 ret = hclgevf_notify_roce_client(hdev, HNAE3_INIT_CLIENT); 1561 /* ignore RoCE notify error if it fails HCLGEVF_RESET_MAX_FAIL_CNT - 1 1562 * times 1563 */ 1564 if (ret && 1565 hdev->rst_stats.rst_fail_cnt < HCLGEVF_RESET_MAX_FAIL_CNT - 1) 1566 return ret; 1567 1568 ret = hclgevf_notify_roce_client(hdev, HNAE3_UP_CLIENT); 1569 if (ret) 1570 return ret; 1571 1572 hdev->last_reset_time = jiffies; 1573 hdev->rst_stats.rst_done_cnt++; 1574 hdev->rst_stats.rst_fail_cnt = 0; 1575 clear_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state); 1576 1577 return 0; 1578 } 1579 1580 static void hclgevf_reset(struct hclgevf_dev *hdev) 1581 { 1582 if (hclgevf_reset_prepare(hdev)) 1583 goto err_reset; 1584 1585 /* check if VF could successfully fetch the hardware reset completion 1586 * status from the hardware 1587 */ 1588 if (hclgevf_reset_wait(hdev)) { 1589 /* can't do much in this situation, will disable VF */ 1590 dev_err(&hdev->pdev->dev, 1591 "failed to fetch H/W reset completion status\n"); 1592 goto err_reset; 1593 } 1594 1595 if (hclgevf_reset_rebuild(hdev)) 1596 goto err_reset; 1597 1598 return; 1599 1600 err_reset: 1601 hclgevf_reset_err_handle(hdev); 1602 } 1603 1604 static enum hnae3_reset_type hclgevf_get_reset_level(unsigned long *addr) 1605 { 1606 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; 1607 1608 /* return the highest priority reset level amongst all */ 1609 if (test_bit(HNAE3_VF_RESET, addr)) { 1610 rst_level = HNAE3_VF_RESET; 1611 clear_bit(HNAE3_VF_RESET, addr); 1612 clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1613 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1614 } else if (test_bit(HNAE3_VF_FULL_RESET, addr)) { 1615 rst_level = HNAE3_VF_FULL_RESET; 1616 clear_bit(HNAE3_VF_FULL_RESET, addr); 1617 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1618 } else if (test_bit(HNAE3_VF_PF_FUNC_RESET, addr)) { 1619 rst_level = HNAE3_VF_PF_FUNC_RESET; 1620 clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1621 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1622 } else if (test_bit(HNAE3_VF_FUNC_RESET, addr)) { 1623 rst_level = HNAE3_VF_FUNC_RESET; 1624 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1625 } else if (test_bit(HNAE3_FLR_RESET, addr)) { 1626 rst_level = HNAE3_FLR_RESET; 1627 clear_bit(HNAE3_FLR_RESET, addr); 1628 } 1629 1630 return rst_level; 1631 } 1632 1633 static void hclgevf_reset_event(struct pci_dev *pdev, 1634 struct hnae3_handle *handle) 1635 { 1636 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 1637 struct hclgevf_dev *hdev = ae_dev->priv; 1638 1639 dev_info(&hdev->pdev->dev, "received reset request from VF enet\n"); 1640 1641 if (hdev->default_reset_request) 1642 hdev->reset_level = 1643 hclgevf_get_reset_level(&hdev->default_reset_request); 1644 else 1645 hdev->reset_level = HNAE3_VF_FUNC_RESET; 1646 1647 /* reset of this VF requested */ 1648 set_bit(HCLGEVF_RESET_REQUESTED, &hdev->reset_state); 1649 hclgevf_reset_task_schedule(hdev); 1650 1651 hdev->last_reset_time = jiffies; 1652 } 1653 1654 static void hclgevf_set_def_reset_request(struct hnae3_ae_dev *ae_dev, 1655 enum hnae3_reset_type rst_type) 1656 { 1657 struct hclgevf_dev *hdev = ae_dev->priv; 1658 1659 set_bit(rst_type, &hdev->default_reset_request); 1660 } 1661 1662 static void hclgevf_enable_vector(struct hclgevf_misc_vector *vector, bool en) 1663 { 1664 writel(en ? 1 : 0, vector->addr); 1665 } 1666 1667 static void hclgevf_reset_prepare_general(struct hnae3_ae_dev *ae_dev, 1668 enum hnae3_reset_type rst_type) 1669 { 1670 #define HCLGEVF_RESET_RETRY_WAIT_MS 500 1671 #define HCLGEVF_RESET_RETRY_CNT 5 1672 1673 struct hclgevf_dev *hdev = ae_dev->priv; 1674 int retry_cnt = 0; 1675 int ret; 1676 1677 while (retry_cnt++ < HCLGEVF_RESET_RETRY_CNT) { 1678 down(&hdev->reset_sem); 1679 set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 1680 hdev->reset_type = rst_type; 1681 ret = hclgevf_reset_prepare(hdev); 1682 if (!ret && !hdev->reset_pending) 1683 break; 1684 1685 dev_err(&hdev->pdev->dev, 1686 "failed to prepare to reset, ret=%d, reset_pending:0x%lx, retry_cnt:%d\n", 1687 ret, hdev->reset_pending, retry_cnt); 1688 clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 1689 up(&hdev->reset_sem); 1690 msleep(HCLGEVF_RESET_RETRY_WAIT_MS); 1691 } 1692 1693 /* disable misc vector before reset done */ 1694 hclgevf_enable_vector(&hdev->misc_vector, false); 1695 1696 if (hdev->reset_type == HNAE3_FLR_RESET) 1697 hdev->rst_stats.flr_rst_cnt++; 1698 } 1699 1700 static void hclgevf_reset_done(struct hnae3_ae_dev *ae_dev) 1701 { 1702 struct hclgevf_dev *hdev = ae_dev->priv; 1703 int ret; 1704 1705 hclgevf_enable_vector(&hdev->misc_vector, true); 1706 1707 ret = hclgevf_reset_rebuild(hdev); 1708 if (ret) 1709 dev_warn(&hdev->pdev->dev, "fail to rebuild, ret=%d\n", 1710 ret); 1711 1712 hdev->reset_type = HNAE3_NONE_RESET; 1713 clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 1714 up(&hdev->reset_sem); 1715 } 1716 1717 static u32 hclgevf_get_fw_version(struct hnae3_handle *handle) 1718 { 1719 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1720 1721 return hdev->fw_version; 1722 } 1723 1724 static void hclgevf_get_misc_vector(struct hclgevf_dev *hdev) 1725 { 1726 struct hclgevf_misc_vector *vector = &hdev->misc_vector; 1727 1728 vector->vector_irq = pci_irq_vector(hdev->pdev, 1729 HCLGEVF_MISC_VECTOR_NUM); 1730 vector->addr = hdev->hw.hw.io_base + HCLGEVF_MISC_VECTOR_REG_BASE; 1731 /* vector status always valid for Vector 0 */ 1732 hdev->vector_status[HCLGEVF_MISC_VECTOR_NUM] = 0; 1733 hdev->vector_irq[HCLGEVF_MISC_VECTOR_NUM] = vector->vector_irq; 1734 1735 hdev->num_msi_left -= 1; 1736 hdev->num_msi_used += 1; 1737 } 1738 1739 void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev) 1740 { 1741 if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) && 1742 test_bit(HCLGEVF_STATE_SERVICE_INITED, &hdev->state) && 1743 !test_and_set_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, 1744 &hdev->state)) 1745 mod_delayed_work(hclgevf_wq, &hdev->service_task, 0); 1746 } 1747 1748 void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev) 1749 { 1750 if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) && 1751 !test_and_set_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, 1752 &hdev->state)) 1753 mod_delayed_work(hclgevf_wq, &hdev->service_task, 0); 1754 } 1755 1756 static void hclgevf_task_schedule(struct hclgevf_dev *hdev, 1757 unsigned long delay) 1758 { 1759 if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) && 1760 !test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) 1761 mod_delayed_work(hclgevf_wq, &hdev->service_task, delay); 1762 } 1763 1764 static void hclgevf_reset_service_task(struct hclgevf_dev *hdev) 1765 { 1766 #define HCLGEVF_MAX_RESET_ATTEMPTS_CNT 3 1767 1768 if (!test_and_clear_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state)) 1769 return; 1770 1771 down(&hdev->reset_sem); 1772 set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 1773 1774 if (test_and_clear_bit(HCLGEVF_RESET_PENDING, 1775 &hdev->reset_state)) { 1776 /* PF has intimated that it is about to reset the hardware. 1777 * We now have to poll & check if hardware has actually 1778 * completed the reset sequence. On hardware reset completion, 1779 * VF needs to reset the client and ae device. 1780 */ 1781 hdev->reset_attempts = 0; 1782 1783 hdev->last_reset_time = jiffies; 1784 hdev->reset_type = 1785 hclgevf_get_reset_level(&hdev->reset_pending); 1786 if (hdev->reset_type != HNAE3_NONE_RESET) 1787 hclgevf_reset(hdev); 1788 } else if (test_and_clear_bit(HCLGEVF_RESET_REQUESTED, 1789 &hdev->reset_state)) { 1790 /* we could be here when either of below happens: 1791 * 1. reset was initiated due to watchdog timeout caused by 1792 * a. IMP was earlier reset and our TX got choked down and 1793 * which resulted in watchdog reacting and inducing VF 1794 * reset. This also means our cmdq would be unreliable. 1795 * b. problem in TX due to other lower layer(example link 1796 * layer not functioning properly etc.) 1797 * 2. VF reset might have been initiated due to some config 1798 * change. 1799 * 1800 * NOTE: Theres no clear way to detect above cases than to react 1801 * to the response of PF for this reset request. PF will ack the 1802 * 1b and 2. cases but we will not get any intimation about 1a 1803 * from PF as cmdq would be in unreliable state i.e. mailbox 1804 * communication between PF and VF would be broken. 1805 * 1806 * if we are never geting into pending state it means either: 1807 * 1. PF is not receiving our request which could be due to IMP 1808 * reset 1809 * 2. PF is screwed 1810 * We cannot do much for 2. but to check first we can try reset 1811 * our PCIe + stack and see if it alleviates the problem. 1812 */ 1813 if (hdev->reset_attempts > HCLGEVF_MAX_RESET_ATTEMPTS_CNT) { 1814 /* prepare for full reset of stack + pcie interface */ 1815 set_bit(HNAE3_VF_FULL_RESET, &hdev->reset_pending); 1816 1817 /* "defer" schedule the reset task again */ 1818 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1819 } else { 1820 hdev->reset_attempts++; 1821 1822 set_bit(hdev->reset_level, &hdev->reset_pending); 1823 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1824 } 1825 hclgevf_reset_task_schedule(hdev); 1826 } 1827 1828 hdev->reset_type = HNAE3_NONE_RESET; 1829 clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 1830 up(&hdev->reset_sem); 1831 } 1832 1833 static void hclgevf_mailbox_service_task(struct hclgevf_dev *hdev) 1834 { 1835 if (!test_and_clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state)) 1836 return; 1837 1838 if (test_and_set_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) 1839 return; 1840 1841 hclgevf_mbx_async_handler(hdev); 1842 1843 clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 1844 } 1845 1846 static void hclgevf_keep_alive(struct hclgevf_dev *hdev) 1847 { 1848 struct hclge_vf_to_pf_msg send_msg; 1849 int ret; 1850 1851 if (test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state)) 1852 return; 1853 1854 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_KEEP_ALIVE, 0); 1855 ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 1856 if (ret) 1857 dev_err(&hdev->pdev->dev, 1858 "VF sends keep alive cmd failed(=%d)\n", ret); 1859 } 1860 1861 static void hclgevf_periodic_service_task(struct hclgevf_dev *hdev) 1862 { 1863 unsigned long delta = round_jiffies_relative(HZ); 1864 struct hnae3_handle *handle = &hdev->nic; 1865 1866 if (test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state) || 1867 test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state)) 1868 return; 1869 1870 if (time_is_after_jiffies(hdev->last_serv_processed + HZ)) { 1871 delta = jiffies - hdev->last_serv_processed; 1872 1873 if (delta < round_jiffies_relative(HZ)) { 1874 delta = round_jiffies_relative(HZ) - delta; 1875 goto out; 1876 } 1877 } 1878 1879 hdev->serv_processed_cnt++; 1880 if (!(hdev->serv_processed_cnt % HCLGEVF_KEEP_ALIVE_TASK_INTERVAL)) 1881 hclgevf_keep_alive(hdev); 1882 1883 if (test_bit(HCLGEVF_STATE_DOWN, &hdev->state)) { 1884 hdev->last_serv_processed = jiffies; 1885 goto out; 1886 } 1887 1888 if (!(hdev->serv_processed_cnt % HCLGEVF_STATS_TIMER_INTERVAL)) 1889 hclge_comm_tqps_update_stats(handle, &hdev->hw.hw); 1890 1891 /* VF does not need to request link status when this bit is set, because 1892 * PF will push its link status to VFs when link status changed. 1893 */ 1894 if (!test_bit(HCLGEVF_STATE_PF_PUSH_LINK_STATUS, &hdev->state)) 1895 hclgevf_request_link_info(hdev); 1896 1897 hclgevf_update_link_mode(hdev); 1898 1899 hclgevf_sync_vlan_filter(hdev); 1900 1901 hclgevf_sync_mac_table(hdev); 1902 1903 hclgevf_sync_promisc_mode(hdev); 1904 1905 hdev->last_serv_processed = jiffies; 1906 1907 out: 1908 hclgevf_task_schedule(hdev, delta); 1909 } 1910 1911 static void hclgevf_service_task(struct work_struct *work) 1912 { 1913 struct hclgevf_dev *hdev = container_of(work, struct hclgevf_dev, 1914 service_task.work); 1915 1916 hclgevf_reset_service_task(hdev); 1917 hclgevf_mailbox_service_task(hdev); 1918 hclgevf_periodic_service_task(hdev); 1919 1920 /* Handle reset and mbx again in case periodical task delays the 1921 * handling by calling hclgevf_task_schedule() in 1922 * hclgevf_periodic_service_task() 1923 */ 1924 hclgevf_reset_service_task(hdev); 1925 hclgevf_mailbox_service_task(hdev); 1926 } 1927 1928 static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regclr) 1929 { 1930 hclgevf_write_dev(&hdev->hw, HCLGE_COMM_VECTOR0_CMDQ_SRC_REG, regclr); 1931 } 1932 1933 static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev, 1934 u32 *clearval) 1935 { 1936 u32 val, cmdq_stat_reg, rst_ing_reg; 1937 1938 /* fetch the events from their corresponding regs */ 1939 cmdq_stat_reg = hclgevf_read_dev(&hdev->hw, 1940 HCLGE_COMM_VECTOR0_CMDQ_STATE_REG); 1941 if (BIT(HCLGEVF_VECTOR0_RST_INT_B) & cmdq_stat_reg) { 1942 rst_ing_reg = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 1943 dev_info(&hdev->pdev->dev, 1944 "receive reset interrupt 0x%x!\n", rst_ing_reg); 1945 set_bit(HNAE3_VF_RESET, &hdev->reset_pending); 1946 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1947 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 1948 *clearval = ~(1U << HCLGEVF_VECTOR0_RST_INT_B); 1949 hdev->rst_stats.vf_rst_cnt++; 1950 /* set up VF hardware reset status, its PF will clear 1951 * this status when PF has initialized done. 1952 */ 1953 val = hclgevf_read_dev(&hdev->hw, HCLGEVF_VF_RST_ING); 1954 hclgevf_write_dev(&hdev->hw, HCLGEVF_VF_RST_ING, 1955 val | HCLGEVF_VF_RST_ING_BIT); 1956 return HCLGEVF_VECTOR0_EVENT_RST; 1957 } 1958 1959 /* check for vector0 mailbox(=CMDQ RX) event source */ 1960 if (BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) { 1961 /* for revision 0x21, clearing interrupt is writing bit 0 1962 * to the clear register, writing bit 1 means to keep the 1963 * old value. 1964 * for revision 0x20, the clear register is a read & write 1965 * register, so we should just write 0 to the bit we are 1966 * handling, and keep other bits as cmdq_stat_reg. 1967 */ 1968 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) 1969 *clearval = ~(1U << HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 1970 else 1971 *clearval = cmdq_stat_reg & 1972 ~BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 1973 1974 return HCLGEVF_VECTOR0_EVENT_MBX; 1975 } 1976 1977 /* print other vector0 event source */ 1978 dev_info(&hdev->pdev->dev, 1979 "vector 0 interrupt from unknown source, cmdq_src = %#x\n", 1980 cmdq_stat_reg); 1981 1982 return HCLGEVF_VECTOR0_EVENT_OTHER; 1983 } 1984 1985 static void hclgevf_reset_timer(struct timer_list *t) 1986 { 1987 struct hclgevf_dev *hdev = from_timer(hdev, t, reset_timer); 1988 1989 hclgevf_clear_event_cause(hdev, HCLGEVF_VECTOR0_EVENT_RST); 1990 hclgevf_reset_task_schedule(hdev); 1991 } 1992 1993 static irqreturn_t hclgevf_misc_irq_handle(int irq, void *data) 1994 { 1995 #define HCLGEVF_RESET_DELAY 5 1996 1997 enum hclgevf_evt_cause event_cause; 1998 struct hclgevf_dev *hdev = data; 1999 u32 clearval; 2000 2001 hclgevf_enable_vector(&hdev->misc_vector, false); 2002 event_cause = hclgevf_check_evt_cause(hdev, &clearval); 2003 if (event_cause != HCLGEVF_VECTOR0_EVENT_OTHER) 2004 hclgevf_clear_event_cause(hdev, clearval); 2005 2006 switch (event_cause) { 2007 case HCLGEVF_VECTOR0_EVENT_RST: 2008 mod_timer(&hdev->reset_timer, 2009 jiffies + msecs_to_jiffies(HCLGEVF_RESET_DELAY)); 2010 break; 2011 case HCLGEVF_VECTOR0_EVENT_MBX: 2012 hclgevf_mbx_handler(hdev); 2013 break; 2014 default: 2015 break; 2016 } 2017 2018 hclgevf_enable_vector(&hdev->misc_vector, true); 2019 2020 return IRQ_HANDLED; 2021 } 2022 2023 static int hclgevf_configure(struct hclgevf_dev *hdev) 2024 { 2025 int ret; 2026 2027 hdev->gro_en = true; 2028 2029 ret = hclgevf_get_basic_info(hdev); 2030 if (ret) 2031 return ret; 2032 2033 /* get current port based vlan state from PF */ 2034 ret = hclgevf_get_port_base_vlan_filter_state(hdev); 2035 if (ret) 2036 return ret; 2037 2038 /* get queue configuration from PF */ 2039 ret = hclgevf_get_queue_info(hdev); 2040 if (ret) 2041 return ret; 2042 2043 /* get queue depth info from PF */ 2044 ret = hclgevf_get_queue_depth(hdev); 2045 if (ret) 2046 return ret; 2047 2048 return hclgevf_get_pf_media_type(hdev); 2049 } 2050 2051 static int hclgevf_alloc_hdev(struct hnae3_ae_dev *ae_dev) 2052 { 2053 struct pci_dev *pdev = ae_dev->pdev; 2054 struct hclgevf_dev *hdev; 2055 2056 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 2057 if (!hdev) 2058 return -ENOMEM; 2059 2060 hdev->pdev = pdev; 2061 hdev->ae_dev = ae_dev; 2062 ae_dev->priv = hdev; 2063 2064 return 0; 2065 } 2066 2067 static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev) 2068 { 2069 struct hnae3_handle *roce = &hdev->roce; 2070 struct hnae3_handle *nic = &hdev->nic; 2071 2072 roce->rinfo.num_vectors = hdev->num_roce_msix; 2073 2074 if (hdev->num_msi_left < roce->rinfo.num_vectors || 2075 hdev->num_msi_left == 0) 2076 return -EINVAL; 2077 2078 roce->rinfo.base_vector = hdev->roce_base_msix_offset; 2079 2080 roce->rinfo.netdev = nic->kinfo.netdev; 2081 roce->rinfo.roce_io_base = hdev->hw.hw.io_base; 2082 roce->rinfo.roce_mem_base = hdev->hw.hw.mem_base; 2083 2084 roce->pdev = nic->pdev; 2085 roce->ae_algo = nic->ae_algo; 2086 bitmap_copy(roce->numa_node_mask.bits, nic->numa_node_mask.bits, 2087 MAX_NUMNODES); 2088 return 0; 2089 } 2090 2091 static int hclgevf_config_gro(struct hclgevf_dev *hdev) 2092 { 2093 struct hclgevf_cfg_gro_status_cmd *req; 2094 struct hclge_desc desc; 2095 int ret; 2096 2097 if (!hnae3_ae_dev_gro_supported(hdev->ae_dev)) 2098 return 0; 2099 2100 hclgevf_cmd_setup_basic_desc(&desc, HCLGE_OPC_GRO_GENERIC_CONFIG, 2101 false); 2102 req = (struct hclgevf_cfg_gro_status_cmd *)desc.data; 2103 2104 req->gro_en = hdev->gro_en ? 1 : 0; 2105 2106 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 2107 if (ret) 2108 dev_err(&hdev->pdev->dev, 2109 "VF GRO hardware config cmd failed, ret = %d.\n", ret); 2110 2111 return ret; 2112 } 2113 2114 static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev) 2115 { 2116 struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg; 2117 u16 tc_offset[HCLGE_COMM_MAX_TC_NUM]; 2118 u16 tc_valid[HCLGE_COMM_MAX_TC_NUM]; 2119 u16 tc_size[HCLGE_COMM_MAX_TC_NUM]; 2120 int ret; 2121 2122 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 2123 ret = hclge_comm_set_rss_algo_key(&hdev->hw.hw, 2124 rss_cfg->rss_algo, 2125 rss_cfg->rss_hash_key); 2126 if (ret) 2127 return ret; 2128 2129 ret = hclge_comm_set_rss_input_tuple(&hdev->hw.hw, rss_cfg); 2130 if (ret) 2131 return ret; 2132 } 2133 2134 ret = hclge_comm_set_rss_indir_table(hdev->ae_dev, &hdev->hw.hw, 2135 rss_cfg->rss_indirection_tbl); 2136 if (ret) 2137 return ret; 2138 2139 hclge_comm_get_rss_tc_info(rss_cfg->rss_size, hdev->hw_tc_map, 2140 tc_offset, tc_valid, tc_size); 2141 2142 return hclge_comm_set_rss_tc_mode(&hdev->hw.hw, tc_offset, 2143 tc_valid, tc_size); 2144 } 2145 2146 static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev) 2147 { 2148 struct hnae3_handle *nic = &hdev->nic; 2149 int ret; 2150 2151 ret = hclgevf_en_hw_strip_rxvtag(nic, true); 2152 if (ret) { 2153 dev_err(&hdev->pdev->dev, 2154 "failed to enable rx vlan offload, ret = %d\n", ret); 2155 return ret; 2156 } 2157 2158 return hclgevf_set_vlan_filter(&hdev->nic, htons(ETH_P_8021Q), 0, 2159 false); 2160 } 2161 2162 static void hclgevf_flush_link_update(struct hclgevf_dev *hdev) 2163 { 2164 #define HCLGEVF_FLUSH_LINK_TIMEOUT 100000 2165 2166 unsigned long last = hdev->serv_processed_cnt; 2167 int i = 0; 2168 2169 while (test_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state) && 2170 i++ < HCLGEVF_FLUSH_LINK_TIMEOUT && 2171 last == hdev->serv_processed_cnt) 2172 usleep_range(1, 1); 2173 } 2174 2175 static void hclgevf_set_timer_task(struct hnae3_handle *handle, bool enable) 2176 { 2177 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2178 2179 if (enable) { 2180 hclgevf_task_schedule(hdev, 0); 2181 } else { 2182 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2183 2184 /* flush memory to make sure DOWN is seen by service task */ 2185 smp_mb__before_atomic(); 2186 hclgevf_flush_link_update(hdev); 2187 } 2188 } 2189 2190 static int hclgevf_ae_start(struct hnae3_handle *handle) 2191 { 2192 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2193 2194 clear_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2195 clear_bit(HCLGEVF_STATE_PF_PUSH_LINK_STATUS, &hdev->state); 2196 2197 hclge_comm_reset_tqp_stats(handle); 2198 2199 hclgevf_request_link_info(hdev); 2200 2201 hclgevf_update_link_mode(hdev); 2202 2203 return 0; 2204 } 2205 2206 static void hclgevf_ae_stop(struct hnae3_handle *handle) 2207 { 2208 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2209 2210 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2211 2212 if (hdev->reset_type != HNAE3_VF_RESET) 2213 hclgevf_reset_tqp(handle); 2214 2215 hclge_comm_reset_tqp_stats(handle); 2216 hclgevf_update_link_status(hdev, 0); 2217 } 2218 2219 static int hclgevf_set_alive(struct hnae3_handle *handle, bool alive) 2220 { 2221 #define HCLGEVF_STATE_ALIVE 1 2222 #define HCLGEVF_STATE_NOT_ALIVE 0 2223 2224 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2225 struct hclge_vf_to_pf_msg send_msg; 2226 2227 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_ALIVE, 0); 2228 send_msg.data[0] = alive ? HCLGEVF_STATE_ALIVE : 2229 HCLGEVF_STATE_NOT_ALIVE; 2230 return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 2231 } 2232 2233 static int hclgevf_client_start(struct hnae3_handle *handle) 2234 { 2235 return hclgevf_set_alive(handle, true); 2236 } 2237 2238 static void hclgevf_client_stop(struct hnae3_handle *handle) 2239 { 2240 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2241 int ret; 2242 2243 ret = hclgevf_set_alive(handle, false); 2244 if (ret) 2245 dev_warn(&hdev->pdev->dev, 2246 "%s failed %d\n", __func__, ret); 2247 } 2248 2249 static void hclgevf_state_init(struct hclgevf_dev *hdev) 2250 { 2251 clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 2252 clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 2253 clear_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state); 2254 2255 INIT_DELAYED_WORK(&hdev->service_task, hclgevf_service_task); 2256 2257 mutex_init(&hdev->mbx_resp.mbx_mutex); 2258 sema_init(&hdev->reset_sem, 1); 2259 2260 spin_lock_init(&hdev->mac_table.mac_list_lock); 2261 INIT_LIST_HEAD(&hdev->mac_table.uc_mac_list); 2262 INIT_LIST_HEAD(&hdev->mac_table.mc_mac_list); 2263 2264 /* bring the device down */ 2265 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2266 } 2267 2268 static void hclgevf_state_uninit(struct hclgevf_dev *hdev) 2269 { 2270 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2271 set_bit(HCLGEVF_STATE_REMOVING, &hdev->state); 2272 2273 if (hdev->service_task.work.func) 2274 cancel_delayed_work_sync(&hdev->service_task); 2275 2276 mutex_destroy(&hdev->mbx_resp.mbx_mutex); 2277 } 2278 2279 static int hclgevf_init_msi(struct hclgevf_dev *hdev) 2280 { 2281 struct pci_dev *pdev = hdev->pdev; 2282 int vectors; 2283 int i; 2284 2285 if (hnae3_dev_roce_supported(hdev)) 2286 vectors = pci_alloc_irq_vectors(pdev, 2287 hdev->roce_base_msix_offset + 1, 2288 hdev->num_msi, 2289 PCI_IRQ_MSIX); 2290 else 2291 vectors = pci_alloc_irq_vectors(pdev, HNAE3_MIN_VECTOR_NUM, 2292 hdev->num_msi, 2293 PCI_IRQ_MSI | PCI_IRQ_MSIX); 2294 2295 if (vectors < 0) { 2296 dev_err(&pdev->dev, 2297 "failed(%d) to allocate MSI/MSI-X vectors\n", 2298 vectors); 2299 return vectors; 2300 } 2301 if (vectors < hdev->num_msi) 2302 dev_warn(&hdev->pdev->dev, 2303 "requested %u MSI/MSI-X, but allocated %d MSI/MSI-X\n", 2304 hdev->num_msi, vectors); 2305 2306 hdev->num_msi = vectors; 2307 hdev->num_msi_left = vectors; 2308 2309 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 2310 sizeof(u16), GFP_KERNEL); 2311 if (!hdev->vector_status) { 2312 pci_free_irq_vectors(pdev); 2313 return -ENOMEM; 2314 } 2315 2316 for (i = 0; i < hdev->num_msi; i++) 2317 hdev->vector_status[i] = HCLGEVF_INVALID_VPORT; 2318 2319 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 2320 sizeof(int), GFP_KERNEL); 2321 if (!hdev->vector_irq) { 2322 devm_kfree(&pdev->dev, hdev->vector_status); 2323 pci_free_irq_vectors(pdev); 2324 return -ENOMEM; 2325 } 2326 2327 return 0; 2328 } 2329 2330 static void hclgevf_uninit_msi(struct hclgevf_dev *hdev) 2331 { 2332 struct pci_dev *pdev = hdev->pdev; 2333 2334 devm_kfree(&pdev->dev, hdev->vector_status); 2335 devm_kfree(&pdev->dev, hdev->vector_irq); 2336 pci_free_irq_vectors(pdev); 2337 } 2338 2339 static int hclgevf_misc_irq_init(struct hclgevf_dev *hdev) 2340 { 2341 int ret; 2342 2343 hclgevf_get_misc_vector(hdev); 2344 2345 snprintf(hdev->misc_vector.name, HNAE3_INT_NAME_LEN, "%s-misc-%s", 2346 HCLGEVF_NAME, pci_name(hdev->pdev)); 2347 ret = request_irq(hdev->misc_vector.vector_irq, hclgevf_misc_irq_handle, 2348 0, hdev->misc_vector.name, hdev); 2349 if (ret) { 2350 dev_err(&hdev->pdev->dev, "VF failed to request misc irq(%d)\n", 2351 hdev->misc_vector.vector_irq); 2352 return ret; 2353 } 2354 2355 hclgevf_clear_event_cause(hdev, 0); 2356 2357 /* enable misc. vector(vector 0) */ 2358 hclgevf_enable_vector(&hdev->misc_vector, true); 2359 2360 return ret; 2361 } 2362 2363 static void hclgevf_misc_irq_uninit(struct hclgevf_dev *hdev) 2364 { 2365 /* disable misc vector(vector 0) */ 2366 hclgevf_enable_vector(&hdev->misc_vector, false); 2367 synchronize_irq(hdev->misc_vector.vector_irq); 2368 free_irq(hdev->misc_vector.vector_irq, hdev); 2369 hclgevf_free_vector(hdev, 0); 2370 } 2371 2372 static void hclgevf_info_show(struct hclgevf_dev *hdev) 2373 { 2374 struct device *dev = &hdev->pdev->dev; 2375 2376 dev_info(dev, "VF info begin:\n"); 2377 2378 dev_info(dev, "Task queue pairs numbers: %u\n", hdev->num_tqps); 2379 dev_info(dev, "Desc num per TX queue: %u\n", hdev->num_tx_desc); 2380 dev_info(dev, "Desc num per RX queue: %u\n", hdev->num_rx_desc); 2381 dev_info(dev, "Numbers of vports: %u\n", hdev->num_alloc_vport); 2382 dev_info(dev, "HW tc map: 0x%x\n", hdev->hw_tc_map); 2383 dev_info(dev, "PF media type of this VF: %u\n", 2384 hdev->hw.mac.media_type); 2385 2386 dev_info(dev, "VF info end.\n"); 2387 } 2388 2389 static int hclgevf_init_nic_client_instance(struct hnae3_ae_dev *ae_dev, 2390 struct hnae3_client *client) 2391 { 2392 struct hclgevf_dev *hdev = ae_dev->priv; 2393 int rst_cnt = hdev->rst_stats.rst_cnt; 2394 int ret; 2395 2396 ret = client->ops->init_instance(&hdev->nic); 2397 if (ret) 2398 return ret; 2399 2400 set_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 2401 if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) || 2402 rst_cnt != hdev->rst_stats.rst_cnt) { 2403 clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 2404 2405 client->ops->uninit_instance(&hdev->nic, 0); 2406 return -EBUSY; 2407 } 2408 2409 hnae3_set_client_init_flag(client, ae_dev, 1); 2410 2411 if (netif_msg_drv(&hdev->nic)) 2412 hclgevf_info_show(hdev); 2413 2414 return 0; 2415 } 2416 2417 static int hclgevf_init_roce_client_instance(struct hnae3_ae_dev *ae_dev, 2418 struct hnae3_client *client) 2419 { 2420 struct hclgevf_dev *hdev = ae_dev->priv; 2421 int ret; 2422 2423 if (!hnae3_dev_roce_supported(hdev) || !hdev->roce_client || 2424 !hdev->nic_client) 2425 return 0; 2426 2427 ret = hclgevf_init_roce_base_info(hdev); 2428 if (ret) 2429 return ret; 2430 2431 ret = client->ops->init_instance(&hdev->roce); 2432 if (ret) 2433 return ret; 2434 2435 set_bit(HCLGEVF_STATE_ROCE_REGISTERED, &hdev->state); 2436 hnae3_set_client_init_flag(client, ae_dev, 1); 2437 2438 return 0; 2439 } 2440 2441 static int hclgevf_init_client_instance(struct hnae3_client *client, 2442 struct hnae3_ae_dev *ae_dev) 2443 { 2444 struct hclgevf_dev *hdev = ae_dev->priv; 2445 int ret; 2446 2447 switch (client->type) { 2448 case HNAE3_CLIENT_KNIC: 2449 hdev->nic_client = client; 2450 hdev->nic.client = client; 2451 2452 ret = hclgevf_init_nic_client_instance(ae_dev, client); 2453 if (ret) 2454 goto clear_nic; 2455 2456 ret = hclgevf_init_roce_client_instance(ae_dev, 2457 hdev->roce_client); 2458 if (ret) 2459 goto clear_roce; 2460 2461 break; 2462 case HNAE3_CLIENT_ROCE: 2463 if (hnae3_dev_roce_supported(hdev)) { 2464 hdev->roce_client = client; 2465 hdev->roce.client = client; 2466 } 2467 2468 ret = hclgevf_init_roce_client_instance(ae_dev, client); 2469 if (ret) 2470 goto clear_roce; 2471 2472 break; 2473 default: 2474 return -EINVAL; 2475 } 2476 2477 return 0; 2478 2479 clear_nic: 2480 hdev->nic_client = NULL; 2481 hdev->nic.client = NULL; 2482 return ret; 2483 clear_roce: 2484 hdev->roce_client = NULL; 2485 hdev->roce.client = NULL; 2486 return ret; 2487 } 2488 2489 static void hclgevf_uninit_client_instance(struct hnae3_client *client, 2490 struct hnae3_ae_dev *ae_dev) 2491 { 2492 struct hclgevf_dev *hdev = ae_dev->priv; 2493 2494 /* un-init roce, if it exists */ 2495 if (hdev->roce_client) { 2496 while (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 2497 msleep(HCLGEVF_WAIT_RESET_DONE); 2498 clear_bit(HCLGEVF_STATE_ROCE_REGISTERED, &hdev->state); 2499 2500 hdev->roce_client->ops->uninit_instance(&hdev->roce, 0); 2501 hdev->roce_client = NULL; 2502 hdev->roce.client = NULL; 2503 } 2504 2505 /* un-init nic/unic, if this was not called by roce client */ 2506 if (client->ops->uninit_instance && hdev->nic_client && 2507 client->type != HNAE3_CLIENT_ROCE) { 2508 while (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 2509 msleep(HCLGEVF_WAIT_RESET_DONE); 2510 clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 2511 2512 client->ops->uninit_instance(&hdev->nic, 0); 2513 hdev->nic_client = NULL; 2514 hdev->nic.client = NULL; 2515 } 2516 } 2517 2518 static int hclgevf_dev_mem_map(struct hclgevf_dev *hdev) 2519 { 2520 struct pci_dev *pdev = hdev->pdev; 2521 struct hclgevf_hw *hw = &hdev->hw; 2522 2523 /* for device does not have device memory, return directly */ 2524 if (!(pci_select_bars(pdev, IORESOURCE_MEM) & BIT(HCLGEVF_MEM_BAR))) 2525 return 0; 2526 2527 hw->hw.mem_base = 2528 devm_ioremap_wc(&pdev->dev, 2529 pci_resource_start(pdev, HCLGEVF_MEM_BAR), 2530 pci_resource_len(pdev, HCLGEVF_MEM_BAR)); 2531 if (!hw->hw.mem_base) { 2532 dev_err(&pdev->dev, "failed to map device memory\n"); 2533 return -EFAULT; 2534 } 2535 2536 return 0; 2537 } 2538 2539 static int hclgevf_pci_init(struct hclgevf_dev *hdev) 2540 { 2541 struct pci_dev *pdev = hdev->pdev; 2542 struct hclgevf_hw *hw; 2543 int ret; 2544 2545 ret = pci_enable_device(pdev); 2546 if (ret) { 2547 dev_err(&pdev->dev, "failed to enable PCI device\n"); 2548 return ret; 2549 } 2550 2551 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 2552 if (ret) { 2553 dev_err(&pdev->dev, "can't set consistent PCI DMA, exiting"); 2554 goto err_disable_device; 2555 } 2556 2557 ret = pci_request_regions(pdev, HCLGEVF_DRIVER_NAME); 2558 if (ret) { 2559 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 2560 goto err_disable_device; 2561 } 2562 2563 pci_set_master(pdev); 2564 hw = &hdev->hw; 2565 hw->hw.io_base = pci_iomap(pdev, 2, 0); 2566 if (!hw->hw.io_base) { 2567 dev_err(&pdev->dev, "can't map configuration register space\n"); 2568 ret = -ENOMEM; 2569 goto err_release_regions; 2570 } 2571 2572 ret = hclgevf_dev_mem_map(hdev); 2573 if (ret) 2574 goto err_unmap_io_base; 2575 2576 return 0; 2577 2578 err_unmap_io_base: 2579 pci_iounmap(pdev, hdev->hw.hw.io_base); 2580 err_release_regions: 2581 pci_release_regions(pdev); 2582 err_disable_device: 2583 pci_disable_device(pdev); 2584 2585 return ret; 2586 } 2587 2588 static void hclgevf_pci_uninit(struct hclgevf_dev *hdev) 2589 { 2590 struct pci_dev *pdev = hdev->pdev; 2591 2592 if (hdev->hw.hw.mem_base) 2593 devm_iounmap(&pdev->dev, hdev->hw.hw.mem_base); 2594 2595 pci_iounmap(pdev, hdev->hw.hw.io_base); 2596 pci_release_regions(pdev); 2597 pci_disable_device(pdev); 2598 } 2599 2600 static int hclgevf_query_vf_resource(struct hclgevf_dev *hdev) 2601 { 2602 struct hclgevf_query_res_cmd *req; 2603 struct hclge_desc desc; 2604 int ret; 2605 2606 hclgevf_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_VF_RSRC, true); 2607 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 2608 if (ret) { 2609 dev_err(&hdev->pdev->dev, 2610 "query vf resource failed, ret = %d.\n", ret); 2611 return ret; 2612 } 2613 2614 req = (struct hclgevf_query_res_cmd *)desc.data; 2615 2616 if (hnae3_dev_roce_supported(hdev)) { 2617 hdev->roce_base_msix_offset = 2618 hnae3_get_field(le16_to_cpu(req->msixcap_localid_ba_rocee), 2619 HCLGEVF_MSIX_OFT_ROCEE_M, 2620 HCLGEVF_MSIX_OFT_ROCEE_S); 2621 hdev->num_roce_msix = 2622 hnae3_get_field(le16_to_cpu(req->vf_intr_vector_number), 2623 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 2624 2625 /* nic's msix numbers is always equals to the roce's. */ 2626 hdev->num_nic_msix = hdev->num_roce_msix; 2627 2628 /* VF should have NIC vectors and Roce vectors, NIC vectors 2629 * are queued before Roce vectors. The offset is fixed to 64. 2630 */ 2631 hdev->num_msi = hdev->num_roce_msix + 2632 hdev->roce_base_msix_offset; 2633 } else { 2634 hdev->num_msi = 2635 hnae3_get_field(le16_to_cpu(req->vf_intr_vector_number), 2636 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 2637 2638 hdev->num_nic_msix = hdev->num_msi; 2639 } 2640 2641 if (hdev->num_nic_msix < HNAE3_MIN_VECTOR_NUM) { 2642 dev_err(&hdev->pdev->dev, 2643 "Just %u msi resources, not enough for vf(min:2).\n", 2644 hdev->num_nic_msix); 2645 return -EINVAL; 2646 } 2647 2648 return 0; 2649 } 2650 2651 static void hclgevf_set_default_dev_specs(struct hclgevf_dev *hdev) 2652 { 2653 #define HCLGEVF_MAX_NON_TSO_BD_NUM 8U 2654 2655 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 2656 2657 ae_dev->dev_specs.max_non_tso_bd_num = 2658 HCLGEVF_MAX_NON_TSO_BD_NUM; 2659 ae_dev->dev_specs.rss_ind_tbl_size = HCLGEVF_RSS_IND_TBL_SIZE; 2660 ae_dev->dev_specs.rss_key_size = HCLGE_COMM_RSS_KEY_SIZE; 2661 ae_dev->dev_specs.max_int_gl = HCLGEVF_DEF_MAX_INT_GL; 2662 ae_dev->dev_specs.max_frm_size = HCLGEVF_MAC_MAX_FRAME; 2663 } 2664 2665 static void hclgevf_parse_dev_specs(struct hclgevf_dev *hdev, 2666 struct hclge_desc *desc) 2667 { 2668 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 2669 struct hclgevf_dev_specs_0_cmd *req0; 2670 struct hclgevf_dev_specs_1_cmd *req1; 2671 2672 req0 = (struct hclgevf_dev_specs_0_cmd *)desc[0].data; 2673 req1 = (struct hclgevf_dev_specs_1_cmd *)desc[1].data; 2674 2675 ae_dev->dev_specs.max_non_tso_bd_num = req0->max_non_tso_bd_num; 2676 ae_dev->dev_specs.rss_ind_tbl_size = 2677 le16_to_cpu(req0->rss_ind_tbl_size); 2678 ae_dev->dev_specs.int_ql_max = le16_to_cpu(req0->int_ql_max); 2679 ae_dev->dev_specs.rss_key_size = le16_to_cpu(req0->rss_key_size); 2680 ae_dev->dev_specs.max_int_gl = le16_to_cpu(req1->max_int_gl); 2681 ae_dev->dev_specs.max_frm_size = le16_to_cpu(req1->max_frm_size); 2682 } 2683 2684 static void hclgevf_check_dev_specs(struct hclgevf_dev *hdev) 2685 { 2686 struct hnae3_dev_specs *dev_specs = &hdev->ae_dev->dev_specs; 2687 2688 if (!dev_specs->max_non_tso_bd_num) 2689 dev_specs->max_non_tso_bd_num = HCLGEVF_MAX_NON_TSO_BD_NUM; 2690 if (!dev_specs->rss_ind_tbl_size) 2691 dev_specs->rss_ind_tbl_size = HCLGEVF_RSS_IND_TBL_SIZE; 2692 if (!dev_specs->rss_key_size) 2693 dev_specs->rss_key_size = HCLGE_COMM_RSS_KEY_SIZE; 2694 if (!dev_specs->max_int_gl) 2695 dev_specs->max_int_gl = HCLGEVF_DEF_MAX_INT_GL; 2696 if (!dev_specs->max_frm_size) 2697 dev_specs->max_frm_size = HCLGEVF_MAC_MAX_FRAME; 2698 } 2699 2700 static int hclgevf_query_dev_specs(struct hclgevf_dev *hdev) 2701 { 2702 struct hclge_desc desc[HCLGEVF_QUERY_DEV_SPECS_BD_NUM]; 2703 int ret; 2704 int i; 2705 2706 /* set default specifications as devices lower than version V3 do not 2707 * support querying specifications from firmware. 2708 */ 2709 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3) { 2710 hclgevf_set_default_dev_specs(hdev); 2711 return 0; 2712 } 2713 2714 for (i = 0; i < HCLGEVF_QUERY_DEV_SPECS_BD_NUM - 1; i++) { 2715 hclgevf_cmd_setup_basic_desc(&desc[i], 2716 HCLGE_OPC_QUERY_DEV_SPECS, true); 2717 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2718 } 2719 hclgevf_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_DEV_SPECS, true); 2720 2721 ret = hclgevf_cmd_send(&hdev->hw, desc, HCLGEVF_QUERY_DEV_SPECS_BD_NUM); 2722 if (ret) 2723 return ret; 2724 2725 hclgevf_parse_dev_specs(hdev, desc); 2726 hclgevf_check_dev_specs(hdev); 2727 2728 return 0; 2729 } 2730 2731 static int hclgevf_pci_reset(struct hclgevf_dev *hdev) 2732 { 2733 struct pci_dev *pdev = hdev->pdev; 2734 int ret = 0; 2735 2736 if ((hdev->reset_type == HNAE3_VF_FULL_RESET || 2737 hdev->reset_type == HNAE3_FLR_RESET) && 2738 test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2739 hclgevf_misc_irq_uninit(hdev); 2740 hclgevf_uninit_msi(hdev); 2741 clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2742 } 2743 2744 if (!test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2745 pci_set_master(pdev); 2746 ret = hclgevf_init_msi(hdev); 2747 if (ret) { 2748 dev_err(&pdev->dev, 2749 "failed(%d) to init MSI/MSI-X\n", ret); 2750 return ret; 2751 } 2752 2753 ret = hclgevf_misc_irq_init(hdev); 2754 if (ret) { 2755 hclgevf_uninit_msi(hdev); 2756 dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 2757 ret); 2758 return ret; 2759 } 2760 2761 set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2762 } 2763 2764 return ret; 2765 } 2766 2767 static int hclgevf_clear_vport_list(struct hclgevf_dev *hdev) 2768 { 2769 struct hclge_vf_to_pf_msg send_msg; 2770 2771 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_HANDLE_VF_TBL, 2772 HCLGE_MBX_VPORT_LIST_CLEAR); 2773 return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 2774 } 2775 2776 static void hclgevf_init_rxd_adv_layout(struct hclgevf_dev *hdev) 2777 { 2778 if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev)) 2779 hclgevf_write_dev(&hdev->hw, HCLGEVF_RXD_ADV_LAYOUT_EN_REG, 1); 2780 } 2781 2782 static void hclgevf_uninit_rxd_adv_layout(struct hclgevf_dev *hdev) 2783 { 2784 if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev)) 2785 hclgevf_write_dev(&hdev->hw, HCLGEVF_RXD_ADV_LAYOUT_EN_REG, 0); 2786 } 2787 2788 static int hclgevf_reset_hdev(struct hclgevf_dev *hdev) 2789 { 2790 struct pci_dev *pdev = hdev->pdev; 2791 int ret; 2792 2793 ret = hclgevf_pci_reset(hdev); 2794 if (ret) { 2795 dev_err(&pdev->dev, "pci reset failed %d\n", ret); 2796 return ret; 2797 } 2798 2799 hclgevf_arq_init(hdev); 2800 ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw, 2801 &hdev->fw_version, false, 2802 hdev->reset_pending); 2803 if (ret) { 2804 dev_err(&pdev->dev, "cmd failed %d\n", ret); 2805 return ret; 2806 } 2807 2808 ret = hclgevf_rss_init_hw(hdev); 2809 if (ret) { 2810 dev_err(&hdev->pdev->dev, 2811 "failed(%d) to initialize RSS\n", ret); 2812 return ret; 2813 } 2814 2815 ret = hclgevf_config_gro(hdev); 2816 if (ret) 2817 return ret; 2818 2819 ret = hclgevf_init_vlan_config(hdev); 2820 if (ret) { 2821 dev_err(&hdev->pdev->dev, 2822 "failed(%d) to initialize VLAN config\n", ret); 2823 return ret; 2824 } 2825 2826 /* get current port based vlan state from PF */ 2827 ret = hclgevf_get_port_base_vlan_filter_state(hdev); 2828 if (ret) 2829 return ret; 2830 2831 set_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state); 2832 2833 hclgevf_init_rxd_adv_layout(hdev); 2834 2835 dev_info(&hdev->pdev->dev, "Reset done\n"); 2836 2837 return 0; 2838 } 2839 2840 static int hclgevf_init_hdev(struct hclgevf_dev *hdev) 2841 { 2842 struct pci_dev *pdev = hdev->pdev; 2843 int ret; 2844 2845 ret = hclgevf_pci_init(hdev); 2846 if (ret) 2847 return ret; 2848 2849 ret = hclgevf_devlink_init(hdev); 2850 if (ret) 2851 goto err_devlink_init; 2852 2853 ret = hclge_comm_cmd_queue_init(hdev->pdev, &hdev->hw.hw); 2854 if (ret) 2855 goto err_cmd_queue_init; 2856 2857 hclgevf_arq_init(hdev); 2858 ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw, 2859 &hdev->fw_version, false, 2860 hdev->reset_pending); 2861 if (ret) 2862 goto err_cmd_init; 2863 2864 /* Get vf resource */ 2865 ret = hclgevf_query_vf_resource(hdev); 2866 if (ret) 2867 goto err_cmd_init; 2868 2869 ret = hclgevf_query_dev_specs(hdev); 2870 if (ret) { 2871 dev_err(&pdev->dev, 2872 "failed to query dev specifications, ret = %d\n", ret); 2873 goto err_cmd_init; 2874 } 2875 2876 ret = hclgevf_init_msi(hdev); 2877 if (ret) { 2878 dev_err(&pdev->dev, "failed(%d) to init MSI/MSI-X\n", ret); 2879 goto err_cmd_init; 2880 } 2881 2882 hclgevf_state_init(hdev); 2883 hdev->reset_level = HNAE3_VF_FUNC_RESET; 2884 hdev->reset_type = HNAE3_NONE_RESET; 2885 2886 ret = hclgevf_misc_irq_init(hdev); 2887 if (ret) 2888 goto err_misc_irq_init; 2889 2890 set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2891 2892 ret = hclgevf_configure(hdev); 2893 if (ret) { 2894 dev_err(&pdev->dev, "failed(%d) to fetch configuration\n", ret); 2895 goto err_config; 2896 } 2897 2898 ret = hclgevf_alloc_tqps(hdev); 2899 if (ret) { 2900 dev_err(&pdev->dev, "failed(%d) to allocate TQPs\n", ret); 2901 goto err_config; 2902 } 2903 2904 ret = hclgevf_set_handle_info(hdev); 2905 if (ret) 2906 goto err_config; 2907 2908 ret = hclgevf_config_gro(hdev); 2909 if (ret) 2910 goto err_config; 2911 2912 /* Initialize RSS for this VF */ 2913 ret = hclge_comm_rss_init_cfg(&hdev->nic, hdev->ae_dev, 2914 &hdev->rss_cfg); 2915 if (ret) { 2916 dev_err(&pdev->dev, "failed to init rss cfg, ret = %d\n", ret); 2917 goto err_config; 2918 } 2919 2920 ret = hclgevf_rss_init_hw(hdev); 2921 if (ret) { 2922 dev_err(&hdev->pdev->dev, 2923 "failed(%d) to initialize RSS\n", ret); 2924 goto err_config; 2925 } 2926 2927 /* ensure vf tbl list as empty before init */ 2928 ret = hclgevf_clear_vport_list(hdev); 2929 if (ret) { 2930 dev_err(&pdev->dev, 2931 "failed to clear tbl list configuration, ret = %d.\n", 2932 ret); 2933 goto err_config; 2934 } 2935 2936 ret = hclgevf_init_vlan_config(hdev); 2937 if (ret) { 2938 dev_err(&hdev->pdev->dev, 2939 "failed(%d) to initialize VLAN config\n", ret); 2940 goto err_config; 2941 } 2942 2943 hclgevf_init_rxd_adv_layout(hdev); 2944 2945 set_bit(HCLGEVF_STATE_SERVICE_INITED, &hdev->state); 2946 2947 hdev->last_reset_time = jiffies; 2948 dev_info(&hdev->pdev->dev, "finished initializing %s driver\n", 2949 HCLGEVF_DRIVER_NAME); 2950 2951 hclgevf_task_schedule(hdev, round_jiffies_relative(HZ)); 2952 timer_setup(&hdev->reset_timer, hclgevf_reset_timer, 0); 2953 2954 return 0; 2955 2956 err_config: 2957 hclgevf_misc_irq_uninit(hdev); 2958 err_misc_irq_init: 2959 hclgevf_state_uninit(hdev); 2960 hclgevf_uninit_msi(hdev); 2961 err_cmd_init: 2962 hclge_comm_cmd_uninit(hdev->ae_dev, &hdev->hw.hw); 2963 err_cmd_queue_init: 2964 hclgevf_devlink_uninit(hdev); 2965 err_devlink_init: 2966 hclgevf_pci_uninit(hdev); 2967 clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2968 return ret; 2969 } 2970 2971 static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev) 2972 { 2973 struct hclge_vf_to_pf_msg send_msg; 2974 2975 hclgevf_state_uninit(hdev); 2976 hclgevf_uninit_rxd_adv_layout(hdev); 2977 2978 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_VF_UNINIT, 0); 2979 hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 2980 2981 if (test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2982 hclgevf_misc_irq_uninit(hdev); 2983 hclgevf_uninit_msi(hdev); 2984 } 2985 2986 hclge_comm_cmd_uninit(hdev->ae_dev, &hdev->hw.hw); 2987 hclgevf_devlink_uninit(hdev); 2988 hclgevf_pci_uninit(hdev); 2989 hclgevf_uninit_mac_list(hdev); 2990 } 2991 2992 static int hclgevf_init_ae_dev(struct hnae3_ae_dev *ae_dev) 2993 { 2994 struct pci_dev *pdev = ae_dev->pdev; 2995 int ret; 2996 2997 ret = hclgevf_alloc_hdev(ae_dev); 2998 if (ret) { 2999 dev_err(&pdev->dev, "hclge device allocation failed\n"); 3000 return ret; 3001 } 3002 3003 ret = hclgevf_init_hdev(ae_dev->priv); 3004 if (ret) { 3005 dev_err(&pdev->dev, "hclge device initialization failed\n"); 3006 return ret; 3007 } 3008 3009 return 0; 3010 } 3011 3012 static void hclgevf_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 3013 { 3014 struct hclgevf_dev *hdev = ae_dev->priv; 3015 3016 hclgevf_uninit_hdev(hdev); 3017 ae_dev->priv = NULL; 3018 } 3019 3020 static u32 hclgevf_get_max_channels(struct hclgevf_dev *hdev) 3021 { 3022 struct hnae3_handle *nic = &hdev->nic; 3023 struct hnae3_knic_private_info *kinfo = &nic->kinfo; 3024 3025 return min_t(u32, hdev->rss_size_max, 3026 hdev->num_tqps / kinfo->tc_info.num_tc); 3027 } 3028 3029 /** 3030 * hclgevf_get_channels - Get the current channels enabled and max supported. 3031 * @handle: hardware information for network interface 3032 * @ch: ethtool channels structure 3033 * 3034 * We don't support separate tx and rx queues as channels. The other count 3035 * represents how many queues are being used for control. max_combined counts 3036 * how many queue pairs we can support. They may not be mapped 1 to 1 with 3037 * q_vectors since we support a lot more queue pairs than q_vectors. 3038 **/ 3039 static void hclgevf_get_channels(struct hnae3_handle *handle, 3040 struct ethtool_channels *ch) 3041 { 3042 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3043 3044 ch->max_combined = hclgevf_get_max_channels(hdev); 3045 ch->other_count = 0; 3046 ch->max_other = 0; 3047 ch->combined_count = handle->kinfo.rss_size; 3048 } 3049 3050 static void hclgevf_get_tqps_and_rss_info(struct hnae3_handle *handle, 3051 u16 *alloc_tqps, u16 *max_rss_size) 3052 { 3053 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3054 3055 *alloc_tqps = hdev->num_tqps; 3056 *max_rss_size = hdev->rss_size_max; 3057 } 3058 3059 static void hclgevf_update_rss_size(struct hnae3_handle *handle, 3060 u32 new_tqps_num) 3061 { 3062 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 3063 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3064 u16 max_rss_size; 3065 3066 kinfo->req_rss_size = new_tqps_num; 3067 3068 max_rss_size = min_t(u16, hdev->rss_size_max, 3069 hdev->num_tqps / kinfo->tc_info.num_tc); 3070 3071 /* Use the user's configuration when it is not larger than 3072 * max_rss_size, otherwise, use the maximum specification value. 3073 */ 3074 if (kinfo->req_rss_size != kinfo->rss_size && kinfo->req_rss_size && 3075 kinfo->req_rss_size <= max_rss_size) 3076 kinfo->rss_size = kinfo->req_rss_size; 3077 else if (kinfo->rss_size > max_rss_size || 3078 (!kinfo->req_rss_size && kinfo->rss_size < max_rss_size)) 3079 kinfo->rss_size = max_rss_size; 3080 3081 kinfo->num_tqps = kinfo->tc_info.num_tc * kinfo->rss_size; 3082 } 3083 3084 static int hclgevf_set_channels(struct hnae3_handle *handle, u32 new_tqps_num, 3085 bool rxfh_configured) 3086 { 3087 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3088 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 3089 u16 tc_offset[HCLGE_COMM_MAX_TC_NUM]; 3090 u16 tc_valid[HCLGE_COMM_MAX_TC_NUM]; 3091 u16 tc_size[HCLGE_COMM_MAX_TC_NUM]; 3092 u16 cur_rss_size = kinfo->rss_size; 3093 u16 cur_tqps = kinfo->num_tqps; 3094 u32 *rss_indir; 3095 unsigned int i; 3096 int ret; 3097 3098 hclgevf_update_rss_size(handle, new_tqps_num); 3099 3100 hclge_comm_get_rss_tc_info(kinfo->rss_size, hdev->hw_tc_map, 3101 tc_offset, tc_valid, tc_size); 3102 ret = hclge_comm_set_rss_tc_mode(&hdev->hw.hw, tc_offset, 3103 tc_valid, tc_size); 3104 if (ret) 3105 return ret; 3106 3107 /* RSS indirection table has been configured by user */ 3108 if (rxfh_configured) 3109 goto out; 3110 3111 /* Reinitializes the rss indirect table according to the new RSS size */ 3112 rss_indir = kcalloc(hdev->ae_dev->dev_specs.rss_ind_tbl_size, 3113 sizeof(u32), GFP_KERNEL); 3114 if (!rss_indir) 3115 return -ENOMEM; 3116 3117 for (i = 0; i < hdev->ae_dev->dev_specs.rss_ind_tbl_size; i++) 3118 rss_indir[i] = i % kinfo->rss_size; 3119 3120 hdev->rss_cfg.rss_size = kinfo->rss_size; 3121 3122 ret = hclgevf_set_rss(handle, rss_indir, NULL, 0); 3123 if (ret) 3124 dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n", 3125 ret); 3126 3127 kfree(rss_indir); 3128 3129 out: 3130 if (!ret) 3131 dev_info(&hdev->pdev->dev, 3132 "Channels changed, rss_size from %u to %u, tqps from %u to %u", 3133 cur_rss_size, kinfo->rss_size, 3134 cur_tqps, kinfo->rss_size * kinfo->tc_info.num_tc); 3135 3136 return ret; 3137 } 3138 3139 static int hclgevf_get_status(struct hnae3_handle *handle) 3140 { 3141 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3142 3143 return hdev->hw.mac.link; 3144 } 3145 3146 static void hclgevf_get_ksettings_an_result(struct hnae3_handle *handle, 3147 u8 *auto_neg, u32 *speed, 3148 u8 *duplex, u32 *lane_num) 3149 { 3150 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3151 3152 if (speed) 3153 *speed = hdev->hw.mac.speed; 3154 if (duplex) 3155 *duplex = hdev->hw.mac.duplex; 3156 if (auto_neg) 3157 *auto_neg = AUTONEG_DISABLE; 3158 } 3159 3160 void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed, 3161 u8 duplex) 3162 { 3163 hdev->hw.mac.speed = speed; 3164 hdev->hw.mac.duplex = duplex; 3165 } 3166 3167 static int hclgevf_gro_en(struct hnae3_handle *handle, bool enable) 3168 { 3169 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3170 bool gro_en_old = hdev->gro_en; 3171 int ret; 3172 3173 hdev->gro_en = enable; 3174 ret = hclgevf_config_gro(hdev); 3175 if (ret) 3176 hdev->gro_en = gro_en_old; 3177 3178 return ret; 3179 } 3180 3181 static void hclgevf_get_media_type(struct hnae3_handle *handle, u8 *media_type, 3182 u8 *module_type) 3183 { 3184 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3185 3186 if (media_type) 3187 *media_type = hdev->hw.mac.media_type; 3188 3189 if (module_type) 3190 *module_type = hdev->hw.mac.module_type; 3191 } 3192 3193 static bool hclgevf_get_hw_reset_stat(struct hnae3_handle *handle) 3194 { 3195 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3196 3197 return !!hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 3198 } 3199 3200 static bool hclgevf_get_cmdq_stat(struct hnae3_handle *handle) 3201 { 3202 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3203 3204 return test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 3205 } 3206 3207 static bool hclgevf_ae_dev_resetting(struct hnae3_handle *handle) 3208 { 3209 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3210 3211 return test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 3212 } 3213 3214 static unsigned long hclgevf_ae_dev_reset_cnt(struct hnae3_handle *handle) 3215 { 3216 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3217 3218 return hdev->rst_stats.hw_rst_done_cnt; 3219 } 3220 3221 static void hclgevf_get_link_mode(struct hnae3_handle *handle, 3222 unsigned long *supported, 3223 unsigned long *advertising) 3224 { 3225 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3226 3227 *supported = hdev->hw.mac.supported; 3228 *advertising = hdev->hw.mac.advertising; 3229 } 3230 3231 void hclgevf_update_port_base_vlan_info(struct hclgevf_dev *hdev, u16 state, 3232 struct hclge_mbx_port_base_vlan *port_base_vlan) 3233 { 3234 struct hnae3_handle *nic = &hdev->nic; 3235 struct hclge_vf_to_pf_msg send_msg; 3236 int ret; 3237 3238 rtnl_lock(); 3239 3240 if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) || 3241 test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) { 3242 dev_warn(&hdev->pdev->dev, 3243 "is resetting when updating port based vlan info\n"); 3244 rtnl_unlock(); 3245 return; 3246 } 3247 3248 ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 3249 if (ret) { 3250 rtnl_unlock(); 3251 return; 3252 } 3253 3254 /* send msg to PF and wait update port based vlan info */ 3255 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 3256 HCLGE_MBX_PORT_BASE_VLAN_CFG); 3257 memcpy(send_msg.data, port_base_vlan, sizeof(*port_base_vlan)); 3258 ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 3259 if (!ret) { 3260 if (state == HNAE3_PORT_BASE_VLAN_DISABLE) 3261 nic->port_base_vlan_state = state; 3262 else 3263 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_ENABLE; 3264 } 3265 3266 hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 3267 rtnl_unlock(); 3268 } 3269 3270 static const struct hnae3_ae_ops hclgevf_ops = { 3271 .init_ae_dev = hclgevf_init_ae_dev, 3272 .uninit_ae_dev = hclgevf_uninit_ae_dev, 3273 .reset_prepare = hclgevf_reset_prepare_general, 3274 .reset_done = hclgevf_reset_done, 3275 .init_client_instance = hclgevf_init_client_instance, 3276 .uninit_client_instance = hclgevf_uninit_client_instance, 3277 .start = hclgevf_ae_start, 3278 .stop = hclgevf_ae_stop, 3279 .client_start = hclgevf_client_start, 3280 .client_stop = hclgevf_client_stop, 3281 .map_ring_to_vector = hclgevf_map_ring_to_vector, 3282 .unmap_ring_from_vector = hclgevf_unmap_ring_from_vector, 3283 .get_vector = hclgevf_get_vector, 3284 .put_vector = hclgevf_put_vector, 3285 .reset_queue = hclgevf_reset_tqp, 3286 .get_mac_addr = hclgevf_get_mac_addr, 3287 .set_mac_addr = hclgevf_set_mac_addr, 3288 .add_uc_addr = hclgevf_add_uc_addr, 3289 .rm_uc_addr = hclgevf_rm_uc_addr, 3290 .add_mc_addr = hclgevf_add_mc_addr, 3291 .rm_mc_addr = hclgevf_rm_mc_addr, 3292 .get_stats = hclgevf_get_stats, 3293 .update_stats = hclgevf_update_stats, 3294 .get_strings = hclgevf_get_strings, 3295 .get_sset_count = hclgevf_get_sset_count, 3296 .get_rss_key_size = hclge_comm_get_rss_key_size, 3297 .get_rss = hclgevf_get_rss, 3298 .set_rss = hclgevf_set_rss, 3299 .get_rss_tuple = hclgevf_get_rss_tuple, 3300 .set_rss_tuple = hclgevf_set_rss_tuple, 3301 .get_tc_size = hclgevf_get_tc_size, 3302 .get_fw_version = hclgevf_get_fw_version, 3303 .set_vlan_filter = hclgevf_set_vlan_filter, 3304 .enable_vlan_filter = hclgevf_enable_vlan_filter, 3305 .enable_hw_strip_rxvtag = hclgevf_en_hw_strip_rxvtag, 3306 .reset_event = hclgevf_reset_event, 3307 .set_default_reset_request = hclgevf_set_def_reset_request, 3308 .set_channels = hclgevf_set_channels, 3309 .get_channels = hclgevf_get_channels, 3310 .get_tqps_and_rss_info = hclgevf_get_tqps_and_rss_info, 3311 .get_regs_len = hclgevf_get_regs_len, 3312 .get_regs = hclgevf_get_regs, 3313 .get_status = hclgevf_get_status, 3314 .get_ksettings_an_result = hclgevf_get_ksettings_an_result, 3315 .get_media_type = hclgevf_get_media_type, 3316 .get_hw_reset_stat = hclgevf_get_hw_reset_stat, 3317 .ae_dev_resetting = hclgevf_ae_dev_resetting, 3318 .ae_dev_reset_cnt = hclgevf_ae_dev_reset_cnt, 3319 .set_gro_en = hclgevf_gro_en, 3320 .set_mtu = hclgevf_set_mtu, 3321 .get_global_queue_id = hclgevf_get_qid_global, 3322 .set_timer_task = hclgevf_set_timer_task, 3323 .get_link_mode = hclgevf_get_link_mode, 3324 .set_promisc_mode = hclgevf_set_promisc_mode, 3325 .request_update_promisc_mode = hclgevf_request_update_promisc_mode, 3326 .get_cmdq_stat = hclgevf_get_cmdq_stat, 3327 }; 3328 3329 static struct hnae3_ae_algo ae_algovf = { 3330 .ops = &hclgevf_ops, 3331 .pdev_id_table = ae_algovf_pci_tbl, 3332 }; 3333 3334 static int __init hclgevf_init(void) 3335 { 3336 pr_info("%s is initializing\n", HCLGEVF_NAME); 3337 3338 hclgevf_wq = alloc_workqueue("%s", WQ_UNBOUND, 0, HCLGEVF_NAME); 3339 if (!hclgevf_wq) { 3340 pr_err("%s: failed to create workqueue\n", HCLGEVF_NAME); 3341 return -ENOMEM; 3342 } 3343 3344 hnae3_register_ae_algo(&ae_algovf); 3345 3346 return 0; 3347 } 3348 3349 static void __exit hclgevf_exit(void) 3350 { 3351 hnae3_unregister_ae_algo(&ae_algovf); 3352 destroy_workqueue(hclgevf_wq); 3353 } 3354 module_init(hclgevf_init); 3355 module_exit(hclgevf_exit); 3356 3357 MODULE_LICENSE("GPL"); 3358 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 3359 MODULE_DESCRIPTION("HCLGEVF Driver"); 3360 MODULE_VERSION(HCLGEVF_MOD_VERSION); 3361