1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/etherdevice.h> 5 #include <linux/iopoll.h> 6 #include <net/rtnetlink.h> 7 #include "hclgevf_cmd.h" 8 #include "hclgevf_main.h" 9 #include "hclge_mbx.h" 10 #include "hnae3.h" 11 12 #define HCLGEVF_NAME "hclgevf" 13 14 #define HCLGEVF_RESET_MAX_FAIL_CNT 5 15 16 static int hclgevf_reset_hdev(struct hclgevf_dev *hdev); 17 static void hclgevf_task_schedule(struct hclgevf_dev *hdev, 18 unsigned long delay); 19 20 static struct hnae3_ae_algo ae_algovf; 21 22 static struct workqueue_struct *hclgevf_wq; 23 24 static const struct pci_device_id ae_algovf_pci_tbl[] = { 25 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_VF), 0}, 26 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF), 27 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 28 /* required last entry */ 29 {0, } 30 }; 31 32 static const u8 hclgevf_hash_key[] = { 33 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2, 34 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0, 35 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4, 36 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C, 37 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA 38 }; 39 40 MODULE_DEVICE_TABLE(pci, ae_algovf_pci_tbl); 41 42 static const u32 cmdq_reg_addr_list[] = {HCLGEVF_CMDQ_TX_ADDR_L_REG, 43 HCLGEVF_CMDQ_TX_ADDR_H_REG, 44 HCLGEVF_CMDQ_TX_DEPTH_REG, 45 HCLGEVF_CMDQ_TX_TAIL_REG, 46 HCLGEVF_CMDQ_TX_HEAD_REG, 47 HCLGEVF_CMDQ_RX_ADDR_L_REG, 48 HCLGEVF_CMDQ_RX_ADDR_H_REG, 49 HCLGEVF_CMDQ_RX_DEPTH_REG, 50 HCLGEVF_CMDQ_RX_TAIL_REG, 51 HCLGEVF_CMDQ_RX_HEAD_REG, 52 HCLGEVF_VECTOR0_CMDQ_SRC_REG, 53 HCLGEVF_VECTOR0_CMDQ_STATE_REG, 54 HCLGEVF_CMDQ_INTR_EN_REG, 55 HCLGEVF_CMDQ_INTR_GEN_REG}; 56 57 static const u32 common_reg_addr_list[] = {HCLGEVF_MISC_VECTOR_REG_BASE, 58 HCLGEVF_RST_ING, 59 HCLGEVF_GRO_EN_REG}; 60 61 static const u32 ring_reg_addr_list[] = {HCLGEVF_RING_RX_ADDR_L_REG, 62 HCLGEVF_RING_RX_ADDR_H_REG, 63 HCLGEVF_RING_RX_BD_NUM_REG, 64 HCLGEVF_RING_RX_BD_LENGTH_REG, 65 HCLGEVF_RING_RX_MERGE_EN_REG, 66 HCLGEVF_RING_RX_TAIL_REG, 67 HCLGEVF_RING_RX_HEAD_REG, 68 HCLGEVF_RING_RX_FBD_NUM_REG, 69 HCLGEVF_RING_RX_OFFSET_REG, 70 HCLGEVF_RING_RX_FBD_OFFSET_REG, 71 HCLGEVF_RING_RX_STASH_REG, 72 HCLGEVF_RING_RX_BD_ERR_REG, 73 HCLGEVF_RING_TX_ADDR_L_REG, 74 HCLGEVF_RING_TX_ADDR_H_REG, 75 HCLGEVF_RING_TX_BD_NUM_REG, 76 HCLGEVF_RING_TX_PRIORITY_REG, 77 HCLGEVF_RING_TX_TC_REG, 78 HCLGEVF_RING_TX_MERGE_EN_REG, 79 HCLGEVF_RING_TX_TAIL_REG, 80 HCLGEVF_RING_TX_HEAD_REG, 81 HCLGEVF_RING_TX_FBD_NUM_REG, 82 HCLGEVF_RING_TX_OFFSET_REG, 83 HCLGEVF_RING_TX_EBD_NUM_REG, 84 HCLGEVF_RING_TX_EBD_OFFSET_REG, 85 HCLGEVF_RING_TX_BD_ERR_REG, 86 HCLGEVF_RING_EN_REG}; 87 88 static const u32 tqp_intr_reg_addr_list[] = {HCLGEVF_TQP_INTR_CTRL_REG, 89 HCLGEVF_TQP_INTR_GL0_REG, 90 HCLGEVF_TQP_INTR_GL1_REG, 91 HCLGEVF_TQP_INTR_GL2_REG, 92 HCLGEVF_TQP_INTR_RL_REG}; 93 94 static struct hclgevf_dev *hclgevf_ae_get_hdev(struct hnae3_handle *handle) 95 { 96 if (!handle->client) 97 return container_of(handle, struct hclgevf_dev, nic); 98 else if (handle->client->type == HNAE3_CLIENT_ROCE) 99 return container_of(handle, struct hclgevf_dev, roce); 100 else 101 return container_of(handle, struct hclgevf_dev, nic); 102 } 103 104 static int hclgevf_tqps_update_stats(struct hnae3_handle *handle) 105 { 106 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 107 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 108 struct hclgevf_desc desc; 109 struct hclgevf_tqp *tqp; 110 int status; 111 int i; 112 113 for (i = 0; i < kinfo->num_tqps; i++) { 114 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 115 hclgevf_cmd_setup_basic_desc(&desc, 116 HCLGEVF_OPC_QUERY_RX_STATUS, 117 true); 118 119 desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 120 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 121 if (status) { 122 dev_err(&hdev->pdev->dev, 123 "Query tqp stat fail, status = %d,queue = %d\n", 124 status, i); 125 return status; 126 } 127 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd += 128 le32_to_cpu(desc.data[1]); 129 130 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_TX_STATUS, 131 true); 132 133 desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 134 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 135 if (status) { 136 dev_err(&hdev->pdev->dev, 137 "Query tqp stat fail, status = %d,queue = %d\n", 138 status, i); 139 return status; 140 } 141 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd += 142 le32_to_cpu(desc.data[1]); 143 } 144 145 return 0; 146 } 147 148 static u64 *hclgevf_tqps_get_stats(struct hnae3_handle *handle, u64 *data) 149 { 150 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 151 struct hclgevf_tqp *tqp; 152 u64 *buff = data; 153 int i; 154 155 for (i = 0; i < kinfo->num_tqps; i++) { 156 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 157 *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd; 158 } 159 for (i = 0; i < kinfo->num_tqps; i++) { 160 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 161 *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd; 162 } 163 164 return buff; 165 } 166 167 static int hclgevf_tqps_get_sset_count(struct hnae3_handle *handle, int strset) 168 { 169 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 170 171 return kinfo->num_tqps * 2; 172 } 173 174 static u8 *hclgevf_tqps_get_strings(struct hnae3_handle *handle, u8 *data) 175 { 176 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 177 u8 *buff = data; 178 int i; 179 180 for (i = 0; i < kinfo->num_tqps; i++) { 181 struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 182 struct hclgevf_tqp, q); 183 snprintf(buff, ETH_GSTRING_LEN, "txq%d_pktnum_rcd", 184 tqp->index); 185 buff += ETH_GSTRING_LEN; 186 } 187 188 for (i = 0; i < kinfo->num_tqps; i++) { 189 struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 190 struct hclgevf_tqp, q); 191 snprintf(buff, ETH_GSTRING_LEN, "rxq%d_pktnum_rcd", 192 tqp->index); 193 buff += ETH_GSTRING_LEN; 194 } 195 196 return buff; 197 } 198 199 static void hclgevf_update_stats(struct hnae3_handle *handle, 200 struct net_device_stats *net_stats) 201 { 202 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 203 int status; 204 205 status = hclgevf_tqps_update_stats(handle); 206 if (status) 207 dev_err(&hdev->pdev->dev, 208 "VF update of TQPS stats fail, status = %d.\n", 209 status); 210 } 211 212 static int hclgevf_get_sset_count(struct hnae3_handle *handle, int strset) 213 { 214 if (strset == ETH_SS_TEST) 215 return -EOPNOTSUPP; 216 else if (strset == ETH_SS_STATS) 217 return hclgevf_tqps_get_sset_count(handle, strset); 218 219 return 0; 220 } 221 222 static void hclgevf_get_strings(struct hnae3_handle *handle, u32 strset, 223 u8 *data) 224 { 225 u8 *p = (char *)data; 226 227 if (strset == ETH_SS_STATS) 228 p = hclgevf_tqps_get_strings(handle, p); 229 } 230 231 static void hclgevf_get_stats(struct hnae3_handle *handle, u64 *data) 232 { 233 hclgevf_tqps_get_stats(handle, data); 234 } 235 236 static void hclgevf_build_send_msg(struct hclge_vf_to_pf_msg *msg, u8 code, 237 u8 subcode) 238 { 239 if (msg) { 240 memset(msg, 0, sizeof(struct hclge_vf_to_pf_msg)); 241 msg->code = code; 242 msg->subcode = subcode; 243 } 244 } 245 246 static int hclgevf_get_tc_info(struct hclgevf_dev *hdev) 247 { 248 struct hclge_vf_to_pf_msg send_msg; 249 u8 resp_msg; 250 int status; 251 252 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_TCINFO, 0); 253 status = hclgevf_send_mbx_msg(hdev, &send_msg, true, &resp_msg, 254 sizeof(resp_msg)); 255 if (status) { 256 dev_err(&hdev->pdev->dev, 257 "VF request to get TC info from PF failed %d", 258 status); 259 return status; 260 } 261 262 hdev->hw_tc_map = resp_msg; 263 264 return 0; 265 } 266 267 static int hclgevf_get_port_base_vlan_filter_state(struct hclgevf_dev *hdev) 268 { 269 struct hnae3_handle *nic = &hdev->nic; 270 struct hclge_vf_to_pf_msg send_msg; 271 u8 resp_msg; 272 int ret; 273 274 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 275 HCLGE_MBX_GET_PORT_BASE_VLAN_STATE); 276 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, &resp_msg, 277 sizeof(u8)); 278 if (ret) { 279 dev_err(&hdev->pdev->dev, 280 "VF request to get port based vlan state failed %d", 281 ret); 282 return ret; 283 } 284 285 nic->port_base_vlan_state = resp_msg; 286 287 return 0; 288 } 289 290 static int hclgevf_get_queue_info(struct hclgevf_dev *hdev) 291 { 292 #define HCLGEVF_TQPS_RSS_INFO_LEN 6 293 #define HCLGEVF_TQPS_ALLOC_OFFSET 0 294 #define HCLGEVF_TQPS_RSS_SIZE_OFFSET 2 295 #define HCLGEVF_TQPS_RX_BUFFER_LEN_OFFSET 4 296 297 u8 resp_msg[HCLGEVF_TQPS_RSS_INFO_LEN]; 298 struct hclge_vf_to_pf_msg send_msg; 299 int status; 300 301 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QINFO, 0); 302 status = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 303 HCLGEVF_TQPS_RSS_INFO_LEN); 304 if (status) { 305 dev_err(&hdev->pdev->dev, 306 "VF request to get tqp info from PF failed %d", 307 status); 308 return status; 309 } 310 311 memcpy(&hdev->num_tqps, &resp_msg[HCLGEVF_TQPS_ALLOC_OFFSET], 312 sizeof(u16)); 313 memcpy(&hdev->rss_size_max, &resp_msg[HCLGEVF_TQPS_RSS_SIZE_OFFSET], 314 sizeof(u16)); 315 memcpy(&hdev->rx_buf_len, &resp_msg[HCLGEVF_TQPS_RX_BUFFER_LEN_OFFSET], 316 sizeof(u16)); 317 318 return 0; 319 } 320 321 static int hclgevf_get_queue_depth(struct hclgevf_dev *hdev) 322 { 323 #define HCLGEVF_TQPS_DEPTH_INFO_LEN 4 324 #define HCLGEVF_TQPS_NUM_TX_DESC_OFFSET 0 325 #define HCLGEVF_TQPS_NUM_RX_DESC_OFFSET 2 326 327 u8 resp_msg[HCLGEVF_TQPS_DEPTH_INFO_LEN]; 328 struct hclge_vf_to_pf_msg send_msg; 329 int ret; 330 331 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QDEPTH, 0); 332 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 333 HCLGEVF_TQPS_DEPTH_INFO_LEN); 334 if (ret) { 335 dev_err(&hdev->pdev->dev, 336 "VF request to get tqp depth info from PF failed %d", 337 ret); 338 return ret; 339 } 340 341 memcpy(&hdev->num_tx_desc, &resp_msg[HCLGEVF_TQPS_NUM_TX_DESC_OFFSET], 342 sizeof(u16)); 343 memcpy(&hdev->num_rx_desc, &resp_msg[HCLGEVF_TQPS_NUM_RX_DESC_OFFSET], 344 sizeof(u16)); 345 346 return 0; 347 } 348 349 static u16 hclgevf_get_qid_global(struct hnae3_handle *handle, u16 queue_id) 350 { 351 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 352 struct hclge_vf_to_pf_msg send_msg; 353 u16 qid_in_pf = 0; 354 u8 resp_data[2]; 355 int ret; 356 357 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QID_IN_PF, 0); 358 memcpy(send_msg.data, &queue_id, sizeof(queue_id)); 359 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_data, 360 sizeof(resp_data)); 361 if (!ret) 362 qid_in_pf = *(u16 *)resp_data; 363 364 return qid_in_pf; 365 } 366 367 static int hclgevf_get_pf_media_type(struct hclgevf_dev *hdev) 368 { 369 struct hclge_vf_to_pf_msg send_msg; 370 u8 resp_msg[2]; 371 int ret; 372 373 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_MEDIA_TYPE, 0); 374 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 375 sizeof(resp_msg)); 376 if (ret) { 377 dev_err(&hdev->pdev->dev, 378 "VF request to get the pf port media type failed %d", 379 ret); 380 return ret; 381 } 382 383 hdev->hw.mac.media_type = resp_msg[0]; 384 hdev->hw.mac.module_type = resp_msg[1]; 385 386 return 0; 387 } 388 389 static int hclgevf_alloc_tqps(struct hclgevf_dev *hdev) 390 { 391 struct hclgevf_tqp *tqp; 392 int i; 393 394 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 395 sizeof(struct hclgevf_tqp), GFP_KERNEL); 396 if (!hdev->htqp) 397 return -ENOMEM; 398 399 tqp = hdev->htqp; 400 401 for (i = 0; i < hdev->num_tqps; i++) { 402 tqp->dev = &hdev->pdev->dev; 403 tqp->index = i; 404 405 tqp->q.ae_algo = &ae_algovf; 406 tqp->q.buf_size = hdev->rx_buf_len; 407 tqp->q.tx_desc_num = hdev->num_tx_desc; 408 tqp->q.rx_desc_num = hdev->num_rx_desc; 409 410 /* need an extended offset to configure queues >= 411 * HCLGEVF_TQP_MAX_SIZE_DEV_V2. 412 */ 413 if (i < HCLGEVF_TQP_MAX_SIZE_DEV_V2) 414 tqp->q.io_base = hdev->hw.io_base + 415 HCLGEVF_TQP_REG_OFFSET + 416 i * HCLGEVF_TQP_REG_SIZE; 417 else 418 tqp->q.io_base = hdev->hw.io_base + 419 HCLGEVF_TQP_REG_OFFSET + 420 HCLGEVF_TQP_EXT_REG_OFFSET + 421 (i - HCLGEVF_TQP_MAX_SIZE_DEV_V2) * 422 HCLGEVF_TQP_REG_SIZE; 423 424 tqp++; 425 } 426 427 return 0; 428 } 429 430 static int hclgevf_knic_setup(struct hclgevf_dev *hdev) 431 { 432 struct hnae3_handle *nic = &hdev->nic; 433 struct hnae3_knic_private_info *kinfo; 434 u16 new_tqps = hdev->num_tqps; 435 unsigned int i; 436 u8 num_tc = 0; 437 438 kinfo = &nic->kinfo; 439 kinfo->num_tx_desc = hdev->num_tx_desc; 440 kinfo->num_rx_desc = hdev->num_rx_desc; 441 kinfo->rx_buf_len = hdev->rx_buf_len; 442 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) 443 if (hdev->hw_tc_map & BIT(i)) 444 num_tc++; 445 446 num_tc = num_tc ? num_tc : 1; 447 kinfo->tc_info.num_tc = num_tc; 448 kinfo->rss_size = min_t(u16, hdev->rss_size_max, new_tqps / num_tc); 449 new_tqps = kinfo->rss_size * num_tc; 450 kinfo->num_tqps = min(new_tqps, hdev->num_tqps); 451 452 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps, 453 sizeof(struct hnae3_queue *), GFP_KERNEL); 454 if (!kinfo->tqp) 455 return -ENOMEM; 456 457 for (i = 0; i < kinfo->num_tqps; i++) { 458 hdev->htqp[i].q.handle = &hdev->nic; 459 hdev->htqp[i].q.tqp_index = i; 460 kinfo->tqp[i] = &hdev->htqp[i].q; 461 } 462 463 /* after init the max rss_size and tqps, adjust the default tqp numbers 464 * and rss size with the actual vector numbers 465 */ 466 kinfo->num_tqps = min_t(u16, hdev->num_nic_msix - 1, kinfo->num_tqps); 467 kinfo->rss_size = min_t(u16, kinfo->num_tqps / num_tc, 468 kinfo->rss_size); 469 470 return 0; 471 } 472 473 static void hclgevf_request_link_info(struct hclgevf_dev *hdev) 474 { 475 struct hclge_vf_to_pf_msg send_msg; 476 int status; 477 478 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_LINK_STATUS, 0); 479 status = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 480 if (status) 481 dev_err(&hdev->pdev->dev, 482 "VF failed to fetch link status(%d) from PF", status); 483 } 484 485 void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state) 486 { 487 struct hnae3_handle *rhandle = &hdev->roce; 488 struct hnae3_handle *handle = &hdev->nic; 489 struct hnae3_client *rclient; 490 struct hnae3_client *client; 491 492 if (test_and_set_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state)) 493 return; 494 495 client = handle->client; 496 rclient = hdev->roce_client; 497 498 link_state = 499 test_bit(HCLGEVF_STATE_DOWN, &hdev->state) ? 0 : link_state; 500 501 if (link_state != hdev->hw.mac.link) { 502 client->ops->link_status_change(handle, !!link_state); 503 if (rclient && rclient->ops->link_status_change) 504 rclient->ops->link_status_change(rhandle, !!link_state); 505 hdev->hw.mac.link = link_state; 506 } 507 508 clear_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state); 509 } 510 511 static void hclgevf_update_link_mode(struct hclgevf_dev *hdev) 512 { 513 #define HCLGEVF_ADVERTISING 0 514 #define HCLGEVF_SUPPORTED 1 515 516 struct hclge_vf_to_pf_msg send_msg; 517 518 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_LINK_MODE, 0); 519 send_msg.data[0] = HCLGEVF_ADVERTISING; 520 hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 521 send_msg.data[0] = HCLGEVF_SUPPORTED; 522 hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 523 } 524 525 static int hclgevf_set_handle_info(struct hclgevf_dev *hdev) 526 { 527 struct hnae3_handle *nic = &hdev->nic; 528 int ret; 529 530 nic->ae_algo = &ae_algovf; 531 nic->pdev = hdev->pdev; 532 nic->numa_node_mask = hdev->numa_node_mask; 533 nic->flags |= HNAE3_SUPPORT_VF; 534 535 ret = hclgevf_knic_setup(hdev); 536 if (ret) 537 dev_err(&hdev->pdev->dev, "VF knic setup failed %d\n", 538 ret); 539 return ret; 540 } 541 542 static void hclgevf_free_vector(struct hclgevf_dev *hdev, int vector_id) 543 { 544 if (hdev->vector_status[vector_id] == HCLGEVF_INVALID_VPORT) { 545 dev_warn(&hdev->pdev->dev, 546 "vector(vector_id %d) has been freed.\n", vector_id); 547 return; 548 } 549 550 hdev->vector_status[vector_id] = HCLGEVF_INVALID_VPORT; 551 hdev->num_msi_left += 1; 552 hdev->num_msi_used -= 1; 553 } 554 555 static int hclgevf_get_vector(struct hnae3_handle *handle, u16 vector_num, 556 struct hnae3_vector_info *vector_info) 557 { 558 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 559 struct hnae3_vector_info *vector = vector_info; 560 int alloc = 0; 561 int i, j; 562 563 vector_num = min_t(u16, hdev->num_nic_msix - 1, vector_num); 564 vector_num = min(hdev->num_msi_left, vector_num); 565 566 for (j = 0; j < vector_num; j++) { 567 for (i = HCLGEVF_MISC_VECTOR_NUM + 1; i < hdev->num_msi; i++) { 568 if (hdev->vector_status[i] == HCLGEVF_INVALID_VPORT) { 569 vector->vector = pci_irq_vector(hdev->pdev, i); 570 vector->io_addr = hdev->hw.io_base + 571 HCLGEVF_VECTOR_REG_BASE + 572 (i - 1) * HCLGEVF_VECTOR_REG_OFFSET; 573 hdev->vector_status[i] = 0; 574 hdev->vector_irq[i] = vector->vector; 575 576 vector++; 577 alloc++; 578 579 break; 580 } 581 } 582 } 583 hdev->num_msi_left -= alloc; 584 hdev->num_msi_used += alloc; 585 586 return alloc; 587 } 588 589 static int hclgevf_get_vector_index(struct hclgevf_dev *hdev, int vector) 590 { 591 int i; 592 593 for (i = 0; i < hdev->num_msi; i++) 594 if (vector == hdev->vector_irq[i]) 595 return i; 596 597 return -EINVAL; 598 } 599 600 static int hclgevf_set_rss_algo_key(struct hclgevf_dev *hdev, 601 const u8 hfunc, const u8 *key) 602 { 603 struct hclgevf_rss_config_cmd *req; 604 unsigned int key_offset = 0; 605 struct hclgevf_desc desc; 606 int key_counts; 607 int key_size; 608 int ret; 609 610 key_counts = HCLGEVF_RSS_KEY_SIZE; 611 req = (struct hclgevf_rss_config_cmd *)desc.data; 612 613 while (key_counts) { 614 hclgevf_cmd_setup_basic_desc(&desc, 615 HCLGEVF_OPC_RSS_GENERIC_CONFIG, 616 false); 617 618 req->hash_config |= (hfunc & HCLGEVF_RSS_HASH_ALGO_MASK); 619 req->hash_config |= 620 (key_offset << HCLGEVF_RSS_HASH_KEY_OFFSET_B); 621 622 key_size = min(HCLGEVF_RSS_HASH_KEY_NUM, key_counts); 623 memcpy(req->hash_key, 624 key + key_offset * HCLGEVF_RSS_HASH_KEY_NUM, key_size); 625 626 key_counts -= key_size; 627 key_offset++; 628 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 629 if (ret) { 630 dev_err(&hdev->pdev->dev, 631 "Configure RSS config fail, status = %d\n", 632 ret); 633 return ret; 634 } 635 } 636 637 return 0; 638 } 639 640 static u32 hclgevf_get_rss_key_size(struct hnae3_handle *handle) 641 { 642 return HCLGEVF_RSS_KEY_SIZE; 643 } 644 645 static int hclgevf_set_rss_indir_table(struct hclgevf_dev *hdev) 646 { 647 const u8 *indir = hdev->rss_cfg.rss_indirection_tbl; 648 struct hclgevf_rss_indirection_table_cmd *req; 649 struct hclgevf_desc desc; 650 int rss_cfg_tbl_num; 651 int status; 652 int i, j; 653 654 req = (struct hclgevf_rss_indirection_table_cmd *)desc.data; 655 rss_cfg_tbl_num = hdev->ae_dev->dev_specs.rss_ind_tbl_size / 656 HCLGEVF_RSS_CFG_TBL_SIZE; 657 658 for (i = 0; i < rss_cfg_tbl_num; i++) { 659 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INDIR_TABLE, 660 false); 661 req->start_table_index = i * HCLGEVF_RSS_CFG_TBL_SIZE; 662 req->rss_set_bitmap = HCLGEVF_RSS_SET_BITMAP_MSK; 663 for (j = 0; j < HCLGEVF_RSS_CFG_TBL_SIZE; j++) 664 req->rss_result[j] = 665 indir[i * HCLGEVF_RSS_CFG_TBL_SIZE + j]; 666 667 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 668 if (status) { 669 dev_err(&hdev->pdev->dev, 670 "VF failed(=%d) to set RSS indirection table\n", 671 status); 672 return status; 673 } 674 } 675 676 return 0; 677 } 678 679 static int hclgevf_set_rss_tc_mode(struct hclgevf_dev *hdev, u16 rss_size) 680 { 681 struct hclgevf_rss_tc_mode_cmd *req; 682 u16 tc_offset[HCLGEVF_MAX_TC_NUM]; 683 u16 tc_valid[HCLGEVF_MAX_TC_NUM]; 684 u16 tc_size[HCLGEVF_MAX_TC_NUM]; 685 struct hclgevf_desc desc; 686 u16 roundup_size; 687 unsigned int i; 688 int status; 689 690 req = (struct hclgevf_rss_tc_mode_cmd *)desc.data; 691 692 roundup_size = roundup_pow_of_two(rss_size); 693 roundup_size = ilog2(roundup_size); 694 695 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 696 tc_valid[i] = !!(hdev->hw_tc_map & BIT(i)); 697 tc_size[i] = roundup_size; 698 tc_offset[i] = rss_size * i; 699 } 700 701 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_TC_MODE, false); 702 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 703 hnae3_set_bit(req->rss_tc_mode[i], HCLGEVF_RSS_TC_VALID_B, 704 (tc_valid[i] & 0x1)); 705 hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_SIZE_M, 706 HCLGEVF_RSS_TC_SIZE_S, tc_size[i]); 707 hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_OFFSET_M, 708 HCLGEVF_RSS_TC_OFFSET_S, tc_offset[i]); 709 } 710 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 711 if (status) 712 dev_err(&hdev->pdev->dev, 713 "VF failed(=%d) to set rss tc mode\n", status); 714 715 return status; 716 } 717 718 /* for revision 0x20, vf shared the same rss config with pf */ 719 static int hclgevf_get_rss_hash_key(struct hclgevf_dev *hdev) 720 { 721 #define HCLGEVF_RSS_MBX_RESP_LEN 8 722 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 723 u8 resp_msg[HCLGEVF_RSS_MBX_RESP_LEN]; 724 struct hclge_vf_to_pf_msg send_msg; 725 u16 msg_num, hash_key_index; 726 u8 index; 727 int ret; 728 729 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_RSS_KEY, 0); 730 msg_num = (HCLGEVF_RSS_KEY_SIZE + HCLGEVF_RSS_MBX_RESP_LEN - 1) / 731 HCLGEVF_RSS_MBX_RESP_LEN; 732 for (index = 0; index < msg_num; index++) { 733 send_msg.data[0] = index; 734 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 735 HCLGEVF_RSS_MBX_RESP_LEN); 736 if (ret) { 737 dev_err(&hdev->pdev->dev, 738 "VF get rss hash key from PF failed, ret=%d", 739 ret); 740 return ret; 741 } 742 743 hash_key_index = HCLGEVF_RSS_MBX_RESP_LEN * index; 744 if (index == msg_num - 1) 745 memcpy(&rss_cfg->rss_hash_key[hash_key_index], 746 &resp_msg[0], 747 HCLGEVF_RSS_KEY_SIZE - hash_key_index); 748 else 749 memcpy(&rss_cfg->rss_hash_key[hash_key_index], 750 &resp_msg[0], HCLGEVF_RSS_MBX_RESP_LEN); 751 } 752 753 return 0; 754 } 755 756 static int hclgevf_get_rss(struct hnae3_handle *handle, u32 *indir, u8 *key, 757 u8 *hfunc) 758 { 759 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 760 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 761 int i, ret; 762 763 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 764 /* Get hash algorithm */ 765 if (hfunc) { 766 switch (rss_cfg->hash_algo) { 767 case HCLGEVF_RSS_HASH_ALGO_TOEPLITZ: 768 *hfunc = ETH_RSS_HASH_TOP; 769 break; 770 case HCLGEVF_RSS_HASH_ALGO_SIMPLE: 771 *hfunc = ETH_RSS_HASH_XOR; 772 break; 773 default: 774 *hfunc = ETH_RSS_HASH_UNKNOWN; 775 break; 776 } 777 } 778 779 /* Get the RSS Key required by the user */ 780 if (key) 781 memcpy(key, rss_cfg->rss_hash_key, 782 HCLGEVF_RSS_KEY_SIZE); 783 } else { 784 if (hfunc) 785 *hfunc = ETH_RSS_HASH_TOP; 786 if (key) { 787 ret = hclgevf_get_rss_hash_key(hdev); 788 if (ret) 789 return ret; 790 memcpy(key, rss_cfg->rss_hash_key, 791 HCLGEVF_RSS_KEY_SIZE); 792 } 793 } 794 795 if (indir) 796 for (i = 0; i < hdev->ae_dev->dev_specs.rss_ind_tbl_size; i++) 797 indir[i] = rss_cfg->rss_indirection_tbl[i]; 798 799 return 0; 800 } 801 802 static int hclgevf_set_rss(struct hnae3_handle *handle, const u32 *indir, 803 const u8 *key, const u8 hfunc) 804 { 805 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 806 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 807 int ret, i; 808 809 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 810 /* Set the RSS Hash Key if specififed by the user */ 811 if (key) { 812 switch (hfunc) { 813 case ETH_RSS_HASH_TOP: 814 rss_cfg->hash_algo = 815 HCLGEVF_RSS_HASH_ALGO_TOEPLITZ; 816 break; 817 case ETH_RSS_HASH_XOR: 818 rss_cfg->hash_algo = 819 HCLGEVF_RSS_HASH_ALGO_SIMPLE; 820 break; 821 case ETH_RSS_HASH_NO_CHANGE: 822 break; 823 default: 824 return -EINVAL; 825 } 826 827 ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 828 key); 829 if (ret) 830 return ret; 831 832 /* Update the shadow RSS key with user specified qids */ 833 memcpy(rss_cfg->rss_hash_key, key, 834 HCLGEVF_RSS_KEY_SIZE); 835 } 836 } 837 838 /* update the shadow RSS table with user specified qids */ 839 for (i = 0; i < hdev->ae_dev->dev_specs.rss_ind_tbl_size; i++) 840 rss_cfg->rss_indirection_tbl[i] = indir[i]; 841 842 /* update the hardware */ 843 return hclgevf_set_rss_indir_table(hdev); 844 } 845 846 static u8 hclgevf_get_rss_hash_bits(struct ethtool_rxnfc *nfc) 847 { 848 u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGEVF_S_PORT_BIT : 0; 849 850 if (nfc->data & RXH_L4_B_2_3) 851 hash_sets |= HCLGEVF_D_PORT_BIT; 852 else 853 hash_sets &= ~HCLGEVF_D_PORT_BIT; 854 855 if (nfc->data & RXH_IP_SRC) 856 hash_sets |= HCLGEVF_S_IP_BIT; 857 else 858 hash_sets &= ~HCLGEVF_S_IP_BIT; 859 860 if (nfc->data & RXH_IP_DST) 861 hash_sets |= HCLGEVF_D_IP_BIT; 862 else 863 hash_sets &= ~HCLGEVF_D_IP_BIT; 864 865 if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW) 866 hash_sets |= HCLGEVF_V_TAG_BIT; 867 868 return hash_sets; 869 } 870 871 static int hclgevf_set_rss_tuple(struct hnae3_handle *handle, 872 struct ethtool_rxnfc *nfc) 873 { 874 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 875 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 876 struct hclgevf_rss_input_tuple_cmd *req; 877 struct hclgevf_desc desc; 878 u8 tuple_sets; 879 int ret; 880 881 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 882 return -EOPNOTSUPP; 883 884 if (nfc->data & 885 ~(RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3)) 886 return -EINVAL; 887 888 req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 889 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 890 891 req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 892 req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 893 req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 894 req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 895 req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 896 req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 897 req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 898 req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 899 900 tuple_sets = hclgevf_get_rss_hash_bits(nfc); 901 switch (nfc->flow_type) { 902 case TCP_V4_FLOW: 903 req->ipv4_tcp_en = tuple_sets; 904 break; 905 case TCP_V6_FLOW: 906 req->ipv6_tcp_en = tuple_sets; 907 break; 908 case UDP_V4_FLOW: 909 req->ipv4_udp_en = tuple_sets; 910 break; 911 case UDP_V6_FLOW: 912 req->ipv6_udp_en = tuple_sets; 913 break; 914 case SCTP_V4_FLOW: 915 req->ipv4_sctp_en = tuple_sets; 916 break; 917 case SCTP_V6_FLOW: 918 if (hdev->ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2 && 919 (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3))) 920 return -EINVAL; 921 922 req->ipv6_sctp_en = tuple_sets; 923 break; 924 case IPV4_FLOW: 925 req->ipv4_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 926 break; 927 case IPV6_FLOW: 928 req->ipv6_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 929 break; 930 default: 931 return -EINVAL; 932 } 933 934 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 935 if (ret) { 936 dev_err(&hdev->pdev->dev, 937 "Set rss tuple fail, status = %d\n", ret); 938 return ret; 939 } 940 941 rss_cfg->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en; 942 rss_cfg->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en; 943 rss_cfg->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en; 944 rss_cfg->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en; 945 rss_cfg->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en; 946 rss_cfg->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en; 947 rss_cfg->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en; 948 rss_cfg->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en; 949 return 0; 950 } 951 952 static int hclgevf_get_rss_tuple(struct hnae3_handle *handle, 953 struct ethtool_rxnfc *nfc) 954 { 955 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 956 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 957 u8 tuple_sets; 958 959 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 960 return -EOPNOTSUPP; 961 962 nfc->data = 0; 963 964 switch (nfc->flow_type) { 965 case TCP_V4_FLOW: 966 tuple_sets = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 967 break; 968 case UDP_V4_FLOW: 969 tuple_sets = rss_cfg->rss_tuple_sets.ipv4_udp_en; 970 break; 971 case TCP_V6_FLOW: 972 tuple_sets = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 973 break; 974 case UDP_V6_FLOW: 975 tuple_sets = rss_cfg->rss_tuple_sets.ipv6_udp_en; 976 break; 977 case SCTP_V4_FLOW: 978 tuple_sets = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 979 break; 980 case SCTP_V6_FLOW: 981 tuple_sets = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 982 break; 983 case IPV4_FLOW: 984 case IPV6_FLOW: 985 tuple_sets = HCLGEVF_S_IP_BIT | HCLGEVF_D_IP_BIT; 986 break; 987 default: 988 return -EINVAL; 989 } 990 991 if (!tuple_sets) 992 return 0; 993 994 if (tuple_sets & HCLGEVF_D_PORT_BIT) 995 nfc->data |= RXH_L4_B_2_3; 996 if (tuple_sets & HCLGEVF_S_PORT_BIT) 997 nfc->data |= RXH_L4_B_0_1; 998 if (tuple_sets & HCLGEVF_D_IP_BIT) 999 nfc->data |= RXH_IP_DST; 1000 if (tuple_sets & HCLGEVF_S_IP_BIT) 1001 nfc->data |= RXH_IP_SRC; 1002 1003 return 0; 1004 } 1005 1006 static int hclgevf_set_rss_input_tuple(struct hclgevf_dev *hdev, 1007 struct hclgevf_rss_cfg *rss_cfg) 1008 { 1009 struct hclgevf_rss_input_tuple_cmd *req; 1010 struct hclgevf_desc desc; 1011 int ret; 1012 1013 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 1014 1015 req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 1016 1017 req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 1018 req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 1019 req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 1020 req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 1021 req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 1022 req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 1023 req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 1024 req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 1025 1026 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1027 if (ret) 1028 dev_err(&hdev->pdev->dev, 1029 "Configure rss input fail, status = %d\n", ret); 1030 return ret; 1031 } 1032 1033 static int hclgevf_get_tc_size(struct hnae3_handle *handle) 1034 { 1035 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1036 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 1037 1038 return rss_cfg->rss_size; 1039 } 1040 1041 static int hclgevf_bind_ring_to_vector(struct hnae3_handle *handle, bool en, 1042 int vector_id, 1043 struct hnae3_ring_chain_node *ring_chain) 1044 { 1045 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1046 struct hclge_vf_to_pf_msg send_msg; 1047 struct hnae3_ring_chain_node *node; 1048 int status; 1049 int i = 0; 1050 1051 memset(&send_msg, 0, sizeof(send_msg)); 1052 send_msg.code = en ? HCLGE_MBX_MAP_RING_TO_VECTOR : 1053 HCLGE_MBX_UNMAP_RING_TO_VECTOR; 1054 send_msg.vector_id = vector_id; 1055 1056 for (node = ring_chain; node; node = node->next) { 1057 send_msg.param[i].ring_type = 1058 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B); 1059 1060 send_msg.param[i].tqp_index = node->tqp_index; 1061 send_msg.param[i].int_gl_index = 1062 hnae3_get_field(node->int_gl_idx, 1063 HNAE3_RING_GL_IDX_M, 1064 HNAE3_RING_GL_IDX_S); 1065 1066 i++; 1067 if (i == HCLGE_MBX_MAX_RING_CHAIN_PARAM_NUM || !node->next) { 1068 send_msg.ring_num = i; 1069 1070 status = hclgevf_send_mbx_msg(hdev, &send_msg, false, 1071 NULL, 0); 1072 if (status) { 1073 dev_err(&hdev->pdev->dev, 1074 "Map TQP fail, status is %d.\n", 1075 status); 1076 return status; 1077 } 1078 i = 0; 1079 } 1080 } 1081 1082 return 0; 1083 } 1084 1085 static int hclgevf_map_ring_to_vector(struct hnae3_handle *handle, int vector, 1086 struct hnae3_ring_chain_node *ring_chain) 1087 { 1088 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1089 int vector_id; 1090 1091 vector_id = hclgevf_get_vector_index(hdev, vector); 1092 if (vector_id < 0) { 1093 dev_err(&handle->pdev->dev, 1094 "Get vector index fail. ret =%d\n", vector_id); 1095 return vector_id; 1096 } 1097 1098 return hclgevf_bind_ring_to_vector(handle, true, vector_id, ring_chain); 1099 } 1100 1101 static int hclgevf_unmap_ring_from_vector( 1102 struct hnae3_handle *handle, 1103 int vector, 1104 struct hnae3_ring_chain_node *ring_chain) 1105 { 1106 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1107 int ret, vector_id; 1108 1109 if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 1110 return 0; 1111 1112 vector_id = hclgevf_get_vector_index(hdev, vector); 1113 if (vector_id < 0) { 1114 dev_err(&handle->pdev->dev, 1115 "Get vector index fail. ret =%d\n", vector_id); 1116 return vector_id; 1117 } 1118 1119 ret = hclgevf_bind_ring_to_vector(handle, false, vector_id, ring_chain); 1120 if (ret) 1121 dev_err(&handle->pdev->dev, 1122 "Unmap ring from vector fail. vector=%d, ret =%d\n", 1123 vector_id, 1124 ret); 1125 1126 return ret; 1127 } 1128 1129 static int hclgevf_put_vector(struct hnae3_handle *handle, int vector) 1130 { 1131 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1132 int vector_id; 1133 1134 vector_id = hclgevf_get_vector_index(hdev, vector); 1135 if (vector_id < 0) { 1136 dev_err(&handle->pdev->dev, 1137 "hclgevf_put_vector get vector index fail. ret =%d\n", 1138 vector_id); 1139 return vector_id; 1140 } 1141 1142 hclgevf_free_vector(hdev, vector_id); 1143 1144 return 0; 1145 } 1146 1147 static int hclgevf_cmd_set_promisc_mode(struct hclgevf_dev *hdev, 1148 bool en_uc_pmc, bool en_mc_pmc, 1149 bool en_bc_pmc) 1150 { 1151 struct hnae3_handle *handle = &hdev->nic; 1152 struct hclge_vf_to_pf_msg send_msg; 1153 int ret; 1154 1155 memset(&send_msg, 0, sizeof(send_msg)); 1156 send_msg.code = HCLGE_MBX_SET_PROMISC_MODE; 1157 send_msg.en_bc = en_bc_pmc ? 1 : 0; 1158 send_msg.en_uc = en_uc_pmc ? 1 : 0; 1159 send_msg.en_mc = en_mc_pmc ? 1 : 0; 1160 send_msg.en_limit_promisc = test_bit(HNAE3_PFLAG_LIMIT_PROMISC, 1161 &handle->priv_flags) ? 1 : 0; 1162 1163 ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 1164 if (ret) 1165 dev_err(&hdev->pdev->dev, 1166 "Set promisc mode fail, status is %d.\n", ret); 1167 1168 return ret; 1169 } 1170 1171 static int hclgevf_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc, 1172 bool en_mc_pmc) 1173 { 1174 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1175 bool en_bc_pmc; 1176 1177 en_bc_pmc = hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2; 1178 1179 return hclgevf_cmd_set_promisc_mode(hdev, en_uc_pmc, en_mc_pmc, 1180 en_bc_pmc); 1181 } 1182 1183 static void hclgevf_request_update_promisc_mode(struct hnae3_handle *handle) 1184 { 1185 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1186 1187 set_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state); 1188 hclgevf_task_schedule(hdev, 0); 1189 } 1190 1191 static void hclgevf_sync_promisc_mode(struct hclgevf_dev *hdev) 1192 { 1193 struct hnae3_handle *handle = &hdev->nic; 1194 bool en_uc_pmc = handle->netdev_flags & HNAE3_UPE; 1195 bool en_mc_pmc = handle->netdev_flags & HNAE3_MPE; 1196 int ret; 1197 1198 if (test_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state)) { 1199 ret = hclgevf_set_promisc_mode(handle, en_uc_pmc, en_mc_pmc); 1200 if (!ret) 1201 clear_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state); 1202 } 1203 } 1204 1205 static int hclgevf_tqp_enable(struct hclgevf_dev *hdev, unsigned int tqp_id, 1206 int stream_id, bool enable) 1207 { 1208 struct hclgevf_cfg_com_tqp_queue_cmd *req; 1209 struct hclgevf_desc desc; 1210 int status; 1211 1212 req = (struct hclgevf_cfg_com_tqp_queue_cmd *)desc.data; 1213 1214 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_CFG_COM_TQP_QUEUE, 1215 false); 1216 req->tqp_id = cpu_to_le16(tqp_id & HCLGEVF_RING_ID_MASK); 1217 req->stream_id = cpu_to_le16(stream_id); 1218 if (enable) 1219 req->enable |= 1U << HCLGEVF_TQP_ENABLE_B; 1220 1221 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1222 if (status) 1223 dev_err(&hdev->pdev->dev, 1224 "TQP enable fail, status =%d.\n", status); 1225 1226 return status; 1227 } 1228 1229 static void hclgevf_reset_tqp_stats(struct hnae3_handle *handle) 1230 { 1231 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 1232 struct hclgevf_tqp *tqp; 1233 int i; 1234 1235 for (i = 0; i < kinfo->num_tqps; i++) { 1236 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 1237 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats)); 1238 } 1239 } 1240 1241 static int hclgevf_get_host_mac_addr(struct hclgevf_dev *hdev, u8 *p) 1242 { 1243 struct hclge_vf_to_pf_msg send_msg; 1244 u8 host_mac[ETH_ALEN]; 1245 int status; 1246 1247 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_MAC_ADDR, 0); 1248 status = hclgevf_send_mbx_msg(hdev, &send_msg, true, host_mac, 1249 ETH_ALEN); 1250 if (status) { 1251 dev_err(&hdev->pdev->dev, 1252 "fail to get VF MAC from host %d", status); 1253 return status; 1254 } 1255 1256 ether_addr_copy(p, host_mac); 1257 1258 return 0; 1259 } 1260 1261 static void hclgevf_get_mac_addr(struct hnae3_handle *handle, u8 *p) 1262 { 1263 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1264 u8 host_mac_addr[ETH_ALEN]; 1265 1266 if (hclgevf_get_host_mac_addr(hdev, host_mac_addr)) 1267 return; 1268 1269 hdev->has_pf_mac = !is_zero_ether_addr(host_mac_addr); 1270 if (hdev->has_pf_mac) 1271 ether_addr_copy(p, host_mac_addr); 1272 else 1273 ether_addr_copy(p, hdev->hw.mac.mac_addr); 1274 } 1275 1276 static int hclgevf_set_mac_addr(struct hnae3_handle *handle, void *p, 1277 bool is_first) 1278 { 1279 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1280 u8 *old_mac_addr = (u8 *)hdev->hw.mac.mac_addr; 1281 struct hclge_vf_to_pf_msg send_msg; 1282 u8 *new_mac_addr = (u8 *)p; 1283 int status; 1284 1285 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_UNICAST, 0); 1286 send_msg.subcode = HCLGE_MBX_MAC_VLAN_UC_MODIFY; 1287 ether_addr_copy(send_msg.data, new_mac_addr); 1288 if (is_first && !hdev->has_pf_mac) 1289 eth_zero_addr(&send_msg.data[ETH_ALEN]); 1290 else 1291 ether_addr_copy(&send_msg.data[ETH_ALEN], old_mac_addr); 1292 status = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1293 if (!status) 1294 ether_addr_copy(hdev->hw.mac.mac_addr, new_mac_addr); 1295 1296 return status; 1297 } 1298 1299 static struct hclgevf_mac_addr_node * 1300 hclgevf_find_mac_node(struct list_head *list, const u8 *mac_addr) 1301 { 1302 struct hclgevf_mac_addr_node *mac_node, *tmp; 1303 1304 list_for_each_entry_safe(mac_node, tmp, list, node) 1305 if (ether_addr_equal(mac_addr, mac_node->mac_addr)) 1306 return mac_node; 1307 1308 return NULL; 1309 } 1310 1311 static void hclgevf_update_mac_node(struct hclgevf_mac_addr_node *mac_node, 1312 enum HCLGEVF_MAC_NODE_STATE state) 1313 { 1314 switch (state) { 1315 /* from set_rx_mode or tmp_add_list */ 1316 case HCLGEVF_MAC_TO_ADD: 1317 if (mac_node->state == HCLGEVF_MAC_TO_DEL) 1318 mac_node->state = HCLGEVF_MAC_ACTIVE; 1319 break; 1320 /* only from set_rx_mode */ 1321 case HCLGEVF_MAC_TO_DEL: 1322 if (mac_node->state == HCLGEVF_MAC_TO_ADD) { 1323 list_del(&mac_node->node); 1324 kfree(mac_node); 1325 } else { 1326 mac_node->state = HCLGEVF_MAC_TO_DEL; 1327 } 1328 break; 1329 /* only from tmp_add_list, the mac_node->state won't be 1330 * HCLGEVF_MAC_ACTIVE 1331 */ 1332 case HCLGEVF_MAC_ACTIVE: 1333 if (mac_node->state == HCLGEVF_MAC_TO_ADD) 1334 mac_node->state = HCLGEVF_MAC_ACTIVE; 1335 break; 1336 } 1337 } 1338 1339 static int hclgevf_update_mac_list(struct hnae3_handle *handle, 1340 enum HCLGEVF_MAC_NODE_STATE state, 1341 enum HCLGEVF_MAC_ADDR_TYPE mac_type, 1342 const unsigned char *addr) 1343 { 1344 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1345 struct hclgevf_mac_addr_node *mac_node; 1346 struct list_head *list; 1347 1348 list = (mac_type == HCLGEVF_MAC_ADDR_UC) ? 1349 &hdev->mac_table.uc_mac_list : &hdev->mac_table.mc_mac_list; 1350 1351 spin_lock_bh(&hdev->mac_table.mac_list_lock); 1352 1353 /* if the mac addr is already in the mac list, no need to add a new 1354 * one into it, just check the mac addr state, convert it to a new 1355 * new state, or just remove it, or do nothing. 1356 */ 1357 mac_node = hclgevf_find_mac_node(list, addr); 1358 if (mac_node) { 1359 hclgevf_update_mac_node(mac_node, state); 1360 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1361 return 0; 1362 } 1363 /* if this address is never added, unnecessary to delete */ 1364 if (state == HCLGEVF_MAC_TO_DEL) { 1365 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1366 return -ENOENT; 1367 } 1368 1369 mac_node = kzalloc(sizeof(*mac_node), GFP_ATOMIC); 1370 if (!mac_node) { 1371 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1372 return -ENOMEM; 1373 } 1374 1375 mac_node->state = state; 1376 ether_addr_copy(mac_node->mac_addr, addr); 1377 list_add_tail(&mac_node->node, list); 1378 1379 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1380 return 0; 1381 } 1382 1383 static int hclgevf_add_uc_addr(struct hnae3_handle *handle, 1384 const unsigned char *addr) 1385 { 1386 return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_ADD, 1387 HCLGEVF_MAC_ADDR_UC, addr); 1388 } 1389 1390 static int hclgevf_rm_uc_addr(struct hnae3_handle *handle, 1391 const unsigned char *addr) 1392 { 1393 return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_DEL, 1394 HCLGEVF_MAC_ADDR_UC, addr); 1395 } 1396 1397 static int hclgevf_add_mc_addr(struct hnae3_handle *handle, 1398 const unsigned char *addr) 1399 { 1400 return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_ADD, 1401 HCLGEVF_MAC_ADDR_MC, addr); 1402 } 1403 1404 static int hclgevf_rm_mc_addr(struct hnae3_handle *handle, 1405 const unsigned char *addr) 1406 { 1407 return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_DEL, 1408 HCLGEVF_MAC_ADDR_MC, addr); 1409 } 1410 1411 static int hclgevf_add_del_mac_addr(struct hclgevf_dev *hdev, 1412 struct hclgevf_mac_addr_node *mac_node, 1413 enum HCLGEVF_MAC_ADDR_TYPE mac_type) 1414 { 1415 struct hclge_vf_to_pf_msg send_msg; 1416 u8 code, subcode; 1417 1418 if (mac_type == HCLGEVF_MAC_ADDR_UC) { 1419 code = HCLGE_MBX_SET_UNICAST; 1420 if (mac_node->state == HCLGEVF_MAC_TO_ADD) 1421 subcode = HCLGE_MBX_MAC_VLAN_UC_ADD; 1422 else 1423 subcode = HCLGE_MBX_MAC_VLAN_UC_REMOVE; 1424 } else { 1425 code = HCLGE_MBX_SET_MULTICAST; 1426 if (mac_node->state == HCLGEVF_MAC_TO_ADD) 1427 subcode = HCLGE_MBX_MAC_VLAN_MC_ADD; 1428 else 1429 subcode = HCLGE_MBX_MAC_VLAN_MC_REMOVE; 1430 } 1431 1432 hclgevf_build_send_msg(&send_msg, code, subcode); 1433 ether_addr_copy(send_msg.data, mac_node->mac_addr); 1434 return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 1435 } 1436 1437 static void hclgevf_config_mac_list(struct hclgevf_dev *hdev, 1438 struct list_head *list, 1439 enum HCLGEVF_MAC_ADDR_TYPE mac_type) 1440 { 1441 struct hclgevf_mac_addr_node *mac_node, *tmp; 1442 int ret; 1443 1444 list_for_each_entry_safe(mac_node, tmp, list, node) { 1445 ret = hclgevf_add_del_mac_addr(hdev, mac_node, mac_type); 1446 if (ret) { 1447 dev_err(&hdev->pdev->dev, 1448 "failed to configure mac %pM, state = %d, ret = %d\n", 1449 mac_node->mac_addr, mac_node->state, ret); 1450 return; 1451 } 1452 if (mac_node->state == HCLGEVF_MAC_TO_ADD) { 1453 mac_node->state = HCLGEVF_MAC_ACTIVE; 1454 } else { 1455 list_del(&mac_node->node); 1456 kfree(mac_node); 1457 } 1458 } 1459 } 1460 1461 static void hclgevf_sync_from_add_list(struct list_head *add_list, 1462 struct list_head *mac_list) 1463 { 1464 struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node; 1465 1466 list_for_each_entry_safe(mac_node, tmp, add_list, node) { 1467 /* if the mac address from tmp_add_list is not in the 1468 * uc/mc_mac_list, it means have received a TO_DEL request 1469 * during the time window of sending mac config request to PF 1470 * If mac_node state is ACTIVE, then change its state to TO_DEL, 1471 * then it will be removed at next time. If is TO_ADD, it means 1472 * send TO_ADD request failed, so just remove the mac node. 1473 */ 1474 new_node = hclgevf_find_mac_node(mac_list, mac_node->mac_addr); 1475 if (new_node) { 1476 hclgevf_update_mac_node(new_node, mac_node->state); 1477 list_del(&mac_node->node); 1478 kfree(mac_node); 1479 } else if (mac_node->state == HCLGEVF_MAC_ACTIVE) { 1480 mac_node->state = HCLGEVF_MAC_TO_DEL; 1481 list_del(&mac_node->node); 1482 list_add_tail(&mac_node->node, mac_list); 1483 } else { 1484 list_del(&mac_node->node); 1485 kfree(mac_node); 1486 } 1487 } 1488 } 1489 1490 static void hclgevf_sync_from_del_list(struct list_head *del_list, 1491 struct list_head *mac_list) 1492 { 1493 struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node; 1494 1495 list_for_each_entry_safe(mac_node, tmp, del_list, node) { 1496 new_node = hclgevf_find_mac_node(mac_list, mac_node->mac_addr); 1497 if (new_node) { 1498 /* If the mac addr is exist in the mac list, it means 1499 * received a new request TO_ADD during the time window 1500 * of sending mac addr configurrequest to PF, so just 1501 * change the mac state to ACTIVE. 1502 */ 1503 new_node->state = HCLGEVF_MAC_ACTIVE; 1504 list_del(&mac_node->node); 1505 kfree(mac_node); 1506 } else { 1507 list_del(&mac_node->node); 1508 list_add_tail(&mac_node->node, mac_list); 1509 } 1510 } 1511 } 1512 1513 static void hclgevf_clear_list(struct list_head *list) 1514 { 1515 struct hclgevf_mac_addr_node *mac_node, *tmp; 1516 1517 list_for_each_entry_safe(mac_node, tmp, list, node) { 1518 list_del(&mac_node->node); 1519 kfree(mac_node); 1520 } 1521 } 1522 1523 static void hclgevf_sync_mac_list(struct hclgevf_dev *hdev, 1524 enum HCLGEVF_MAC_ADDR_TYPE mac_type) 1525 { 1526 struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node; 1527 struct list_head tmp_add_list, tmp_del_list; 1528 struct list_head *list; 1529 1530 INIT_LIST_HEAD(&tmp_add_list); 1531 INIT_LIST_HEAD(&tmp_del_list); 1532 1533 /* move the mac addr to the tmp_add_list and tmp_del_list, then 1534 * we can add/delete these mac addr outside the spin lock 1535 */ 1536 list = (mac_type == HCLGEVF_MAC_ADDR_UC) ? 1537 &hdev->mac_table.uc_mac_list : &hdev->mac_table.mc_mac_list; 1538 1539 spin_lock_bh(&hdev->mac_table.mac_list_lock); 1540 1541 list_for_each_entry_safe(mac_node, tmp, list, node) { 1542 switch (mac_node->state) { 1543 case HCLGEVF_MAC_TO_DEL: 1544 list_del(&mac_node->node); 1545 list_add_tail(&mac_node->node, &tmp_del_list); 1546 break; 1547 case HCLGEVF_MAC_TO_ADD: 1548 new_node = kzalloc(sizeof(*new_node), GFP_ATOMIC); 1549 if (!new_node) 1550 goto stop_traverse; 1551 1552 ether_addr_copy(new_node->mac_addr, mac_node->mac_addr); 1553 new_node->state = mac_node->state; 1554 list_add_tail(&new_node->node, &tmp_add_list); 1555 break; 1556 default: 1557 break; 1558 } 1559 } 1560 1561 stop_traverse: 1562 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1563 1564 /* delete first, in order to get max mac table space for adding */ 1565 hclgevf_config_mac_list(hdev, &tmp_del_list, mac_type); 1566 hclgevf_config_mac_list(hdev, &tmp_add_list, mac_type); 1567 1568 /* if some mac addresses were added/deleted fail, move back to the 1569 * mac_list, and retry at next time. 1570 */ 1571 spin_lock_bh(&hdev->mac_table.mac_list_lock); 1572 1573 hclgevf_sync_from_del_list(&tmp_del_list, list); 1574 hclgevf_sync_from_add_list(&tmp_add_list, list); 1575 1576 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1577 } 1578 1579 static void hclgevf_sync_mac_table(struct hclgevf_dev *hdev) 1580 { 1581 hclgevf_sync_mac_list(hdev, HCLGEVF_MAC_ADDR_UC); 1582 hclgevf_sync_mac_list(hdev, HCLGEVF_MAC_ADDR_MC); 1583 } 1584 1585 static void hclgevf_uninit_mac_list(struct hclgevf_dev *hdev) 1586 { 1587 spin_lock_bh(&hdev->mac_table.mac_list_lock); 1588 1589 hclgevf_clear_list(&hdev->mac_table.uc_mac_list); 1590 hclgevf_clear_list(&hdev->mac_table.mc_mac_list); 1591 1592 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1593 } 1594 1595 static int hclgevf_set_vlan_filter(struct hnae3_handle *handle, 1596 __be16 proto, u16 vlan_id, 1597 bool is_kill) 1598 { 1599 #define HCLGEVF_VLAN_MBX_IS_KILL_OFFSET 0 1600 #define HCLGEVF_VLAN_MBX_VLAN_ID_OFFSET 1 1601 #define HCLGEVF_VLAN_MBX_PROTO_OFFSET 3 1602 1603 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1604 struct hclge_vf_to_pf_msg send_msg; 1605 int ret; 1606 1607 if (vlan_id > HCLGEVF_MAX_VLAN_ID) 1608 return -EINVAL; 1609 1610 if (proto != htons(ETH_P_8021Q)) 1611 return -EPROTONOSUPPORT; 1612 1613 /* When device is resetting or reset failed, firmware is unable to 1614 * handle mailbox. Just record the vlan id, and remove it after 1615 * reset finished. 1616 */ 1617 if ((test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) || 1618 test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) && is_kill) { 1619 set_bit(vlan_id, hdev->vlan_del_fail_bmap); 1620 return -EBUSY; 1621 } 1622 1623 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 1624 HCLGE_MBX_VLAN_FILTER); 1625 send_msg.data[HCLGEVF_VLAN_MBX_IS_KILL_OFFSET] = is_kill; 1626 memcpy(&send_msg.data[HCLGEVF_VLAN_MBX_VLAN_ID_OFFSET], &vlan_id, 1627 sizeof(vlan_id)); 1628 memcpy(&send_msg.data[HCLGEVF_VLAN_MBX_PROTO_OFFSET], &proto, 1629 sizeof(proto)); 1630 /* when remove hw vlan filter failed, record the vlan id, 1631 * and try to remove it from hw later, to be consistence 1632 * with stack. 1633 */ 1634 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1635 if (is_kill && ret) 1636 set_bit(vlan_id, hdev->vlan_del_fail_bmap); 1637 1638 return ret; 1639 } 1640 1641 static void hclgevf_sync_vlan_filter(struct hclgevf_dev *hdev) 1642 { 1643 #define HCLGEVF_MAX_SYNC_COUNT 60 1644 struct hnae3_handle *handle = &hdev->nic; 1645 int ret, sync_cnt = 0; 1646 u16 vlan_id; 1647 1648 vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID); 1649 while (vlan_id != VLAN_N_VID) { 1650 ret = hclgevf_set_vlan_filter(handle, htons(ETH_P_8021Q), 1651 vlan_id, true); 1652 if (ret) 1653 return; 1654 1655 clear_bit(vlan_id, hdev->vlan_del_fail_bmap); 1656 sync_cnt++; 1657 if (sync_cnt >= HCLGEVF_MAX_SYNC_COUNT) 1658 return; 1659 1660 vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID); 1661 } 1662 } 1663 1664 static int hclgevf_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) 1665 { 1666 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1667 struct hclge_vf_to_pf_msg send_msg; 1668 1669 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 1670 HCLGE_MBX_VLAN_RX_OFF_CFG); 1671 send_msg.data[0] = enable ? 1 : 0; 1672 return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 1673 } 1674 1675 static int hclgevf_reset_tqp(struct hnae3_handle *handle, u16 queue_id) 1676 { 1677 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1678 struct hclge_vf_to_pf_msg send_msg; 1679 int ret; 1680 1681 /* disable vf queue before send queue reset msg to PF */ 1682 ret = hclgevf_tqp_enable(hdev, queue_id, 0, false); 1683 if (ret) 1684 return ret; 1685 1686 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_QUEUE_RESET, 0); 1687 memcpy(send_msg.data, &queue_id, sizeof(queue_id)); 1688 return hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1689 } 1690 1691 static int hclgevf_set_mtu(struct hnae3_handle *handle, int new_mtu) 1692 { 1693 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1694 struct hclge_vf_to_pf_msg send_msg; 1695 1696 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_MTU, 0); 1697 memcpy(send_msg.data, &new_mtu, sizeof(new_mtu)); 1698 return hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1699 } 1700 1701 static int hclgevf_notify_client(struct hclgevf_dev *hdev, 1702 enum hnae3_reset_notify_type type) 1703 { 1704 struct hnae3_client *client = hdev->nic_client; 1705 struct hnae3_handle *handle = &hdev->nic; 1706 int ret; 1707 1708 if (!test_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state) || 1709 !client) 1710 return 0; 1711 1712 if (!client->ops->reset_notify) 1713 return -EOPNOTSUPP; 1714 1715 ret = client->ops->reset_notify(handle, type); 1716 if (ret) 1717 dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n", 1718 type, ret); 1719 1720 return ret; 1721 } 1722 1723 static int hclgevf_notify_roce_client(struct hclgevf_dev *hdev, 1724 enum hnae3_reset_notify_type type) 1725 { 1726 struct hnae3_client *client = hdev->roce_client; 1727 struct hnae3_handle *handle = &hdev->roce; 1728 int ret; 1729 1730 if (!test_bit(HCLGEVF_STATE_ROCE_REGISTERED, &hdev->state) || !client) 1731 return 0; 1732 1733 if (!client->ops->reset_notify) 1734 return -EOPNOTSUPP; 1735 1736 ret = client->ops->reset_notify(handle, type); 1737 if (ret) 1738 dev_err(&hdev->pdev->dev, "notify roce client failed %d(%d)", 1739 type, ret); 1740 return ret; 1741 } 1742 1743 static int hclgevf_reset_wait(struct hclgevf_dev *hdev) 1744 { 1745 #define HCLGEVF_RESET_WAIT_US 20000 1746 #define HCLGEVF_RESET_WAIT_CNT 2000 1747 #define HCLGEVF_RESET_WAIT_TIMEOUT_US \ 1748 (HCLGEVF_RESET_WAIT_US * HCLGEVF_RESET_WAIT_CNT) 1749 1750 u32 val; 1751 int ret; 1752 1753 if (hdev->reset_type == HNAE3_VF_RESET) 1754 ret = readl_poll_timeout(hdev->hw.io_base + 1755 HCLGEVF_VF_RST_ING, val, 1756 !(val & HCLGEVF_VF_RST_ING_BIT), 1757 HCLGEVF_RESET_WAIT_US, 1758 HCLGEVF_RESET_WAIT_TIMEOUT_US); 1759 else 1760 ret = readl_poll_timeout(hdev->hw.io_base + 1761 HCLGEVF_RST_ING, val, 1762 !(val & HCLGEVF_RST_ING_BITS), 1763 HCLGEVF_RESET_WAIT_US, 1764 HCLGEVF_RESET_WAIT_TIMEOUT_US); 1765 1766 /* hardware completion status should be available by this time */ 1767 if (ret) { 1768 dev_err(&hdev->pdev->dev, 1769 "couldn't get reset done status from h/w, timeout!\n"); 1770 return ret; 1771 } 1772 1773 /* we will wait a bit more to let reset of the stack to complete. This 1774 * might happen in case reset assertion was made by PF. Yes, this also 1775 * means we might end up waiting bit more even for VF reset. 1776 */ 1777 msleep(5000); 1778 1779 return 0; 1780 } 1781 1782 static void hclgevf_reset_handshake(struct hclgevf_dev *hdev, bool enable) 1783 { 1784 u32 reg_val; 1785 1786 reg_val = hclgevf_read_dev(&hdev->hw, HCLGEVF_NIC_CSQ_DEPTH_REG); 1787 if (enable) 1788 reg_val |= HCLGEVF_NIC_SW_RST_RDY; 1789 else 1790 reg_val &= ~HCLGEVF_NIC_SW_RST_RDY; 1791 1792 hclgevf_write_dev(&hdev->hw, HCLGEVF_NIC_CSQ_DEPTH_REG, 1793 reg_val); 1794 } 1795 1796 static int hclgevf_reset_stack(struct hclgevf_dev *hdev) 1797 { 1798 int ret; 1799 1800 /* uninitialize the nic client */ 1801 ret = hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT); 1802 if (ret) 1803 return ret; 1804 1805 /* re-initialize the hclge device */ 1806 ret = hclgevf_reset_hdev(hdev); 1807 if (ret) { 1808 dev_err(&hdev->pdev->dev, 1809 "hclge device re-init failed, VF is disabled!\n"); 1810 return ret; 1811 } 1812 1813 /* bring up the nic client again */ 1814 ret = hclgevf_notify_client(hdev, HNAE3_INIT_CLIENT); 1815 if (ret) 1816 return ret; 1817 1818 /* clear handshake status with IMP */ 1819 hclgevf_reset_handshake(hdev, false); 1820 1821 /* bring up the nic to enable TX/RX again */ 1822 return hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 1823 } 1824 1825 static int hclgevf_reset_prepare_wait(struct hclgevf_dev *hdev) 1826 { 1827 #define HCLGEVF_RESET_SYNC_TIME 100 1828 1829 if (hdev->reset_type == HNAE3_VF_FUNC_RESET) { 1830 struct hclge_vf_to_pf_msg send_msg; 1831 int ret; 1832 1833 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_RESET, 0); 1834 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1835 if (ret) { 1836 dev_err(&hdev->pdev->dev, 1837 "failed to assert VF reset, ret = %d\n", ret); 1838 return ret; 1839 } 1840 hdev->rst_stats.vf_func_rst_cnt++; 1841 } 1842 1843 set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 1844 /* inform hardware that preparatory work is done */ 1845 msleep(HCLGEVF_RESET_SYNC_TIME); 1846 hclgevf_reset_handshake(hdev, true); 1847 dev_info(&hdev->pdev->dev, "prepare reset(%d) wait done\n", 1848 hdev->reset_type); 1849 1850 return 0; 1851 } 1852 1853 static void hclgevf_dump_rst_info(struct hclgevf_dev *hdev) 1854 { 1855 dev_info(&hdev->pdev->dev, "VF function reset count: %u\n", 1856 hdev->rst_stats.vf_func_rst_cnt); 1857 dev_info(&hdev->pdev->dev, "FLR reset count: %u\n", 1858 hdev->rst_stats.flr_rst_cnt); 1859 dev_info(&hdev->pdev->dev, "VF reset count: %u\n", 1860 hdev->rst_stats.vf_rst_cnt); 1861 dev_info(&hdev->pdev->dev, "reset done count: %u\n", 1862 hdev->rst_stats.rst_done_cnt); 1863 dev_info(&hdev->pdev->dev, "HW reset done count: %u\n", 1864 hdev->rst_stats.hw_rst_done_cnt); 1865 dev_info(&hdev->pdev->dev, "reset count: %u\n", 1866 hdev->rst_stats.rst_cnt); 1867 dev_info(&hdev->pdev->dev, "reset fail count: %u\n", 1868 hdev->rst_stats.rst_fail_cnt); 1869 dev_info(&hdev->pdev->dev, "vector0 interrupt enable status: 0x%x\n", 1870 hclgevf_read_dev(&hdev->hw, HCLGEVF_MISC_VECTOR_REG_BASE)); 1871 dev_info(&hdev->pdev->dev, "vector0 interrupt status: 0x%x\n", 1872 hclgevf_read_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_STATE_REG)); 1873 dev_info(&hdev->pdev->dev, "handshake status: 0x%x\n", 1874 hclgevf_read_dev(&hdev->hw, HCLGEVF_CMDQ_TX_DEPTH_REG)); 1875 dev_info(&hdev->pdev->dev, "function reset status: 0x%x\n", 1876 hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING)); 1877 dev_info(&hdev->pdev->dev, "hdev state: 0x%lx\n", hdev->state); 1878 } 1879 1880 static void hclgevf_reset_err_handle(struct hclgevf_dev *hdev) 1881 { 1882 /* recover handshake status with IMP when reset fail */ 1883 hclgevf_reset_handshake(hdev, true); 1884 hdev->rst_stats.rst_fail_cnt++; 1885 dev_err(&hdev->pdev->dev, "failed to reset VF(%u)\n", 1886 hdev->rst_stats.rst_fail_cnt); 1887 1888 if (hdev->rst_stats.rst_fail_cnt < HCLGEVF_RESET_MAX_FAIL_CNT) 1889 set_bit(hdev->reset_type, &hdev->reset_pending); 1890 1891 if (hclgevf_is_reset_pending(hdev)) { 1892 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1893 hclgevf_reset_task_schedule(hdev); 1894 } else { 1895 set_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state); 1896 hclgevf_dump_rst_info(hdev); 1897 } 1898 } 1899 1900 static int hclgevf_reset_prepare(struct hclgevf_dev *hdev) 1901 { 1902 int ret; 1903 1904 hdev->rst_stats.rst_cnt++; 1905 1906 /* perform reset of the stack & ae device for a client */ 1907 ret = hclgevf_notify_roce_client(hdev, HNAE3_DOWN_CLIENT); 1908 if (ret) 1909 return ret; 1910 1911 rtnl_lock(); 1912 /* bring down the nic to stop any ongoing TX/RX */ 1913 ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 1914 rtnl_unlock(); 1915 if (ret) 1916 return ret; 1917 1918 return hclgevf_reset_prepare_wait(hdev); 1919 } 1920 1921 static int hclgevf_reset_rebuild(struct hclgevf_dev *hdev) 1922 { 1923 int ret; 1924 1925 hdev->rst_stats.hw_rst_done_cnt++; 1926 ret = hclgevf_notify_roce_client(hdev, HNAE3_UNINIT_CLIENT); 1927 if (ret) 1928 return ret; 1929 1930 rtnl_lock(); 1931 /* now, re-initialize the nic client and ae device */ 1932 ret = hclgevf_reset_stack(hdev); 1933 rtnl_unlock(); 1934 if (ret) { 1935 dev_err(&hdev->pdev->dev, "failed to reset VF stack\n"); 1936 return ret; 1937 } 1938 1939 ret = hclgevf_notify_roce_client(hdev, HNAE3_INIT_CLIENT); 1940 /* ignore RoCE notify error if it fails HCLGEVF_RESET_MAX_FAIL_CNT - 1 1941 * times 1942 */ 1943 if (ret && 1944 hdev->rst_stats.rst_fail_cnt < HCLGEVF_RESET_MAX_FAIL_CNT - 1) 1945 return ret; 1946 1947 ret = hclgevf_notify_roce_client(hdev, HNAE3_UP_CLIENT); 1948 if (ret) 1949 return ret; 1950 1951 hdev->last_reset_time = jiffies; 1952 hdev->rst_stats.rst_done_cnt++; 1953 hdev->rst_stats.rst_fail_cnt = 0; 1954 clear_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state); 1955 1956 return 0; 1957 } 1958 1959 static void hclgevf_reset(struct hclgevf_dev *hdev) 1960 { 1961 if (hclgevf_reset_prepare(hdev)) 1962 goto err_reset; 1963 1964 /* check if VF could successfully fetch the hardware reset completion 1965 * status from the hardware 1966 */ 1967 if (hclgevf_reset_wait(hdev)) { 1968 /* can't do much in this situation, will disable VF */ 1969 dev_err(&hdev->pdev->dev, 1970 "failed to fetch H/W reset completion status\n"); 1971 goto err_reset; 1972 } 1973 1974 if (hclgevf_reset_rebuild(hdev)) 1975 goto err_reset; 1976 1977 return; 1978 1979 err_reset: 1980 hclgevf_reset_err_handle(hdev); 1981 } 1982 1983 static enum hnae3_reset_type hclgevf_get_reset_level(struct hclgevf_dev *hdev, 1984 unsigned long *addr) 1985 { 1986 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; 1987 1988 /* return the highest priority reset level amongst all */ 1989 if (test_bit(HNAE3_VF_RESET, addr)) { 1990 rst_level = HNAE3_VF_RESET; 1991 clear_bit(HNAE3_VF_RESET, addr); 1992 clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1993 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1994 } else if (test_bit(HNAE3_VF_FULL_RESET, addr)) { 1995 rst_level = HNAE3_VF_FULL_RESET; 1996 clear_bit(HNAE3_VF_FULL_RESET, addr); 1997 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1998 } else if (test_bit(HNAE3_VF_PF_FUNC_RESET, addr)) { 1999 rst_level = HNAE3_VF_PF_FUNC_RESET; 2000 clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 2001 clear_bit(HNAE3_VF_FUNC_RESET, addr); 2002 } else if (test_bit(HNAE3_VF_FUNC_RESET, addr)) { 2003 rst_level = HNAE3_VF_FUNC_RESET; 2004 clear_bit(HNAE3_VF_FUNC_RESET, addr); 2005 } else if (test_bit(HNAE3_FLR_RESET, addr)) { 2006 rst_level = HNAE3_FLR_RESET; 2007 clear_bit(HNAE3_FLR_RESET, addr); 2008 } 2009 2010 return rst_level; 2011 } 2012 2013 static void hclgevf_reset_event(struct pci_dev *pdev, 2014 struct hnae3_handle *handle) 2015 { 2016 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2017 struct hclgevf_dev *hdev = ae_dev->priv; 2018 2019 dev_info(&hdev->pdev->dev, "received reset request from VF enet\n"); 2020 2021 if (hdev->default_reset_request) 2022 hdev->reset_level = 2023 hclgevf_get_reset_level(hdev, 2024 &hdev->default_reset_request); 2025 else 2026 hdev->reset_level = HNAE3_VF_FUNC_RESET; 2027 2028 /* reset of this VF requested */ 2029 set_bit(HCLGEVF_RESET_REQUESTED, &hdev->reset_state); 2030 hclgevf_reset_task_schedule(hdev); 2031 2032 hdev->last_reset_time = jiffies; 2033 } 2034 2035 static void hclgevf_set_def_reset_request(struct hnae3_ae_dev *ae_dev, 2036 enum hnae3_reset_type rst_type) 2037 { 2038 struct hclgevf_dev *hdev = ae_dev->priv; 2039 2040 set_bit(rst_type, &hdev->default_reset_request); 2041 } 2042 2043 static void hclgevf_enable_vector(struct hclgevf_misc_vector *vector, bool en) 2044 { 2045 writel(en ? 1 : 0, vector->addr); 2046 } 2047 2048 static void hclgevf_flr_prepare(struct hnae3_ae_dev *ae_dev) 2049 { 2050 #define HCLGEVF_FLR_RETRY_WAIT_MS 500 2051 #define HCLGEVF_FLR_RETRY_CNT 5 2052 2053 struct hclgevf_dev *hdev = ae_dev->priv; 2054 int retry_cnt = 0; 2055 int ret; 2056 2057 retry: 2058 down(&hdev->reset_sem); 2059 set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 2060 hdev->reset_type = HNAE3_FLR_RESET; 2061 ret = hclgevf_reset_prepare(hdev); 2062 if (ret) { 2063 dev_err(&hdev->pdev->dev, "fail to prepare FLR, ret=%d\n", 2064 ret); 2065 if (hdev->reset_pending || 2066 retry_cnt++ < HCLGEVF_FLR_RETRY_CNT) { 2067 dev_err(&hdev->pdev->dev, 2068 "reset_pending:0x%lx, retry_cnt:%d\n", 2069 hdev->reset_pending, retry_cnt); 2070 clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 2071 up(&hdev->reset_sem); 2072 msleep(HCLGEVF_FLR_RETRY_WAIT_MS); 2073 goto retry; 2074 } 2075 } 2076 2077 /* disable misc vector before FLR done */ 2078 hclgevf_enable_vector(&hdev->misc_vector, false); 2079 hdev->rst_stats.flr_rst_cnt++; 2080 } 2081 2082 static void hclgevf_flr_done(struct hnae3_ae_dev *ae_dev) 2083 { 2084 struct hclgevf_dev *hdev = ae_dev->priv; 2085 int ret; 2086 2087 hclgevf_enable_vector(&hdev->misc_vector, true); 2088 2089 ret = hclgevf_reset_rebuild(hdev); 2090 if (ret) 2091 dev_warn(&hdev->pdev->dev, "fail to rebuild, ret=%d\n", 2092 ret); 2093 2094 hdev->reset_type = HNAE3_NONE_RESET; 2095 clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 2096 up(&hdev->reset_sem); 2097 } 2098 2099 static u32 hclgevf_get_fw_version(struct hnae3_handle *handle) 2100 { 2101 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2102 2103 return hdev->fw_version; 2104 } 2105 2106 static void hclgevf_get_misc_vector(struct hclgevf_dev *hdev) 2107 { 2108 struct hclgevf_misc_vector *vector = &hdev->misc_vector; 2109 2110 vector->vector_irq = pci_irq_vector(hdev->pdev, 2111 HCLGEVF_MISC_VECTOR_NUM); 2112 vector->addr = hdev->hw.io_base + HCLGEVF_MISC_VECTOR_REG_BASE; 2113 /* vector status always valid for Vector 0 */ 2114 hdev->vector_status[HCLGEVF_MISC_VECTOR_NUM] = 0; 2115 hdev->vector_irq[HCLGEVF_MISC_VECTOR_NUM] = vector->vector_irq; 2116 2117 hdev->num_msi_left -= 1; 2118 hdev->num_msi_used += 1; 2119 } 2120 2121 void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev) 2122 { 2123 if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) && 2124 !test_and_set_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, 2125 &hdev->state)) 2126 mod_delayed_work(hclgevf_wq, &hdev->service_task, 0); 2127 } 2128 2129 void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev) 2130 { 2131 if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) && 2132 !test_and_set_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, 2133 &hdev->state)) 2134 mod_delayed_work(hclgevf_wq, &hdev->service_task, 0); 2135 } 2136 2137 static void hclgevf_task_schedule(struct hclgevf_dev *hdev, 2138 unsigned long delay) 2139 { 2140 if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) && 2141 !test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) 2142 mod_delayed_work(hclgevf_wq, &hdev->service_task, delay); 2143 } 2144 2145 static void hclgevf_reset_service_task(struct hclgevf_dev *hdev) 2146 { 2147 #define HCLGEVF_MAX_RESET_ATTEMPTS_CNT 3 2148 2149 if (!test_and_clear_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state)) 2150 return; 2151 2152 down(&hdev->reset_sem); 2153 set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 2154 2155 if (test_and_clear_bit(HCLGEVF_RESET_PENDING, 2156 &hdev->reset_state)) { 2157 /* PF has initmated that it is about to reset the hardware. 2158 * We now have to poll & check if hardware has actually 2159 * completed the reset sequence. On hardware reset completion, 2160 * VF needs to reset the client and ae device. 2161 */ 2162 hdev->reset_attempts = 0; 2163 2164 hdev->last_reset_time = jiffies; 2165 while ((hdev->reset_type = 2166 hclgevf_get_reset_level(hdev, &hdev->reset_pending)) 2167 != HNAE3_NONE_RESET) 2168 hclgevf_reset(hdev); 2169 } else if (test_and_clear_bit(HCLGEVF_RESET_REQUESTED, 2170 &hdev->reset_state)) { 2171 /* we could be here when either of below happens: 2172 * 1. reset was initiated due to watchdog timeout caused by 2173 * a. IMP was earlier reset and our TX got choked down and 2174 * which resulted in watchdog reacting and inducing VF 2175 * reset. This also means our cmdq would be unreliable. 2176 * b. problem in TX due to other lower layer(example link 2177 * layer not functioning properly etc.) 2178 * 2. VF reset might have been initiated due to some config 2179 * change. 2180 * 2181 * NOTE: Theres no clear way to detect above cases than to react 2182 * to the response of PF for this reset request. PF will ack the 2183 * 1b and 2. cases but we will not get any intimation about 1a 2184 * from PF as cmdq would be in unreliable state i.e. mailbox 2185 * communication between PF and VF would be broken. 2186 * 2187 * if we are never geting into pending state it means either: 2188 * 1. PF is not receiving our request which could be due to IMP 2189 * reset 2190 * 2. PF is screwed 2191 * We cannot do much for 2. but to check first we can try reset 2192 * our PCIe + stack and see if it alleviates the problem. 2193 */ 2194 if (hdev->reset_attempts > HCLGEVF_MAX_RESET_ATTEMPTS_CNT) { 2195 /* prepare for full reset of stack + pcie interface */ 2196 set_bit(HNAE3_VF_FULL_RESET, &hdev->reset_pending); 2197 2198 /* "defer" schedule the reset task again */ 2199 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 2200 } else { 2201 hdev->reset_attempts++; 2202 2203 set_bit(hdev->reset_level, &hdev->reset_pending); 2204 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 2205 } 2206 hclgevf_reset_task_schedule(hdev); 2207 } 2208 2209 hdev->reset_type = HNAE3_NONE_RESET; 2210 clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 2211 up(&hdev->reset_sem); 2212 } 2213 2214 static void hclgevf_mailbox_service_task(struct hclgevf_dev *hdev) 2215 { 2216 if (!test_and_clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state)) 2217 return; 2218 2219 if (test_and_set_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) 2220 return; 2221 2222 hclgevf_mbx_async_handler(hdev); 2223 2224 clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 2225 } 2226 2227 static void hclgevf_keep_alive(struct hclgevf_dev *hdev) 2228 { 2229 struct hclge_vf_to_pf_msg send_msg; 2230 int ret; 2231 2232 if (test_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state)) 2233 return; 2234 2235 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_KEEP_ALIVE, 0); 2236 ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 2237 if (ret) 2238 dev_err(&hdev->pdev->dev, 2239 "VF sends keep alive cmd failed(=%d)\n", ret); 2240 } 2241 2242 static void hclgevf_periodic_service_task(struct hclgevf_dev *hdev) 2243 { 2244 unsigned long delta = round_jiffies_relative(HZ); 2245 struct hnae3_handle *handle = &hdev->nic; 2246 2247 if (test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) 2248 return; 2249 2250 if (time_is_after_jiffies(hdev->last_serv_processed + HZ)) { 2251 delta = jiffies - hdev->last_serv_processed; 2252 2253 if (delta < round_jiffies_relative(HZ)) { 2254 delta = round_jiffies_relative(HZ) - delta; 2255 goto out; 2256 } 2257 } 2258 2259 hdev->serv_processed_cnt++; 2260 if (!(hdev->serv_processed_cnt % HCLGEVF_KEEP_ALIVE_TASK_INTERVAL)) 2261 hclgevf_keep_alive(hdev); 2262 2263 if (test_bit(HCLGEVF_STATE_DOWN, &hdev->state)) { 2264 hdev->last_serv_processed = jiffies; 2265 goto out; 2266 } 2267 2268 if (!(hdev->serv_processed_cnt % HCLGEVF_STATS_TIMER_INTERVAL)) 2269 hclgevf_tqps_update_stats(handle); 2270 2271 /* request the link status from the PF. PF would be able to tell VF 2272 * about such updates in future so we might remove this later 2273 */ 2274 hclgevf_request_link_info(hdev); 2275 2276 hclgevf_update_link_mode(hdev); 2277 2278 hclgevf_sync_vlan_filter(hdev); 2279 2280 hclgevf_sync_mac_table(hdev); 2281 2282 hclgevf_sync_promisc_mode(hdev); 2283 2284 hdev->last_serv_processed = jiffies; 2285 2286 out: 2287 hclgevf_task_schedule(hdev, delta); 2288 } 2289 2290 static void hclgevf_service_task(struct work_struct *work) 2291 { 2292 struct hclgevf_dev *hdev = container_of(work, struct hclgevf_dev, 2293 service_task.work); 2294 2295 hclgevf_reset_service_task(hdev); 2296 hclgevf_mailbox_service_task(hdev); 2297 hclgevf_periodic_service_task(hdev); 2298 2299 /* Handle reset and mbx again in case periodical task delays the 2300 * handling by calling hclgevf_task_schedule() in 2301 * hclgevf_periodic_service_task() 2302 */ 2303 hclgevf_reset_service_task(hdev); 2304 hclgevf_mailbox_service_task(hdev); 2305 } 2306 2307 static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regclr) 2308 { 2309 hclgevf_write_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_SRC_REG, regclr); 2310 } 2311 2312 static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev, 2313 u32 *clearval) 2314 { 2315 u32 val, cmdq_stat_reg, rst_ing_reg; 2316 2317 /* fetch the events from their corresponding regs */ 2318 cmdq_stat_reg = hclgevf_read_dev(&hdev->hw, 2319 HCLGEVF_VECTOR0_CMDQ_STATE_REG); 2320 2321 if (BIT(HCLGEVF_VECTOR0_RST_INT_B) & cmdq_stat_reg) { 2322 rst_ing_reg = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 2323 dev_info(&hdev->pdev->dev, 2324 "receive reset interrupt 0x%x!\n", rst_ing_reg); 2325 set_bit(HNAE3_VF_RESET, &hdev->reset_pending); 2326 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 2327 set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 2328 *clearval = ~(1U << HCLGEVF_VECTOR0_RST_INT_B); 2329 hdev->rst_stats.vf_rst_cnt++; 2330 /* set up VF hardware reset status, its PF will clear 2331 * this status when PF has initialized done. 2332 */ 2333 val = hclgevf_read_dev(&hdev->hw, HCLGEVF_VF_RST_ING); 2334 hclgevf_write_dev(&hdev->hw, HCLGEVF_VF_RST_ING, 2335 val | HCLGEVF_VF_RST_ING_BIT); 2336 return HCLGEVF_VECTOR0_EVENT_RST; 2337 } 2338 2339 /* check for vector0 mailbox(=CMDQ RX) event source */ 2340 if (BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) { 2341 /* for revision 0x21, clearing interrupt is writing bit 0 2342 * to the clear register, writing bit 1 means to keep the 2343 * old value. 2344 * for revision 0x20, the clear register is a read & write 2345 * register, so we should just write 0 to the bit we are 2346 * handling, and keep other bits as cmdq_stat_reg. 2347 */ 2348 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) 2349 *clearval = ~(1U << HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 2350 else 2351 *clearval = cmdq_stat_reg & 2352 ~BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 2353 2354 return HCLGEVF_VECTOR0_EVENT_MBX; 2355 } 2356 2357 /* print other vector0 event source */ 2358 dev_info(&hdev->pdev->dev, 2359 "vector 0 interrupt from unknown source, cmdq_src = %#x\n", 2360 cmdq_stat_reg); 2361 2362 return HCLGEVF_VECTOR0_EVENT_OTHER; 2363 } 2364 2365 static irqreturn_t hclgevf_misc_irq_handle(int irq, void *data) 2366 { 2367 enum hclgevf_evt_cause event_cause; 2368 struct hclgevf_dev *hdev = data; 2369 u32 clearval; 2370 2371 hclgevf_enable_vector(&hdev->misc_vector, false); 2372 event_cause = hclgevf_check_evt_cause(hdev, &clearval); 2373 2374 switch (event_cause) { 2375 case HCLGEVF_VECTOR0_EVENT_RST: 2376 hclgevf_reset_task_schedule(hdev); 2377 break; 2378 case HCLGEVF_VECTOR0_EVENT_MBX: 2379 hclgevf_mbx_handler(hdev); 2380 break; 2381 default: 2382 break; 2383 } 2384 2385 if (event_cause != HCLGEVF_VECTOR0_EVENT_OTHER) { 2386 hclgevf_clear_event_cause(hdev, clearval); 2387 hclgevf_enable_vector(&hdev->misc_vector, true); 2388 } 2389 2390 return IRQ_HANDLED; 2391 } 2392 2393 static int hclgevf_configure(struct hclgevf_dev *hdev) 2394 { 2395 int ret; 2396 2397 /* get current port based vlan state from PF */ 2398 ret = hclgevf_get_port_base_vlan_filter_state(hdev); 2399 if (ret) 2400 return ret; 2401 2402 /* get queue configuration from PF */ 2403 ret = hclgevf_get_queue_info(hdev); 2404 if (ret) 2405 return ret; 2406 2407 /* get queue depth info from PF */ 2408 ret = hclgevf_get_queue_depth(hdev); 2409 if (ret) 2410 return ret; 2411 2412 ret = hclgevf_get_pf_media_type(hdev); 2413 if (ret) 2414 return ret; 2415 2416 /* get tc configuration from PF */ 2417 return hclgevf_get_tc_info(hdev); 2418 } 2419 2420 static int hclgevf_alloc_hdev(struct hnae3_ae_dev *ae_dev) 2421 { 2422 struct pci_dev *pdev = ae_dev->pdev; 2423 struct hclgevf_dev *hdev; 2424 2425 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 2426 if (!hdev) 2427 return -ENOMEM; 2428 2429 hdev->pdev = pdev; 2430 hdev->ae_dev = ae_dev; 2431 ae_dev->priv = hdev; 2432 2433 return 0; 2434 } 2435 2436 static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev) 2437 { 2438 struct hnae3_handle *roce = &hdev->roce; 2439 struct hnae3_handle *nic = &hdev->nic; 2440 2441 roce->rinfo.num_vectors = hdev->num_roce_msix; 2442 2443 if (hdev->num_msi_left < roce->rinfo.num_vectors || 2444 hdev->num_msi_left == 0) 2445 return -EINVAL; 2446 2447 roce->rinfo.base_vector = hdev->roce_base_vector; 2448 2449 roce->rinfo.netdev = nic->kinfo.netdev; 2450 roce->rinfo.roce_io_base = hdev->hw.io_base; 2451 roce->rinfo.roce_mem_base = hdev->hw.mem_base; 2452 2453 roce->pdev = nic->pdev; 2454 roce->ae_algo = nic->ae_algo; 2455 roce->numa_node_mask = nic->numa_node_mask; 2456 2457 return 0; 2458 } 2459 2460 static int hclgevf_config_gro(struct hclgevf_dev *hdev, bool en) 2461 { 2462 struct hclgevf_cfg_gro_status_cmd *req; 2463 struct hclgevf_desc desc; 2464 int ret; 2465 2466 if (!hnae3_dev_gro_supported(hdev)) 2467 return 0; 2468 2469 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_GRO_GENERIC_CONFIG, 2470 false); 2471 req = (struct hclgevf_cfg_gro_status_cmd *)desc.data; 2472 2473 req->gro_en = en ? 1 : 0; 2474 2475 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 2476 if (ret) 2477 dev_err(&hdev->pdev->dev, 2478 "VF GRO hardware config cmd failed, ret = %d.\n", ret); 2479 2480 return ret; 2481 } 2482 2483 static int hclgevf_rss_init_cfg(struct hclgevf_dev *hdev) 2484 { 2485 u16 rss_ind_tbl_size = hdev->ae_dev->dev_specs.rss_ind_tbl_size; 2486 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 2487 struct hclgevf_rss_tuple_cfg *tuple_sets; 2488 u32 i; 2489 2490 rss_cfg->hash_algo = HCLGEVF_RSS_HASH_ALGO_TOEPLITZ; 2491 rss_cfg->rss_size = hdev->nic.kinfo.rss_size; 2492 tuple_sets = &rss_cfg->rss_tuple_sets; 2493 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 2494 u8 *rss_ind_tbl; 2495 2496 rss_cfg->hash_algo = HCLGEVF_RSS_HASH_ALGO_SIMPLE; 2497 2498 rss_ind_tbl = devm_kcalloc(&hdev->pdev->dev, rss_ind_tbl_size, 2499 sizeof(*rss_ind_tbl), GFP_KERNEL); 2500 if (!rss_ind_tbl) 2501 return -ENOMEM; 2502 2503 rss_cfg->rss_indirection_tbl = rss_ind_tbl; 2504 memcpy(rss_cfg->rss_hash_key, hclgevf_hash_key, 2505 HCLGEVF_RSS_KEY_SIZE); 2506 2507 tuple_sets->ipv4_tcp_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2508 tuple_sets->ipv4_udp_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2509 tuple_sets->ipv4_sctp_en = HCLGEVF_RSS_INPUT_TUPLE_SCTP; 2510 tuple_sets->ipv4_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2511 tuple_sets->ipv6_tcp_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2512 tuple_sets->ipv6_udp_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2513 tuple_sets->ipv6_sctp_en = 2514 hdev->ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2 ? 2515 HCLGEVF_RSS_INPUT_TUPLE_SCTP_NO_PORT : 2516 HCLGEVF_RSS_INPUT_TUPLE_SCTP; 2517 tuple_sets->ipv6_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2518 } 2519 2520 /* Initialize RSS indirect table */ 2521 for (i = 0; i < rss_ind_tbl_size; i++) 2522 rss_cfg->rss_indirection_tbl[i] = i % rss_cfg->rss_size; 2523 2524 return 0; 2525 } 2526 2527 static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev) 2528 { 2529 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 2530 int ret; 2531 2532 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 2533 ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 2534 rss_cfg->rss_hash_key); 2535 if (ret) 2536 return ret; 2537 2538 ret = hclgevf_set_rss_input_tuple(hdev, rss_cfg); 2539 if (ret) 2540 return ret; 2541 } 2542 2543 ret = hclgevf_set_rss_indir_table(hdev); 2544 if (ret) 2545 return ret; 2546 2547 return hclgevf_set_rss_tc_mode(hdev, rss_cfg->rss_size); 2548 } 2549 2550 static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev) 2551 { 2552 return hclgevf_set_vlan_filter(&hdev->nic, htons(ETH_P_8021Q), 0, 2553 false); 2554 } 2555 2556 static void hclgevf_flush_link_update(struct hclgevf_dev *hdev) 2557 { 2558 #define HCLGEVF_FLUSH_LINK_TIMEOUT 100000 2559 2560 unsigned long last = hdev->serv_processed_cnt; 2561 int i = 0; 2562 2563 while (test_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state) && 2564 i++ < HCLGEVF_FLUSH_LINK_TIMEOUT && 2565 last == hdev->serv_processed_cnt) 2566 usleep_range(1, 1); 2567 } 2568 2569 static void hclgevf_set_timer_task(struct hnae3_handle *handle, bool enable) 2570 { 2571 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2572 2573 if (enable) { 2574 hclgevf_task_schedule(hdev, 0); 2575 } else { 2576 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2577 2578 /* flush memory to make sure DOWN is seen by service task */ 2579 smp_mb__before_atomic(); 2580 hclgevf_flush_link_update(hdev); 2581 } 2582 } 2583 2584 static int hclgevf_ae_start(struct hnae3_handle *handle) 2585 { 2586 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2587 2588 hclgevf_reset_tqp_stats(handle); 2589 2590 hclgevf_request_link_info(hdev); 2591 2592 hclgevf_update_link_mode(hdev); 2593 2594 clear_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2595 2596 return 0; 2597 } 2598 2599 static void hclgevf_ae_stop(struct hnae3_handle *handle) 2600 { 2601 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2602 int i; 2603 2604 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2605 2606 if (hdev->reset_type != HNAE3_VF_RESET) 2607 for (i = 0; i < handle->kinfo.num_tqps; i++) 2608 if (hclgevf_reset_tqp(handle, i)) 2609 break; 2610 2611 hclgevf_reset_tqp_stats(handle); 2612 hclgevf_update_link_status(hdev, 0); 2613 } 2614 2615 static int hclgevf_set_alive(struct hnae3_handle *handle, bool alive) 2616 { 2617 #define HCLGEVF_STATE_ALIVE 1 2618 #define HCLGEVF_STATE_NOT_ALIVE 0 2619 2620 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2621 struct hclge_vf_to_pf_msg send_msg; 2622 2623 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_ALIVE, 0); 2624 send_msg.data[0] = alive ? HCLGEVF_STATE_ALIVE : 2625 HCLGEVF_STATE_NOT_ALIVE; 2626 return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 2627 } 2628 2629 static int hclgevf_client_start(struct hnae3_handle *handle) 2630 { 2631 return hclgevf_set_alive(handle, true); 2632 } 2633 2634 static void hclgevf_client_stop(struct hnae3_handle *handle) 2635 { 2636 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2637 int ret; 2638 2639 ret = hclgevf_set_alive(handle, false); 2640 if (ret) 2641 dev_warn(&hdev->pdev->dev, 2642 "%s failed %d\n", __func__, ret); 2643 } 2644 2645 static void hclgevf_state_init(struct hclgevf_dev *hdev) 2646 { 2647 clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 2648 clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 2649 clear_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state); 2650 2651 INIT_DELAYED_WORK(&hdev->service_task, hclgevf_service_task); 2652 2653 mutex_init(&hdev->mbx_resp.mbx_mutex); 2654 sema_init(&hdev->reset_sem, 1); 2655 2656 spin_lock_init(&hdev->mac_table.mac_list_lock); 2657 INIT_LIST_HEAD(&hdev->mac_table.uc_mac_list); 2658 INIT_LIST_HEAD(&hdev->mac_table.mc_mac_list); 2659 2660 /* bring the device down */ 2661 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2662 } 2663 2664 static void hclgevf_state_uninit(struct hclgevf_dev *hdev) 2665 { 2666 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2667 set_bit(HCLGEVF_STATE_REMOVING, &hdev->state); 2668 2669 if (hdev->service_task.work.func) 2670 cancel_delayed_work_sync(&hdev->service_task); 2671 2672 mutex_destroy(&hdev->mbx_resp.mbx_mutex); 2673 } 2674 2675 static int hclgevf_init_msi(struct hclgevf_dev *hdev) 2676 { 2677 struct pci_dev *pdev = hdev->pdev; 2678 int vectors; 2679 int i; 2680 2681 if (hnae3_dev_roce_supported(hdev)) 2682 vectors = pci_alloc_irq_vectors(pdev, 2683 hdev->roce_base_msix_offset + 1, 2684 hdev->num_msi, 2685 PCI_IRQ_MSIX); 2686 else 2687 vectors = pci_alloc_irq_vectors(pdev, HNAE3_MIN_VECTOR_NUM, 2688 hdev->num_msi, 2689 PCI_IRQ_MSI | PCI_IRQ_MSIX); 2690 2691 if (vectors < 0) { 2692 dev_err(&pdev->dev, 2693 "failed(%d) to allocate MSI/MSI-X vectors\n", 2694 vectors); 2695 return vectors; 2696 } 2697 if (vectors < hdev->num_msi) 2698 dev_warn(&hdev->pdev->dev, 2699 "requested %u MSI/MSI-X, but allocated %d MSI/MSI-X\n", 2700 hdev->num_msi, vectors); 2701 2702 hdev->num_msi = vectors; 2703 hdev->num_msi_left = vectors; 2704 2705 hdev->base_msi_vector = pdev->irq; 2706 hdev->roce_base_vector = pdev->irq + hdev->roce_base_msix_offset; 2707 2708 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 2709 sizeof(u16), GFP_KERNEL); 2710 if (!hdev->vector_status) { 2711 pci_free_irq_vectors(pdev); 2712 return -ENOMEM; 2713 } 2714 2715 for (i = 0; i < hdev->num_msi; i++) 2716 hdev->vector_status[i] = HCLGEVF_INVALID_VPORT; 2717 2718 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 2719 sizeof(int), GFP_KERNEL); 2720 if (!hdev->vector_irq) { 2721 devm_kfree(&pdev->dev, hdev->vector_status); 2722 pci_free_irq_vectors(pdev); 2723 return -ENOMEM; 2724 } 2725 2726 return 0; 2727 } 2728 2729 static void hclgevf_uninit_msi(struct hclgevf_dev *hdev) 2730 { 2731 struct pci_dev *pdev = hdev->pdev; 2732 2733 devm_kfree(&pdev->dev, hdev->vector_status); 2734 devm_kfree(&pdev->dev, hdev->vector_irq); 2735 pci_free_irq_vectors(pdev); 2736 } 2737 2738 static int hclgevf_misc_irq_init(struct hclgevf_dev *hdev) 2739 { 2740 int ret; 2741 2742 hclgevf_get_misc_vector(hdev); 2743 2744 snprintf(hdev->misc_vector.name, HNAE3_INT_NAME_LEN, "%s-misc-%s", 2745 HCLGEVF_NAME, pci_name(hdev->pdev)); 2746 ret = request_irq(hdev->misc_vector.vector_irq, hclgevf_misc_irq_handle, 2747 0, hdev->misc_vector.name, hdev); 2748 if (ret) { 2749 dev_err(&hdev->pdev->dev, "VF failed to request misc irq(%d)\n", 2750 hdev->misc_vector.vector_irq); 2751 return ret; 2752 } 2753 2754 hclgevf_clear_event_cause(hdev, 0); 2755 2756 /* enable misc. vector(vector 0) */ 2757 hclgevf_enable_vector(&hdev->misc_vector, true); 2758 2759 return ret; 2760 } 2761 2762 static void hclgevf_misc_irq_uninit(struct hclgevf_dev *hdev) 2763 { 2764 /* disable misc vector(vector 0) */ 2765 hclgevf_enable_vector(&hdev->misc_vector, false); 2766 synchronize_irq(hdev->misc_vector.vector_irq); 2767 free_irq(hdev->misc_vector.vector_irq, hdev); 2768 hclgevf_free_vector(hdev, 0); 2769 } 2770 2771 static void hclgevf_info_show(struct hclgevf_dev *hdev) 2772 { 2773 struct device *dev = &hdev->pdev->dev; 2774 2775 dev_info(dev, "VF info begin:\n"); 2776 2777 dev_info(dev, "Task queue pairs numbers: %u\n", hdev->num_tqps); 2778 dev_info(dev, "Desc num per TX queue: %u\n", hdev->num_tx_desc); 2779 dev_info(dev, "Desc num per RX queue: %u\n", hdev->num_rx_desc); 2780 dev_info(dev, "Numbers of vports: %u\n", hdev->num_alloc_vport); 2781 dev_info(dev, "HW tc map: 0x%x\n", hdev->hw_tc_map); 2782 dev_info(dev, "PF media type of this VF: %u\n", 2783 hdev->hw.mac.media_type); 2784 2785 dev_info(dev, "VF info end.\n"); 2786 } 2787 2788 static int hclgevf_init_nic_client_instance(struct hnae3_ae_dev *ae_dev, 2789 struct hnae3_client *client) 2790 { 2791 struct hclgevf_dev *hdev = ae_dev->priv; 2792 int rst_cnt = hdev->rst_stats.rst_cnt; 2793 int ret; 2794 2795 ret = client->ops->init_instance(&hdev->nic); 2796 if (ret) 2797 return ret; 2798 2799 set_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 2800 if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) || 2801 rst_cnt != hdev->rst_stats.rst_cnt) { 2802 clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 2803 2804 client->ops->uninit_instance(&hdev->nic, 0); 2805 return -EBUSY; 2806 } 2807 2808 hnae3_set_client_init_flag(client, ae_dev, 1); 2809 2810 if (netif_msg_drv(&hdev->nic)) 2811 hclgevf_info_show(hdev); 2812 2813 return 0; 2814 } 2815 2816 static int hclgevf_init_roce_client_instance(struct hnae3_ae_dev *ae_dev, 2817 struct hnae3_client *client) 2818 { 2819 struct hclgevf_dev *hdev = ae_dev->priv; 2820 int ret; 2821 2822 if (!hnae3_dev_roce_supported(hdev) || !hdev->roce_client || 2823 !hdev->nic_client) 2824 return 0; 2825 2826 ret = hclgevf_init_roce_base_info(hdev); 2827 if (ret) 2828 return ret; 2829 2830 ret = client->ops->init_instance(&hdev->roce); 2831 if (ret) 2832 return ret; 2833 2834 set_bit(HCLGEVF_STATE_ROCE_REGISTERED, &hdev->state); 2835 hnae3_set_client_init_flag(client, ae_dev, 1); 2836 2837 return 0; 2838 } 2839 2840 static int hclgevf_init_client_instance(struct hnae3_client *client, 2841 struct hnae3_ae_dev *ae_dev) 2842 { 2843 struct hclgevf_dev *hdev = ae_dev->priv; 2844 int ret; 2845 2846 switch (client->type) { 2847 case HNAE3_CLIENT_KNIC: 2848 hdev->nic_client = client; 2849 hdev->nic.client = client; 2850 2851 ret = hclgevf_init_nic_client_instance(ae_dev, client); 2852 if (ret) 2853 goto clear_nic; 2854 2855 ret = hclgevf_init_roce_client_instance(ae_dev, 2856 hdev->roce_client); 2857 if (ret) 2858 goto clear_roce; 2859 2860 break; 2861 case HNAE3_CLIENT_ROCE: 2862 if (hnae3_dev_roce_supported(hdev)) { 2863 hdev->roce_client = client; 2864 hdev->roce.client = client; 2865 } 2866 2867 ret = hclgevf_init_roce_client_instance(ae_dev, client); 2868 if (ret) 2869 goto clear_roce; 2870 2871 break; 2872 default: 2873 return -EINVAL; 2874 } 2875 2876 return 0; 2877 2878 clear_nic: 2879 hdev->nic_client = NULL; 2880 hdev->nic.client = NULL; 2881 return ret; 2882 clear_roce: 2883 hdev->roce_client = NULL; 2884 hdev->roce.client = NULL; 2885 return ret; 2886 } 2887 2888 static void hclgevf_uninit_client_instance(struct hnae3_client *client, 2889 struct hnae3_ae_dev *ae_dev) 2890 { 2891 struct hclgevf_dev *hdev = ae_dev->priv; 2892 2893 /* un-init roce, if it exists */ 2894 if (hdev->roce_client) { 2895 clear_bit(HCLGEVF_STATE_ROCE_REGISTERED, &hdev->state); 2896 hdev->roce_client->ops->uninit_instance(&hdev->roce, 0); 2897 hdev->roce_client = NULL; 2898 hdev->roce.client = NULL; 2899 } 2900 2901 /* un-init nic/unic, if this was not called by roce client */ 2902 if (client->ops->uninit_instance && hdev->nic_client && 2903 client->type != HNAE3_CLIENT_ROCE) { 2904 clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 2905 2906 client->ops->uninit_instance(&hdev->nic, 0); 2907 hdev->nic_client = NULL; 2908 hdev->nic.client = NULL; 2909 } 2910 } 2911 2912 static int hclgevf_dev_mem_map(struct hclgevf_dev *hdev) 2913 { 2914 #define HCLGEVF_MEM_BAR 4 2915 2916 struct pci_dev *pdev = hdev->pdev; 2917 struct hclgevf_hw *hw = &hdev->hw; 2918 2919 /* for device does not have device memory, return directly */ 2920 if (!(pci_select_bars(pdev, IORESOURCE_MEM) & BIT(HCLGEVF_MEM_BAR))) 2921 return 0; 2922 2923 hw->mem_base = devm_ioremap_wc(&pdev->dev, 2924 pci_resource_start(pdev, 2925 HCLGEVF_MEM_BAR), 2926 pci_resource_len(pdev, HCLGEVF_MEM_BAR)); 2927 if (!hw->mem_base) { 2928 dev_err(&pdev->dev, "failed to map device memory\n"); 2929 return -EFAULT; 2930 } 2931 2932 return 0; 2933 } 2934 2935 static int hclgevf_pci_init(struct hclgevf_dev *hdev) 2936 { 2937 struct pci_dev *pdev = hdev->pdev; 2938 struct hclgevf_hw *hw; 2939 int ret; 2940 2941 ret = pci_enable_device(pdev); 2942 if (ret) { 2943 dev_err(&pdev->dev, "failed to enable PCI device\n"); 2944 return ret; 2945 } 2946 2947 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 2948 if (ret) { 2949 dev_err(&pdev->dev, "can't set consistent PCI DMA, exiting"); 2950 goto err_disable_device; 2951 } 2952 2953 ret = pci_request_regions(pdev, HCLGEVF_DRIVER_NAME); 2954 if (ret) { 2955 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 2956 goto err_disable_device; 2957 } 2958 2959 pci_set_master(pdev); 2960 hw = &hdev->hw; 2961 hw->hdev = hdev; 2962 hw->io_base = pci_iomap(pdev, 2, 0); 2963 if (!hw->io_base) { 2964 dev_err(&pdev->dev, "can't map configuration register space\n"); 2965 ret = -ENOMEM; 2966 goto err_clr_master; 2967 } 2968 2969 ret = hclgevf_dev_mem_map(hdev); 2970 if (ret) 2971 goto err_unmap_io_base; 2972 2973 return 0; 2974 2975 err_unmap_io_base: 2976 pci_iounmap(pdev, hdev->hw.io_base); 2977 err_clr_master: 2978 pci_clear_master(pdev); 2979 pci_release_regions(pdev); 2980 err_disable_device: 2981 pci_disable_device(pdev); 2982 2983 return ret; 2984 } 2985 2986 static void hclgevf_pci_uninit(struct hclgevf_dev *hdev) 2987 { 2988 struct pci_dev *pdev = hdev->pdev; 2989 2990 if (hdev->hw.mem_base) 2991 devm_iounmap(&pdev->dev, hdev->hw.mem_base); 2992 2993 pci_iounmap(pdev, hdev->hw.io_base); 2994 pci_clear_master(pdev); 2995 pci_release_regions(pdev); 2996 pci_disable_device(pdev); 2997 } 2998 2999 static int hclgevf_query_vf_resource(struct hclgevf_dev *hdev) 3000 { 3001 struct hclgevf_query_res_cmd *req; 3002 struct hclgevf_desc desc; 3003 int ret; 3004 3005 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_VF_RSRC, true); 3006 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 3007 if (ret) { 3008 dev_err(&hdev->pdev->dev, 3009 "query vf resource failed, ret = %d.\n", ret); 3010 return ret; 3011 } 3012 3013 req = (struct hclgevf_query_res_cmd *)desc.data; 3014 3015 if (hnae3_dev_roce_supported(hdev)) { 3016 hdev->roce_base_msix_offset = 3017 hnae3_get_field(le16_to_cpu(req->msixcap_localid_ba_rocee), 3018 HCLGEVF_MSIX_OFT_ROCEE_M, 3019 HCLGEVF_MSIX_OFT_ROCEE_S); 3020 hdev->num_roce_msix = 3021 hnae3_get_field(le16_to_cpu(req->vf_intr_vector_number), 3022 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 3023 3024 /* nic's msix numbers is always equals to the roce's. */ 3025 hdev->num_nic_msix = hdev->num_roce_msix; 3026 3027 /* VF should have NIC vectors and Roce vectors, NIC vectors 3028 * are queued before Roce vectors. The offset is fixed to 64. 3029 */ 3030 hdev->num_msi = hdev->num_roce_msix + 3031 hdev->roce_base_msix_offset; 3032 } else { 3033 hdev->num_msi = 3034 hnae3_get_field(le16_to_cpu(req->vf_intr_vector_number), 3035 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 3036 3037 hdev->num_nic_msix = hdev->num_msi; 3038 } 3039 3040 if (hdev->num_nic_msix < HNAE3_MIN_VECTOR_NUM) { 3041 dev_err(&hdev->pdev->dev, 3042 "Just %u msi resources, not enough for vf(min:2).\n", 3043 hdev->num_nic_msix); 3044 return -EINVAL; 3045 } 3046 3047 return 0; 3048 } 3049 3050 static void hclgevf_set_default_dev_specs(struct hclgevf_dev *hdev) 3051 { 3052 #define HCLGEVF_MAX_NON_TSO_BD_NUM 8U 3053 3054 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 3055 3056 ae_dev->dev_specs.max_non_tso_bd_num = 3057 HCLGEVF_MAX_NON_TSO_BD_NUM; 3058 ae_dev->dev_specs.rss_ind_tbl_size = HCLGEVF_RSS_IND_TBL_SIZE; 3059 ae_dev->dev_specs.rss_key_size = HCLGEVF_RSS_KEY_SIZE; 3060 ae_dev->dev_specs.max_int_gl = HCLGEVF_DEF_MAX_INT_GL; 3061 } 3062 3063 static void hclgevf_parse_dev_specs(struct hclgevf_dev *hdev, 3064 struct hclgevf_desc *desc) 3065 { 3066 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 3067 struct hclgevf_dev_specs_0_cmd *req0; 3068 struct hclgevf_dev_specs_1_cmd *req1; 3069 3070 req0 = (struct hclgevf_dev_specs_0_cmd *)desc[0].data; 3071 req1 = (struct hclgevf_dev_specs_1_cmd *)desc[1].data; 3072 3073 ae_dev->dev_specs.max_non_tso_bd_num = req0->max_non_tso_bd_num; 3074 ae_dev->dev_specs.rss_ind_tbl_size = 3075 le16_to_cpu(req0->rss_ind_tbl_size); 3076 ae_dev->dev_specs.int_ql_max = le16_to_cpu(req0->int_ql_max); 3077 ae_dev->dev_specs.rss_key_size = le16_to_cpu(req0->rss_key_size); 3078 ae_dev->dev_specs.max_int_gl = le16_to_cpu(req1->max_int_gl); 3079 } 3080 3081 static void hclgevf_check_dev_specs(struct hclgevf_dev *hdev) 3082 { 3083 struct hnae3_dev_specs *dev_specs = &hdev->ae_dev->dev_specs; 3084 3085 if (!dev_specs->max_non_tso_bd_num) 3086 dev_specs->max_non_tso_bd_num = HCLGEVF_MAX_NON_TSO_BD_NUM; 3087 if (!dev_specs->rss_ind_tbl_size) 3088 dev_specs->rss_ind_tbl_size = HCLGEVF_RSS_IND_TBL_SIZE; 3089 if (!dev_specs->rss_key_size) 3090 dev_specs->rss_key_size = HCLGEVF_RSS_KEY_SIZE; 3091 if (!dev_specs->max_int_gl) 3092 dev_specs->max_int_gl = HCLGEVF_DEF_MAX_INT_GL; 3093 } 3094 3095 static int hclgevf_query_dev_specs(struct hclgevf_dev *hdev) 3096 { 3097 struct hclgevf_desc desc[HCLGEVF_QUERY_DEV_SPECS_BD_NUM]; 3098 int ret; 3099 int i; 3100 3101 /* set default specifications as devices lower than version V3 do not 3102 * support querying specifications from firmware. 3103 */ 3104 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3) { 3105 hclgevf_set_default_dev_specs(hdev); 3106 return 0; 3107 } 3108 3109 for (i = 0; i < HCLGEVF_QUERY_DEV_SPECS_BD_NUM - 1; i++) { 3110 hclgevf_cmd_setup_basic_desc(&desc[i], 3111 HCLGEVF_OPC_QUERY_DEV_SPECS, true); 3112 desc[i].flag |= cpu_to_le16(HCLGEVF_CMD_FLAG_NEXT); 3113 } 3114 hclgevf_cmd_setup_basic_desc(&desc[i], HCLGEVF_OPC_QUERY_DEV_SPECS, 3115 true); 3116 3117 ret = hclgevf_cmd_send(&hdev->hw, desc, HCLGEVF_QUERY_DEV_SPECS_BD_NUM); 3118 if (ret) 3119 return ret; 3120 3121 hclgevf_parse_dev_specs(hdev, desc); 3122 hclgevf_check_dev_specs(hdev); 3123 3124 return 0; 3125 } 3126 3127 static int hclgevf_pci_reset(struct hclgevf_dev *hdev) 3128 { 3129 struct pci_dev *pdev = hdev->pdev; 3130 int ret = 0; 3131 3132 if (hdev->reset_type == HNAE3_VF_FULL_RESET && 3133 test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 3134 hclgevf_misc_irq_uninit(hdev); 3135 hclgevf_uninit_msi(hdev); 3136 clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 3137 } 3138 3139 if (!test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 3140 pci_set_master(pdev); 3141 ret = hclgevf_init_msi(hdev); 3142 if (ret) { 3143 dev_err(&pdev->dev, 3144 "failed(%d) to init MSI/MSI-X\n", ret); 3145 return ret; 3146 } 3147 3148 ret = hclgevf_misc_irq_init(hdev); 3149 if (ret) { 3150 hclgevf_uninit_msi(hdev); 3151 dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 3152 ret); 3153 return ret; 3154 } 3155 3156 set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 3157 } 3158 3159 return ret; 3160 } 3161 3162 static int hclgevf_clear_vport_list(struct hclgevf_dev *hdev) 3163 { 3164 struct hclge_vf_to_pf_msg send_msg; 3165 3166 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_HANDLE_VF_TBL, 3167 HCLGE_MBX_VPORT_LIST_CLEAR); 3168 return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 3169 } 3170 3171 static int hclgevf_reset_hdev(struct hclgevf_dev *hdev) 3172 { 3173 struct pci_dev *pdev = hdev->pdev; 3174 int ret; 3175 3176 ret = hclgevf_pci_reset(hdev); 3177 if (ret) { 3178 dev_err(&pdev->dev, "pci reset failed %d\n", ret); 3179 return ret; 3180 } 3181 3182 ret = hclgevf_cmd_init(hdev); 3183 if (ret) { 3184 dev_err(&pdev->dev, "cmd failed %d\n", ret); 3185 return ret; 3186 } 3187 3188 ret = hclgevf_rss_init_hw(hdev); 3189 if (ret) { 3190 dev_err(&hdev->pdev->dev, 3191 "failed(%d) to initialize RSS\n", ret); 3192 return ret; 3193 } 3194 3195 ret = hclgevf_config_gro(hdev, true); 3196 if (ret) 3197 return ret; 3198 3199 ret = hclgevf_init_vlan_config(hdev); 3200 if (ret) { 3201 dev_err(&hdev->pdev->dev, 3202 "failed(%d) to initialize VLAN config\n", ret); 3203 return ret; 3204 } 3205 3206 set_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state); 3207 3208 dev_info(&hdev->pdev->dev, "Reset done\n"); 3209 3210 return 0; 3211 } 3212 3213 static int hclgevf_init_hdev(struct hclgevf_dev *hdev) 3214 { 3215 struct pci_dev *pdev = hdev->pdev; 3216 int ret; 3217 3218 ret = hclgevf_pci_init(hdev); 3219 if (ret) 3220 return ret; 3221 3222 ret = hclgevf_cmd_queue_init(hdev); 3223 if (ret) 3224 goto err_cmd_queue_init; 3225 3226 ret = hclgevf_cmd_init(hdev); 3227 if (ret) 3228 goto err_cmd_init; 3229 3230 /* Get vf resource */ 3231 ret = hclgevf_query_vf_resource(hdev); 3232 if (ret) 3233 goto err_cmd_init; 3234 3235 ret = hclgevf_query_dev_specs(hdev); 3236 if (ret) { 3237 dev_err(&pdev->dev, 3238 "failed to query dev specifications, ret = %d\n", ret); 3239 goto err_cmd_init; 3240 } 3241 3242 ret = hclgevf_init_msi(hdev); 3243 if (ret) { 3244 dev_err(&pdev->dev, "failed(%d) to init MSI/MSI-X\n", ret); 3245 goto err_cmd_init; 3246 } 3247 3248 hclgevf_state_init(hdev); 3249 hdev->reset_level = HNAE3_VF_FUNC_RESET; 3250 hdev->reset_type = HNAE3_NONE_RESET; 3251 3252 ret = hclgevf_misc_irq_init(hdev); 3253 if (ret) 3254 goto err_misc_irq_init; 3255 3256 set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 3257 3258 ret = hclgevf_configure(hdev); 3259 if (ret) { 3260 dev_err(&pdev->dev, "failed(%d) to fetch configuration\n", ret); 3261 goto err_config; 3262 } 3263 3264 ret = hclgevf_alloc_tqps(hdev); 3265 if (ret) { 3266 dev_err(&pdev->dev, "failed(%d) to allocate TQPs\n", ret); 3267 goto err_config; 3268 } 3269 3270 ret = hclgevf_set_handle_info(hdev); 3271 if (ret) 3272 goto err_config; 3273 3274 ret = hclgevf_config_gro(hdev, true); 3275 if (ret) 3276 goto err_config; 3277 3278 /* Initialize RSS for this VF */ 3279 ret = hclgevf_rss_init_cfg(hdev); 3280 if (ret) { 3281 dev_err(&pdev->dev, "failed to init rss cfg, ret = %d\n", ret); 3282 goto err_config; 3283 } 3284 3285 ret = hclgevf_rss_init_hw(hdev); 3286 if (ret) { 3287 dev_err(&hdev->pdev->dev, 3288 "failed(%d) to initialize RSS\n", ret); 3289 goto err_config; 3290 } 3291 3292 /* ensure vf tbl list as empty before init*/ 3293 ret = hclgevf_clear_vport_list(hdev); 3294 if (ret) { 3295 dev_err(&pdev->dev, 3296 "failed to clear tbl list configuration, ret = %d.\n", 3297 ret); 3298 goto err_config; 3299 } 3300 3301 ret = hclgevf_init_vlan_config(hdev); 3302 if (ret) { 3303 dev_err(&hdev->pdev->dev, 3304 "failed(%d) to initialize VLAN config\n", ret); 3305 goto err_config; 3306 } 3307 3308 hdev->last_reset_time = jiffies; 3309 dev_info(&hdev->pdev->dev, "finished initializing %s driver\n", 3310 HCLGEVF_DRIVER_NAME); 3311 3312 hclgevf_task_schedule(hdev, round_jiffies_relative(HZ)); 3313 3314 return 0; 3315 3316 err_config: 3317 hclgevf_misc_irq_uninit(hdev); 3318 err_misc_irq_init: 3319 hclgevf_state_uninit(hdev); 3320 hclgevf_uninit_msi(hdev); 3321 err_cmd_init: 3322 hclgevf_cmd_uninit(hdev); 3323 err_cmd_queue_init: 3324 hclgevf_pci_uninit(hdev); 3325 clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 3326 return ret; 3327 } 3328 3329 static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev) 3330 { 3331 struct hclge_vf_to_pf_msg send_msg; 3332 3333 hclgevf_state_uninit(hdev); 3334 3335 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_VF_UNINIT, 0); 3336 hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 3337 3338 if (test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 3339 hclgevf_misc_irq_uninit(hdev); 3340 hclgevf_uninit_msi(hdev); 3341 } 3342 3343 hclgevf_cmd_uninit(hdev); 3344 hclgevf_pci_uninit(hdev); 3345 hclgevf_uninit_mac_list(hdev); 3346 } 3347 3348 static int hclgevf_init_ae_dev(struct hnae3_ae_dev *ae_dev) 3349 { 3350 struct pci_dev *pdev = ae_dev->pdev; 3351 int ret; 3352 3353 ret = hclgevf_alloc_hdev(ae_dev); 3354 if (ret) { 3355 dev_err(&pdev->dev, "hclge device allocation failed\n"); 3356 return ret; 3357 } 3358 3359 ret = hclgevf_init_hdev(ae_dev->priv); 3360 if (ret) { 3361 dev_err(&pdev->dev, "hclge device initialization failed\n"); 3362 return ret; 3363 } 3364 3365 return 0; 3366 } 3367 3368 static void hclgevf_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 3369 { 3370 struct hclgevf_dev *hdev = ae_dev->priv; 3371 3372 hclgevf_uninit_hdev(hdev); 3373 ae_dev->priv = NULL; 3374 } 3375 3376 static u32 hclgevf_get_max_channels(struct hclgevf_dev *hdev) 3377 { 3378 struct hnae3_handle *nic = &hdev->nic; 3379 struct hnae3_knic_private_info *kinfo = &nic->kinfo; 3380 3381 return min_t(u32, hdev->rss_size_max, 3382 hdev->num_tqps / kinfo->tc_info.num_tc); 3383 } 3384 3385 /** 3386 * hclgevf_get_channels - Get the current channels enabled and max supported. 3387 * @handle: hardware information for network interface 3388 * @ch: ethtool channels structure 3389 * 3390 * We don't support separate tx and rx queues as channels. The other count 3391 * represents how many queues are being used for control. max_combined counts 3392 * how many queue pairs we can support. They may not be mapped 1 to 1 with 3393 * q_vectors since we support a lot more queue pairs than q_vectors. 3394 **/ 3395 static void hclgevf_get_channels(struct hnae3_handle *handle, 3396 struct ethtool_channels *ch) 3397 { 3398 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3399 3400 ch->max_combined = hclgevf_get_max_channels(hdev); 3401 ch->other_count = 0; 3402 ch->max_other = 0; 3403 ch->combined_count = handle->kinfo.rss_size; 3404 } 3405 3406 static void hclgevf_get_tqps_and_rss_info(struct hnae3_handle *handle, 3407 u16 *alloc_tqps, u16 *max_rss_size) 3408 { 3409 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3410 3411 *alloc_tqps = hdev->num_tqps; 3412 *max_rss_size = hdev->rss_size_max; 3413 } 3414 3415 static void hclgevf_update_rss_size(struct hnae3_handle *handle, 3416 u32 new_tqps_num) 3417 { 3418 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 3419 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3420 u16 max_rss_size; 3421 3422 kinfo->req_rss_size = new_tqps_num; 3423 3424 max_rss_size = min_t(u16, hdev->rss_size_max, 3425 hdev->num_tqps / kinfo->tc_info.num_tc); 3426 3427 /* Use the user's configuration when it is not larger than 3428 * max_rss_size, otherwise, use the maximum specification value. 3429 */ 3430 if (kinfo->req_rss_size != kinfo->rss_size && kinfo->req_rss_size && 3431 kinfo->req_rss_size <= max_rss_size) 3432 kinfo->rss_size = kinfo->req_rss_size; 3433 else if (kinfo->rss_size > max_rss_size || 3434 (!kinfo->req_rss_size && kinfo->rss_size < max_rss_size)) 3435 kinfo->rss_size = max_rss_size; 3436 3437 kinfo->num_tqps = kinfo->tc_info.num_tc * kinfo->rss_size; 3438 } 3439 3440 static int hclgevf_set_channels(struct hnae3_handle *handle, u32 new_tqps_num, 3441 bool rxfh_configured) 3442 { 3443 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3444 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 3445 u16 cur_rss_size = kinfo->rss_size; 3446 u16 cur_tqps = kinfo->num_tqps; 3447 u32 *rss_indir; 3448 unsigned int i; 3449 int ret; 3450 3451 hclgevf_update_rss_size(handle, new_tqps_num); 3452 3453 ret = hclgevf_set_rss_tc_mode(hdev, kinfo->rss_size); 3454 if (ret) 3455 return ret; 3456 3457 /* RSS indirection table has been configuared by user */ 3458 if (rxfh_configured) 3459 goto out; 3460 3461 /* Reinitializes the rss indirect table according to the new RSS size */ 3462 rss_indir = kcalloc(hdev->ae_dev->dev_specs.rss_ind_tbl_size, 3463 sizeof(u32), GFP_KERNEL); 3464 if (!rss_indir) 3465 return -ENOMEM; 3466 3467 for (i = 0; i < hdev->ae_dev->dev_specs.rss_ind_tbl_size; i++) 3468 rss_indir[i] = i % kinfo->rss_size; 3469 3470 hdev->rss_cfg.rss_size = kinfo->rss_size; 3471 3472 ret = hclgevf_set_rss(handle, rss_indir, NULL, 0); 3473 if (ret) 3474 dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n", 3475 ret); 3476 3477 kfree(rss_indir); 3478 3479 out: 3480 if (!ret) 3481 dev_info(&hdev->pdev->dev, 3482 "Channels changed, rss_size from %u to %u, tqps from %u to %u", 3483 cur_rss_size, kinfo->rss_size, 3484 cur_tqps, kinfo->rss_size * kinfo->tc_info.num_tc); 3485 3486 return ret; 3487 } 3488 3489 static int hclgevf_get_status(struct hnae3_handle *handle) 3490 { 3491 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3492 3493 return hdev->hw.mac.link; 3494 } 3495 3496 static void hclgevf_get_ksettings_an_result(struct hnae3_handle *handle, 3497 u8 *auto_neg, u32 *speed, 3498 u8 *duplex) 3499 { 3500 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3501 3502 if (speed) 3503 *speed = hdev->hw.mac.speed; 3504 if (duplex) 3505 *duplex = hdev->hw.mac.duplex; 3506 if (auto_neg) 3507 *auto_neg = AUTONEG_DISABLE; 3508 } 3509 3510 void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed, 3511 u8 duplex) 3512 { 3513 hdev->hw.mac.speed = speed; 3514 hdev->hw.mac.duplex = duplex; 3515 } 3516 3517 static int hclgevf_gro_en(struct hnae3_handle *handle, bool enable) 3518 { 3519 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3520 3521 return hclgevf_config_gro(hdev, enable); 3522 } 3523 3524 static void hclgevf_get_media_type(struct hnae3_handle *handle, u8 *media_type, 3525 u8 *module_type) 3526 { 3527 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3528 3529 if (media_type) 3530 *media_type = hdev->hw.mac.media_type; 3531 3532 if (module_type) 3533 *module_type = hdev->hw.mac.module_type; 3534 } 3535 3536 static bool hclgevf_get_hw_reset_stat(struct hnae3_handle *handle) 3537 { 3538 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3539 3540 return !!hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 3541 } 3542 3543 static bool hclgevf_get_cmdq_stat(struct hnae3_handle *handle) 3544 { 3545 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3546 3547 return test_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 3548 } 3549 3550 static bool hclgevf_ae_dev_resetting(struct hnae3_handle *handle) 3551 { 3552 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3553 3554 return test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 3555 } 3556 3557 static unsigned long hclgevf_ae_dev_reset_cnt(struct hnae3_handle *handle) 3558 { 3559 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3560 3561 return hdev->rst_stats.hw_rst_done_cnt; 3562 } 3563 3564 static void hclgevf_get_link_mode(struct hnae3_handle *handle, 3565 unsigned long *supported, 3566 unsigned long *advertising) 3567 { 3568 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3569 3570 *supported = hdev->hw.mac.supported; 3571 *advertising = hdev->hw.mac.advertising; 3572 } 3573 3574 #define MAX_SEPARATE_NUM 4 3575 #define SEPARATOR_VALUE 0xFFFFFFFF 3576 #define REG_NUM_PER_LINE 4 3577 #define REG_LEN_PER_LINE (REG_NUM_PER_LINE * sizeof(u32)) 3578 3579 static int hclgevf_get_regs_len(struct hnae3_handle *handle) 3580 { 3581 int cmdq_lines, common_lines, ring_lines, tqp_intr_lines; 3582 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3583 3584 cmdq_lines = sizeof(cmdq_reg_addr_list) / REG_LEN_PER_LINE + 1; 3585 common_lines = sizeof(common_reg_addr_list) / REG_LEN_PER_LINE + 1; 3586 ring_lines = sizeof(ring_reg_addr_list) / REG_LEN_PER_LINE + 1; 3587 tqp_intr_lines = sizeof(tqp_intr_reg_addr_list) / REG_LEN_PER_LINE + 1; 3588 3589 return (cmdq_lines + common_lines + ring_lines * hdev->num_tqps + 3590 tqp_intr_lines * (hdev->num_msi_used - 1)) * REG_LEN_PER_LINE; 3591 } 3592 3593 static void hclgevf_get_regs(struct hnae3_handle *handle, u32 *version, 3594 void *data) 3595 { 3596 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3597 int i, j, reg_um, separator_num; 3598 u32 *reg = data; 3599 3600 *version = hdev->fw_version; 3601 3602 /* fetching per-VF registers values from VF PCIe register space */ 3603 reg_um = sizeof(cmdq_reg_addr_list) / sizeof(u32); 3604 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 3605 for (i = 0; i < reg_um; i++) 3606 *reg++ = hclgevf_read_dev(&hdev->hw, cmdq_reg_addr_list[i]); 3607 for (i = 0; i < separator_num; i++) 3608 *reg++ = SEPARATOR_VALUE; 3609 3610 reg_um = sizeof(common_reg_addr_list) / sizeof(u32); 3611 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 3612 for (i = 0; i < reg_um; i++) 3613 *reg++ = hclgevf_read_dev(&hdev->hw, common_reg_addr_list[i]); 3614 for (i = 0; i < separator_num; i++) 3615 *reg++ = SEPARATOR_VALUE; 3616 3617 reg_um = sizeof(ring_reg_addr_list) / sizeof(u32); 3618 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 3619 for (j = 0; j < hdev->num_tqps; j++) { 3620 for (i = 0; i < reg_um; i++) 3621 *reg++ = hclgevf_read_dev(&hdev->hw, 3622 ring_reg_addr_list[i] + 3623 0x200 * j); 3624 for (i = 0; i < separator_num; i++) 3625 *reg++ = SEPARATOR_VALUE; 3626 } 3627 3628 reg_um = sizeof(tqp_intr_reg_addr_list) / sizeof(u32); 3629 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 3630 for (j = 0; j < hdev->num_msi_used - 1; j++) { 3631 for (i = 0; i < reg_um; i++) 3632 *reg++ = hclgevf_read_dev(&hdev->hw, 3633 tqp_intr_reg_addr_list[i] + 3634 4 * j); 3635 for (i = 0; i < separator_num; i++) 3636 *reg++ = SEPARATOR_VALUE; 3637 } 3638 } 3639 3640 void hclgevf_update_port_base_vlan_info(struct hclgevf_dev *hdev, u16 state, 3641 u8 *port_base_vlan_info, u8 data_size) 3642 { 3643 struct hnae3_handle *nic = &hdev->nic; 3644 struct hclge_vf_to_pf_msg send_msg; 3645 int ret; 3646 3647 rtnl_lock(); 3648 3649 if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) || 3650 test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) { 3651 dev_warn(&hdev->pdev->dev, 3652 "is resetting when updating port based vlan info\n"); 3653 rtnl_unlock(); 3654 return; 3655 } 3656 3657 ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 3658 if (ret) { 3659 rtnl_unlock(); 3660 return; 3661 } 3662 3663 /* send msg to PF and wait update port based vlan info */ 3664 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 3665 HCLGE_MBX_PORT_BASE_VLAN_CFG); 3666 memcpy(send_msg.data, port_base_vlan_info, data_size); 3667 ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 3668 if (!ret) { 3669 if (state == HNAE3_PORT_BASE_VLAN_DISABLE) 3670 nic->port_base_vlan_state = state; 3671 else 3672 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_ENABLE; 3673 } 3674 3675 hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 3676 rtnl_unlock(); 3677 } 3678 3679 static const struct hnae3_ae_ops hclgevf_ops = { 3680 .init_ae_dev = hclgevf_init_ae_dev, 3681 .uninit_ae_dev = hclgevf_uninit_ae_dev, 3682 .flr_prepare = hclgevf_flr_prepare, 3683 .flr_done = hclgevf_flr_done, 3684 .init_client_instance = hclgevf_init_client_instance, 3685 .uninit_client_instance = hclgevf_uninit_client_instance, 3686 .start = hclgevf_ae_start, 3687 .stop = hclgevf_ae_stop, 3688 .client_start = hclgevf_client_start, 3689 .client_stop = hclgevf_client_stop, 3690 .map_ring_to_vector = hclgevf_map_ring_to_vector, 3691 .unmap_ring_from_vector = hclgevf_unmap_ring_from_vector, 3692 .get_vector = hclgevf_get_vector, 3693 .put_vector = hclgevf_put_vector, 3694 .reset_queue = hclgevf_reset_tqp, 3695 .get_mac_addr = hclgevf_get_mac_addr, 3696 .set_mac_addr = hclgevf_set_mac_addr, 3697 .add_uc_addr = hclgevf_add_uc_addr, 3698 .rm_uc_addr = hclgevf_rm_uc_addr, 3699 .add_mc_addr = hclgevf_add_mc_addr, 3700 .rm_mc_addr = hclgevf_rm_mc_addr, 3701 .get_stats = hclgevf_get_stats, 3702 .update_stats = hclgevf_update_stats, 3703 .get_strings = hclgevf_get_strings, 3704 .get_sset_count = hclgevf_get_sset_count, 3705 .get_rss_key_size = hclgevf_get_rss_key_size, 3706 .get_rss = hclgevf_get_rss, 3707 .set_rss = hclgevf_set_rss, 3708 .get_rss_tuple = hclgevf_get_rss_tuple, 3709 .set_rss_tuple = hclgevf_set_rss_tuple, 3710 .get_tc_size = hclgevf_get_tc_size, 3711 .get_fw_version = hclgevf_get_fw_version, 3712 .set_vlan_filter = hclgevf_set_vlan_filter, 3713 .enable_hw_strip_rxvtag = hclgevf_en_hw_strip_rxvtag, 3714 .reset_event = hclgevf_reset_event, 3715 .set_default_reset_request = hclgevf_set_def_reset_request, 3716 .set_channels = hclgevf_set_channels, 3717 .get_channels = hclgevf_get_channels, 3718 .get_tqps_and_rss_info = hclgevf_get_tqps_and_rss_info, 3719 .get_regs_len = hclgevf_get_regs_len, 3720 .get_regs = hclgevf_get_regs, 3721 .get_status = hclgevf_get_status, 3722 .get_ksettings_an_result = hclgevf_get_ksettings_an_result, 3723 .get_media_type = hclgevf_get_media_type, 3724 .get_hw_reset_stat = hclgevf_get_hw_reset_stat, 3725 .ae_dev_resetting = hclgevf_ae_dev_resetting, 3726 .ae_dev_reset_cnt = hclgevf_ae_dev_reset_cnt, 3727 .set_gro_en = hclgevf_gro_en, 3728 .set_mtu = hclgevf_set_mtu, 3729 .get_global_queue_id = hclgevf_get_qid_global, 3730 .set_timer_task = hclgevf_set_timer_task, 3731 .get_link_mode = hclgevf_get_link_mode, 3732 .set_promisc_mode = hclgevf_set_promisc_mode, 3733 .request_update_promisc_mode = hclgevf_request_update_promisc_mode, 3734 .get_cmdq_stat = hclgevf_get_cmdq_stat, 3735 }; 3736 3737 static struct hnae3_ae_algo ae_algovf = { 3738 .ops = &hclgevf_ops, 3739 .pdev_id_table = ae_algovf_pci_tbl, 3740 }; 3741 3742 static int hclgevf_init(void) 3743 { 3744 pr_info("%s is initializing\n", HCLGEVF_NAME); 3745 3746 hclgevf_wq = alloc_workqueue("%s", 0, 0, HCLGEVF_NAME); 3747 if (!hclgevf_wq) { 3748 pr_err("%s: failed to create workqueue\n", HCLGEVF_NAME); 3749 return -ENOMEM; 3750 } 3751 3752 hnae3_register_ae_algo(&ae_algovf); 3753 3754 return 0; 3755 } 3756 3757 static void hclgevf_exit(void) 3758 { 3759 hnae3_unregister_ae_algo(&ae_algovf); 3760 destroy_workqueue(hclgevf_wq); 3761 } 3762 module_init(hclgevf_init); 3763 module_exit(hclgevf_exit); 3764 3765 MODULE_LICENSE("GPL"); 3766 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 3767 MODULE_DESCRIPTION("HCLGEVF Driver"); 3768 MODULE_VERSION(HCLGEVF_MOD_VERSION); 3769