1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/etherdevice.h> 5 #include <linux/iopoll.h> 6 #include <net/rtnetlink.h> 7 #include "hclgevf_cmd.h" 8 #include "hclgevf_main.h" 9 #include "hclge_mbx.h" 10 #include "hnae3.h" 11 12 #define HCLGEVF_NAME "hclgevf" 13 14 #define HCLGEVF_RESET_MAX_FAIL_CNT 5 15 16 static int hclgevf_reset_hdev(struct hclgevf_dev *hdev); 17 static void hclgevf_task_schedule(struct hclgevf_dev *hdev, 18 unsigned long delay); 19 20 static struct hnae3_ae_algo ae_algovf; 21 22 static struct workqueue_struct *hclgevf_wq; 23 24 static const struct pci_device_id ae_algovf_pci_tbl[] = { 25 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_VF), 0}, 26 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF), 27 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 28 /* required last entry */ 29 {0, } 30 }; 31 32 static const u8 hclgevf_hash_key[] = { 33 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2, 34 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0, 35 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4, 36 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C, 37 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA 38 }; 39 40 MODULE_DEVICE_TABLE(pci, ae_algovf_pci_tbl); 41 42 static const u32 cmdq_reg_addr_list[] = {HCLGEVF_CMDQ_TX_ADDR_L_REG, 43 HCLGEVF_CMDQ_TX_ADDR_H_REG, 44 HCLGEVF_CMDQ_TX_DEPTH_REG, 45 HCLGEVF_CMDQ_TX_TAIL_REG, 46 HCLGEVF_CMDQ_TX_HEAD_REG, 47 HCLGEVF_CMDQ_RX_ADDR_L_REG, 48 HCLGEVF_CMDQ_RX_ADDR_H_REG, 49 HCLGEVF_CMDQ_RX_DEPTH_REG, 50 HCLGEVF_CMDQ_RX_TAIL_REG, 51 HCLGEVF_CMDQ_RX_HEAD_REG, 52 HCLGEVF_VECTOR0_CMDQ_SRC_REG, 53 HCLGEVF_VECTOR0_CMDQ_STATE_REG, 54 HCLGEVF_CMDQ_INTR_EN_REG, 55 HCLGEVF_CMDQ_INTR_GEN_REG}; 56 57 static const u32 common_reg_addr_list[] = {HCLGEVF_MISC_VECTOR_REG_BASE, 58 HCLGEVF_RST_ING, 59 HCLGEVF_GRO_EN_REG}; 60 61 static const u32 ring_reg_addr_list[] = {HCLGEVF_RING_RX_ADDR_L_REG, 62 HCLGEVF_RING_RX_ADDR_H_REG, 63 HCLGEVF_RING_RX_BD_NUM_REG, 64 HCLGEVF_RING_RX_BD_LENGTH_REG, 65 HCLGEVF_RING_RX_MERGE_EN_REG, 66 HCLGEVF_RING_RX_TAIL_REG, 67 HCLGEVF_RING_RX_HEAD_REG, 68 HCLGEVF_RING_RX_FBD_NUM_REG, 69 HCLGEVF_RING_RX_OFFSET_REG, 70 HCLGEVF_RING_RX_FBD_OFFSET_REG, 71 HCLGEVF_RING_RX_STASH_REG, 72 HCLGEVF_RING_RX_BD_ERR_REG, 73 HCLGEVF_RING_TX_ADDR_L_REG, 74 HCLGEVF_RING_TX_ADDR_H_REG, 75 HCLGEVF_RING_TX_BD_NUM_REG, 76 HCLGEVF_RING_TX_PRIORITY_REG, 77 HCLGEVF_RING_TX_TC_REG, 78 HCLGEVF_RING_TX_MERGE_EN_REG, 79 HCLGEVF_RING_TX_TAIL_REG, 80 HCLGEVF_RING_TX_HEAD_REG, 81 HCLGEVF_RING_TX_FBD_NUM_REG, 82 HCLGEVF_RING_TX_OFFSET_REG, 83 HCLGEVF_RING_TX_EBD_NUM_REG, 84 HCLGEVF_RING_TX_EBD_OFFSET_REG, 85 HCLGEVF_RING_TX_BD_ERR_REG, 86 HCLGEVF_RING_EN_REG}; 87 88 static const u32 tqp_intr_reg_addr_list[] = {HCLGEVF_TQP_INTR_CTRL_REG, 89 HCLGEVF_TQP_INTR_GL0_REG, 90 HCLGEVF_TQP_INTR_GL1_REG, 91 HCLGEVF_TQP_INTR_GL2_REG, 92 HCLGEVF_TQP_INTR_RL_REG}; 93 94 static struct hclgevf_dev *hclgevf_ae_get_hdev(struct hnae3_handle *handle) 95 { 96 if (!handle->client) 97 return container_of(handle, struct hclgevf_dev, nic); 98 else if (handle->client->type == HNAE3_CLIENT_ROCE) 99 return container_of(handle, struct hclgevf_dev, roce); 100 else 101 return container_of(handle, struct hclgevf_dev, nic); 102 } 103 104 static int hclgevf_tqps_update_stats(struct hnae3_handle *handle) 105 { 106 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 107 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 108 struct hclgevf_desc desc; 109 struct hclgevf_tqp *tqp; 110 int status; 111 int i; 112 113 for (i = 0; i < kinfo->num_tqps; i++) { 114 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 115 hclgevf_cmd_setup_basic_desc(&desc, 116 HCLGEVF_OPC_QUERY_RX_STATUS, 117 true); 118 119 desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 120 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 121 if (status) { 122 dev_err(&hdev->pdev->dev, 123 "Query tqp stat fail, status = %d,queue = %d\n", 124 status, i); 125 return status; 126 } 127 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd += 128 le32_to_cpu(desc.data[1]); 129 130 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_TX_STATUS, 131 true); 132 133 desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 134 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 135 if (status) { 136 dev_err(&hdev->pdev->dev, 137 "Query tqp stat fail, status = %d,queue = %d\n", 138 status, i); 139 return status; 140 } 141 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd += 142 le32_to_cpu(desc.data[1]); 143 } 144 145 return 0; 146 } 147 148 static u64 *hclgevf_tqps_get_stats(struct hnae3_handle *handle, u64 *data) 149 { 150 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 151 struct hclgevf_tqp *tqp; 152 u64 *buff = data; 153 int i; 154 155 for (i = 0; i < kinfo->num_tqps; i++) { 156 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 157 *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd; 158 } 159 for (i = 0; i < kinfo->num_tqps; i++) { 160 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 161 *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd; 162 } 163 164 return buff; 165 } 166 167 static int hclgevf_tqps_get_sset_count(struct hnae3_handle *handle, int strset) 168 { 169 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 170 171 return kinfo->num_tqps * 2; 172 } 173 174 static u8 *hclgevf_tqps_get_strings(struct hnae3_handle *handle, u8 *data) 175 { 176 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 177 u8 *buff = data; 178 int i; 179 180 for (i = 0; i < kinfo->num_tqps; i++) { 181 struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 182 struct hclgevf_tqp, q); 183 snprintf(buff, ETH_GSTRING_LEN, "txq%u_pktnum_rcd", 184 tqp->index); 185 buff += ETH_GSTRING_LEN; 186 } 187 188 for (i = 0; i < kinfo->num_tqps; i++) { 189 struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 190 struct hclgevf_tqp, q); 191 snprintf(buff, ETH_GSTRING_LEN, "rxq%u_pktnum_rcd", 192 tqp->index); 193 buff += ETH_GSTRING_LEN; 194 } 195 196 return buff; 197 } 198 199 static void hclgevf_update_stats(struct hnae3_handle *handle, 200 struct net_device_stats *net_stats) 201 { 202 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 203 int status; 204 205 status = hclgevf_tqps_update_stats(handle); 206 if (status) 207 dev_err(&hdev->pdev->dev, 208 "VF update of TQPS stats fail, status = %d.\n", 209 status); 210 } 211 212 static int hclgevf_get_sset_count(struct hnae3_handle *handle, int strset) 213 { 214 if (strset == ETH_SS_TEST) 215 return -EOPNOTSUPP; 216 else if (strset == ETH_SS_STATS) 217 return hclgevf_tqps_get_sset_count(handle, strset); 218 219 return 0; 220 } 221 222 static void hclgevf_get_strings(struct hnae3_handle *handle, u32 strset, 223 u8 *data) 224 { 225 u8 *p = (char *)data; 226 227 if (strset == ETH_SS_STATS) 228 p = hclgevf_tqps_get_strings(handle, p); 229 } 230 231 static void hclgevf_get_stats(struct hnae3_handle *handle, u64 *data) 232 { 233 hclgevf_tqps_get_stats(handle, data); 234 } 235 236 static void hclgevf_build_send_msg(struct hclge_vf_to_pf_msg *msg, u8 code, 237 u8 subcode) 238 { 239 if (msg) { 240 memset(msg, 0, sizeof(struct hclge_vf_to_pf_msg)); 241 msg->code = code; 242 msg->subcode = subcode; 243 } 244 } 245 246 static int hclgevf_get_basic_info(struct hclgevf_dev *hdev) 247 { 248 struct hnae3_ae_dev *ae_dev = hdev->ae_dev; 249 u8 resp_msg[HCLGE_MBX_MAX_RESP_DATA_SIZE]; 250 struct hclge_basic_info *basic_info; 251 struct hclge_vf_to_pf_msg send_msg; 252 unsigned long caps; 253 int status; 254 255 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_BASIC_INFO, 0); 256 status = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 257 sizeof(resp_msg)); 258 if (status) { 259 dev_err(&hdev->pdev->dev, 260 "failed to get basic info from pf, ret = %d", status); 261 return status; 262 } 263 264 basic_info = (struct hclge_basic_info *)resp_msg; 265 266 hdev->hw_tc_map = basic_info->hw_tc_map; 267 hdev->mbx_api_version = basic_info->mbx_api_version; 268 caps = basic_info->pf_caps; 269 if (test_bit(HNAE3_PF_SUPPORT_VLAN_FLTR_MDF_B, &caps)) 270 set_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps); 271 272 return 0; 273 } 274 275 static int hclgevf_get_port_base_vlan_filter_state(struct hclgevf_dev *hdev) 276 { 277 struct hnae3_handle *nic = &hdev->nic; 278 struct hclge_vf_to_pf_msg send_msg; 279 u8 resp_msg; 280 int ret; 281 282 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 283 HCLGE_MBX_GET_PORT_BASE_VLAN_STATE); 284 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, &resp_msg, 285 sizeof(u8)); 286 if (ret) { 287 dev_err(&hdev->pdev->dev, 288 "VF request to get port based vlan state failed %d", 289 ret); 290 return ret; 291 } 292 293 nic->port_base_vlan_state = resp_msg; 294 295 return 0; 296 } 297 298 static int hclgevf_get_queue_info(struct hclgevf_dev *hdev) 299 { 300 #define HCLGEVF_TQPS_RSS_INFO_LEN 6 301 #define HCLGEVF_TQPS_ALLOC_OFFSET 0 302 #define HCLGEVF_TQPS_RSS_SIZE_OFFSET 2 303 #define HCLGEVF_TQPS_RX_BUFFER_LEN_OFFSET 4 304 305 u8 resp_msg[HCLGEVF_TQPS_RSS_INFO_LEN]; 306 struct hclge_vf_to_pf_msg send_msg; 307 int status; 308 309 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QINFO, 0); 310 status = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 311 HCLGEVF_TQPS_RSS_INFO_LEN); 312 if (status) { 313 dev_err(&hdev->pdev->dev, 314 "VF request to get tqp info from PF failed %d", 315 status); 316 return status; 317 } 318 319 memcpy(&hdev->num_tqps, &resp_msg[HCLGEVF_TQPS_ALLOC_OFFSET], 320 sizeof(u16)); 321 memcpy(&hdev->rss_size_max, &resp_msg[HCLGEVF_TQPS_RSS_SIZE_OFFSET], 322 sizeof(u16)); 323 memcpy(&hdev->rx_buf_len, &resp_msg[HCLGEVF_TQPS_RX_BUFFER_LEN_OFFSET], 324 sizeof(u16)); 325 326 return 0; 327 } 328 329 static int hclgevf_get_queue_depth(struct hclgevf_dev *hdev) 330 { 331 #define HCLGEVF_TQPS_DEPTH_INFO_LEN 4 332 #define HCLGEVF_TQPS_NUM_TX_DESC_OFFSET 0 333 #define HCLGEVF_TQPS_NUM_RX_DESC_OFFSET 2 334 335 u8 resp_msg[HCLGEVF_TQPS_DEPTH_INFO_LEN]; 336 struct hclge_vf_to_pf_msg send_msg; 337 int ret; 338 339 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QDEPTH, 0); 340 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 341 HCLGEVF_TQPS_DEPTH_INFO_LEN); 342 if (ret) { 343 dev_err(&hdev->pdev->dev, 344 "VF request to get tqp depth info from PF failed %d", 345 ret); 346 return ret; 347 } 348 349 memcpy(&hdev->num_tx_desc, &resp_msg[HCLGEVF_TQPS_NUM_TX_DESC_OFFSET], 350 sizeof(u16)); 351 memcpy(&hdev->num_rx_desc, &resp_msg[HCLGEVF_TQPS_NUM_RX_DESC_OFFSET], 352 sizeof(u16)); 353 354 return 0; 355 } 356 357 static u16 hclgevf_get_qid_global(struct hnae3_handle *handle, u16 queue_id) 358 { 359 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 360 struct hclge_vf_to_pf_msg send_msg; 361 u16 qid_in_pf = 0; 362 u8 resp_data[2]; 363 int ret; 364 365 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QID_IN_PF, 0); 366 memcpy(send_msg.data, &queue_id, sizeof(queue_id)); 367 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_data, 368 sizeof(resp_data)); 369 if (!ret) 370 qid_in_pf = *(u16 *)resp_data; 371 372 return qid_in_pf; 373 } 374 375 static int hclgevf_get_pf_media_type(struct hclgevf_dev *hdev) 376 { 377 struct hclge_vf_to_pf_msg send_msg; 378 u8 resp_msg[2]; 379 int ret; 380 381 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_MEDIA_TYPE, 0); 382 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 383 sizeof(resp_msg)); 384 if (ret) { 385 dev_err(&hdev->pdev->dev, 386 "VF request to get the pf port media type failed %d", 387 ret); 388 return ret; 389 } 390 391 hdev->hw.mac.media_type = resp_msg[0]; 392 hdev->hw.mac.module_type = resp_msg[1]; 393 394 return 0; 395 } 396 397 static int hclgevf_alloc_tqps(struct hclgevf_dev *hdev) 398 { 399 struct hclgevf_tqp *tqp; 400 int i; 401 402 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 403 sizeof(struct hclgevf_tqp), GFP_KERNEL); 404 if (!hdev->htqp) 405 return -ENOMEM; 406 407 tqp = hdev->htqp; 408 409 for (i = 0; i < hdev->num_tqps; i++) { 410 tqp->dev = &hdev->pdev->dev; 411 tqp->index = i; 412 413 tqp->q.ae_algo = &ae_algovf; 414 tqp->q.buf_size = hdev->rx_buf_len; 415 tqp->q.tx_desc_num = hdev->num_tx_desc; 416 tqp->q.rx_desc_num = hdev->num_rx_desc; 417 418 /* need an extended offset to configure queues >= 419 * HCLGEVF_TQP_MAX_SIZE_DEV_V2. 420 */ 421 if (i < HCLGEVF_TQP_MAX_SIZE_DEV_V2) 422 tqp->q.io_base = hdev->hw.io_base + 423 HCLGEVF_TQP_REG_OFFSET + 424 i * HCLGEVF_TQP_REG_SIZE; 425 else 426 tqp->q.io_base = hdev->hw.io_base + 427 HCLGEVF_TQP_REG_OFFSET + 428 HCLGEVF_TQP_EXT_REG_OFFSET + 429 (i - HCLGEVF_TQP_MAX_SIZE_DEV_V2) * 430 HCLGEVF_TQP_REG_SIZE; 431 432 tqp++; 433 } 434 435 return 0; 436 } 437 438 static int hclgevf_knic_setup(struct hclgevf_dev *hdev) 439 { 440 struct hnae3_handle *nic = &hdev->nic; 441 struct hnae3_knic_private_info *kinfo; 442 u16 new_tqps = hdev->num_tqps; 443 unsigned int i; 444 u8 num_tc = 0; 445 446 kinfo = &nic->kinfo; 447 kinfo->num_tx_desc = hdev->num_tx_desc; 448 kinfo->num_rx_desc = hdev->num_rx_desc; 449 kinfo->rx_buf_len = hdev->rx_buf_len; 450 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) 451 if (hdev->hw_tc_map & BIT(i)) 452 num_tc++; 453 454 num_tc = num_tc ? num_tc : 1; 455 kinfo->tc_info.num_tc = num_tc; 456 kinfo->rss_size = min_t(u16, hdev->rss_size_max, new_tqps / num_tc); 457 new_tqps = kinfo->rss_size * num_tc; 458 kinfo->num_tqps = min(new_tqps, hdev->num_tqps); 459 460 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps, 461 sizeof(struct hnae3_queue *), GFP_KERNEL); 462 if (!kinfo->tqp) 463 return -ENOMEM; 464 465 for (i = 0; i < kinfo->num_tqps; i++) { 466 hdev->htqp[i].q.handle = &hdev->nic; 467 hdev->htqp[i].q.tqp_index = i; 468 kinfo->tqp[i] = &hdev->htqp[i].q; 469 } 470 471 /* after init the max rss_size and tqps, adjust the default tqp numbers 472 * and rss size with the actual vector numbers 473 */ 474 kinfo->num_tqps = min_t(u16, hdev->num_nic_msix - 1, kinfo->num_tqps); 475 kinfo->rss_size = min_t(u16, kinfo->num_tqps / num_tc, 476 kinfo->rss_size); 477 478 return 0; 479 } 480 481 static void hclgevf_request_link_info(struct hclgevf_dev *hdev) 482 { 483 struct hclge_vf_to_pf_msg send_msg; 484 int status; 485 486 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_LINK_STATUS, 0); 487 status = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 488 if (status) 489 dev_err(&hdev->pdev->dev, 490 "VF failed to fetch link status(%d) from PF", status); 491 } 492 493 void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state) 494 { 495 struct hnae3_handle *rhandle = &hdev->roce; 496 struct hnae3_handle *handle = &hdev->nic; 497 struct hnae3_client *rclient; 498 struct hnae3_client *client; 499 500 if (test_and_set_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state)) 501 return; 502 503 client = handle->client; 504 rclient = hdev->roce_client; 505 506 link_state = 507 test_bit(HCLGEVF_STATE_DOWN, &hdev->state) ? 0 : link_state; 508 if (link_state != hdev->hw.mac.link) { 509 client->ops->link_status_change(handle, !!link_state); 510 if (rclient && rclient->ops->link_status_change) 511 rclient->ops->link_status_change(rhandle, !!link_state); 512 hdev->hw.mac.link = link_state; 513 } 514 515 clear_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state); 516 } 517 518 static void hclgevf_update_link_mode(struct hclgevf_dev *hdev) 519 { 520 #define HCLGEVF_ADVERTISING 0 521 #define HCLGEVF_SUPPORTED 1 522 523 struct hclge_vf_to_pf_msg send_msg; 524 525 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_LINK_MODE, 0); 526 send_msg.data[0] = HCLGEVF_ADVERTISING; 527 hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 528 send_msg.data[0] = HCLGEVF_SUPPORTED; 529 hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 530 } 531 532 static int hclgevf_set_handle_info(struct hclgevf_dev *hdev) 533 { 534 struct hnae3_handle *nic = &hdev->nic; 535 int ret; 536 537 nic->ae_algo = &ae_algovf; 538 nic->pdev = hdev->pdev; 539 nic->numa_node_mask = hdev->numa_node_mask; 540 nic->flags |= HNAE3_SUPPORT_VF; 541 542 ret = hclgevf_knic_setup(hdev); 543 if (ret) 544 dev_err(&hdev->pdev->dev, "VF knic setup failed %d\n", 545 ret); 546 return ret; 547 } 548 549 static void hclgevf_free_vector(struct hclgevf_dev *hdev, int vector_id) 550 { 551 if (hdev->vector_status[vector_id] == HCLGEVF_INVALID_VPORT) { 552 dev_warn(&hdev->pdev->dev, 553 "vector(vector_id %d) has been freed.\n", vector_id); 554 return; 555 } 556 557 hdev->vector_status[vector_id] = HCLGEVF_INVALID_VPORT; 558 hdev->num_msi_left += 1; 559 hdev->num_msi_used -= 1; 560 } 561 562 static int hclgevf_get_vector(struct hnae3_handle *handle, u16 vector_num, 563 struct hnae3_vector_info *vector_info) 564 { 565 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 566 struct hnae3_vector_info *vector = vector_info; 567 int alloc = 0; 568 int i, j; 569 570 vector_num = min_t(u16, hdev->num_nic_msix - 1, vector_num); 571 vector_num = min(hdev->num_msi_left, vector_num); 572 573 for (j = 0; j < vector_num; j++) { 574 for (i = HCLGEVF_MISC_VECTOR_NUM + 1; i < hdev->num_msi; i++) { 575 if (hdev->vector_status[i] == HCLGEVF_INVALID_VPORT) { 576 vector->vector = pci_irq_vector(hdev->pdev, i); 577 vector->io_addr = hdev->hw.io_base + 578 HCLGEVF_VECTOR_REG_BASE + 579 (i - 1) * HCLGEVF_VECTOR_REG_OFFSET; 580 hdev->vector_status[i] = 0; 581 hdev->vector_irq[i] = vector->vector; 582 583 vector++; 584 alloc++; 585 586 break; 587 } 588 } 589 } 590 hdev->num_msi_left -= alloc; 591 hdev->num_msi_used += alloc; 592 593 return alloc; 594 } 595 596 static int hclgevf_get_vector_index(struct hclgevf_dev *hdev, int vector) 597 { 598 int i; 599 600 for (i = 0; i < hdev->num_msi; i++) 601 if (vector == hdev->vector_irq[i]) 602 return i; 603 604 return -EINVAL; 605 } 606 607 static int hclgevf_set_rss_algo_key(struct hclgevf_dev *hdev, 608 const u8 hfunc, const u8 *key) 609 { 610 struct hclgevf_rss_config_cmd *req; 611 unsigned int key_offset = 0; 612 struct hclgevf_desc desc; 613 int key_counts; 614 int key_size; 615 int ret; 616 617 key_counts = HCLGEVF_RSS_KEY_SIZE; 618 req = (struct hclgevf_rss_config_cmd *)desc.data; 619 620 while (key_counts) { 621 hclgevf_cmd_setup_basic_desc(&desc, 622 HCLGEVF_OPC_RSS_GENERIC_CONFIG, 623 false); 624 625 req->hash_config |= (hfunc & HCLGEVF_RSS_HASH_ALGO_MASK); 626 req->hash_config |= 627 (key_offset << HCLGEVF_RSS_HASH_KEY_OFFSET_B); 628 629 key_size = min(HCLGEVF_RSS_HASH_KEY_NUM, key_counts); 630 memcpy(req->hash_key, 631 key + key_offset * HCLGEVF_RSS_HASH_KEY_NUM, key_size); 632 633 key_counts -= key_size; 634 key_offset++; 635 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 636 if (ret) { 637 dev_err(&hdev->pdev->dev, 638 "Configure RSS config fail, status = %d\n", 639 ret); 640 return ret; 641 } 642 } 643 644 return 0; 645 } 646 647 static u32 hclgevf_get_rss_key_size(struct hnae3_handle *handle) 648 { 649 return HCLGEVF_RSS_KEY_SIZE; 650 } 651 652 static int hclgevf_set_rss_indir_table(struct hclgevf_dev *hdev) 653 { 654 const u8 *indir = hdev->rss_cfg.rss_indirection_tbl; 655 struct hclgevf_rss_indirection_table_cmd *req; 656 struct hclgevf_desc desc; 657 int rss_cfg_tbl_num; 658 int status; 659 int i, j; 660 661 req = (struct hclgevf_rss_indirection_table_cmd *)desc.data; 662 rss_cfg_tbl_num = hdev->ae_dev->dev_specs.rss_ind_tbl_size / 663 HCLGEVF_RSS_CFG_TBL_SIZE; 664 665 for (i = 0; i < rss_cfg_tbl_num; i++) { 666 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INDIR_TABLE, 667 false); 668 req->start_table_index = 669 cpu_to_le16(i * HCLGEVF_RSS_CFG_TBL_SIZE); 670 req->rss_set_bitmap = cpu_to_le16(HCLGEVF_RSS_SET_BITMAP_MSK); 671 for (j = 0; j < HCLGEVF_RSS_CFG_TBL_SIZE; j++) 672 req->rss_result[j] = 673 indir[i * HCLGEVF_RSS_CFG_TBL_SIZE + j]; 674 675 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 676 if (status) { 677 dev_err(&hdev->pdev->dev, 678 "VF failed(=%d) to set RSS indirection table\n", 679 status); 680 return status; 681 } 682 } 683 684 return 0; 685 } 686 687 static int hclgevf_set_rss_tc_mode(struct hclgevf_dev *hdev, u16 rss_size) 688 { 689 struct hclgevf_rss_tc_mode_cmd *req; 690 u16 tc_offset[HCLGEVF_MAX_TC_NUM]; 691 u16 tc_valid[HCLGEVF_MAX_TC_NUM]; 692 u16 tc_size[HCLGEVF_MAX_TC_NUM]; 693 struct hclgevf_desc desc; 694 u16 roundup_size; 695 unsigned int i; 696 int status; 697 698 req = (struct hclgevf_rss_tc_mode_cmd *)desc.data; 699 700 roundup_size = roundup_pow_of_two(rss_size); 701 roundup_size = ilog2(roundup_size); 702 703 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 704 tc_valid[i] = !!(hdev->hw_tc_map & BIT(i)); 705 tc_size[i] = roundup_size; 706 tc_offset[i] = rss_size * i; 707 } 708 709 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_TC_MODE, false); 710 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 711 u16 mode = 0; 712 713 hnae3_set_bit(mode, HCLGEVF_RSS_TC_VALID_B, 714 (tc_valid[i] & 0x1)); 715 hnae3_set_field(mode, HCLGEVF_RSS_TC_SIZE_M, 716 HCLGEVF_RSS_TC_SIZE_S, tc_size[i]); 717 hnae3_set_bit(mode, HCLGEVF_RSS_TC_SIZE_MSB_B, 718 tc_size[i] >> HCLGEVF_RSS_TC_SIZE_MSB_OFFSET & 719 0x1); 720 hnae3_set_field(mode, HCLGEVF_RSS_TC_OFFSET_M, 721 HCLGEVF_RSS_TC_OFFSET_S, tc_offset[i]); 722 723 req->rss_tc_mode[i] = cpu_to_le16(mode); 724 } 725 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 726 if (status) 727 dev_err(&hdev->pdev->dev, 728 "VF failed(=%d) to set rss tc mode\n", status); 729 730 return status; 731 } 732 733 /* for revision 0x20, vf shared the same rss config with pf */ 734 static int hclgevf_get_rss_hash_key(struct hclgevf_dev *hdev) 735 { 736 #define HCLGEVF_RSS_MBX_RESP_LEN 8 737 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 738 u8 resp_msg[HCLGEVF_RSS_MBX_RESP_LEN]; 739 struct hclge_vf_to_pf_msg send_msg; 740 u16 msg_num, hash_key_index; 741 u8 index; 742 int ret; 743 744 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_RSS_KEY, 0); 745 msg_num = (HCLGEVF_RSS_KEY_SIZE + HCLGEVF_RSS_MBX_RESP_LEN - 1) / 746 HCLGEVF_RSS_MBX_RESP_LEN; 747 for (index = 0; index < msg_num; index++) { 748 send_msg.data[0] = index; 749 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 750 HCLGEVF_RSS_MBX_RESP_LEN); 751 if (ret) { 752 dev_err(&hdev->pdev->dev, 753 "VF get rss hash key from PF failed, ret=%d", 754 ret); 755 return ret; 756 } 757 758 hash_key_index = HCLGEVF_RSS_MBX_RESP_LEN * index; 759 if (index == msg_num - 1) 760 memcpy(&rss_cfg->rss_hash_key[hash_key_index], 761 &resp_msg[0], 762 HCLGEVF_RSS_KEY_SIZE - hash_key_index); 763 else 764 memcpy(&rss_cfg->rss_hash_key[hash_key_index], 765 &resp_msg[0], HCLGEVF_RSS_MBX_RESP_LEN); 766 } 767 768 return 0; 769 } 770 771 static int hclgevf_get_rss(struct hnae3_handle *handle, u32 *indir, u8 *key, 772 u8 *hfunc) 773 { 774 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 775 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 776 int i, ret; 777 778 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 779 /* Get hash algorithm */ 780 if (hfunc) { 781 switch (rss_cfg->hash_algo) { 782 case HCLGEVF_RSS_HASH_ALGO_TOEPLITZ: 783 *hfunc = ETH_RSS_HASH_TOP; 784 break; 785 case HCLGEVF_RSS_HASH_ALGO_SIMPLE: 786 *hfunc = ETH_RSS_HASH_XOR; 787 break; 788 default: 789 *hfunc = ETH_RSS_HASH_UNKNOWN; 790 break; 791 } 792 } 793 794 /* Get the RSS Key required by the user */ 795 if (key) 796 memcpy(key, rss_cfg->rss_hash_key, 797 HCLGEVF_RSS_KEY_SIZE); 798 } else { 799 if (hfunc) 800 *hfunc = ETH_RSS_HASH_TOP; 801 if (key) { 802 ret = hclgevf_get_rss_hash_key(hdev); 803 if (ret) 804 return ret; 805 memcpy(key, rss_cfg->rss_hash_key, 806 HCLGEVF_RSS_KEY_SIZE); 807 } 808 } 809 810 if (indir) 811 for (i = 0; i < hdev->ae_dev->dev_specs.rss_ind_tbl_size; i++) 812 indir[i] = rss_cfg->rss_indirection_tbl[i]; 813 814 return 0; 815 } 816 817 static int hclgevf_set_rss(struct hnae3_handle *handle, const u32 *indir, 818 const u8 *key, const u8 hfunc) 819 { 820 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 821 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 822 int ret, i; 823 824 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 825 /* Set the RSS Hash Key if specififed by the user */ 826 if (key) { 827 switch (hfunc) { 828 case ETH_RSS_HASH_TOP: 829 rss_cfg->hash_algo = 830 HCLGEVF_RSS_HASH_ALGO_TOEPLITZ; 831 break; 832 case ETH_RSS_HASH_XOR: 833 rss_cfg->hash_algo = 834 HCLGEVF_RSS_HASH_ALGO_SIMPLE; 835 break; 836 case ETH_RSS_HASH_NO_CHANGE: 837 break; 838 default: 839 return -EINVAL; 840 } 841 842 ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 843 key); 844 if (ret) 845 return ret; 846 847 /* Update the shadow RSS key with user specified qids */ 848 memcpy(rss_cfg->rss_hash_key, key, 849 HCLGEVF_RSS_KEY_SIZE); 850 } 851 } 852 853 /* update the shadow RSS table with user specified qids */ 854 for (i = 0; i < hdev->ae_dev->dev_specs.rss_ind_tbl_size; i++) 855 rss_cfg->rss_indirection_tbl[i] = indir[i]; 856 857 /* update the hardware */ 858 return hclgevf_set_rss_indir_table(hdev); 859 } 860 861 static u8 hclgevf_get_rss_hash_bits(struct ethtool_rxnfc *nfc) 862 { 863 u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGEVF_S_PORT_BIT : 0; 864 865 if (nfc->data & RXH_L4_B_2_3) 866 hash_sets |= HCLGEVF_D_PORT_BIT; 867 else 868 hash_sets &= ~HCLGEVF_D_PORT_BIT; 869 870 if (nfc->data & RXH_IP_SRC) 871 hash_sets |= HCLGEVF_S_IP_BIT; 872 else 873 hash_sets &= ~HCLGEVF_S_IP_BIT; 874 875 if (nfc->data & RXH_IP_DST) 876 hash_sets |= HCLGEVF_D_IP_BIT; 877 else 878 hash_sets &= ~HCLGEVF_D_IP_BIT; 879 880 if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW) 881 hash_sets |= HCLGEVF_V_TAG_BIT; 882 883 return hash_sets; 884 } 885 886 static int hclgevf_init_rss_tuple_cmd(struct hnae3_handle *handle, 887 struct ethtool_rxnfc *nfc, 888 struct hclgevf_rss_input_tuple_cmd *req) 889 { 890 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 891 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 892 u8 tuple_sets; 893 894 req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 895 req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 896 req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 897 req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 898 req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 899 req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 900 req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 901 req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 902 903 tuple_sets = hclgevf_get_rss_hash_bits(nfc); 904 switch (nfc->flow_type) { 905 case TCP_V4_FLOW: 906 req->ipv4_tcp_en = tuple_sets; 907 break; 908 case TCP_V6_FLOW: 909 req->ipv6_tcp_en = tuple_sets; 910 break; 911 case UDP_V4_FLOW: 912 req->ipv4_udp_en = tuple_sets; 913 break; 914 case UDP_V6_FLOW: 915 req->ipv6_udp_en = tuple_sets; 916 break; 917 case SCTP_V4_FLOW: 918 req->ipv4_sctp_en = tuple_sets; 919 break; 920 case SCTP_V6_FLOW: 921 if (hdev->ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2 && 922 (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3))) 923 return -EINVAL; 924 925 req->ipv6_sctp_en = tuple_sets; 926 break; 927 case IPV4_FLOW: 928 req->ipv4_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 929 break; 930 case IPV6_FLOW: 931 req->ipv6_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 932 break; 933 default: 934 return -EINVAL; 935 } 936 937 return 0; 938 } 939 940 static int hclgevf_set_rss_tuple(struct hnae3_handle *handle, 941 struct ethtool_rxnfc *nfc) 942 { 943 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 944 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 945 struct hclgevf_rss_input_tuple_cmd *req; 946 struct hclgevf_desc desc; 947 int ret; 948 949 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 950 return -EOPNOTSUPP; 951 952 if (nfc->data & 953 ~(RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3)) 954 return -EINVAL; 955 956 req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 957 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 958 959 ret = hclgevf_init_rss_tuple_cmd(handle, nfc, req); 960 if (ret) { 961 dev_err(&hdev->pdev->dev, 962 "failed to init rss tuple cmd, ret = %d\n", ret); 963 return ret; 964 } 965 966 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 967 if (ret) { 968 dev_err(&hdev->pdev->dev, 969 "Set rss tuple fail, status = %d\n", ret); 970 return ret; 971 } 972 973 rss_cfg->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en; 974 rss_cfg->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en; 975 rss_cfg->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en; 976 rss_cfg->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en; 977 rss_cfg->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en; 978 rss_cfg->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en; 979 rss_cfg->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en; 980 rss_cfg->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en; 981 return 0; 982 } 983 984 static int hclgevf_get_rss_tuple_by_flow_type(struct hclgevf_dev *hdev, 985 int flow_type, u8 *tuple_sets) 986 { 987 switch (flow_type) { 988 case TCP_V4_FLOW: 989 *tuple_sets = hdev->rss_cfg.rss_tuple_sets.ipv4_tcp_en; 990 break; 991 case UDP_V4_FLOW: 992 *tuple_sets = hdev->rss_cfg.rss_tuple_sets.ipv4_udp_en; 993 break; 994 case TCP_V6_FLOW: 995 *tuple_sets = hdev->rss_cfg.rss_tuple_sets.ipv6_tcp_en; 996 break; 997 case UDP_V6_FLOW: 998 *tuple_sets = hdev->rss_cfg.rss_tuple_sets.ipv6_udp_en; 999 break; 1000 case SCTP_V4_FLOW: 1001 *tuple_sets = hdev->rss_cfg.rss_tuple_sets.ipv4_sctp_en; 1002 break; 1003 case SCTP_V6_FLOW: 1004 *tuple_sets = hdev->rss_cfg.rss_tuple_sets.ipv6_sctp_en; 1005 break; 1006 case IPV4_FLOW: 1007 case IPV6_FLOW: 1008 *tuple_sets = HCLGEVF_S_IP_BIT | HCLGEVF_D_IP_BIT; 1009 break; 1010 default: 1011 return -EINVAL; 1012 } 1013 1014 return 0; 1015 } 1016 1017 static u64 hclgevf_convert_rss_tuple(u8 tuple_sets) 1018 { 1019 u64 tuple_data = 0; 1020 1021 if (tuple_sets & HCLGEVF_D_PORT_BIT) 1022 tuple_data |= RXH_L4_B_2_3; 1023 if (tuple_sets & HCLGEVF_S_PORT_BIT) 1024 tuple_data |= RXH_L4_B_0_1; 1025 if (tuple_sets & HCLGEVF_D_IP_BIT) 1026 tuple_data |= RXH_IP_DST; 1027 if (tuple_sets & HCLGEVF_S_IP_BIT) 1028 tuple_data |= RXH_IP_SRC; 1029 1030 return tuple_data; 1031 } 1032 1033 static int hclgevf_get_rss_tuple(struct hnae3_handle *handle, 1034 struct ethtool_rxnfc *nfc) 1035 { 1036 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1037 u8 tuple_sets; 1038 int ret; 1039 1040 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 1041 return -EOPNOTSUPP; 1042 1043 nfc->data = 0; 1044 1045 ret = hclgevf_get_rss_tuple_by_flow_type(hdev, nfc->flow_type, 1046 &tuple_sets); 1047 if (ret || !tuple_sets) 1048 return ret; 1049 1050 nfc->data = hclgevf_convert_rss_tuple(tuple_sets); 1051 1052 return 0; 1053 } 1054 1055 static int hclgevf_set_rss_input_tuple(struct hclgevf_dev *hdev, 1056 struct hclgevf_rss_cfg *rss_cfg) 1057 { 1058 struct hclgevf_rss_input_tuple_cmd *req; 1059 struct hclgevf_desc desc; 1060 int ret; 1061 1062 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 1063 1064 req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 1065 1066 req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 1067 req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 1068 req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 1069 req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 1070 req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 1071 req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 1072 req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 1073 req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 1074 1075 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1076 if (ret) 1077 dev_err(&hdev->pdev->dev, 1078 "Configure rss input fail, status = %d\n", ret); 1079 return ret; 1080 } 1081 1082 static int hclgevf_get_tc_size(struct hnae3_handle *handle) 1083 { 1084 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1085 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 1086 1087 return rss_cfg->rss_size; 1088 } 1089 1090 static int hclgevf_bind_ring_to_vector(struct hnae3_handle *handle, bool en, 1091 int vector_id, 1092 struct hnae3_ring_chain_node *ring_chain) 1093 { 1094 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1095 struct hclge_vf_to_pf_msg send_msg; 1096 struct hnae3_ring_chain_node *node; 1097 int status; 1098 int i = 0; 1099 1100 memset(&send_msg, 0, sizeof(send_msg)); 1101 send_msg.code = en ? HCLGE_MBX_MAP_RING_TO_VECTOR : 1102 HCLGE_MBX_UNMAP_RING_TO_VECTOR; 1103 send_msg.vector_id = vector_id; 1104 1105 for (node = ring_chain; node; node = node->next) { 1106 send_msg.param[i].ring_type = 1107 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B); 1108 1109 send_msg.param[i].tqp_index = node->tqp_index; 1110 send_msg.param[i].int_gl_index = 1111 hnae3_get_field(node->int_gl_idx, 1112 HNAE3_RING_GL_IDX_M, 1113 HNAE3_RING_GL_IDX_S); 1114 1115 i++; 1116 if (i == HCLGE_MBX_MAX_RING_CHAIN_PARAM_NUM || !node->next) { 1117 send_msg.ring_num = i; 1118 1119 status = hclgevf_send_mbx_msg(hdev, &send_msg, false, 1120 NULL, 0); 1121 if (status) { 1122 dev_err(&hdev->pdev->dev, 1123 "Map TQP fail, status is %d.\n", 1124 status); 1125 return status; 1126 } 1127 i = 0; 1128 } 1129 } 1130 1131 return 0; 1132 } 1133 1134 static int hclgevf_map_ring_to_vector(struct hnae3_handle *handle, int vector, 1135 struct hnae3_ring_chain_node *ring_chain) 1136 { 1137 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1138 int vector_id; 1139 1140 vector_id = hclgevf_get_vector_index(hdev, vector); 1141 if (vector_id < 0) { 1142 dev_err(&handle->pdev->dev, 1143 "Get vector index fail. ret =%d\n", vector_id); 1144 return vector_id; 1145 } 1146 1147 return hclgevf_bind_ring_to_vector(handle, true, vector_id, ring_chain); 1148 } 1149 1150 static int hclgevf_unmap_ring_from_vector( 1151 struct hnae3_handle *handle, 1152 int vector, 1153 struct hnae3_ring_chain_node *ring_chain) 1154 { 1155 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1156 int ret, vector_id; 1157 1158 if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 1159 return 0; 1160 1161 vector_id = hclgevf_get_vector_index(hdev, vector); 1162 if (vector_id < 0) { 1163 dev_err(&handle->pdev->dev, 1164 "Get vector index fail. ret =%d\n", vector_id); 1165 return vector_id; 1166 } 1167 1168 ret = hclgevf_bind_ring_to_vector(handle, false, vector_id, ring_chain); 1169 if (ret) 1170 dev_err(&handle->pdev->dev, 1171 "Unmap ring from vector fail. vector=%d, ret =%d\n", 1172 vector_id, 1173 ret); 1174 1175 return ret; 1176 } 1177 1178 static int hclgevf_put_vector(struct hnae3_handle *handle, int vector) 1179 { 1180 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1181 int vector_id; 1182 1183 vector_id = hclgevf_get_vector_index(hdev, vector); 1184 if (vector_id < 0) { 1185 dev_err(&handle->pdev->dev, 1186 "hclgevf_put_vector get vector index fail. ret =%d\n", 1187 vector_id); 1188 return vector_id; 1189 } 1190 1191 hclgevf_free_vector(hdev, vector_id); 1192 1193 return 0; 1194 } 1195 1196 static int hclgevf_cmd_set_promisc_mode(struct hclgevf_dev *hdev, 1197 bool en_uc_pmc, bool en_mc_pmc, 1198 bool en_bc_pmc) 1199 { 1200 struct hnae3_handle *handle = &hdev->nic; 1201 struct hclge_vf_to_pf_msg send_msg; 1202 int ret; 1203 1204 memset(&send_msg, 0, sizeof(send_msg)); 1205 send_msg.code = HCLGE_MBX_SET_PROMISC_MODE; 1206 send_msg.en_bc = en_bc_pmc ? 1 : 0; 1207 send_msg.en_uc = en_uc_pmc ? 1 : 0; 1208 send_msg.en_mc = en_mc_pmc ? 1 : 0; 1209 send_msg.en_limit_promisc = test_bit(HNAE3_PFLAG_LIMIT_PROMISC, 1210 &handle->priv_flags) ? 1 : 0; 1211 1212 ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 1213 if (ret) 1214 dev_err(&hdev->pdev->dev, 1215 "Set promisc mode fail, status is %d.\n", ret); 1216 1217 return ret; 1218 } 1219 1220 static int hclgevf_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc, 1221 bool en_mc_pmc) 1222 { 1223 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1224 bool en_bc_pmc; 1225 1226 en_bc_pmc = hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2; 1227 1228 return hclgevf_cmd_set_promisc_mode(hdev, en_uc_pmc, en_mc_pmc, 1229 en_bc_pmc); 1230 } 1231 1232 static void hclgevf_request_update_promisc_mode(struct hnae3_handle *handle) 1233 { 1234 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1235 1236 set_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state); 1237 hclgevf_task_schedule(hdev, 0); 1238 } 1239 1240 static void hclgevf_sync_promisc_mode(struct hclgevf_dev *hdev) 1241 { 1242 struct hnae3_handle *handle = &hdev->nic; 1243 bool en_uc_pmc = handle->netdev_flags & HNAE3_UPE; 1244 bool en_mc_pmc = handle->netdev_flags & HNAE3_MPE; 1245 int ret; 1246 1247 if (test_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state)) { 1248 ret = hclgevf_set_promisc_mode(handle, en_uc_pmc, en_mc_pmc); 1249 if (!ret) 1250 clear_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state); 1251 } 1252 } 1253 1254 static int hclgevf_tqp_enable_cmd_send(struct hclgevf_dev *hdev, u16 tqp_id, 1255 u16 stream_id, bool enable) 1256 { 1257 struct hclgevf_cfg_com_tqp_queue_cmd *req; 1258 struct hclgevf_desc desc; 1259 1260 req = (struct hclgevf_cfg_com_tqp_queue_cmd *)desc.data; 1261 1262 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_CFG_COM_TQP_QUEUE, 1263 false); 1264 req->tqp_id = cpu_to_le16(tqp_id & HCLGEVF_RING_ID_MASK); 1265 req->stream_id = cpu_to_le16(stream_id); 1266 if (enable) 1267 req->enable |= 1U << HCLGEVF_TQP_ENABLE_B; 1268 1269 return hclgevf_cmd_send(&hdev->hw, &desc, 1); 1270 } 1271 1272 static int hclgevf_tqp_enable(struct hnae3_handle *handle, bool enable) 1273 { 1274 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1275 int ret; 1276 u16 i; 1277 1278 for (i = 0; i < handle->kinfo.num_tqps; i++) { 1279 ret = hclgevf_tqp_enable_cmd_send(hdev, i, 0, enable); 1280 if (ret) 1281 return ret; 1282 } 1283 1284 return 0; 1285 } 1286 1287 static void hclgevf_reset_tqp_stats(struct hnae3_handle *handle) 1288 { 1289 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 1290 struct hclgevf_tqp *tqp; 1291 int i; 1292 1293 for (i = 0; i < kinfo->num_tqps; i++) { 1294 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 1295 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats)); 1296 } 1297 } 1298 1299 static int hclgevf_get_host_mac_addr(struct hclgevf_dev *hdev, u8 *p) 1300 { 1301 struct hclge_vf_to_pf_msg send_msg; 1302 u8 host_mac[ETH_ALEN]; 1303 int status; 1304 1305 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_MAC_ADDR, 0); 1306 status = hclgevf_send_mbx_msg(hdev, &send_msg, true, host_mac, 1307 ETH_ALEN); 1308 if (status) { 1309 dev_err(&hdev->pdev->dev, 1310 "fail to get VF MAC from host %d", status); 1311 return status; 1312 } 1313 1314 ether_addr_copy(p, host_mac); 1315 1316 return 0; 1317 } 1318 1319 static void hclgevf_get_mac_addr(struct hnae3_handle *handle, u8 *p) 1320 { 1321 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1322 u8 host_mac_addr[ETH_ALEN]; 1323 1324 if (hclgevf_get_host_mac_addr(hdev, host_mac_addr)) 1325 return; 1326 1327 hdev->has_pf_mac = !is_zero_ether_addr(host_mac_addr); 1328 if (hdev->has_pf_mac) 1329 ether_addr_copy(p, host_mac_addr); 1330 else 1331 ether_addr_copy(p, hdev->hw.mac.mac_addr); 1332 } 1333 1334 static int hclgevf_set_mac_addr(struct hnae3_handle *handle, void *p, 1335 bool is_first) 1336 { 1337 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1338 u8 *old_mac_addr = (u8 *)hdev->hw.mac.mac_addr; 1339 struct hclge_vf_to_pf_msg send_msg; 1340 u8 *new_mac_addr = (u8 *)p; 1341 int status; 1342 1343 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_UNICAST, 0); 1344 send_msg.subcode = HCLGE_MBX_MAC_VLAN_UC_MODIFY; 1345 ether_addr_copy(send_msg.data, new_mac_addr); 1346 if (is_first && !hdev->has_pf_mac) 1347 eth_zero_addr(&send_msg.data[ETH_ALEN]); 1348 else 1349 ether_addr_copy(&send_msg.data[ETH_ALEN], old_mac_addr); 1350 status = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1351 if (!status) 1352 ether_addr_copy(hdev->hw.mac.mac_addr, new_mac_addr); 1353 1354 return status; 1355 } 1356 1357 static struct hclgevf_mac_addr_node * 1358 hclgevf_find_mac_node(struct list_head *list, const u8 *mac_addr) 1359 { 1360 struct hclgevf_mac_addr_node *mac_node, *tmp; 1361 1362 list_for_each_entry_safe(mac_node, tmp, list, node) 1363 if (ether_addr_equal(mac_addr, mac_node->mac_addr)) 1364 return mac_node; 1365 1366 return NULL; 1367 } 1368 1369 static void hclgevf_update_mac_node(struct hclgevf_mac_addr_node *mac_node, 1370 enum HCLGEVF_MAC_NODE_STATE state) 1371 { 1372 switch (state) { 1373 /* from set_rx_mode or tmp_add_list */ 1374 case HCLGEVF_MAC_TO_ADD: 1375 if (mac_node->state == HCLGEVF_MAC_TO_DEL) 1376 mac_node->state = HCLGEVF_MAC_ACTIVE; 1377 break; 1378 /* only from set_rx_mode */ 1379 case HCLGEVF_MAC_TO_DEL: 1380 if (mac_node->state == HCLGEVF_MAC_TO_ADD) { 1381 list_del(&mac_node->node); 1382 kfree(mac_node); 1383 } else { 1384 mac_node->state = HCLGEVF_MAC_TO_DEL; 1385 } 1386 break; 1387 /* only from tmp_add_list, the mac_node->state won't be 1388 * HCLGEVF_MAC_ACTIVE 1389 */ 1390 case HCLGEVF_MAC_ACTIVE: 1391 if (mac_node->state == HCLGEVF_MAC_TO_ADD) 1392 mac_node->state = HCLGEVF_MAC_ACTIVE; 1393 break; 1394 } 1395 } 1396 1397 static int hclgevf_update_mac_list(struct hnae3_handle *handle, 1398 enum HCLGEVF_MAC_NODE_STATE state, 1399 enum HCLGEVF_MAC_ADDR_TYPE mac_type, 1400 const unsigned char *addr) 1401 { 1402 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1403 struct hclgevf_mac_addr_node *mac_node; 1404 struct list_head *list; 1405 1406 list = (mac_type == HCLGEVF_MAC_ADDR_UC) ? 1407 &hdev->mac_table.uc_mac_list : &hdev->mac_table.mc_mac_list; 1408 1409 spin_lock_bh(&hdev->mac_table.mac_list_lock); 1410 1411 /* if the mac addr is already in the mac list, no need to add a new 1412 * one into it, just check the mac addr state, convert it to a new 1413 * new state, or just remove it, or do nothing. 1414 */ 1415 mac_node = hclgevf_find_mac_node(list, addr); 1416 if (mac_node) { 1417 hclgevf_update_mac_node(mac_node, state); 1418 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1419 return 0; 1420 } 1421 /* if this address is never added, unnecessary to delete */ 1422 if (state == HCLGEVF_MAC_TO_DEL) { 1423 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1424 return -ENOENT; 1425 } 1426 1427 mac_node = kzalloc(sizeof(*mac_node), GFP_ATOMIC); 1428 if (!mac_node) { 1429 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1430 return -ENOMEM; 1431 } 1432 1433 mac_node->state = state; 1434 ether_addr_copy(mac_node->mac_addr, addr); 1435 list_add_tail(&mac_node->node, list); 1436 1437 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1438 return 0; 1439 } 1440 1441 static int hclgevf_add_uc_addr(struct hnae3_handle *handle, 1442 const unsigned char *addr) 1443 { 1444 return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_ADD, 1445 HCLGEVF_MAC_ADDR_UC, addr); 1446 } 1447 1448 static int hclgevf_rm_uc_addr(struct hnae3_handle *handle, 1449 const unsigned char *addr) 1450 { 1451 return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_DEL, 1452 HCLGEVF_MAC_ADDR_UC, addr); 1453 } 1454 1455 static int hclgevf_add_mc_addr(struct hnae3_handle *handle, 1456 const unsigned char *addr) 1457 { 1458 return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_ADD, 1459 HCLGEVF_MAC_ADDR_MC, addr); 1460 } 1461 1462 static int hclgevf_rm_mc_addr(struct hnae3_handle *handle, 1463 const unsigned char *addr) 1464 { 1465 return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_DEL, 1466 HCLGEVF_MAC_ADDR_MC, addr); 1467 } 1468 1469 static int hclgevf_add_del_mac_addr(struct hclgevf_dev *hdev, 1470 struct hclgevf_mac_addr_node *mac_node, 1471 enum HCLGEVF_MAC_ADDR_TYPE mac_type) 1472 { 1473 struct hclge_vf_to_pf_msg send_msg; 1474 u8 code, subcode; 1475 1476 if (mac_type == HCLGEVF_MAC_ADDR_UC) { 1477 code = HCLGE_MBX_SET_UNICAST; 1478 if (mac_node->state == HCLGEVF_MAC_TO_ADD) 1479 subcode = HCLGE_MBX_MAC_VLAN_UC_ADD; 1480 else 1481 subcode = HCLGE_MBX_MAC_VLAN_UC_REMOVE; 1482 } else { 1483 code = HCLGE_MBX_SET_MULTICAST; 1484 if (mac_node->state == HCLGEVF_MAC_TO_ADD) 1485 subcode = HCLGE_MBX_MAC_VLAN_MC_ADD; 1486 else 1487 subcode = HCLGE_MBX_MAC_VLAN_MC_REMOVE; 1488 } 1489 1490 hclgevf_build_send_msg(&send_msg, code, subcode); 1491 ether_addr_copy(send_msg.data, mac_node->mac_addr); 1492 return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 1493 } 1494 1495 static void hclgevf_config_mac_list(struct hclgevf_dev *hdev, 1496 struct list_head *list, 1497 enum HCLGEVF_MAC_ADDR_TYPE mac_type) 1498 { 1499 struct hclgevf_mac_addr_node *mac_node, *tmp; 1500 int ret; 1501 1502 list_for_each_entry_safe(mac_node, tmp, list, node) { 1503 ret = hclgevf_add_del_mac_addr(hdev, mac_node, mac_type); 1504 if (ret) { 1505 dev_err(&hdev->pdev->dev, 1506 "failed to configure mac %pM, state = %d, ret = %d\n", 1507 mac_node->mac_addr, mac_node->state, ret); 1508 return; 1509 } 1510 if (mac_node->state == HCLGEVF_MAC_TO_ADD) { 1511 mac_node->state = HCLGEVF_MAC_ACTIVE; 1512 } else { 1513 list_del(&mac_node->node); 1514 kfree(mac_node); 1515 } 1516 } 1517 } 1518 1519 static void hclgevf_sync_from_add_list(struct list_head *add_list, 1520 struct list_head *mac_list) 1521 { 1522 struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node; 1523 1524 list_for_each_entry_safe(mac_node, tmp, add_list, node) { 1525 /* if the mac address from tmp_add_list is not in the 1526 * uc/mc_mac_list, it means have received a TO_DEL request 1527 * during the time window of sending mac config request to PF 1528 * If mac_node state is ACTIVE, then change its state to TO_DEL, 1529 * then it will be removed at next time. If is TO_ADD, it means 1530 * send TO_ADD request failed, so just remove the mac node. 1531 */ 1532 new_node = hclgevf_find_mac_node(mac_list, mac_node->mac_addr); 1533 if (new_node) { 1534 hclgevf_update_mac_node(new_node, mac_node->state); 1535 list_del(&mac_node->node); 1536 kfree(mac_node); 1537 } else if (mac_node->state == HCLGEVF_MAC_ACTIVE) { 1538 mac_node->state = HCLGEVF_MAC_TO_DEL; 1539 list_del(&mac_node->node); 1540 list_add_tail(&mac_node->node, mac_list); 1541 } else { 1542 list_del(&mac_node->node); 1543 kfree(mac_node); 1544 } 1545 } 1546 } 1547 1548 static void hclgevf_sync_from_del_list(struct list_head *del_list, 1549 struct list_head *mac_list) 1550 { 1551 struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node; 1552 1553 list_for_each_entry_safe(mac_node, tmp, del_list, node) { 1554 new_node = hclgevf_find_mac_node(mac_list, mac_node->mac_addr); 1555 if (new_node) { 1556 /* If the mac addr is exist in the mac list, it means 1557 * received a new request TO_ADD during the time window 1558 * of sending mac addr configurrequest to PF, so just 1559 * change the mac state to ACTIVE. 1560 */ 1561 new_node->state = HCLGEVF_MAC_ACTIVE; 1562 list_del(&mac_node->node); 1563 kfree(mac_node); 1564 } else { 1565 list_del(&mac_node->node); 1566 list_add_tail(&mac_node->node, mac_list); 1567 } 1568 } 1569 } 1570 1571 static void hclgevf_clear_list(struct list_head *list) 1572 { 1573 struct hclgevf_mac_addr_node *mac_node, *tmp; 1574 1575 list_for_each_entry_safe(mac_node, tmp, list, node) { 1576 list_del(&mac_node->node); 1577 kfree(mac_node); 1578 } 1579 } 1580 1581 static void hclgevf_sync_mac_list(struct hclgevf_dev *hdev, 1582 enum HCLGEVF_MAC_ADDR_TYPE mac_type) 1583 { 1584 struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node; 1585 struct list_head tmp_add_list, tmp_del_list; 1586 struct list_head *list; 1587 1588 INIT_LIST_HEAD(&tmp_add_list); 1589 INIT_LIST_HEAD(&tmp_del_list); 1590 1591 /* move the mac addr to the tmp_add_list and tmp_del_list, then 1592 * we can add/delete these mac addr outside the spin lock 1593 */ 1594 list = (mac_type == HCLGEVF_MAC_ADDR_UC) ? 1595 &hdev->mac_table.uc_mac_list : &hdev->mac_table.mc_mac_list; 1596 1597 spin_lock_bh(&hdev->mac_table.mac_list_lock); 1598 1599 list_for_each_entry_safe(mac_node, tmp, list, node) { 1600 switch (mac_node->state) { 1601 case HCLGEVF_MAC_TO_DEL: 1602 list_del(&mac_node->node); 1603 list_add_tail(&mac_node->node, &tmp_del_list); 1604 break; 1605 case HCLGEVF_MAC_TO_ADD: 1606 new_node = kzalloc(sizeof(*new_node), GFP_ATOMIC); 1607 if (!new_node) 1608 goto stop_traverse; 1609 1610 ether_addr_copy(new_node->mac_addr, mac_node->mac_addr); 1611 new_node->state = mac_node->state; 1612 list_add_tail(&new_node->node, &tmp_add_list); 1613 break; 1614 default: 1615 break; 1616 } 1617 } 1618 1619 stop_traverse: 1620 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1621 1622 /* delete first, in order to get max mac table space for adding */ 1623 hclgevf_config_mac_list(hdev, &tmp_del_list, mac_type); 1624 hclgevf_config_mac_list(hdev, &tmp_add_list, mac_type); 1625 1626 /* if some mac addresses were added/deleted fail, move back to the 1627 * mac_list, and retry at next time. 1628 */ 1629 spin_lock_bh(&hdev->mac_table.mac_list_lock); 1630 1631 hclgevf_sync_from_del_list(&tmp_del_list, list); 1632 hclgevf_sync_from_add_list(&tmp_add_list, list); 1633 1634 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1635 } 1636 1637 static void hclgevf_sync_mac_table(struct hclgevf_dev *hdev) 1638 { 1639 hclgevf_sync_mac_list(hdev, HCLGEVF_MAC_ADDR_UC); 1640 hclgevf_sync_mac_list(hdev, HCLGEVF_MAC_ADDR_MC); 1641 } 1642 1643 static void hclgevf_uninit_mac_list(struct hclgevf_dev *hdev) 1644 { 1645 spin_lock_bh(&hdev->mac_table.mac_list_lock); 1646 1647 hclgevf_clear_list(&hdev->mac_table.uc_mac_list); 1648 hclgevf_clear_list(&hdev->mac_table.mc_mac_list); 1649 1650 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1651 } 1652 1653 static int hclgevf_enable_vlan_filter(struct hnae3_handle *handle, bool enable) 1654 { 1655 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1656 struct hnae3_ae_dev *ae_dev = hdev->ae_dev; 1657 struct hclge_vf_to_pf_msg send_msg; 1658 1659 if (!test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps)) 1660 return -EOPNOTSUPP; 1661 1662 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 1663 HCLGE_MBX_ENABLE_VLAN_FILTER); 1664 send_msg.data[0] = enable ? 1 : 0; 1665 1666 return hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1667 } 1668 1669 static int hclgevf_set_vlan_filter(struct hnae3_handle *handle, 1670 __be16 proto, u16 vlan_id, 1671 bool is_kill) 1672 { 1673 #define HCLGEVF_VLAN_MBX_IS_KILL_OFFSET 0 1674 #define HCLGEVF_VLAN_MBX_VLAN_ID_OFFSET 1 1675 #define HCLGEVF_VLAN_MBX_PROTO_OFFSET 3 1676 1677 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1678 struct hclge_vf_to_pf_msg send_msg; 1679 int ret; 1680 1681 if (vlan_id > HCLGEVF_MAX_VLAN_ID) 1682 return -EINVAL; 1683 1684 if (proto != htons(ETH_P_8021Q)) 1685 return -EPROTONOSUPPORT; 1686 1687 /* When device is resetting or reset failed, firmware is unable to 1688 * handle mailbox. Just record the vlan id, and remove it after 1689 * reset finished. 1690 */ 1691 if ((test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) || 1692 test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) && is_kill) { 1693 set_bit(vlan_id, hdev->vlan_del_fail_bmap); 1694 return -EBUSY; 1695 } 1696 1697 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 1698 HCLGE_MBX_VLAN_FILTER); 1699 send_msg.data[HCLGEVF_VLAN_MBX_IS_KILL_OFFSET] = is_kill; 1700 memcpy(&send_msg.data[HCLGEVF_VLAN_MBX_VLAN_ID_OFFSET], &vlan_id, 1701 sizeof(vlan_id)); 1702 memcpy(&send_msg.data[HCLGEVF_VLAN_MBX_PROTO_OFFSET], &proto, 1703 sizeof(proto)); 1704 /* when remove hw vlan filter failed, record the vlan id, 1705 * and try to remove it from hw later, to be consistence 1706 * with stack. 1707 */ 1708 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1709 if (is_kill && ret) 1710 set_bit(vlan_id, hdev->vlan_del_fail_bmap); 1711 1712 return ret; 1713 } 1714 1715 static void hclgevf_sync_vlan_filter(struct hclgevf_dev *hdev) 1716 { 1717 #define HCLGEVF_MAX_SYNC_COUNT 60 1718 struct hnae3_handle *handle = &hdev->nic; 1719 int ret, sync_cnt = 0; 1720 u16 vlan_id; 1721 1722 vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID); 1723 while (vlan_id != VLAN_N_VID) { 1724 ret = hclgevf_set_vlan_filter(handle, htons(ETH_P_8021Q), 1725 vlan_id, true); 1726 if (ret) 1727 return; 1728 1729 clear_bit(vlan_id, hdev->vlan_del_fail_bmap); 1730 sync_cnt++; 1731 if (sync_cnt >= HCLGEVF_MAX_SYNC_COUNT) 1732 return; 1733 1734 vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID); 1735 } 1736 } 1737 1738 static int hclgevf_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) 1739 { 1740 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1741 struct hclge_vf_to_pf_msg send_msg; 1742 1743 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 1744 HCLGE_MBX_VLAN_RX_OFF_CFG); 1745 send_msg.data[0] = enable ? 1 : 0; 1746 return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 1747 } 1748 1749 static int hclgevf_reset_tqp(struct hnae3_handle *handle) 1750 { 1751 #define HCLGEVF_RESET_ALL_QUEUE_DONE 1U 1752 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1753 struct hclge_vf_to_pf_msg send_msg; 1754 u8 return_status = 0; 1755 int ret; 1756 u16 i; 1757 1758 /* disable vf queue before send queue reset msg to PF */ 1759 ret = hclgevf_tqp_enable(handle, false); 1760 if (ret) { 1761 dev_err(&hdev->pdev->dev, "failed to disable tqp, ret = %d\n", 1762 ret); 1763 return ret; 1764 } 1765 1766 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_QUEUE_RESET, 0); 1767 1768 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, &return_status, 1769 sizeof(return_status)); 1770 if (ret || return_status == HCLGEVF_RESET_ALL_QUEUE_DONE) 1771 return ret; 1772 1773 for (i = 1; i < handle->kinfo.num_tqps; i++) { 1774 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_QUEUE_RESET, 0); 1775 memcpy(send_msg.data, &i, sizeof(i)); 1776 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1777 if (ret) 1778 return ret; 1779 } 1780 1781 return 0; 1782 } 1783 1784 static int hclgevf_set_mtu(struct hnae3_handle *handle, int new_mtu) 1785 { 1786 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1787 struct hclge_vf_to_pf_msg send_msg; 1788 1789 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_MTU, 0); 1790 memcpy(send_msg.data, &new_mtu, sizeof(new_mtu)); 1791 return hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1792 } 1793 1794 static int hclgevf_notify_client(struct hclgevf_dev *hdev, 1795 enum hnae3_reset_notify_type type) 1796 { 1797 struct hnae3_client *client = hdev->nic_client; 1798 struct hnae3_handle *handle = &hdev->nic; 1799 int ret; 1800 1801 if (!test_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state) || 1802 !client) 1803 return 0; 1804 1805 if (!client->ops->reset_notify) 1806 return -EOPNOTSUPP; 1807 1808 ret = client->ops->reset_notify(handle, type); 1809 if (ret) 1810 dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n", 1811 type, ret); 1812 1813 return ret; 1814 } 1815 1816 static int hclgevf_notify_roce_client(struct hclgevf_dev *hdev, 1817 enum hnae3_reset_notify_type type) 1818 { 1819 struct hnae3_client *client = hdev->roce_client; 1820 struct hnae3_handle *handle = &hdev->roce; 1821 int ret; 1822 1823 if (!test_bit(HCLGEVF_STATE_ROCE_REGISTERED, &hdev->state) || !client) 1824 return 0; 1825 1826 if (!client->ops->reset_notify) 1827 return -EOPNOTSUPP; 1828 1829 ret = client->ops->reset_notify(handle, type); 1830 if (ret) 1831 dev_err(&hdev->pdev->dev, "notify roce client failed %d(%d)", 1832 type, ret); 1833 return ret; 1834 } 1835 1836 static int hclgevf_reset_wait(struct hclgevf_dev *hdev) 1837 { 1838 #define HCLGEVF_RESET_WAIT_US 20000 1839 #define HCLGEVF_RESET_WAIT_CNT 2000 1840 #define HCLGEVF_RESET_WAIT_TIMEOUT_US \ 1841 (HCLGEVF_RESET_WAIT_US * HCLGEVF_RESET_WAIT_CNT) 1842 1843 u32 val; 1844 int ret; 1845 1846 if (hdev->reset_type == HNAE3_VF_RESET) 1847 ret = readl_poll_timeout(hdev->hw.io_base + 1848 HCLGEVF_VF_RST_ING, val, 1849 !(val & HCLGEVF_VF_RST_ING_BIT), 1850 HCLGEVF_RESET_WAIT_US, 1851 HCLGEVF_RESET_WAIT_TIMEOUT_US); 1852 else 1853 ret = readl_poll_timeout(hdev->hw.io_base + 1854 HCLGEVF_RST_ING, val, 1855 !(val & HCLGEVF_RST_ING_BITS), 1856 HCLGEVF_RESET_WAIT_US, 1857 HCLGEVF_RESET_WAIT_TIMEOUT_US); 1858 1859 /* hardware completion status should be available by this time */ 1860 if (ret) { 1861 dev_err(&hdev->pdev->dev, 1862 "couldn't get reset done status from h/w, timeout!\n"); 1863 return ret; 1864 } 1865 1866 /* we will wait a bit more to let reset of the stack to complete. This 1867 * might happen in case reset assertion was made by PF. Yes, this also 1868 * means we might end up waiting bit more even for VF reset. 1869 */ 1870 msleep(5000); 1871 1872 return 0; 1873 } 1874 1875 static void hclgevf_reset_handshake(struct hclgevf_dev *hdev, bool enable) 1876 { 1877 u32 reg_val; 1878 1879 reg_val = hclgevf_read_dev(&hdev->hw, HCLGEVF_NIC_CSQ_DEPTH_REG); 1880 if (enable) 1881 reg_val |= HCLGEVF_NIC_SW_RST_RDY; 1882 else 1883 reg_val &= ~HCLGEVF_NIC_SW_RST_RDY; 1884 1885 hclgevf_write_dev(&hdev->hw, HCLGEVF_NIC_CSQ_DEPTH_REG, 1886 reg_val); 1887 } 1888 1889 static int hclgevf_reset_stack(struct hclgevf_dev *hdev) 1890 { 1891 int ret; 1892 1893 /* uninitialize the nic client */ 1894 ret = hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT); 1895 if (ret) 1896 return ret; 1897 1898 /* re-initialize the hclge device */ 1899 ret = hclgevf_reset_hdev(hdev); 1900 if (ret) { 1901 dev_err(&hdev->pdev->dev, 1902 "hclge device re-init failed, VF is disabled!\n"); 1903 return ret; 1904 } 1905 1906 /* bring up the nic client again */ 1907 ret = hclgevf_notify_client(hdev, HNAE3_INIT_CLIENT); 1908 if (ret) 1909 return ret; 1910 1911 /* clear handshake status with IMP */ 1912 hclgevf_reset_handshake(hdev, false); 1913 1914 /* bring up the nic to enable TX/RX again */ 1915 return hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 1916 } 1917 1918 static int hclgevf_reset_prepare_wait(struct hclgevf_dev *hdev) 1919 { 1920 #define HCLGEVF_RESET_SYNC_TIME 100 1921 1922 if (hdev->reset_type == HNAE3_VF_FUNC_RESET) { 1923 struct hclge_vf_to_pf_msg send_msg; 1924 int ret; 1925 1926 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_RESET, 0); 1927 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1928 if (ret) { 1929 dev_err(&hdev->pdev->dev, 1930 "failed to assert VF reset, ret = %d\n", ret); 1931 return ret; 1932 } 1933 hdev->rst_stats.vf_func_rst_cnt++; 1934 } 1935 1936 set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 1937 /* inform hardware that preparatory work is done */ 1938 msleep(HCLGEVF_RESET_SYNC_TIME); 1939 hclgevf_reset_handshake(hdev, true); 1940 dev_info(&hdev->pdev->dev, "prepare reset(%d) wait done\n", 1941 hdev->reset_type); 1942 1943 return 0; 1944 } 1945 1946 static void hclgevf_dump_rst_info(struct hclgevf_dev *hdev) 1947 { 1948 dev_info(&hdev->pdev->dev, "VF function reset count: %u\n", 1949 hdev->rst_stats.vf_func_rst_cnt); 1950 dev_info(&hdev->pdev->dev, "FLR reset count: %u\n", 1951 hdev->rst_stats.flr_rst_cnt); 1952 dev_info(&hdev->pdev->dev, "VF reset count: %u\n", 1953 hdev->rst_stats.vf_rst_cnt); 1954 dev_info(&hdev->pdev->dev, "reset done count: %u\n", 1955 hdev->rst_stats.rst_done_cnt); 1956 dev_info(&hdev->pdev->dev, "HW reset done count: %u\n", 1957 hdev->rst_stats.hw_rst_done_cnt); 1958 dev_info(&hdev->pdev->dev, "reset count: %u\n", 1959 hdev->rst_stats.rst_cnt); 1960 dev_info(&hdev->pdev->dev, "reset fail count: %u\n", 1961 hdev->rst_stats.rst_fail_cnt); 1962 dev_info(&hdev->pdev->dev, "vector0 interrupt enable status: 0x%x\n", 1963 hclgevf_read_dev(&hdev->hw, HCLGEVF_MISC_VECTOR_REG_BASE)); 1964 dev_info(&hdev->pdev->dev, "vector0 interrupt status: 0x%x\n", 1965 hclgevf_read_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_STATE_REG)); 1966 dev_info(&hdev->pdev->dev, "handshake status: 0x%x\n", 1967 hclgevf_read_dev(&hdev->hw, HCLGEVF_CMDQ_TX_DEPTH_REG)); 1968 dev_info(&hdev->pdev->dev, "function reset status: 0x%x\n", 1969 hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING)); 1970 dev_info(&hdev->pdev->dev, "hdev state: 0x%lx\n", hdev->state); 1971 } 1972 1973 static void hclgevf_reset_err_handle(struct hclgevf_dev *hdev) 1974 { 1975 /* recover handshake status with IMP when reset fail */ 1976 hclgevf_reset_handshake(hdev, true); 1977 hdev->rst_stats.rst_fail_cnt++; 1978 dev_err(&hdev->pdev->dev, "failed to reset VF(%u)\n", 1979 hdev->rst_stats.rst_fail_cnt); 1980 1981 if (hdev->rst_stats.rst_fail_cnt < HCLGEVF_RESET_MAX_FAIL_CNT) 1982 set_bit(hdev->reset_type, &hdev->reset_pending); 1983 1984 if (hclgevf_is_reset_pending(hdev)) { 1985 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1986 hclgevf_reset_task_schedule(hdev); 1987 } else { 1988 set_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state); 1989 hclgevf_dump_rst_info(hdev); 1990 } 1991 } 1992 1993 static int hclgevf_reset_prepare(struct hclgevf_dev *hdev) 1994 { 1995 int ret; 1996 1997 hdev->rst_stats.rst_cnt++; 1998 1999 /* perform reset of the stack & ae device for a client */ 2000 ret = hclgevf_notify_roce_client(hdev, HNAE3_DOWN_CLIENT); 2001 if (ret) 2002 return ret; 2003 2004 rtnl_lock(); 2005 /* bring down the nic to stop any ongoing TX/RX */ 2006 ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 2007 rtnl_unlock(); 2008 if (ret) 2009 return ret; 2010 2011 return hclgevf_reset_prepare_wait(hdev); 2012 } 2013 2014 static int hclgevf_reset_rebuild(struct hclgevf_dev *hdev) 2015 { 2016 int ret; 2017 2018 hdev->rst_stats.hw_rst_done_cnt++; 2019 ret = hclgevf_notify_roce_client(hdev, HNAE3_UNINIT_CLIENT); 2020 if (ret) 2021 return ret; 2022 2023 rtnl_lock(); 2024 /* now, re-initialize the nic client and ae device */ 2025 ret = hclgevf_reset_stack(hdev); 2026 rtnl_unlock(); 2027 if (ret) { 2028 dev_err(&hdev->pdev->dev, "failed to reset VF stack\n"); 2029 return ret; 2030 } 2031 2032 ret = hclgevf_notify_roce_client(hdev, HNAE3_INIT_CLIENT); 2033 /* ignore RoCE notify error if it fails HCLGEVF_RESET_MAX_FAIL_CNT - 1 2034 * times 2035 */ 2036 if (ret && 2037 hdev->rst_stats.rst_fail_cnt < HCLGEVF_RESET_MAX_FAIL_CNT - 1) 2038 return ret; 2039 2040 ret = hclgevf_notify_roce_client(hdev, HNAE3_UP_CLIENT); 2041 if (ret) 2042 return ret; 2043 2044 hdev->last_reset_time = jiffies; 2045 hdev->rst_stats.rst_done_cnt++; 2046 hdev->rst_stats.rst_fail_cnt = 0; 2047 clear_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state); 2048 2049 return 0; 2050 } 2051 2052 static void hclgevf_reset(struct hclgevf_dev *hdev) 2053 { 2054 if (hclgevf_reset_prepare(hdev)) 2055 goto err_reset; 2056 2057 /* check if VF could successfully fetch the hardware reset completion 2058 * status from the hardware 2059 */ 2060 if (hclgevf_reset_wait(hdev)) { 2061 /* can't do much in this situation, will disable VF */ 2062 dev_err(&hdev->pdev->dev, 2063 "failed to fetch H/W reset completion status\n"); 2064 goto err_reset; 2065 } 2066 2067 if (hclgevf_reset_rebuild(hdev)) 2068 goto err_reset; 2069 2070 return; 2071 2072 err_reset: 2073 hclgevf_reset_err_handle(hdev); 2074 } 2075 2076 static enum hnae3_reset_type hclgevf_get_reset_level(struct hclgevf_dev *hdev, 2077 unsigned long *addr) 2078 { 2079 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; 2080 2081 /* return the highest priority reset level amongst all */ 2082 if (test_bit(HNAE3_VF_RESET, addr)) { 2083 rst_level = HNAE3_VF_RESET; 2084 clear_bit(HNAE3_VF_RESET, addr); 2085 clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 2086 clear_bit(HNAE3_VF_FUNC_RESET, addr); 2087 } else if (test_bit(HNAE3_VF_FULL_RESET, addr)) { 2088 rst_level = HNAE3_VF_FULL_RESET; 2089 clear_bit(HNAE3_VF_FULL_RESET, addr); 2090 clear_bit(HNAE3_VF_FUNC_RESET, addr); 2091 } else if (test_bit(HNAE3_VF_PF_FUNC_RESET, addr)) { 2092 rst_level = HNAE3_VF_PF_FUNC_RESET; 2093 clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 2094 clear_bit(HNAE3_VF_FUNC_RESET, addr); 2095 } else if (test_bit(HNAE3_VF_FUNC_RESET, addr)) { 2096 rst_level = HNAE3_VF_FUNC_RESET; 2097 clear_bit(HNAE3_VF_FUNC_RESET, addr); 2098 } else if (test_bit(HNAE3_FLR_RESET, addr)) { 2099 rst_level = HNAE3_FLR_RESET; 2100 clear_bit(HNAE3_FLR_RESET, addr); 2101 } 2102 2103 return rst_level; 2104 } 2105 2106 static void hclgevf_reset_event(struct pci_dev *pdev, 2107 struct hnae3_handle *handle) 2108 { 2109 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2110 struct hclgevf_dev *hdev = ae_dev->priv; 2111 2112 dev_info(&hdev->pdev->dev, "received reset request from VF enet\n"); 2113 2114 if (hdev->default_reset_request) 2115 hdev->reset_level = 2116 hclgevf_get_reset_level(hdev, 2117 &hdev->default_reset_request); 2118 else 2119 hdev->reset_level = HNAE3_VF_FUNC_RESET; 2120 2121 /* reset of this VF requested */ 2122 set_bit(HCLGEVF_RESET_REQUESTED, &hdev->reset_state); 2123 hclgevf_reset_task_schedule(hdev); 2124 2125 hdev->last_reset_time = jiffies; 2126 } 2127 2128 static void hclgevf_set_def_reset_request(struct hnae3_ae_dev *ae_dev, 2129 enum hnae3_reset_type rst_type) 2130 { 2131 struct hclgevf_dev *hdev = ae_dev->priv; 2132 2133 set_bit(rst_type, &hdev->default_reset_request); 2134 } 2135 2136 static void hclgevf_enable_vector(struct hclgevf_misc_vector *vector, bool en) 2137 { 2138 writel(en ? 1 : 0, vector->addr); 2139 } 2140 2141 static void hclgevf_reset_prepare_general(struct hnae3_ae_dev *ae_dev, 2142 enum hnae3_reset_type rst_type) 2143 { 2144 #define HCLGEVF_RESET_RETRY_WAIT_MS 500 2145 #define HCLGEVF_RESET_RETRY_CNT 5 2146 2147 struct hclgevf_dev *hdev = ae_dev->priv; 2148 int retry_cnt = 0; 2149 int ret; 2150 2151 retry: 2152 down(&hdev->reset_sem); 2153 set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 2154 hdev->reset_type = rst_type; 2155 ret = hclgevf_reset_prepare(hdev); 2156 if (ret) { 2157 dev_err(&hdev->pdev->dev, "fail to prepare to reset, ret=%d\n", 2158 ret); 2159 if (hdev->reset_pending || 2160 retry_cnt++ < HCLGEVF_RESET_RETRY_CNT) { 2161 dev_err(&hdev->pdev->dev, 2162 "reset_pending:0x%lx, retry_cnt:%d\n", 2163 hdev->reset_pending, retry_cnt); 2164 clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 2165 up(&hdev->reset_sem); 2166 msleep(HCLGEVF_RESET_RETRY_WAIT_MS); 2167 goto retry; 2168 } 2169 } 2170 2171 /* disable misc vector before reset done */ 2172 hclgevf_enable_vector(&hdev->misc_vector, false); 2173 2174 if (hdev->reset_type == HNAE3_FLR_RESET) 2175 hdev->rst_stats.flr_rst_cnt++; 2176 } 2177 2178 static void hclgevf_reset_done(struct hnae3_ae_dev *ae_dev) 2179 { 2180 struct hclgevf_dev *hdev = ae_dev->priv; 2181 int ret; 2182 2183 hclgevf_enable_vector(&hdev->misc_vector, true); 2184 2185 ret = hclgevf_reset_rebuild(hdev); 2186 if (ret) 2187 dev_warn(&hdev->pdev->dev, "fail to rebuild, ret=%d\n", 2188 ret); 2189 2190 hdev->reset_type = HNAE3_NONE_RESET; 2191 clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 2192 up(&hdev->reset_sem); 2193 } 2194 2195 static u32 hclgevf_get_fw_version(struct hnae3_handle *handle) 2196 { 2197 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2198 2199 return hdev->fw_version; 2200 } 2201 2202 static void hclgevf_get_misc_vector(struct hclgevf_dev *hdev) 2203 { 2204 struct hclgevf_misc_vector *vector = &hdev->misc_vector; 2205 2206 vector->vector_irq = pci_irq_vector(hdev->pdev, 2207 HCLGEVF_MISC_VECTOR_NUM); 2208 vector->addr = hdev->hw.io_base + HCLGEVF_MISC_VECTOR_REG_BASE; 2209 /* vector status always valid for Vector 0 */ 2210 hdev->vector_status[HCLGEVF_MISC_VECTOR_NUM] = 0; 2211 hdev->vector_irq[HCLGEVF_MISC_VECTOR_NUM] = vector->vector_irq; 2212 2213 hdev->num_msi_left -= 1; 2214 hdev->num_msi_used += 1; 2215 } 2216 2217 void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev) 2218 { 2219 if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) && 2220 !test_and_set_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, 2221 &hdev->state)) 2222 mod_delayed_work(hclgevf_wq, &hdev->service_task, 0); 2223 } 2224 2225 void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev) 2226 { 2227 if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) && 2228 !test_and_set_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, 2229 &hdev->state)) 2230 mod_delayed_work(hclgevf_wq, &hdev->service_task, 0); 2231 } 2232 2233 static void hclgevf_task_schedule(struct hclgevf_dev *hdev, 2234 unsigned long delay) 2235 { 2236 if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) && 2237 !test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) 2238 mod_delayed_work(hclgevf_wq, &hdev->service_task, delay); 2239 } 2240 2241 static void hclgevf_reset_service_task(struct hclgevf_dev *hdev) 2242 { 2243 #define HCLGEVF_MAX_RESET_ATTEMPTS_CNT 3 2244 2245 if (!test_and_clear_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state)) 2246 return; 2247 2248 down(&hdev->reset_sem); 2249 set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 2250 2251 if (test_and_clear_bit(HCLGEVF_RESET_PENDING, 2252 &hdev->reset_state)) { 2253 /* PF has intimated that it is about to reset the hardware. 2254 * We now have to poll & check if hardware has actually 2255 * completed the reset sequence. On hardware reset completion, 2256 * VF needs to reset the client and ae device. 2257 */ 2258 hdev->reset_attempts = 0; 2259 2260 hdev->last_reset_time = jiffies; 2261 while ((hdev->reset_type = 2262 hclgevf_get_reset_level(hdev, &hdev->reset_pending)) 2263 != HNAE3_NONE_RESET) 2264 hclgevf_reset(hdev); 2265 } else if (test_and_clear_bit(HCLGEVF_RESET_REQUESTED, 2266 &hdev->reset_state)) { 2267 /* we could be here when either of below happens: 2268 * 1. reset was initiated due to watchdog timeout caused by 2269 * a. IMP was earlier reset and our TX got choked down and 2270 * which resulted in watchdog reacting and inducing VF 2271 * reset. This also means our cmdq would be unreliable. 2272 * b. problem in TX due to other lower layer(example link 2273 * layer not functioning properly etc.) 2274 * 2. VF reset might have been initiated due to some config 2275 * change. 2276 * 2277 * NOTE: Theres no clear way to detect above cases than to react 2278 * to the response of PF for this reset request. PF will ack the 2279 * 1b and 2. cases but we will not get any intimation about 1a 2280 * from PF as cmdq would be in unreliable state i.e. mailbox 2281 * communication between PF and VF would be broken. 2282 * 2283 * if we are never geting into pending state it means either: 2284 * 1. PF is not receiving our request which could be due to IMP 2285 * reset 2286 * 2. PF is screwed 2287 * We cannot do much for 2. but to check first we can try reset 2288 * our PCIe + stack and see if it alleviates the problem. 2289 */ 2290 if (hdev->reset_attempts > HCLGEVF_MAX_RESET_ATTEMPTS_CNT) { 2291 /* prepare for full reset of stack + pcie interface */ 2292 set_bit(HNAE3_VF_FULL_RESET, &hdev->reset_pending); 2293 2294 /* "defer" schedule the reset task again */ 2295 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 2296 } else { 2297 hdev->reset_attempts++; 2298 2299 set_bit(hdev->reset_level, &hdev->reset_pending); 2300 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 2301 } 2302 hclgevf_reset_task_schedule(hdev); 2303 } 2304 2305 hdev->reset_type = HNAE3_NONE_RESET; 2306 clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 2307 up(&hdev->reset_sem); 2308 } 2309 2310 static void hclgevf_mailbox_service_task(struct hclgevf_dev *hdev) 2311 { 2312 if (!test_and_clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state)) 2313 return; 2314 2315 if (test_and_set_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) 2316 return; 2317 2318 hclgevf_mbx_async_handler(hdev); 2319 2320 clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 2321 } 2322 2323 static void hclgevf_keep_alive(struct hclgevf_dev *hdev) 2324 { 2325 struct hclge_vf_to_pf_msg send_msg; 2326 int ret; 2327 2328 if (test_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state)) 2329 return; 2330 2331 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_KEEP_ALIVE, 0); 2332 ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 2333 if (ret) 2334 dev_err(&hdev->pdev->dev, 2335 "VF sends keep alive cmd failed(=%d)\n", ret); 2336 } 2337 2338 static void hclgevf_periodic_service_task(struct hclgevf_dev *hdev) 2339 { 2340 unsigned long delta = round_jiffies_relative(HZ); 2341 struct hnae3_handle *handle = &hdev->nic; 2342 2343 if (test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) 2344 return; 2345 2346 if (time_is_after_jiffies(hdev->last_serv_processed + HZ)) { 2347 delta = jiffies - hdev->last_serv_processed; 2348 2349 if (delta < round_jiffies_relative(HZ)) { 2350 delta = round_jiffies_relative(HZ) - delta; 2351 goto out; 2352 } 2353 } 2354 2355 hdev->serv_processed_cnt++; 2356 if (!(hdev->serv_processed_cnt % HCLGEVF_KEEP_ALIVE_TASK_INTERVAL)) 2357 hclgevf_keep_alive(hdev); 2358 2359 if (test_bit(HCLGEVF_STATE_DOWN, &hdev->state)) { 2360 hdev->last_serv_processed = jiffies; 2361 goto out; 2362 } 2363 2364 if (!(hdev->serv_processed_cnt % HCLGEVF_STATS_TIMER_INTERVAL)) 2365 hclgevf_tqps_update_stats(handle); 2366 2367 /* VF does not need to request link status when this bit is set, because 2368 * PF will push its link status to VFs when link status changed. 2369 */ 2370 if (!test_bit(HCLGEVF_STATE_PF_PUSH_LINK_STATUS, &hdev->state)) 2371 hclgevf_request_link_info(hdev); 2372 2373 hclgevf_update_link_mode(hdev); 2374 2375 hclgevf_sync_vlan_filter(hdev); 2376 2377 hclgevf_sync_mac_table(hdev); 2378 2379 hclgevf_sync_promisc_mode(hdev); 2380 2381 hdev->last_serv_processed = jiffies; 2382 2383 out: 2384 hclgevf_task_schedule(hdev, delta); 2385 } 2386 2387 static void hclgevf_service_task(struct work_struct *work) 2388 { 2389 struct hclgevf_dev *hdev = container_of(work, struct hclgevf_dev, 2390 service_task.work); 2391 2392 hclgevf_reset_service_task(hdev); 2393 hclgevf_mailbox_service_task(hdev); 2394 hclgevf_periodic_service_task(hdev); 2395 2396 /* Handle reset and mbx again in case periodical task delays the 2397 * handling by calling hclgevf_task_schedule() in 2398 * hclgevf_periodic_service_task() 2399 */ 2400 hclgevf_reset_service_task(hdev); 2401 hclgevf_mailbox_service_task(hdev); 2402 } 2403 2404 static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regclr) 2405 { 2406 hclgevf_write_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_SRC_REG, regclr); 2407 } 2408 2409 static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev, 2410 u32 *clearval) 2411 { 2412 u32 val, cmdq_stat_reg, rst_ing_reg; 2413 2414 /* fetch the events from their corresponding regs */ 2415 cmdq_stat_reg = hclgevf_read_dev(&hdev->hw, 2416 HCLGEVF_VECTOR0_CMDQ_STATE_REG); 2417 if (BIT(HCLGEVF_VECTOR0_RST_INT_B) & cmdq_stat_reg) { 2418 rst_ing_reg = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 2419 dev_info(&hdev->pdev->dev, 2420 "receive reset interrupt 0x%x!\n", rst_ing_reg); 2421 set_bit(HNAE3_VF_RESET, &hdev->reset_pending); 2422 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 2423 set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 2424 *clearval = ~(1U << HCLGEVF_VECTOR0_RST_INT_B); 2425 hdev->rst_stats.vf_rst_cnt++; 2426 /* set up VF hardware reset status, its PF will clear 2427 * this status when PF has initialized done. 2428 */ 2429 val = hclgevf_read_dev(&hdev->hw, HCLGEVF_VF_RST_ING); 2430 hclgevf_write_dev(&hdev->hw, HCLGEVF_VF_RST_ING, 2431 val | HCLGEVF_VF_RST_ING_BIT); 2432 return HCLGEVF_VECTOR0_EVENT_RST; 2433 } 2434 2435 /* check for vector0 mailbox(=CMDQ RX) event source */ 2436 if (BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) { 2437 /* for revision 0x21, clearing interrupt is writing bit 0 2438 * to the clear register, writing bit 1 means to keep the 2439 * old value. 2440 * for revision 0x20, the clear register is a read & write 2441 * register, so we should just write 0 to the bit we are 2442 * handling, and keep other bits as cmdq_stat_reg. 2443 */ 2444 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) 2445 *clearval = ~(1U << HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 2446 else 2447 *clearval = cmdq_stat_reg & 2448 ~BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 2449 2450 return HCLGEVF_VECTOR0_EVENT_MBX; 2451 } 2452 2453 /* print other vector0 event source */ 2454 dev_info(&hdev->pdev->dev, 2455 "vector 0 interrupt from unknown source, cmdq_src = %#x\n", 2456 cmdq_stat_reg); 2457 2458 return HCLGEVF_VECTOR0_EVENT_OTHER; 2459 } 2460 2461 static irqreturn_t hclgevf_misc_irq_handle(int irq, void *data) 2462 { 2463 enum hclgevf_evt_cause event_cause; 2464 struct hclgevf_dev *hdev = data; 2465 u32 clearval; 2466 2467 hclgevf_enable_vector(&hdev->misc_vector, false); 2468 event_cause = hclgevf_check_evt_cause(hdev, &clearval); 2469 2470 switch (event_cause) { 2471 case HCLGEVF_VECTOR0_EVENT_RST: 2472 hclgevf_reset_task_schedule(hdev); 2473 break; 2474 case HCLGEVF_VECTOR0_EVENT_MBX: 2475 hclgevf_mbx_handler(hdev); 2476 break; 2477 default: 2478 break; 2479 } 2480 2481 if (event_cause != HCLGEVF_VECTOR0_EVENT_OTHER) { 2482 hclgevf_clear_event_cause(hdev, clearval); 2483 hclgevf_enable_vector(&hdev->misc_vector, true); 2484 } 2485 2486 return IRQ_HANDLED; 2487 } 2488 2489 static int hclgevf_configure(struct hclgevf_dev *hdev) 2490 { 2491 int ret; 2492 2493 ret = hclgevf_get_basic_info(hdev); 2494 if (ret) 2495 return ret; 2496 2497 /* get current port based vlan state from PF */ 2498 ret = hclgevf_get_port_base_vlan_filter_state(hdev); 2499 if (ret) 2500 return ret; 2501 2502 /* get queue configuration from PF */ 2503 ret = hclgevf_get_queue_info(hdev); 2504 if (ret) 2505 return ret; 2506 2507 /* get queue depth info from PF */ 2508 ret = hclgevf_get_queue_depth(hdev); 2509 if (ret) 2510 return ret; 2511 2512 return hclgevf_get_pf_media_type(hdev); 2513 } 2514 2515 static int hclgevf_alloc_hdev(struct hnae3_ae_dev *ae_dev) 2516 { 2517 struct pci_dev *pdev = ae_dev->pdev; 2518 struct hclgevf_dev *hdev; 2519 2520 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 2521 if (!hdev) 2522 return -ENOMEM; 2523 2524 hdev->pdev = pdev; 2525 hdev->ae_dev = ae_dev; 2526 ae_dev->priv = hdev; 2527 2528 return 0; 2529 } 2530 2531 static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev) 2532 { 2533 struct hnae3_handle *roce = &hdev->roce; 2534 struct hnae3_handle *nic = &hdev->nic; 2535 2536 roce->rinfo.num_vectors = hdev->num_roce_msix; 2537 2538 if (hdev->num_msi_left < roce->rinfo.num_vectors || 2539 hdev->num_msi_left == 0) 2540 return -EINVAL; 2541 2542 roce->rinfo.base_vector = hdev->roce_base_vector; 2543 2544 roce->rinfo.netdev = nic->kinfo.netdev; 2545 roce->rinfo.roce_io_base = hdev->hw.io_base; 2546 roce->rinfo.roce_mem_base = hdev->hw.mem_base; 2547 2548 roce->pdev = nic->pdev; 2549 roce->ae_algo = nic->ae_algo; 2550 roce->numa_node_mask = nic->numa_node_mask; 2551 2552 return 0; 2553 } 2554 2555 static int hclgevf_config_gro(struct hclgevf_dev *hdev, bool en) 2556 { 2557 struct hclgevf_cfg_gro_status_cmd *req; 2558 struct hclgevf_desc desc; 2559 int ret; 2560 2561 if (!hnae3_dev_gro_supported(hdev)) 2562 return 0; 2563 2564 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_GRO_GENERIC_CONFIG, 2565 false); 2566 req = (struct hclgevf_cfg_gro_status_cmd *)desc.data; 2567 2568 req->gro_en = en ? 1 : 0; 2569 2570 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 2571 if (ret) 2572 dev_err(&hdev->pdev->dev, 2573 "VF GRO hardware config cmd failed, ret = %d.\n", ret); 2574 2575 return ret; 2576 } 2577 2578 static int hclgevf_rss_init_cfg(struct hclgevf_dev *hdev) 2579 { 2580 u16 rss_ind_tbl_size = hdev->ae_dev->dev_specs.rss_ind_tbl_size; 2581 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 2582 struct hclgevf_rss_tuple_cfg *tuple_sets; 2583 u32 i; 2584 2585 rss_cfg->hash_algo = HCLGEVF_RSS_HASH_ALGO_TOEPLITZ; 2586 rss_cfg->rss_size = hdev->nic.kinfo.rss_size; 2587 tuple_sets = &rss_cfg->rss_tuple_sets; 2588 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 2589 u8 *rss_ind_tbl; 2590 2591 rss_cfg->hash_algo = HCLGEVF_RSS_HASH_ALGO_SIMPLE; 2592 2593 rss_ind_tbl = devm_kcalloc(&hdev->pdev->dev, rss_ind_tbl_size, 2594 sizeof(*rss_ind_tbl), GFP_KERNEL); 2595 if (!rss_ind_tbl) 2596 return -ENOMEM; 2597 2598 rss_cfg->rss_indirection_tbl = rss_ind_tbl; 2599 memcpy(rss_cfg->rss_hash_key, hclgevf_hash_key, 2600 HCLGEVF_RSS_KEY_SIZE); 2601 2602 tuple_sets->ipv4_tcp_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2603 tuple_sets->ipv4_udp_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2604 tuple_sets->ipv4_sctp_en = HCLGEVF_RSS_INPUT_TUPLE_SCTP; 2605 tuple_sets->ipv4_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2606 tuple_sets->ipv6_tcp_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2607 tuple_sets->ipv6_udp_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2608 tuple_sets->ipv6_sctp_en = 2609 hdev->ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2 ? 2610 HCLGEVF_RSS_INPUT_TUPLE_SCTP_NO_PORT : 2611 HCLGEVF_RSS_INPUT_TUPLE_SCTP; 2612 tuple_sets->ipv6_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2613 } 2614 2615 /* Initialize RSS indirect table */ 2616 for (i = 0; i < rss_ind_tbl_size; i++) 2617 rss_cfg->rss_indirection_tbl[i] = i % rss_cfg->rss_size; 2618 2619 return 0; 2620 } 2621 2622 static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev) 2623 { 2624 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 2625 int ret; 2626 2627 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 2628 ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 2629 rss_cfg->rss_hash_key); 2630 if (ret) 2631 return ret; 2632 2633 ret = hclgevf_set_rss_input_tuple(hdev, rss_cfg); 2634 if (ret) 2635 return ret; 2636 } 2637 2638 ret = hclgevf_set_rss_indir_table(hdev); 2639 if (ret) 2640 return ret; 2641 2642 return hclgevf_set_rss_tc_mode(hdev, rss_cfg->rss_size); 2643 } 2644 2645 static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev) 2646 { 2647 return hclgevf_set_vlan_filter(&hdev->nic, htons(ETH_P_8021Q), 0, 2648 false); 2649 } 2650 2651 static void hclgevf_flush_link_update(struct hclgevf_dev *hdev) 2652 { 2653 #define HCLGEVF_FLUSH_LINK_TIMEOUT 100000 2654 2655 unsigned long last = hdev->serv_processed_cnt; 2656 int i = 0; 2657 2658 while (test_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state) && 2659 i++ < HCLGEVF_FLUSH_LINK_TIMEOUT && 2660 last == hdev->serv_processed_cnt) 2661 usleep_range(1, 1); 2662 } 2663 2664 static void hclgevf_set_timer_task(struct hnae3_handle *handle, bool enable) 2665 { 2666 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2667 2668 if (enable) { 2669 hclgevf_task_schedule(hdev, 0); 2670 } else { 2671 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2672 2673 /* flush memory to make sure DOWN is seen by service task */ 2674 smp_mb__before_atomic(); 2675 hclgevf_flush_link_update(hdev); 2676 } 2677 } 2678 2679 static int hclgevf_ae_start(struct hnae3_handle *handle) 2680 { 2681 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2682 2683 clear_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2684 clear_bit(HCLGEVF_STATE_PF_PUSH_LINK_STATUS, &hdev->state); 2685 2686 hclgevf_reset_tqp_stats(handle); 2687 2688 hclgevf_request_link_info(hdev); 2689 2690 hclgevf_update_link_mode(hdev); 2691 2692 return 0; 2693 } 2694 2695 static void hclgevf_ae_stop(struct hnae3_handle *handle) 2696 { 2697 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2698 2699 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2700 2701 if (hdev->reset_type != HNAE3_VF_RESET) 2702 hclgevf_reset_tqp(handle); 2703 2704 hclgevf_reset_tqp_stats(handle); 2705 hclgevf_update_link_status(hdev, 0); 2706 } 2707 2708 static int hclgevf_set_alive(struct hnae3_handle *handle, bool alive) 2709 { 2710 #define HCLGEVF_STATE_ALIVE 1 2711 #define HCLGEVF_STATE_NOT_ALIVE 0 2712 2713 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2714 struct hclge_vf_to_pf_msg send_msg; 2715 2716 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_ALIVE, 0); 2717 send_msg.data[0] = alive ? HCLGEVF_STATE_ALIVE : 2718 HCLGEVF_STATE_NOT_ALIVE; 2719 return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 2720 } 2721 2722 static int hclgevf_client_start(struct hnae3_handle *handle) 2723 { 2724 return hclgevf_set_alive(handle, true); 2725 } 2726 2727 static void hclgevf_client_stop(struct hnae3_handle *handle) 2728 { 2729 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2730 int ret; 2731 2732 ret = hclgevf_set_alive(handle, false); 2733 if (ret) 2734 dev_warn(&hdev->pdev->dev, 2735 "%s failed %d\n", __func__, ret); 2736 } 2737 2738 static void hclgevf_state_init(struct hclgevf_dev *hdev) 2739 { 2740 clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 2741 clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 2742 clear_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state); 2743 2744 INIT_DELAYED_WORK(&hdev->service_task, hclgevf_service_task); 2745 2746 mutex_init(&hdev->mbx_resp.mbx_mutex); 2747 sema_init(&hdev->reset_sem, 1); 2748 2749 spin_lock_init(&hdev->mac_table.mac_list_lock); 2750 INIT_LIST_HEAD(&hdev->mac_table.uc_mac_list); 2751 INIT_LIST_HEAD(&hdev->mac_table.mc_mac_list); 2752 2753 /* bring the device down */ 2754 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2755 } 2756 2757 static void hclgevf_state_uninit(struct hclgevf_dev *hdev) 2758 { 2759 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2760 set_bit(HCLGEVF_STATE_REMOVING, &hdev->state); 2761 2762 if (hdev->service_task.work.func) 2763 cancel_delayed_work_sync(&hdev->service_task); 2764 2765 mutex_destroy(&hdev->mbx_resp.mbx_mutex); 2766 } 2767 2768 static int hclgevf_init_msi(struct hclgevf_dev *hdev) 2769 { 2770 struct pci_dev *pdev = hdev->pdev; 2771 int vectors; 2772 int i; 2773 2774 if (hnae3_dev_roce_supported(hdev)) 2775 vectors = pci_alloc_irq_vectors(pdev, 2776 hdev->roce_base_msix_offset + 1, 2777 hdev->num_msi, 2778 PCI_IRQ_MSIX); 2779 else 2780 vectors = pci_alloc_irq_vectors(pdev, HNAE3_MIN_VECTOR_NUM, 2781 hdev->num_msi, 2782 PCI_IRQ_MSI | PCI_IRQ_MSIX); 2783 2784 if (vectors < 0) { 2785 dev_err(&pdev->dev, 2786 "failed(%d) to allocate MSI/MSI-X vectors\n", 2787 vectors); 2788 return vectors; 2789 } 2790 if (vectors < hdev->num_msi) 2791 dev_warn(&hdev->pdev->dev, 2792 "requested %u MSI/MSI-X, but allocated %d MSI/MSI-X\n", 2793 hdev->num_msi, vectors); 2794 2795 hdev->num_msi = vectors; 2796 hdev->num_msi_left = vectors; 2797 2798 hdev->base_msi_vector = pdev->irq; 2799 hdev->roce_base_vector = pdev->irq + hdev->roce_base_msix_offset; 2800 2801 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 2802 sizeof(u16), GFP_KERNEL); 2803 if (!hdev->vector_status) { 2804 pci_free_irq_vectors(pdev); 2805 return -ENOMEM; 2806 } 2807 2808 for (i = 0; i < hdev->num_msi; i++) 2809 hdev->vector_status[i] = HCLGEVF_INVALID_VPORT; 2810 2811 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 2812 sizeof(int), GFP_KERNEL); 2813 if (!hdev->vector_irq) { 2814 devm_kfree(&pdev->dev, hdev->vector_status); 2815 pci_free_irq_vectors(pdev); 2816 return -ENOMEM; 2817 } 2818 2819 return 0; 2820 } 2821 2822 static void hclgevf_uninit_msi(struct hclgevf_dev *hdev) 2823 { 2824 struct pci_dev *pdev = hdev->pdev; 2825 2826 devm_kfree(&pdev->dev, hdev->vector_status); 2827 devm_kfree(&pdev->dev, hdev->vector_irq); 2828 pci_free_irq_vectors(pdev); 2829 } 2830 2831 static int hclgevf_misc_irq_init(struct hclgevf_dev *hdev) 2832 { 2833 int ret; 2834 2835 hclgevf_get_misc_vector(hdev); 2836 2837 snprintf(hdev->misc_vector.name, HNAE3_INT_NAME_LEN, "%s-misc-%s", 2838 HCLGEVF_NAME, pci_name(hdev->pdev)); 2839 ret = request_irq(hdev->misc_vector.vector_irq, hclgevf_misc_irq_handle, 2840 0, hdev->misc_vector.name, hdev); 2841 if (ret) { 2842 dev_err(&hdev->pdev->dev, "VF failed to request misc irq(%d)\n", 2843 hdev->misc_vector.vector_irq); 2844 return ret; 2845 } 2846 2847 hclgevf_clear_event_cause(hdev, 0); 2848 2849 /* enable misc. vector(vector 0) */ 2850 hclgevf_enable_vector(&hdev->misc_vector, true); 2851 2852 return ret; 2853 } 2854 2855 static void hclgevf_misc_irq_uninit(struct hclgevf_dev *hdev) 2856 { 2857 /* disable misc vector(vector 0) */ 2858 hclgevf_enable_vector(&hdev->misc_vector, false); 2859 synchronize_irq(hdev->misc_vector.vector_irq); 2860 free_irq(hdev->misc_vector.vector_irq, hdev); 2861 hclgevf_free_vector(hdev, 0); 2862 } 2863 2864 static void hclgevf_info_show(struct hclgevf_dev *hdev) 2865 { 2866 struct device *dev = &hdev->pdev->dev; 2867 2868 dev_info(dev, "VF info begin:\n"); 2869 2870 dev_info(dev, "Task queue pairs numbers: %u\n", hdev->num_tqps); 2871 dev_info(dev, "Desc num per TX queue: %u\n", hdev->num_tx_desc); 2872 dev_info(dev, "Desc num per RX queue: %u\n", hdev->num_rx_desc); 2873 dev_info(dev, "Numbers of vports: %u\n", hdev->num_alloc_vport); 2874 dev_info(dev, "HW tc map: 0x%x\n", hdev->hw_tc_map); 2875 dev_info(dev, "PF media type of this VF: %u\n", 2876 hdev->hw.mac.media_type); 2877 2878 dev_info(dev, "VF info end.\n"); 2879 } 2880 2881 static int hclgevf_init_nic_client_instance(struct hnae3_ae_dev *ae_dev, 2882 struct hnae3_client *client) 2883 { 2884 struct hclgevf_dev *hdev = ae_dev->priv; 2885 int rst_cnt = hdev->rst_stats.rst_cnt; 2886 int ret; 2887 2888 ret = client->ops->init_instance(&hdev->nic); 2889 if (ret) 2890 return ret; 2891 2892 set_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 2893 if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) || 2894 rst_cnt != hdev->rst_stats.rst_cnt) { 2895 clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 2896 2897 client->ops->uninit_instance(&hdev->nic, 0); 2898 return -EBUSY; 2899 } 2900 2901 hnae3_set_client_init_flag(client, ae_dev, 1); 2902 2903 if (netif_msg_drv(&hdev->nic)) 2904 hclgevf_info_show(hdev); 2905 2906 return 0; 2907 } 2908 2909 static int hclgevf_init_roce_client_instance(struct hnae3_ae_dev *ae_dev, 2910 struct hnae3_client *client) 2911 { 2912 struct hclgevf_dev *hdev = ae_dev->priv; 2913 int ret; 2914 2915 if (!hnae3_dev_roce_supported(hdev) || !hdev->roce_client || 2916 !hdev->nic_client) 2917 return 0; 2918 2919 ret = hclgevf_init_roce_base_info(hdev); 2920 if (ret) 2921 return ret; 2922 2923 ret = client->ops->init_instance(&hdev->roce); 2924 if (ret) 2925 return ret; 2926 2927 set_bit(HCLGEVF_STATE_ROCE_REGISTERED, &hdev->state); 2928 hnae3_set_client_init_flag(client, ae_dev, 1); 2929 2930 return 0; 2931 } 2932 2933 static int hclgevf_init_client_instance(struct hnae3_client *client, 2934 struct hnae3_ae_dev *ae_dev) 2935 { 2936 struct hclgevf_dev *hdev = ae_dev->priv; 2937 int ret; 2938 2939 switch (client->type) { 2940 case HNAE3_CLIENT_KNIC: 2941 hdev->nic_client = client; 2942 hdev->nic.client = client; 2943 2944 ret = hclgevf_init_nic_client_instance(ae_dev, client); 2945 if (ret) 2946 goto clear_nic; 2947 2948 ret = hclgevf_init_roce_client_instance(ae_dev, 2949 hdev->roce_client); 2950 if (ret) 2951 goto clear_roce; 2952 2953 break; 2954 case HNAE3_CLIENT_ROCE: 2955 if (hnae3_dev_roce_supported(hdev)) { 2956 hdev->roce_client = client; 2957 hdev->roce.client = client; 2958 } 2959 2960 ret = hclgevf_init_roce_client_instance(ae_dev, client); 2961 if (ret) 2962 goto clear_roce; 2963 2964 break; 2965 default: 2966 return -EINVAL; 2967 } 2968 2969 return 0; 2970 2971 clear_nic: 2972 hdev->nic_client = NULL; 2973 hdev->nic.client = NULL; 2974 return ret; 2975 clear_roce: 2976 hdev->roce_client = NULL; 2977 hdev->roce.client = NULL; 2978 return ret; 2979 } 2980 2981 static void hclgevf_uninit_client_instance(struct hnae3_client *client, 2982 struct hnae3_ae_dev *ae_dev) 2983 { 2984 struct hclgevf_dev *hdev = ae_dev->priv; 2985 2986 /* un-init roce, if it exists */ 2987 if (hdev->roce_client) { 2988 clear_bit(HCLGEVF_STATE_ROCE_REGISTERED, &hdev->state); 2989 hdev->roce_client->ops->uninit_instance(&hdev->roce, 0); 2990 hdev->roce_client = NULL; 2991 hdev->roce.client = NULL; 2992 } 2993 2994 /* un-init nic/unic, if this was not called by roce client */ 2995 if (client->ops->uninit_instance && hdev->nic_client && 2996 client->type != HNAE3_CLIENT_ROCE) { 2997 clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 2998 2999 client->ops->uninit_instance(&hdev->nic, 0); 3000 hdev->nic_client = NULL; 3001 hdev->nic.client = NULL; 3002 } 3003 } 3004 3005 static int hclgevf_dev_mem_map(struct hclgevf_dev *hdev) 3006 { 3007 #define HCLGEVF_MEM_BAR 4 3008 3009 struct pci_dev *pdev = hdev->pdev; 3010 struct hclgevf_hw *hw = &hdev->hw; 3011 3012 /* for device does not have device memory, return directly */ 3013 if (!(pci_select_bars(pdev, IORESOURCE_MEM) & BIT(HCLGEVF_MEM_BAR))) 3014 return 0; 3015 3016 hw->mem_base = devm_ioremap_wc(&pdev->dev, 3017 pci_resource_start(pdev, 3018 HCLGEVF_MEM_BAR), 3019 pci_resource_len(pdev, HCLGEVF_MEM_BAR)); 3020 if (!hw->mem_base) { 3021 dev_err(&pdev->dev, "failed to map device memory\n"); 3022 return -EFAULT; 3023 } 3024 3025 return 0; 3026 } 3027 3028 static int hclgevf_pci_init(struct hclgevf_dev *hdev) 3029 { 3030 struct pci_dev *pdev = hdev->pdev; 3031 struct hclgevf_hw *hw; 3032 int ret; 3033 3034 ret = pci_enable_device(pdev); 3035 if (ret) { 3036 dev_err(&pdev->dev, "failed to enable PCI device\n"); 3037 return ret; 3038 } 3039 3040 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 3041 if (ret) { 3042 dev_err(&pdev->dev, "can't set consistent PCI DMA, exiting"); 3043 goto err_disable_device; 3044 } 3045 3046 ret = pci_request_regions(pdev, HCLGEVF_DRIVER_NAME); 3047 if (ret) { 3048 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 3049 goto err_disable_device; 3050 } 3051 3052 pci_set_master(pdev); 3053 hw = &hdev->hw; 3054 hw->hdev = hdev; 3055 hw->io_base = pci_iomap(pdev, 2, 0); 3056 if (!hw->io_base) { 3057 dev_err(&pdev->dev, "can't map configuration register space\n"); 3058 ret = -ENOMEM; 3059 goto err_clr_master; 3060 } 3061 3062 ret = hclgevf_dev_mem_map(hdev); 3063 if (ret) 3064 goto err_unmap_io_base; 3065 3066 return 0; 3067 3068 err_unmap_io_base: 3069 pci_iounmap(pdev, hdev->hw.io_base); 3070 err_clr_master: 3071 pci_clear_master(pdev); 3072 pci_release_regions(pdev); 3073 err_disable_device: 3074 pci_disable_device(pdev); 3075 3076 return ret; 3077 } 3078 3079 static void hclgevf_pci_uninit(struct hclgevf_dev *hdev) 3080 { 3081 struct pci_dev *pdev = hdev->pdev; 3082 3083 if (hdev->hw.mem_base) 3084 devm_iounmap(&pdev->dev, hdev->hw.mem_base); 3085 3086 pci_iounmap(pdev, hdev->hw.io_base); 3087 pci_clear_master(pdev); 3088 pci_release_regions(pdev); 3089 pci_disable_device(pdev); 3090 } 3091 3092 static int hclgevf_query_vf_resource(struct hclgevf_dev *hdev) 3093 { 3094 struct hclgevf_query_res_cmd *req; 3095 struct hclgevf_desc desc; 3096 int ret; 3097 3098 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_VF_RSRC, true); 3099 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 3100 if (ret) { 3101 dev_err(&hdev->pdev->dev, 3102 "query vf resource failed, ret = %d.\n", ret); 3103 return ret; 3104 } 3105 3106 req = (struct hclgevf_query_res_cmd *)desc.data; 3107 3108 if (hnae3_dev_roce_supported(hdev)) { 3109 hdev->roce_base_msix_offset = 3110 hnae3_get_field(le16_to_cpu(req->msixcap_localid_ba_rocee), 3111 HCLGEVF_MSIX_OFT_ROCEE_M, 3112 HCLGEVF_MSIX_OFT_ROCEE_S); 3113 hdev->num_roce_msix = 3114 hnae3_get_field(le16_to_cpu(req->vf_intr_vector_number), 3115 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 3116 3117 /* nic's msix numbers is always equals to the roce's. */ 3118 hdev->num_nic_msix = hdev->num_roce_msix; 3119 3120 /* VF should have NIC vectors and Roce vectors, NIC vectors 3121 * are queued before Roce vectors. The offset is fixed to 64. 3122 */ 3123 hdev->num_msi = hdev->num_roce_msix + 3124 hdev->roce_base_msix_offset; 3125 } else { 3126 hdev->num_msi = 3127 hnae3_get_field(le16_to_cpu(req->vf_intr_vector_number), 3128 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 3129 3130 hdev->num_nic_msix = hdev->num_msi; 3131 } 3132 3133 if (hdev->num_nic_msix < HNAE3_MIN_VECTOR_NUM) { 3134 dev_err(&hdev->pdev->dev, 3135 "Just %u msi resources, not enough for vf(min:2).\n", 3136 hdev->num_nic_msix); 3137 return -EINVAL; 3138 } 3139 3140 return 0; 3141 } 3142 3143 static void hclgevf_set_default_dev_specs(struct hclgevf_dev *hdev) 3144 { 3145 #define HCLGEVF_MAX_NON_TSO_BD_NUM 8U 3146 3147 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 3148 3149 ae_dev->dev_specs.max_non_tso_bd_num = 3150 HCLGEVF_MAX_NON_TSO_BD_NUM; 3151 ae_dev->dev_specs.rss_ind_tbl_size = HCLGEVF_RSS_IND_TBL_SIZE; 3152 ae_dev->dev_specs.rss_key_size = HCLGEVF_RSS_KEY_SIZE; 3153 ae_dev->dev_specs.max_int_gl = HCLGEVF_DEF_MAX_INT_GL; 3154 ae_dev->dev_specs.max_frm_size = HCLGEVF_MAC_MAX_FRAME; 3155 } 3156 3157 static void hclgevf_parse_dev_specs(struct hclgevf_dev *hdev, 3158 struct hclgevf_desc *desc) 3159 { 3160 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 3161 struct hclgevf_dev_specs_0_cmd *req0; 3162 struct hclgevf_dev_specs_1_cmd *req1; 3163 3164 req0 = (struct hclgevf_dev_specs_0_cmd *)desc[0].data; 3165 req1 = (struct hclgevf_dev_specs_1_cmd *)desc[1].data; 3166 3167 ae_dev->dev_specs.max_non_tso_bd_num = req0->max_non_tso_bd_num; 3168 ae_dev->dev_specs.rss_ind_tbl_size = 3169 le16_to_cpu(req0->rss_ind_tbl_size); 3170 ae_dev->dev_specs.int_ql_max = le16_to_cpu(req0->int_ql_max); 3171 ae_dev->dev_specs.rss_key_size = le16_to_cpu(req0->rss_key_size); 3172 ae_dev->dev_specs.max_int_gl = le16_to_cpu(req1->max_int_gl); 3173 ae_dev->dev_specs.max_frm_size = le16_to_cpu(req1->max_frm_size); 3174 } 3175 3176 static void hclgevf_check_dev_specs(struct hclgevf_dev *hdev) 3177 { 3178 struct hnae3_dev_specs *dev_specs = &hdev->ae_dev->dev_specs; 3179 3180 if (!dev_specs->max_non_tso_bd_num) 3181 dev_specs->max_non_tso_bd_num = HCLGEVF_MAX_NON_TSO_BD_NUM; 3182 if (!dev_specs->rss_ind_tbl_size) 3183 dev_specs->rss_ind_tbl_size = HCLGEVF_RSS_IND_TBL_SIZE; 3184 if (!dev_specs->rss_key_size) 3185 dev_specs->rss_key_size = HCLGEVF_RSS_KEY_SIZE; 3186 if (!dev_specs->max_int_gl) 3187 dev_specs->max_int_gl = HCLGEVF_DEF_MAX_INT_GL; 3188 if (!dev_specs->max_frm_size) 3189 dev_specs->max_frm_size = HCLGEVF_MAC_MAX_FRAME; 3190 } 3191 3192 static int hclgevf_query_dev_specs(struct hclgevf_dev *hdev) 3193 { 3194 struct hclgevf_desc desc[HCLGEVF_QUERY_DEV_SPECS_BD_NUM]; 3195 int ret; 3196 int i; 3197 3198 /* set default specifications as devices lower than version V3 do not 3199 * support querying specifications from firmware. 3200 */ 3201 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3) { 3202 hclgevf_set_default_dev_specs(hdev); 3203 return 0; 3204 } 3205 3206 for (i = 0; i < HCLGEVF_QUERY_DEV_SPECS_BD_NUM - 1; i++) { 3207 hclgevf_cmd_setup_basic_desc(&desc[i], 3208 HCLGEVF_OPC_QUERY_DEV_SPECS, true); 3209 desc[i].flag |= cpu_to_le16(HCLGEVF_CMD_FLAG_NEXT); 3210 } 3211 hclgevf_cmd_setup_basic_desc(&desc[i], HCLGEVF_OPC_QUERY_DEV_SPECS, 3212 true); 3213 3214 ret = hclgevf_cmd_send(&hdev->hw, desc, HCLGEVF_QUERY_DEV_SPECS_BD_NUM); 3215 if (ret) 3216 return ret; 3217 3218 hclgevf_parse_dev_specs(hdev, desc); 3219 hclgevf_check_dev_specs(hdev); 3220 3221 return 0; 3222 } 3223 3224 static int hclgevf_pci_reset(struct hclgevf_dev *hdev) 3225 { 3226 struct pci_dev *pdev = hdev->pdev; 3227 int ret = 0; 3228 3229 if (hdev->reset_type == HNAE3_VF_FULL_RESET && 3230 test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 3231 hclgevf_misc_irq_uninit(hdev); 3232 hclgevf_uninit_msi(hdev); 3233 clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 3234 } 3235 3236 if (!test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 3237 pci_set_master(pdev); 3238 ret = hclgevf_init_msi(hdev); 3239 if (ret) { 3240 dev_err(&pdev->dev, 3241 "failed(%d) to init MSI/MSI-X\n", ret); 3242 return ret; 3243 } 3244 3245 ret = hclgevf_misc_irq_init(hdev); 3246 if (ret) { 3247 hclgevf_uninit_msi(hdev); 3248 dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 3249 ret); 3250 return ret; 3251 } 3252 3253 set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 3254 } 3255 3256 return ret; 3257 } 3258 3259 static int hclgevf_clear_vport_list(struct hclgevf_dev *hdev) 3260 { 3261 struct hclge_vf_to_pf_msg send_msg; 3262 3263 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_HANDLE_VF_TBL, 3264 HCLGE_MBX_VPORT_LIST_CLEAR); 3265 return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 3266 } 3267 3268 static void hclgevf_init_rxd_adv_layout(struct hclgevf_dev *hdev) 3269 { 3270 if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev)) 3271 hclgevf_write_dev(&hdev->hw, HCLGEVF_RXD_ADV_LAYOUT_EN_REG, 1); 3272 } 3273 3274 static void hclgevf_uninit_rxd_adv_layout(struct hclgevf_dev *hdev) 3275 { 3276 if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev)) 3277 hclgevf_write_dev(&hdev->hw, HCLGEVF_RXD_ADV_LAYOUT_EN_REG, 0); 3278 } 3279 3280 static int hclgevf_reset_hdev(struct hclgevf_dev *hdev) 3281 { 3282 struct pci_dev *pdev = hdev->pdev; 3283 int ret; 3284 3285 ret = hclgevf_pci_reset(hdev); 3286 if (ret) { 3287 dev_err(&pdev->dev, "pci reset failed %d\n", ret); 3288 return ret; 3289 } 3290 3291 ret = hclgevf_cmd_init(hdev); 3292 if (ret) { 3293 dev_err(&pdev->dev, "cmd failed %d\n", ret); 3294 return ret; 3295 } 3296 3297 ret = hclgevf_rss_init_hw(hdev); 3298 if (ret) { 3299 dev_err(&hdev->pdev->dev, 3300 "failed(%d) to initialize RSS\n", ret); 3301 return ret; 3302 } 3303 3304 ret = hclgevf_config_gro(hdev, true); 3305 if (ret) 3306 return ret; 3307 3308 ret = hclgevf_init_vlan_config(hdev); 3309 if (ret) { 3310 dev_err(&hdev->pdev->dev, 3311 "failed(%d) to initialize VLAN config\n", ret); 3312 return ret; 3313 } 3314 3315 set_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state); 3316 3317 hclgevf_init_rxd_adv_layout(hdev); 3318 3319 dev_info(&hdev->pdev->dev, "Reset done\n"); 3320 3321 return 0; 3322 } 3323 3324 static int hclgevf_init_hdev(struct hclgevf_dev *hdev) 3325 { 3326 struct pci_dev *pdev = hdev->pdev; 3327 int ret; 3328 3329 ret = hclgevf_pci_init(hdev); 3330 if (ret) 3331 return ret; 3332 3333 ret = hclgevf_cmd_queue_init(hdev); 3334 if (ret) 3335 goto err_cmd_queue_init; 3336 3337 ret = hclgevf_cmd_init(hdev); 3338 if (ret) 3339 goto err_cmd_init; 3340 3341 /* Get vf resource */ 3342 ret = hclgevf_query_vf_resource(hdev); 3343 if (ret) 3344 goto err_cmd_init; 3345 3346 ret = hclgevf_query_dev_specs(hdev); 3347 if (ret) { 3348 dev_err(&pdev->dev, 3349 "failed to query dev specifications, ret = %d\n", ret); 3350 goto err_cmd_init; 3351 } 3352 3353 ret = hclgevf_init_msi(hdev); 3354 if (ret) { 3355 dev_err(&pdev->dev, "failed(%d) to init MSI/MSI-X\n", ret); 3356 goto err_cmd_init; 3357 } 3358 3359 hclgevf_state_init(hdev); 3360 hdev->reset_level = HNAE3_VF_FUNC_RESET; 3361 hdev->reset_type = HNAE3_NONE_RESET; 3362 3363 ret = hclgevf_misc_irq_init(hdev); 3364 if (ret) 3365 goto err_misc_irq_init; 3366 3367 set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 3368 3369 ret = hclgevf_configure(hdev); 3370 if (ret) { 3371 dev_err(&pdev->dev, "failed(%d) to fetch configuration\n", ret); 3372 goto err_config; 3373 } 3374 3375 ret = hclgevf_alloc_tqps(hdev); 3376 if (ret) { 3377 dev_err(&pdev->dev, "failed(%d) to allocate TQPs\n", ret); 3378 goto err_config; 3379 } 3380 3381 ret = hclgevf_set_handle_info(hdev); 3382 if (ret) 3383 goto err_config; 3384 3385 ret = hclgevf_config_gro(hdev, true); 3386 if (ret) 3387 goto err_config; 3388 3389 /* Initialize RSS for this VF */ 3390 ret = hclgevf_rss_init_cfg(hdev); 3391 if (ret) { 3392 dev_err(&pdev->dev, "failed to init rss cfg, ret = %d\n", ret); 3393 goto err_config; 3394 } 3395 3396 ret = hclgevf_rss_init_hw(hdev); 3397 if (ret) { 3398 dev_err(&hdev->pdev->dev, 3399 "failed(%d) to initialize RSS\n", ret); 3400 goto err_config; 3401 } 3402 3403 /* ensure vf tbl list as empty before init*/ 3404 ret = hclgevf_clear_vport_list(hdev); 3405 if (ret) { 3406 dev_err(&pdev->dev, 3407 "failed to clear tbl list configuration, ret = %d.\n", 3408 ret); 3409 goto err_config; 3410 } 3411 3412 ret = hclgevf_init_vlan_config(hdev); 3413 if (ret) { 3414 dev_err(&hdev->pdev->dev, 3415 "failed(%d) to initialize VLAN config\n", ret); 3416 goto err_config; 3417 } 3418 3419 hclgevf_init_rxd_adv_layout(hdev); 3420 3421 hdev->last_reset_time = jiffies; 3422 dev_info(&hdev->pdev->dev, "finished initializing %s driver\n", 3423 HCLGEVF_DRIVER_NAME); 3424 3425 hclgevf_task_schedule(hdev, round_jiffies_relative(HZ)); 3426 3427 return 0; 3428 3429 err_config: 3430 hclgevf_misc_irq_uninit(hdev); 3431 err_misc_irq_init: 3432 hclgevf_state_uninit(hdev); 3433 hclgevf_uninit_msi(hdev); 3434 err_cmd_init: 3435 hclgevf_cmd_uninit(hdev); 3436 err_cmd_queue_init: 3437 hclgevf_pci_uninit(hdev); 3438 clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 3439 return ret; 3440 } 3441 3442 static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev) 3443 { 3444 struct hclge_vf_to_pf_msg send_msg; 3445 3446 hclgevf_state_uninit(hdev); 3447 hclgevf_uninit_rxd_adv_layout(hdev); 3448 3449 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_VF_UNINIT, 0); 3450 hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 3451 3452 if (test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 3453 hclgevf_misc_irq_uninit(hdev); 3454 hclgevf_uninit_msi(hdev); 3455 } 3456 3457 hclgevf_cmd_uninit(hdev); 3458 hclgevf_pci_uninit(hdev); 3459 hclgevf_uninit_mac_list(hdev); 3460 } 3461 3462 static int hclgevf_init_ae_dev(struct hnae3_ae_dev *ae_dev) 3463 { 3464 struct pci_dev *pdev = ae_dev->pdev; 3465 int ret; 3466 3467 ret = hclgevf_alloc_hdev(ae_dev); 3468 if (ret) { 3469 dev_err(&pdev->dev, "hclge device allocation failed\n"); 3470 return ret; 3471 } 3472 3473 ret = hclgevf_init_hdev(ae_dev->priv); 3474 if (ret) { 3475 dev_err(&pdev->dev, "hclge device initialization failed\n"); 3476 return ret; 3477 } 3478 3479 return 0; 3480 } 3481 3482 static void hclgevf_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 3483 { 3484 struct hclgevf_dev *hdev = ae_dev->priv; 3485 3486 hclgevf_uninit_hdev(hdev); 3487 ae_dev->priv = NULL; 3488 } 3489 3490 static u32 hclgevf_get_max_channels(struct hclgevf_dev *hdev) 3491 { 3492 struct hnae3_handle *nic = &hdev->nic; 3493 struct hnae3_knic_private_info *kinfo = &nic->kinfo; 3494 3495 return min_t(u32, hdev->rss_size_max, 3496 hdev->num_tqps / kinfo->tc_info.num_tc); 3497 } 3498 3499 /** 3500 * hclgevf_get_channels - Get the current channels enabled and max supported. 3501 * @handle: hardware information for network interface 3502 * @ch: ethtool channels structure 3503 * 3504 * We don't support separate tx and rx queues as channels. The other count 3505 * represents how many queues are being used for control. max_combined counts 3506 * how many queue pairs we can support. They may not be mapped 1 to 1 with 3507 * q_vectors since we support a lot more queue pairs than q_vectors. 3508 **/ 3509 static void hclgevf_get_channels(struct hnae3_handle *handle, 3510 struct ethtool_channels *ch) 3511 { 3512 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3513 3514 ch->max_combined = hclgevf_get_max_channels(hdev); 3515 ch->other_count = 0; 3516 ch->max_other = 0; 3517 ch->combined_count = handle->kinfo.rss_size; 3518 } 3519 3520 static void hclgevf_get_tqps_and_rss_info(struct hnae3_handle *handle, 3521 u16 *alloc_tqps, u16 *max_rss_size) 3522 { 3523 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3524 3525 *alloc_tqps = hdev->num_tqps; 3526 *max_rss_size = hdev->rss_size_max; 3527 } 3528 3529 static void hclgevf_update_rss_size(struct hnae3_handle *handle, 3530 u32 new_tqps_num) 3531 { 3532 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 3533 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3534 u16 max_rss_size; 3535 3536 kinfo->req_rss_size = new_tqps_num; 3537 3538 max_rss_size = min_t(u16, hdev->rss_size_max, 3539 hdev->num_tqps / kinfo->tc_info.num_tc); 3540 3541 /* Use the user's configuration when it is not larger than 3542 * max_rss_size, otherwise, use the maximum specification value. 3543 */ 3544 if (kinfo->req_rss_size != kinfo->rss_size && kinfo->req_rss_size && 3545 kinfo->req_rss_size <= max_rss_size) 3546 kinfo->rss_size = kinfo->req_rss_size; 3547 else if (kinfo->rss_size > max_rss_size || 3548 (!kinfo->req_rss_size && kinfo->rss_size < max_rss_size)) 3549 kinfo->rss_size = max_rss_size; 3550 3551 kinfo->num_tqps = kinfo->tc_info.num_tc * kinfo->rss_size; 3552 } 3553 3554 static int hclgevf_set_channels(struct hnae3_handle *handle, u32 new_tqps_num, 3555 bool rxfh_configured) 3556 { 3557 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3558 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 3559 u16 cur_rss_size = kinfo->rss_size; 3560 u16 cur_tqps = kinfo->num_tqps; 3561 u32 *rss_indir; 3562 unsigned int i; 3563 int ret; 3564 3565 hclgevf_update_rss_size(handle, new_tqps_num); 3566 3567 ret = hclgevf_set_rss_tc_mode(hdev, kinfo->rss_size); 3568 if (ret) 3569 return ret; 3570 3571 /* RSS indirection table has been configured by user */ 3572 if (rxfh_configured) 3573 goto out; 3574 3575 /* Reinitializes the rss indirect table according to the new RSS size */ 3576 rss_indir = kcalloc(hdev->ae_dev->dev_specs.rss_ind_tbl_size, 3577 sizeof(u32), GFP_KERNEL); 3578 if (!rss_indir) 3579 return -ENOMEM; 3580 3581 for (i = 0; i < hdev->ae_dev->dev_specs.rss_ind_tbl_size; i++) 3582 rss_indir[i] = i % kinfo->rss_size; 3583 3584 hdev->rss_cfg.rss_size = kinfo->rss_size; 3585 3586 ret = hclgevf_set_rss(handle, rss_indir, NULL, 0); 3587 if (ret) 3588 dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n", 3589 ret); 3590 3591 kfree(rss_indir); 3592 3593 out: 3594 if (!ret) 3595 dev_info(&hdev->pdev->dev, 3596 "Channels changed, rss_size from %u to %u, tqps from %u to %u", 3597 cur_rss_size, kinfo->rss_size, 3598 cur_tqps, kinfo->rss_size * kinfo->tc_info.num_tc); 3599 3600 return ret; 3601 } 3602 3603 static int hclgevf_get_status(struct hnae3_handle *handle) 3604 { 3605 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3606 3607 return hdev->hw.mac.link; 3608 } 3609 3610 static void hclgevf_get_ksettings_an_result(struct hnae3_handle *handle, 3611 u8 *auto_neg, u32 *speed, 3612 u8 *duplex) 3613 { 3614 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3615 3616 if (speed) 3617 *speed = hdev->hw.mac.speed; 3618 if (duplex) 3619 *duplex = hdev->hw.mac.duplex; 3620 if (auto_neg) 3621 *auto_neg = AUTONEG_DISABLE; 3622 } 3623 3624 void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed, 3625 u8 duplex) 3626 { 3627 hdev->hw.mac.speed = speed; 3628 hdev->hw.mac.duplex = duplex; 3629 } 3630 3631 static int hclgevf_gro_en(struct hnae3_handle *handle, bool enable) 3632 { 3633 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3634 3635 return hclgevf_config_gro(hdev, enable); 3636 } 3637 3638 static void hclgevf_get_media_type(struct hnae3_handle *handle, u8 *media_type, 3639 u8 *module_type) 3640 { 3641 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3642 3643 if (media_type) 3644 *media_type = hdev->hw.mac.media_type; 3645 3646 if (module_type) 3647 *module_type = hdev->hw.mac.module_type; 3648 } 3649 3650 static bool hclgevf_get_hw_reset_stat(struct hnae3_handle *handle) 3651 { 3652 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3653 3654 return !!hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 3655 } 3656 3657 static bool hclgevf_get_cmdq_stat(struct hnae3_handle *handle) 3658 { 3659 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3660 3661 return test_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 3662 } 3663 3664 static bool hclgevf_ae_dev_resetting(struct hnae3_handle *handle) 3665 { 3666 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3667 3668 return test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 3669 } 3670 3671 static unsigned long hclgevf_ae_dev_reset_cnt(struct hnae3_handle *handle) 3672 { 3673 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3674 3675 return hdev->rst_stats.hw_rst_done_cnt; 3676 } 3677 3678 static void hclgevf_get_link_mode(struct hnae3_handle *handle, 3679 unsigned long *supported, 3680 unsigned long *advertising) 3681 { 3682 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3683 3684 *supported = hdev->hw.mac.supported; 3685 *advertising = hdev->hw.mac.advertising; 3686 } 3687 3688 #define MAX_SEPARATE_NUM 4 3689 #define SEPARATOR_VALUE 0xFDFCFBFA 3690 #define REG_NUM_PER_LINE 4 3691 #define REG_LEN_PER_LINE (REG_NUM_PER_LINE * sizeof(u32)) 3692 3693 static int hclgevf_get_regs_len(struct hnae3_handle *handle) 3694 { 3695 int cmdq_lines, common_lines, ring_lines, tqp_intr_lines; 3696 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3697 3698 cmdq_lines = sizeof(cmdq_reg_addr_list) / REG_LEN_PER_LINE + 1; 3699 common_lines = sizeof(common_reg_addr_list) / REG_LEN_PER_LINE + 1; 3700 ring_lines = sizeof(ring_reg_addr_list) / REG_LEN_PER_LINE + 1; 3701 tqp_intr_lines = sizeof(tqp_intr_reg_addr_list) / REG_LEN_PER_LINE + 1; 3702 3703 return (cmdq_lines + common_lines + ring_lines * hdev->num_tqps + 3704 tqp_intr_lines * (hdev->num_msi_used - 1)) * REG_LEN_PER_LINE; 3705 } 3706 3707 static void hclgevf_get_regs(struct hnae3_handle *handle, u32 *version, 3708 void *data) 3709 { 3710 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3711 int i, j, reg_um, separator_num; 3712 u32 *reg = data; 3713 3714 *version = hdev->fw_version; 3715 3716 /* fetching per-VF registers values from VF PCIe register space */ 3717 reg_um = sizeof(cmdq_reg_addr_list) / sizeof(u32); 3718 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 3719 for (i = 0; i < reg_um; i++) 3720 *reg++ = hclgevf_read_dev(&hdev->hw, cmdq_reg_addr_list[i]); 3721 for (i = 0; i < separator_num; i++) 3722 *reg++ = SEPARATOR_VALUE; 3723 3724 reg_um = sizeof(common_reg_addr_list) / sizeof(u32); 3725 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 3726 for (i = 0; i < reg_um; i++) 3727 *reg++ = hclgevf_read_dev(&hdev->hw, common_reg_addr_list[i]); 3728 for (i = 0; i < separator_num; i++) 3729 *reg++ = SEPARATOR_VALUE; 3730 3731 reg_um = sizeof(ring_reg_addr_list) / sizeof(u32); 3732 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 3733 for (j = 0; j < hdev->num_tqps; j++) { 3734 for (i = 0; i < reg_um; i++) 3735 *reg++ = hclgevf_read_dev(&hdev->hw, 3736 ring_reg_addr_list[i] + 3737 0x200 * j); 3738 for (i = 0; i < separator_num; i++) 3739 *reg++ = SEPARATOR_VALUE; 3740 } 3741 3742 reg_um = sizeof(tqp_intr_reg_addr_list) / sizeof(u32); 3743 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 3744 for (j = 0; j < hdev->num_msi_used - 1; j++) { 3745 for (i = 0; i < reg_um; i++) 3746 *reg++ = hclgevf_read_dev(&hdev->hw, 3747 tqp_intr_reg_addr_list[i] + 3748 4 * j); 3749 for (i = 0; i < separator_num; i++) 3750 *reg++ = SEPARATOR_VALUE; 3751 } 3752 } 3753 3754 void hclgevf_update_port_base_vlan_info(struct hclgevf_dev *hdev, u16 state, 3755 u8 *port_base_vlan_info, u8 data_size) 3756 { 3757 struct hnae3_handle *nic = &hdev->nic; 3758 struct hclge_vf_to_pf_msg send_msg; 3759 int ret; 3760 3761 rtnl_lock(); 3762 3763 if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) || 3764 test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) { 3765 dev_warn(&hdev->pdev->dev, 3766 "is resetting when updating port based vlan info\n"); 3767 rtnl_unlock(); 3768 return; 3769 } 3770 3771 ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 3772 if (ret) { 3773 rtnl_unlock(); 3774 return; 3775 } 3776 3777 /* send msg to PF and wait update port based vlan info */ 3778 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 3779 HCLGE_MBX_PORT_BASE_VLAN_CFG); 3780 memcpy(send_msg.data, port_base_vlan_info, data_size); 3781 ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 3782 if (!ret) { 3783 if (state == HNAE3_PORT_BASE_VLAN_DISABLE) 3784 nic->port_base_vlan_state = state; 3785 else 3786 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_ENABLE; 3787 } 3788 3789 hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 3790 rtnl_unlock(); 3791 } 3792 3793 static const struct hnae3_ae_ops hclgevf_ops = { 3794 .init_ae_dev = hclgevf_init_ae_dev, 3795 .uninit_ae_dev = hclgevf_uninit_ae_dev, 3796 .reset_prepare = hclgevf_reset_prepare_general, 3797 .reset_done = hclgevf_reset_done, 3798 .init_client_instance = hclgevf_init_client_instance, 3799 .uninit_client_instance = hclgevf_uninit_client_instance, 3800 .start = hclgevf_ae_start, 3801 .stop = hclgevf_ae_stop, 3802 .client_start = hclgevf_client_start, 3803 .client_stop = hclgevf_client_stop, 3804 .map_ring_to_vector = hclgevf_map_ring_to_vector, 3805 .unmap_ring_from_vector = hclgevf_unmap_ring_from_vector, 3806 .get_vector = hclgevf_get_vector, 3807 .put_vector = hclgevf_put_vector, 3808 .reset_queue = hclgevf_reset_tqp, 3809 .get_mac_addr = hclgevf_get_mac_addr, 3810 .set_mac_addr = hclgevf_set_mac_addr, 3811 .add_uc_addr = hclgevf_add_uc_addr, 3812 .rm_uc_addr = hclgevf_rm_uc_addr, 3813 .add_mc_addr = hclgevf_add_mc_addr, 3814 .rm_mc_addr = hclgevf_rm_mc_addr, 3815 .get_stats = hclgevf_get_stats, 3816 .update_stats = hclgevf_update_stats, 3817 .get_strings = hclgevf_get_strings, 3818 .get_sset_count = hclgevf_get_sset_count, 3819 .get_rss_key_size = hclgevf_get_rss_key_size, 3820 .get_rss = hclgevf_get_rss, 3821 .set_rss = hclgevf_set_rss, 3822 .get_rss_tuple = hclgevf_get_rss_tuple, 3823 .set_rss_tuple = hclgevf_set_rss_tuple, 3824 .get_tc_size = hclgevf_get_tc_size, 3825 .get_fw_version = hclgevf_get_fw_version, 3826 .set_vlan_filter = hclgevf_set_vlan_filter, 3827 .enable_vlan_filter = hclgevf_enable_vlan_filter, 3828 .enable_hw_strip_rxvtag = hclgevf_en_hw_strip_rxvtag, 3829 .reset_event = hclgevf_reset_event, 3830 .set_default_reset_request = hclgevf_set_def_reset_request, 3831 .set_channels = hclgevf_set_channels, 3832 .get_channels = hclgevf_get_channels, 3833 .get_tqps_and_rss_info = hclgevf_get_tqps_and_rss_info, 3834 .get_regs_len = hclgevf_get_regs_len, 3835 .get_regs = hclgevf_get_regs, 3836 .get_status = hclgevf_get_status, 3837 .get_ksettings_an_result = hclgevf_get_ksettings_an_result, 3838 .get_media_type = hclgevf_get_media_type, 3839 .get_hw_reset_stat = hclgevf_get_hw_reset_stat, 3840 .ae_dev_resetting = hclgevf_ae_dev_resetting, 3841 .ae_dev_reset_cnt = hclgevf_ae_dev_reset_cnt, 3842 .set_gro_en = hclgevf_gro_en, 3843 .set_mtu = hclgevf_set_mtu, 3844 .get_global_queue_id = hclgevf_get_qid_global, 3845 .set_timer_task = hclgevf_set_timer_task, 3846 .get_link_mode = hclgevf_get_link_mode, 3847 .set_promisc_mode = hclgevf_set_promisc_mode, 3848 .request_update_promisc_mode = hclgevf_request_update_promisc_mode, 3849 .get_cmdq_stat = hclgevf_get_cmdq_stat, 3850 }; 3851 3852 static struct hnae3_ae_algo ae_algovf = { 3853 .ops = &hclgevf_ops, 3854 .pdev_id_table = ae_algovf_pci_tbl, 3855 }; 3856 3857 static int hclgevf_init(void) 3858 { 3859 pr_info("%s is initializing\n", HCLGEVF_NAME); 3860 3861 hclgevf_wq = alloc_workqueue("%s", 0, 0, HCLGEVF_NAME); 3862 if (!hclgevf_wq) { 3863 pr_err("%s: failed to create workqueue\n", HCLGEVF_NAME); 3864 return -ENOMEM; 3865 } 3866 3867 hnae3_register_ae_algo(&ae_algovf); 3868 3869 return 0; 3870 } 3871 3872 static void hclgevf_exit(void) 3873 { 3874 hnae3_unregister_ae_algo(&ae_algovf); 3875 destroy_workqueue(hclgevf_wq); 3876 } 3877 module_init(hclgevf_init); 3878 module_exit(hclgevf_exit); 3879 3880 MODULE_LICENSE("GPL"); 3881 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 3882 MODULE_DESCRIPTION("HCLGEVF Driver"); 3883 MODULE_VERSION(HCLGEVF_MOD_VERSION); 3884