1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/etherdevice.h> 5 #include <linux/iopoll.h> 6 #include <net/rtnetlink.h> 7 #include "hclgevf_cmd.h" 8 #include "hclgevf_main.h" 9 #include "hclge_mbx.h" 10 #include "hnae3.h" 11 12 #define HCLGEVF_NAME "hclgevf" 13 14 #define HCLGEVF_RESET_MAX_FAIL_CNT 5 15 16 static int hclgevf_reset_hdev(struct hclgevf_dev *hdev); 17 static struct hnae3_ae_algo ae_algovf; 18 19 static const struct pci_device_id ae_algovf_pci_tbl[] = { 20 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0}, 21 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF), 0}, 22 /* required last entry */ 23 {0, } 24 }; 25 26 static const u8 hclgevf_hash_key[] = { 27 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2, 28 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0, 29 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4, 30 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C, 31 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA 32 }; 33 34 MODULE_DEVICE_TABLE(pci, ae_algovf_pci_tbl); 35 36 static const u32 cmdq_reg_addr_list[] = {HCLGEVF_CMDQ_TX_ADDR_L_REG, 37 HCLGEVF_CMDQ_TX_ADDR_H_REG, 38 HCLGEVF_CMDQ_TX_DEPTH_REG, 39 HCLGEVF_CMDQ_TX_TAIL_REG, 40 HCLGEVF_CMDQ_TX_HEAD_REG, 41 HCLGEVF_CMDQ_RX_ADDR_L_REG, 42 HCLGEVF_CMDQ_RX_ADDR_H_REG, 43 HCLGEVF_CMDQ_RX_DEPTH_REG, 44 HCLGEVF_CMDQ_RX_TAIL_REG, 45 HCLGEVF_CMDQ_RX_HEAD_REG, 46 HCLGEVF_VECTOR0_CMDQ_SRC_REG, 47 HCLGEVF_CMDQ_INTR_STS_REG, 48 HCLGEVF_CMDQ_INTR_EN_REG, 49 HCLGEVF_CMDQ_INTR_GEN_REG}; 50 51 static const u32 common_reg_addr_list[] = {HCLGEVF_MISC_VECTOR_REG_BASE, 52 HCLGEVF_RST_ING, 53 HCLGEVF_GRO_EN_REG}; 54 55 static const u32 ring_reg_addr_list[] = {HCLGEVF_RING_RX_ADDR_L_REG, 56 HCLGEVF_RING_RX_ADDR_H_REG, 57 HCLGEVF_RING_RX_BD_NUM_REG, 58 HCLGEVF_RING_RX_BD_LENGTH_REG, 59 HCLGEVF_RING_RX_MERGE_EN_REG, 60 HCLGEVF_RING_RX_TAIL_REG, 61 HCLGEVF_RING_RX_HEAD_REG, 62 HCLGEVF_RING_RX_FBD_NUM_REG, 63 HCLGEVF_RING_RX_OFFSET_REG, 64 HCLGEVF_RING_RX_FBD_OFFSET_REG, 65 HCLGEVF_RING_RX_STASH_REG, 66 HCLGEVF_RING_RX_BD_ERR_REG, 67 HCLGEVF_RING_TX_ADDR_L_REG, 68 HCLGEVF_RING_TX_ADDR_H_REG, 69 HCLGEVF_RING_TX_BD_NUM_REG, 70 HCLGEVF_RING_TX_PRIORITY_REG, 71 HCLGEVF_RING_TX_TC_REG, 72 HCLGEVF_RING_TX_MERGE_EN_REG, 73 HCLGEVF_RING_TX_TAIL_REG, 74 HCLGEVF_RING_TX_HEAD_REG, 75 HCLGEVF_RING_TX_FBD_NUM_REG, 76 HCLGEVF_RING_TX_OFFSET_REG, 77 HCLGEVF_RING_TX_EBD_NUM_REG, 78 HCLGEVF_RING_TX_EBD_OFFSET_REG, 79 HCLGEVF_RING_TX_BD_ERR_REG, 80 HCLGEVF_RING_EN_REG}; 81 82 static const u32 tqp_intr_reg_addr_list[] = {HCLGEVF_TQP_INTR_CTRL_REG, 83 HCLGEVF_TQP_INTR_GL0_REG, 84 HCLGEVF_TQP_INTR_GL1_REG, 85 HCLGEVF_TQP_INTR_GL2_REG, 86 HCLGEVF_TQP_INTR_RL_REG}; 87 88 static struct hclgevf_dev *hclgevf_ae_get_hdev(struct hnae3_handle *handle) 89 { 90 if (!handle->client) 91 return container_of(handle, struct hclgevf_dev, nic); 92 else if (handle->client->type == HNAE3_CLIENT_ROCE) 93 return container_of(handle, struct hclgevf_dev, roce); 94 else 95 return container_of(handle, struct hclgevf_dev, nic); 96 } 97 98 static int hclgevf_tqps_update_stats(struct hnae3_handle *handle) 99 { 100 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 101 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 102 struct hclgevf_desc desc; 103 struct hclgevf_tqp *tqp; 104 int status; 105 int i; 106 107 for (i = 0; i < kinfo->num_tqps; i++) { 108 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 109 hclgevf_cmd_setup_basic_desc(&desc, 110 HCLGEVF_OPC_QUERY_RX_STATUS, 111 true); 112 113 desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 114 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 115 if (status) { 116 dev_err(&hdev->pdev->dev, 117 "Query tqp stat fail, status = %d,queue = %d\n", 118 status, i); 119 return status; 120 } 121 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd += 122 le32_to_cpu(desc.data[1]); 123 124 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_TX_STATUS, 125 true); 126 127 desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 128 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 129 if (status) { 130 dev_err(&hdev->pdev->dev, 131 "Query tqp stat fail, status = %d,queue = %d\n", 132 status, i); 133 return status; 134 } 135 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd += 136 le32_to_cpu(desc.data[1]); 137 } 138 139 return 0; 140 } 141 142 static u64 *hclgevf_tqps_get_stats(struct hnae3_handle *handle, u64 *data) 143 { 144 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 145 struct hclgevf_tqp *tqp; 146 u64 *buff = data; 147 int i; 148 149 for (i = 0; i < kinfo->num_tqps; i++) { 150 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 151 *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd; 152 } 153 for (i = 0; i < kinfo->num_tqps; i++) { 154 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 155 *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd; 156 } 157 158 return buff; 159 } 160 161 static int hclgevf_tqps_get_sset_count(struct hnae3_handle *handle, int strset) 162 { 163 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 164 165 return kinfo->num_tqps * 2; 166 } 167 168 static u8 *hclgevf_tqps_get_strings(struct hnae3_handle *handle, u8 *data) 169 { 170 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 171 u8 *buff = data; 172 int i = 0; 173 174 for (i = 0; i < kinfo->num_tqps; i++) { 175 struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 176 struct hclgevf_tqp, q); 177 snprintf(buff, ETH_GSTRING_LEN, "txq%d_pktnum_rcd", 178 tqp->index); 179 buff += ETH_GSTRING_LEN; 180 } 181 182 for (i = 0; i < kinfo->num_tqps; i++) { 183 struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 184 struct hclgevf_tqp, q); 185 snprintf(buff, ETH_GSTRING_LEN, "rxq%d_pktnum_rcd", 186 tqp->index); 187 buff += ETH_GSTRING_LEN; 188 } 189 190 return buff; 191 } 192 193 static void hclgevf_update_stats(struct hnae3_handle *handle, 194 struct net_device_stats *net_stats) 195 { 196 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 197 int status; 198 199 status = hclgevf_tqps_update_stats(handle); 200 if (status) 201 dev_err(&hdev->pdev->dev, 202 "VF update of TQPS stats fail, status = %d.\n", 203 status); 204 } 205 206 static int hclgevf_get_sset_count(struct hnae3_handle *handle, int strset) 207 { 208 if (strset == ETH_SS_TEST) 209 return -EOPNOTSUPP; 210 else if (strset == ETH_SS_STATS) 211 return hclgevf_tqps_get_sset_count(handle, strset); 212 213 return 0; 214 } 215 216 static void hclgevf_get_strings(struct hnae3_handle *handle, u32 strset, 217 u8 *data) 218 { 219 u8 *p = (char *)data; 220 221 if (strset == ETH_SS_STATS) 222 p = hclgevf_tqps_get_strings(handle, p); 223 } 224 225 static void hclgevf_get_stats(struct hnae3_handle *handle, u64 *data) 226 { 227 hclgevf_tqps_get_stats(handle, data); 228 } 229 230 static int hclgevf_get_tc_info(struct hclgevf_dev *hdev) 231 { 232 u8 resp_msg; 233 int status; 234 235 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_TCINFO, 0, NULL, 0, 236 true, &resp_msg, sizeof(resp_msg)); 237 if (status) { 238 dev_err(&hdev->pdev->dev, 239 "VF request to get TC info from PF failed %d", 240 status); 241 return status; 242 } 243 244 hdev->hw_tc_map = resp_msg; 245 246 return 0; 247 } 248 249 static int hclgevf_get_port_base_vlan_filter_state(struct hclgevf_dev *hdev) 250 { 251 struct hnae3_handle *nic = &hdev->nic; 252 u8 resp_msg; 253 int ret; 254 255 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 256 HCLGE_MBX_GET_PORT_BASE_VLAN_STATE, 257 NULL, 0, true, &resp_msg, sizeof(u8)); 258 if (ret) { 259 dev_err(&hdev->pdev->dev, 260 "VF request to get port based vlan state failed %d", 261 ret); 262 return ret; 263 } 264 265 nic->port_base_vlan_state = resp_msg; 266 267 return 0; 268 } 269 270 static int hclgevf_get_queue_info(struct hclgevf_dev *hdev) 271 { 272 #define HCLGEVF_TQPS_RSS_INFO_LEN 6 273 u8 resp_msg[HCLGEVF_TQPS_RSS_INFO_LEN]; 274 int status; 275 276 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QINFO, 0, NULL, 0, 277 true, resp_msg, 278 HCLGEVF_TQPS_RSS_INFO_LEN); 279 if (status) { 280 dev_err(&hdev->pdev->dev, 281 "VF request to get tqp info from PF failed %d", 282 status); 283 return status; 284 } 285 286 memcpy(&hdev->num_tqps, &resp_msg[0], sizeof(u16)); 287 memcpy(&hdev->rss_size_max, &resp_msg[2], sizeof(u16)); 288 memcpy(&hdev->rx_buf_len, &resp_msg[4], sizeof(u16)); 289 290 return 0; 291 } 292 293 static int hclgevf_get_queue_depth(struct hclgevf_dev *hdev) 294 { 295 #define HCLGEVF_TQPS_DEPTH_INFO_LEN 4 296 u8 resp_msg[HCLGEVF_TQPS_DEPTH_INFO_LEN]; 297 int ret; 298 299 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QDEPTH, 0, NULL, 0, 300 true, resp_msg, 301 HCLGEVF_TQPS_DEPTH_INFO_LEN); 302 if (ret) { 303 dev_err(&hdev->pdev->dev, 304 "VF request to get tqp depth info from PF failed %d", 305 ret); 306 return ret; 307 } 308 309 memcpy(&hdev->num_tx_desc, &resp_msg[0], sizeof(u16)); 310 memcpy(&hdev->num_rx_desc, &resp_msg[2], sizeof(u16)); 311 312 return 0; 313 } 314 315 static u16 hclgevf_get_qid_global(struct hnae3_handle *handle, u16 queue_id) 316 { 317 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 318 u8 msg_data[2], resp_data[2]; 319 u16 qid_in_pf = 0; 320 int ret; 321 322 memcpy(&msg_data[0], &queue_id, sizeof(queue_id)); 323 324 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QID_IN_PF, 0, msg_data, 325 sizeof(msg_data), true, resp_data, 326 sizeof(resp_data)); 327 if (!ret) 328 qid_in_pf = *(u16 *)resp_data; 329 330 return qid_in_pf; 331 } 332 333 static int hclgevf_get_pf_media_type(struct hclgevf_dev *hdev) 334 { 335 u8 resp_msg[2]; 336 int ret; 337 338 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_MEDIA_TYPE, 0, NULL, 0, 339 true, resp_msg, sizeof(resp_msg)); 340 if (ret) { 341 dev_err(&hdev->pdev->dev, 342 "VF request to get the pf port media type failed %d", 343 ret); 344 return ret; 345 } 346 347 hdev->hw.mac.media_type = resp_msg[0]; 348 hdev->hw.mac.module_type = resp_msg[1]; 349 350 return 0; 351 } 352 353 static int hclgevf_alloc_tqps(struct hclgevf_dev *hdev) 354 { 355 struct hclgevf_tqp *tqp; 356 int i; 357 358 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 359 sizeof(struct hclgevf_tqp), GFP_KERNEL); 360 if (!hdev->htqp) 361 return -ENOMEM; 362 363 tqp = hdev->htqp; 364 365 for (i = 0; i < hdev->num_tqps; i++) { 366 tqp->dev = &hdev->pdev->dev; 367 tqp->index = i; 368 369 tqp->q.ae_algo = &ae_algovf; 370 tqp->q.buf_size = hdev->rx_buf_len; 371 tqp->q.tx_desc_num = hdev->num_tx_desc; 372 tqp->q.rx_desc_num = hdev->num_rx_desc; 373 tqp->q.io_base = hdev->hw.io_base + HCLGEVF_TQP_REG_OFFSET + 374 i * HCLGEVF_TQP_REG_SIZE; 375 376 tqp++; 377 } 378 379 return 0; 380 } 381 382 static int hclgevf_knic_setup(struct hclgevf_dev *hdev) 383 { 384 struct hnae3_handle *nic = &hdev->nic; 385 struct hnae3_knic_private_info *kinfo; 386 u16 new_tqps = hdev->num_tqps; 387 unsigned int i; 388 389 kinfo = &nic->kinfo; 390 kinfo->num_tc = 0; 391 kinfo->num_tx_desc = hdev->num_tx_desc; 392 kinfo->num_rx_desc = hdev->num_rx_desc; 393 kinfo->rx_buf_len = hdev->rx_buf_len; 394 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) 395 if (hdev->hw_tc_map & BIT(i)) 396 kinfo->num_tc++; 397 398 kinfo->rss_size 399 = min_t(u16, hdev->rss_size_max, new_tqps / kinfo->num_tc); 400 new_tqps = kinfo->rss_size * kinfo->num_tc; 401 kinfo->num_tqps = min(new_tqps, hdev->num_tqps); 402 403 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps, 404 sizeof(struct hnae3_queue *), GFP_KERNEL); 405 if (!kinfo->tqp) 406 return -ENOMEM; 407 408 for (i = 0; i < kinfo->num_tqps; i++) { 409 hdev->htqp[i].q.handle = &hdev->nic; 410 hdev->htqp[i].q.tqp_index = i; 411 kinfo->tqp[i] = &hdev->htqp[i].q; 412 } 413 414 return 0; 415 } 416 417 static void hclgevf_request_link_info(struct hclgevf_dev *hdev) 418 { 419 int status; 420 u8 resp_msg; 421 422 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_STATUS, 0, NULL, 423 0, false, &resp_msg, sizeof(resp_msg)); 424 if (status) 425 dev_err(&hdev->pdev->dev, 426 "VF failed to fetch link status(%d) from PF", status); 427 } 428 429 void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state) 430 { 431 struct hnae3_handle *rhandle = &hdev->roce; 432 struct hnae3_handle *handle = &hdev->nic; 433 struct hnae3_client *rclient; 434 struct hnae3_client *client; 435 436 client = handle->client; 437 rclient = hdev->roce_client; 438 439 link_state = 440 test_bit(HCLGEVF_STATE_DOWN, &hdev->state) ? 0 : link_state; 441 442 if (link_state != hdev->hw.mac.link) { 443 client->ops->link_status_change(handle, !!link_state); 444 if (rclient && rclient->ops->link_status_change) 445 rclient->ops->link_status_change(rhandle, !!link_state); 446 hdev->hw.mac.link = link_state; 447 } 448 } 449 450 static void hclgevf_update_link_mode(struct hclgevf_dev *hdev) 451 { 452 #define HCLGEVF_ADVERTISING 0 453 #define HCLGEVF_SUPPORTED 1 454 u8 send_msg; 455 u8 resp_msg; 456 457 send_msg = HCLGEVF_ADVERTISING; 458 hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_MODE, 0, 459 &send_msg, sizeof(send_msg), false, 460 &resp_msg, sizeof(resp_msg)); 461 send_msg = HCLGEVF_SUPPORTED; 462 hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_MODE, 0, 463 &send_msg, sizeof(send_msg), false, 464 &resp_msg, sizeof(resp_msg)); 465 } 466 467 static int hclgevf_set_handle_info(struct hclgevf_dev *hdev) 468 { 469 struct hnae3_handle *nic = &hdev->nic; 470 int ret; 471 472 nic->ae_algo = &ae_algovf; 473 nic->pdev = hdev->pdev; 474 nic->numa_node_mask = hdev->numa_node_mask; 475 nic->flags |= HNAE3_SUPPORT_VF; 476 477 ret = hclgevf_knic_setup(hdev); 478 if (ret) 479 dev_err(&hdev->pdev->dev, "VF knic setup failed %d\n", 480 ret); 481 return ret; 482 } 483 484 static void hclgevf_free_vector(struct hclgevf_dev *hdev, int vector_id) 485 { 486 if (hdev->vector_status[vector_id] == HCLGEVF_INVALID_VPORT) { 487 dev_warn(&hdev->pdev->dev, 488 "vector(vector_id %d) has been freed.\n", vector_id); 489 return; 490 } 491 492 hdev->vector_status[vector_id] = HCLGEVF_INVALID_VPORT; 493 hdev->num_msi_left += 1; 494 hdev->num_msi_used -= 1; 495 } 496 497 static int hclgevf_get_vector(struct hnae3_handle *handle, u16 vector_num, 498 struct hnae3_vector_info *vector_info) 499 { 500 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 501 struct hnae3_vector_info *vector = vector_info; 502 int alloc = 0; 503 int i, j; 504 505 vector_num = min(hdev->num_msi_left, vector_num); 506 507 for (j = 0; j < vector_num; j++) { 508 for (i = HCLGEVF_MISC_VECTOR_NUM + 1; i < hdev->num_msi; i++) { 509 if (hdev->vector_status[i] == HCLGEVF_INVALID_VPORT) { 510 vector->vector = pci_irq_vector(hdev->pdev, i); 511 vector->io_addr = hdev->hw.io_base + 512 HCLGEVF_VECTOR_REG_BASE + 513 (i - 1) * HCLGEVF_VECTOR_REG_OFFSET; 514 hdev->vector_status[i] = 0; 515 hdev->vector_irq[i] = vector->vector; 516 517 vector++; 518 alloc++; 519 520 break; 521 } 522 } 523 } 524 hdev->num_msi_left -= alloc; 525 hdev->num_msi_used += alloc; 526 527 return alloc; 528 } 529 530 static int hclgevf_get_vector_index(struct hclgevf_dev *hdev, int vector) 531 { 532 int i; 533 534 for (i = 0; i < hdev->num_msi; i++) 535 if (vector == hdev->vector_irq[i]) 536 return i; 537 538 return -EINVAL; 539 } 540 541 static int hclgevf_set_rss_algo_key(struct hclgevf_dev *hdev, 542 const u8 hfunc, const u8 *key) 543 { 544 struct hclgevf_rss_config_cmd *req; 545 unsigned int key_offset = 0; 546 struct hclgevf_desc desc; 547 int key_counts; 548 int key_size; 549 int ret; 550 551 key_counts = HCLGEVF_RSS_KEY_SIZE; 552 req = (struct hclgevf_rss_config_cmd *)desc.data; 553 554 while (key_counts) { 555 hclgevf_cmd_setup_basic_desc(&desc, 556 HCLGEVF_OPC_RSS_GENERIC_CONFIG, 557 false); 558 559 req->hash_config |= (hfunc & HCLGEVF_RSS_HASH_ALGO_MASK); 560 req->hash_config |= 561 (key_offset << HCLGEVF_RSS_HASH_KEY_OFFSET_B); 562 563 key_size = min(HCLGEVF_RSS_HASH_KEY_NUM, key_counts); 564 memcpy(req->hash_key, 565 key + key_offset * HCLGEVF_RSS_HASH_KEY_NUM, key_size); 566 567 key_counts -= key_size; 568 key_offset++; 569 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 570 if (ret) { 571 dev_err(&hdev->pdev->dev, 572 "Configure RSS config fail, status = %d\n", 573 ret); 574 return ret; 575 } 576 } 577 578 return 0; 579 } 580 581 static u32 hclgevf_get_rss_key_size(struct hnae3_handle *handle) 582 { 583 return HCLGEVF_RSS_KEY_SIZE; 584 } 585 586 static u32 hclgevf_get_rss_indir_size(struct hnae3_handle *handle) 587 { 588 return HCLGEVF_RSS_IND_TBL_SIZE; 589 } 590 591 static int hclgevf_set_rss_indir_table(struct hclgevf_dev *hdev) 592 { 593 const u8 *indir = hdev->rss_cfg.rss_indirection_tbl; 594 struct hclgevf_rss_indirection_table_cmd *req; 595 struct hclgevf_desc desc; 596 int status; 597 int i, j; 598 599 req = (struct hclgevf_rss_indirection_table_cmd *)desc.data; 600 601 for (i = 0; i < HCLGEVF_RSS_CFG_TBL_NUM; i++) { 602 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INDIR_TABLE, 603 false); 604 req->start_table_index = i * HCLGEVF_RSS_CFG_TBL_SIZE; 605 req->rss_set_bitmap = HCLGEVF_RSS_SET_BITMAP_MSK; 606 for (j = 0; j < HCLGEVF_RSS_CFG_TBL_SIZE; j++) 607 req->rss_result[j] = 608 indir[i * HCLGEVF_RSS_CFG_TBL_SIZE + j]; 609 610 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 611 if (status) { 612 dev_err(&hdev->pdev->dev, 613 "VF failed(=%d) to set RSS indirection table\n", 614 status); 615 return status; 616 } 617 } 618 619 return 0; 620 } 621 622 static int hclgevf_set_rss_tc_mode(struct hclgevf_dev *hdev, u16 rss_size) 623 { 624 struct hclgevf_rss_tc_mode_cmd *req; 625 u16 tc_offset[HCLGEVF_MAX_TC_NUM]; 626 u16 tc_valid[HCLGEVF_MAX_TC_NUM]; 627 u16 tc_size[HCLGEVF_MAX_TC_NUM]; 628 struct hclgevf_desc desc; 629 u16 roundup_size; 630 int status; 631 unsigned int i; 632 633 req = (struct hclgevf_rss_tc_mode_cmd *)desc.data; 634 635 roundup_size = roundup_pow_of_two(rss_size); 636 roundup_size = ilog2(roundup_size); 637 638 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 639 tc_valid[i] = !!(hdev->hw_tc_map & BIT(i)); 640 tc_size[i] = roundup_size; 641 tc_offset[i] = rss_size * i; 642 } 643 644 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_TC_MODE, false); 645 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 646 hnae3_set_bit(req->rss_tc_mode[i], HCLGEVF_RSS_TC_VALID_B, 647 (tc_valid[i] & 0x1)); 648 hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_SIZE_M, 649 HCLGEVF_RSS_TC_SIZE_S, tc_size[i]); 650 hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_OFFSET_M, 651 HCLGEVF_RSS_TC_OFFSET_S, tc_offset[i]); 652 } 653 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 654 if (status) 655 dev_err(&hdev->pdev->dev, 656 "VF failed(=%d) to set rss tc mode\n", status); 657 658 return status; 659 } 660 661 /* for revision 0x20, vf shared the same rss config with pf */ 662 static int hclgevf_get_rss_hash_key(struct hclgevf_dev *hdev) 663 { 664 #define HCLGEVF_RSS_MBX_RESP_LEN 8 665 666 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 667 u8 resp_msg[HCLGEVF_RSS_MBX_RESP_LEN]; 668 u16 msg_num, hash_key_index; 669 u8 index; 670 int ret; 671 672 msg_num = (HCLGEVF_RSS_KEY_SIZE + HCLGEVF_RSS_MBX_RESP_LEN - 1) / 673 HCLGEVF_RSS_MBX_RESP_LEN; 674 for (index = 0; index < msg_num; index++) { 675 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_RSS_KEY, 0, 676 &index, sizeof(index), 677 true, resp_msg, 678 HCLGEVF_RSS_MBX_RESP_LEN); 679 if (ret) { 680 dev_err(&hdev->pdev->dev, 681 "VF get rss hash key from PF failed, ret=%d", 682 ret); 683 return ret; 684 } 685 686 hash_key_index = HCLGEVF_RSS_MBX_RESP_LEN * index; 687 if (index == msg_num - 1) 688 memcpy(&rss_cfg->rss_hash_key[hash_key_index], 689 &resp_msg[0], 690 HCLGEVF_RSS_KEY_SIZE - hash_key_index); 691 else 692 memcpy(&rss_cfg->rss_hash_key[hash_key_index], 693 &resp_msg[0], HCLGEVF_RSS_MBX_RESP_LEN); 694 } 695 696 return 0; 697 } 698 699 static int hclgevf_get_rss(struct hnae3_handle *handle, u32 *indir, u8 *key, 700 u8 *hfunc) 701 { 702 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 703 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 704 int i, ret; 705 706 if (handle->pdev->revision >= 0x21) { 707 /* Get hash algorithm */ 708 if (hfunc) { 709 switch (rss_cfg->hash_algo) { 710 case HCLGEVF_RSS_HASH_ALGO_TOEPLITZ: 711 *hfunc = ETH_RSS_HASH_TOP; 712 break; 713 case HCLGEVF_RSS_HASH_ALGO_SIMPLE: 714 *hfunc = ETH_RSS_HASH_XOR; 715 break; 716 default: 717 *hfunc = ETH_RSS_HASH_UNKNOWN; 718 break; 719 } 720 } 721 722 /* Get the RSS Key required by the user */ 723 if (key) 724 memcpy(key, rss_cfg->rss_hash_key, 725 HCLGEVF_RSS_KEY_SIZE); 726 } else { 727 if (hfunc) 728 *hfunc = ETH_RSS_HASH_TOP; 729 if (key) { 730 ret = hclgevf_get_rss_hash_key(hdev); 731 if (ret) 732 return ret; 733 memcpy(key, rss_cfg->rss_hash_key, 734 HCLGEVF_RSS_KEY_SIZE); 735 } 736 } 737 738 if (indir) 739 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 740 indir[i] = rss_cfg->rss_indirection_tbl[i]; 741 742 return 0; 743 } 744 745 static int hclgevf_set_rss(struct hnae3_handle *handle, const u32 *indir, 746 const u8 *key, const u8 hfunc) 747 { 748 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 749 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 750 int ret, i; 751 752 if (handle->pdev->revision >= 0x21) { 753 /* Set the RSS Hash Key if specififed by the user */ 754 if (key) { 755 switch (hfunc) { 756 case ETH_RSS_HASH_TOP: 757 rss_cfg->hash_algo = 758 HCLGEVF_RSS_HASH_ALGO_TOEPLITZ; 759 break; 760 case ETH_RSS_HASH_XOR: 761 rss_cfg->hash_algo = 762 HCLGEVF_RSS_HASH_ALGO_SIMPLE; 763 break; 764 case ETH_RSS_HASH_NO_CHANGE: 765 break; 766 default: 767 return -EINVAL; 768 } 769 770 ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 771 key); 772 if (ret) 773 return ret; 774 775 /* Update the shadow RSS key with user specified qids */ 776 memcpy(rss_cfg->rss_hash_key, key, 777 HCLGEVF_RSS_KEY_SIZE); 778 } 779 } 780 781 /* update the shadow RSS table with user specified qids */ 782 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 783 rss_cfg->rss_indirection_tbl[i] = indir[i]; 784 785 /* update the hardware */ 786 return hclgevf_set_rss_indir_table(hdev); 787 } 788 789 static u8 hclgevf_get_rss_hash_bits(struct ethtool_rxnfc *nfc) 790 { 791 u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGEVF_S_PORT_BIT : 0; 792 793 if (nfc->data & RXH_L4_B_2_3) 794 hash_sets |= HCLGEVF_D_PORT_BIT; 795 else 796 hash_sets &= ~HCLGEVF_D_PORT_BIT; 797 798 if (nfc->data & RXH_IP_SRC) 799 hash_sets |= HCLGEVF_S_IP_BIT; 800 else 801 hash_sets &= ~HCLGEVF_S_IP_BIT; 802 803 if (nfc->data & RXH_IP_DST) 804 hash_sets |= HCLGEVF_D_IP_BIT; 805 else 806 hash_sets &= ~HCLGEVF_D_IP_BIT; 807 808 if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW) 809 hash_sets |= HCLGEVF_V_TAG_BIT; 810 811 return hash_sets; 812 } 813 814 static int hclgevf_set_rss_tuple(struct hnae3_handle *handle, 815 struct ethtool_rxnfc *nfc) 816 { 817 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 818 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 819 struct hclgevf_rss_input_tuple_cmd *req; 820 struct hclgevf_desc desc; 821 u8 tuple_sets; 822 int ret; 823 824 if (handle->pdev->revision == 0x20) 825 return -EOPNOTSUPP; 826 827 if (nfc->data & 828 ~(RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3)) 829 return -EINVAL; 830 831 req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 832 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 833 834 req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 835 req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 836 req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 837 req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 838 req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 839 req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 840 req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 841 req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 842 843 tuple_sets = hclgevf_get_rss_hash_bits(nfc); 844 switch (nfc->flow_type) { 845 case TCP_V4_FLOW: 846 req->ipv4_tcp_en = tuple_sets; 847 break; 848 case TCP_V6_FLOW: 849 req->ipv6_tcp_en = tuple_sets; 850 break; 851 case UDP_V4_FLOW: 852 req->ipv4_udp_en = tuple_sets; 853 break; 854 case UDP_V6_FLOW: 855 req->ipv6_udp_en = tuple_sets; 856 break; 857 case SCTP_V4_FLOW: 858 req->ipv4_sctp_en = tuple_sets; 859 break; 860 case SCTP_V6_FLOW: 861 if ((nfc->data & RXH_L4_B_0_1) || 862 (nfc->data & RXH_L4_B_2_3)) 863 return -EINVAL; 864 865 req->ipv6_sctp_en = tuple_sets; 866 break; 867 case IPV4_FLOW: 868 req->ipv4_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 869 break; 870 case IPV6_FLOW: 871 req->ipv6_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 872 break; 873 default: 874 return -EINVAL; 875 } 876 877 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 878 if (ret) { 879 dev_err(&hdev->pdev->dev, 880 "Set rss tuple fail, status = %d\n", ret); 881 return ret; 882 } 883 884 rss_cfg->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en; 885 rss_cfg->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en; 886 rss_cfg->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en; 887 rss_cfg->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en; 888 rss_cfg->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en; 889 rss_cfg->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en; 890 rss_cfg->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en; 891 rss_cfg->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en; 892 return 0; 893 } 894 895 static int hclgevf_get_rss_tuple(struct hnae3_handle *handle, 896 struct ethtool_rxnfc *nfc) 897 { 898 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 899 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 900 u8 tuple_sets; 901 902 if (handle->pdev->revision == 0x20) 903 return -EOPNOTSUPP; 904 905 nfc->data = 0; 906 907 switch (nfc->flow_type) { 908 case TCP_V4_FLOW: 909 tuple_sets = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 910 break; 911 case UDP_V4_FLOW: 912 tuple_sets = rss_cfg->rss_tuple_sets.ipv4_udp_en; 913 break; 914 case TCP_V6_FLOW: 915 tuple_sets = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 916 break; 917 case UDP_V6_FLOW: 918 tuple_sets = rss_cfg->rss_tuple_sets.ipv6_udp_en; 919 break; 920 case SCTP_V4_FLOW: 921 tuple_sets = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 922 break; 923 case SCTP_V6_FLOW: 924 tuple_sets = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 925 break; 926 case IPV4_FLOW: 927 case IPV6_FLOW: 928 tuple_sets = HCLGEVF_S_IP_BIT | HCLGEVF_D_IP_BIT; 929 break; 930 default: 931 return -EINVAL; 932 } 933 934 if (!tuple_sets) 935 return 0; 936 937 if (tuple_sets & HCLGEVF_D_PORT_BIT) 938 nfc->data |= RXH_L4_B_2_3; 939 if (tuple_sets & HCLGEVF_S_PORT_BIT) 940 nfc->data |= RXH_L4_B_0_1; 941 if (tuple_sets & HCLGEVF_D_IP_BIT) 942 nfc->data |= RXH_IP_DST; 943 if (tuple_sets & HCLGEVF_S_IP_BIT) 944 nfc->data |= RXH_IP_SRC; 945 946 return 0; 947 } 948 949 static int hclgevf_set_rss_input_tuple(struct hclgevf_dev *hdev, 950 struct hclgevf_rss_cfg *rss_cfg) 951 { 952 struct hclgevf_rss_input_tuple_cmd *req; 953 struct hclgevf_desc desc; 954 int ret; 955 956 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 957 958 req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 959 960 req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 961 req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 962 req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 963 req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 964 req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 965 req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 966 req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 967 req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 968 969 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 970 if (ret) 971 dev_err(&hdev->pdev->dev, 972 "Configure rss input fail, status = %d\n", ret); 973 return ret; 974 } 975 976 static int hclgevf_get_tc_size(struct hnae3_handle *handle) 977 { 978 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 979 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 980 981 return rss_cfg->rss_size; 982 } 983 984 static int hclgevf_bind_ring_to_vector(struct hnae3_handle *handle, bool en, 985 int vector_id, 986 struct hnae3_ring_chain_node *ring_chain) 987 { 988 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 989 struct hnae3_ring_chain_node *node; 990 struct hclge_mbx_vf_to_pf_cmd *req; 991 struct hclgevf_desc desc; 992 int i = 0; 993 int status; 994 u8 type; 995 996 req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data; 997 type = en ? HCLGE_MBX_MAP_RING_TO_VECTOR : 998 HCLGE_MBX_UNMAP_RING_TO_VECTOR; 999 1000 for (node = ring_chain; node; node = node->next) { 1001 int idx_offset = HCLGE_MBX_RING_MAP_BASIC_MSG_NUM + 1002 HCLGE_MBX_RING_NODE_VARIABLE_NUM * i; 1003 1004 if (i == 0) { 1005 hclgevf_cmd_setup_basic_desc(&desc, 1006 HCLGEVF_OPC_MBX_VF_TO_PF, 1007 false); 1008 req->msg[0] = type; 1009 req->msg[1] = vector_id; 1010 } 1011 1012 req->msg[idx_offset] = 1013 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B); 1014 req->msg[idx_offset + 1] = node->tqp_index; 1015 req->msg[idx_offset + 2] = hnae3_get_field(node->int_gl_idx, 1016 HNAE3_RING_GL_IDX_M, 1017 HNAE3_RING_GL_IDX_S); 1018 1019 i++; 1020 if ((i == (HCLGE_MBX_VF_MSG_DATA_NUM - 1021 HCLGE_MBX_RING_MAP_BASIC_MSG_NUM) / 1022 HCLGE_MBX_RING_NODE_VARIABLE_NUM) || 1023 !node->next) { 1024 req->msg[2] = i; 1025 1026 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1027 if (status) { 1028 dev_err(&hdev->pdev->dev, 1029 "Map TQP fail, status is %d.\n", 1030 status); 1031 return status; 1032 } 1033 i = 0; 1034 hclgevf_cmd_setup_basic_desc(&desc, 1035 HCLGEVF_OPC_MBX_VF_TO_PF, 1036 false); 1037 req->msg[0] = type; 1038 req->msg[1] = vector_id; 1039 } 1040 } 1041 1042 return 0; 1043 } 1044 1045 static int hclgevf_map_ring_to_vector(struct hnae3_handle *handle, int vector, 1046 struct hnae3_ring_chain_node *ring_chain) 1047 { 1048 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1049 int vector_id; 1050 1051 vector_id = hclgevf_get_vector_index(hdev, vector); 1052 if (vector_id < 0) { 1053 dev_err(&handle->pdev->dev, 1054 "Get vector index fail. ret =%d\n", vector_id); 1055 return vector_id; 1056 } 1057 1058 return hclgevf_bind_ring_to_vector(handle, true, vector_id, ring_chain); 1059 } 1060 1061 static int hclgevf_unmap_ring_from_vector( 1062 struct hnae3_handle *handle, 1063 int vector, 1064 struct hnae3_ring_chain_node *ring_chain) 1065 { 1066 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1067 int ret, vector_id; 1068 1069 if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 1070 return 0; 1071 1072 vector_id = hclgevf_get_vector_index(hdev, vector); 1073 if (vector_id < 0) { 1074 dev_err(&handle->pdev->dev, 1075 "Get vector index fail. ret =%d\n", vector_id); 1076 return vector_id; 1077 } 1078 1079 ret = hclgevf_bind_ring_to_vector(handle, false, vector_id, ring_chain); 1080 if (ret) 1081 dev_err(&handle->pdev->dev, 1082 "Unmap ring from vector fail. vector=%d, ret =%d\n", 1083 vector_id, 1084 ret); 1085 1086 return ret; 1087 } 1088 1089 static int hclgevf_put_vector(struct hnae3_handle *handle, int vector) 1090 { 1091 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1092 int vector_id; 1093 1094 vector_id = hclgevf_get_vector_index(hdev, vector); 1095 if (vector_id < 0) { 1096 dev_err(&handle->pdev->dev, 1097 "hclgevf_put_vector get vector index fail. ret =%d\n", 1098 vector_id); 1099 return vector_id; 1100 } 1101 1102 hclgevf_free_vector(hdev, vector_id); 1103 1104 return 0; 1105 } 1106 1107 static int hclgevf_cmd_set_promisc_mode(struct hclgevf_dev *hdev, 1108 bool en_bc_pmc) 1109 { 1110 struct hclge_mbx_vf_to_pf_cmd *req; 1111 struct hclgevf_desc desc; 1112 int ret; 1113 1114 req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data; 1115 1116 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_MBX_VF_TO_PF, false); 1117 req->msg[0] = HCLGE_MBX_SET_PROMISC_MODE; 1118 req->msg[1] = en_bc_pmc ? 1 : 0; 1119 1120 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1121 if (ret) 1122 dev_err(&hdev->pdev->dev, 1123 "Set promisc mode fail, status is %d.\n", ret); 1124 1125 return ret; 1126 } 1127 1128 static int hclgevf_set_promisc_mode(struct hclgevf_dev *hdev, bool en_bc_pmc) 1129 { 1130 return hclgevf_cmd_set_promisc_mode(hdev, en_bc_pmc); 1131 } 1132 1133 static int hclgevf_tqp_enable(struct hclgevf_dev *hdev, unsigned int tqp_id, 1134 int stream_id, bool enable) 1135 { 1136 struct hclgevf_cfg_com_tqp_queue_cmd *req; 1137 struct hclgevf_desc desc; 1138 int status; 1139 1140 req = (struct hclgevf_cfg_com_tqp_queue_cmd *)desc.data; 1141 1142 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_CFG_COM_TQP_QUEUE, 1143 false); 1144 req->tqp_id = cpu_to_le16(tqp_id & HCLGEVF_RING_ID_MASK); 1145 req->stream_id = cpu_to_le16(stream_id); 1146 if (enable) 1147 req->enable |= 1U << HCLGEVF_TQP_ENABLE_B; 1148 1149 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1150 if (status) 1151 dev_err(&hdev->pdev->dev, 1152 "TQP enable fail, status =%d.\n", status); 1153 1154 return status; 1155 } 1156 1157 static void hclgevf_reset_tqp_stats(struct hnae3_handle *handle) 1158 { 1159 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 1160 struct hclgevf_tqp *tqp; 1161 int i; 1162 1163 for (i = 0; i < kinfo->num_tqps; i++) { 1164 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 1165 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats)); 1166 } 1167 } 1168 1169 static void hclgevf_get_mac_addr(struct hnae3_handle *handle, u8 *p) 1170 { 1171 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1172 1173 ether_addr_copy(p, hdev->hw.mac.mac_addr); 1174 } 1175 1176 static int hclgevf_set_mac_addr(struct hnae3_handle *handle, void *p, 1177 bool is_first) 1178 { 1179 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1180 u8 *old_mac_addr = (u8 *)hdev->hw.mac.mac_addr; 1181 u8 *new_mac_addr = (u8 *)p; 1182 u8 msg_data[ETH_ALEN * 2]; 1183 u16 subcode; 1184 int status; 1185 1186 ether_addr_copy(msg_data, new_mac_addr); 1187 ether_addr_copy(&msg_data[ETH_ALEN], old_mac_addr); 1188 1189 subcode = is_first ? HCLGE_MBX_MAC_VLAN_UC_ADD : 1190 HCLGE_MBX_MAC_VLAN_UC_MODIFY; 1191 1192 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 1193 subcode, msg_data, sizeof(msg_data), 1194 true, NULL, 0); 1195 if (!status) 1196 ether_addr_copy(hdev->hw.mac.mac_addr, new_mac_addr); 1197 1198 return status; 1199 } 1200 1201 static int hclgevf_add_uc_addr(struct hnae3_handle *handle, 1202 const unsigned char *addr) 1203 { 1204 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1205 1206 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 1207 HCLGE_MBX_MAC_VLAN_UC_ADD, 1208 addr, ETH_ALEN, false, NULL, 0); 1209 } 1210 1211 static int hclgevf_rm_uc_addr(struct hnae3_handle *handle, 1212 const unsigned char *addr) 1213 { 1214 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1215 1216 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST, 1217 HCLGE_MBX_MAC_VLAN_UC_REMOVE, 1218 addr, ETH_ALEN, false, NULL, 0); 1219 } 1220 1221 static int hclgevf_add_mc_addr(struct hnae3_handle *handle, 1222 const unsigned char *addr) 1223 { 1224 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1225 1226 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 1227 HCLGE_MBX_MAC_VLAN_MC_ADD, 1228 addr, ETH_ALEN, false, NULL, 0); 1229 } 1230 1231 static int hclgevf_rm_mc_addr(struct hnae3_handle *handle, 1232 const unsigned char *addr) 1233 { 1234 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1235 1236 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST, 1237 HCLGE_MBX_MAC_VLAN_MC_REMOVE, 1238 addr, ETH_ALEN, false, NULL, 0); 1239 } 1240 1241 static int hclgevf_set_vlan_filter(struct hnae3_handle *handle, 1242 __be16 proto, u16 vlan_id, 1243 bool is_kill) 1244 { 1245 #define HCLGEVF_VLAN_MBX_MSG_LEN 5 1246 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1247 u8 msg_data[HCLGEVF_VLAN_MBX_MSG_LEN]; 1248 int ret; 1249 1250 if (vlan_id > HCLGEVF_MAX_VLAN_ID) 1251 return -EINVAL; 1252 1253 if (proto != htons(ETH_P_8021Q)) 1254 return -EPROTONOSUPPORT; 1255 1256 /* When device is resetting, firmware is unable to handle 1257 * mailbox. Just record the vlan id, and remove it after 1258 * reset finished. 1259 */ 1260 if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) && is_kill) { 1261 set_bit(vlan_id, hdev->vlan_del_fail_bmap); 1262 return -EBUSY; 1263 } 1264 1265 msg_data[0] = is_kill; 1266 memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id)); 1267 memcpy(&msg_data[3], &proto, sizeof(proto)); 1268 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 1269 HCLGE_MBX_VLAN_FILTER, msg_data, 1270 HCLGEVF_VLAN_MBX_MSG_LEN, false, NULL, 0); 1271 1272 /* When remove hw vlan filter failed, record the vlan id, 1273 * and try to remove it from hw later, to be consistence 1274 * with stack. 1275 */ 1276 if (is_kill && ret) 1277 set_bit(vlan_id, hdev->vlan_del_fail_bmap); 1278 1279 return ret; 1280 } 1281 1282 static void hclgevf_sync_vlan_filter(struct hclgevf_dev *hdev) 1283 { 1284 #define HCLGEVF_MAX_SYNC_COUNT 60 1285 struct hnae3_handle *handle = &hdev->nic; 1286 int ret, sync_cnt = 0; 1287 u16 vlan_id; 1288 1289 vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID); 1290 while (vlan_id != VLAN_N_VID) { 1291 ret = hclgevf_set_vlan_filter(handle, htons(ETH_P_8021Q), 1292 vlan_id, true); 1293 if (ret) 1294 return; 1295 1296 clear_bit(vlan_id, hdev->vlan_del_fail_bmap); 1297 sync_cnt++; 1298 if (sync_cnt >= HCLGEVF_MAX_SYNC_COUNT) 1299 return; 1300 1301 vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID); 1302 } 1303 } 1304 1305 static int hclgevf_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) 1306 { 1307 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1308 u8 msg_data; 1309 1310 msg_data = enable ? 1 : 0; 1311 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 1312 HCLGE_MBX_VLAN_RX_OFF_CFG, &msg_data, 1313 1, false, NULL, 0); 1314 } 1315 1316 static int hclgevf_reset_tqp(struct hnae3_handle *handle, u16 queue_id) 1317 { 1318 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1319 u8 msg_data[2]; 1320 int ret; 1321 1322 memcpy(msg_data, &queue_id, sizeof(queue_id)); 1323 1324 /* disable vf queue before send queue reset msg to PF */ 1325 ret = hclgevf_tqp_enable(hdev, queue_id, 0, false); 1326 if (ret) 1327 return ret; 1328 1329 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_QUEUE_RESET, 0, msg_data, 1330 sizeof(msg_data), true, NULL, 0); 1331 } 1332 1333 static int hclgevf_set_mtu(struct hnae3_handle *handle, int new_mtu) 1334 { 1335 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1336 1337 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MTU, 0, (u8 *)&new_mtu, 1338 sizeof(new_mtu), true, NULL, 0); 1339 } 1340 1341 static int hclgevf_notify_client(struct hclgevf_dev *hdev, 1342 enum hnae3_reset_notify_type type) 1343 { 1344 struct hnae3_client *client = hdev->nic_client; 1345 struct hnae3_handle *handle = &hdev->nic; 1346 int ret; 1347 1348 if (!test_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state) || 1349 !client) 1350 return 0; 1351 1352 if (!client->ops->reset_notify) 1353 return -EOPNOTSUPP; 1354 1355 ret = client->ops->reset_notify(handle, type); 1356 if (ret) 1357 dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n", 1358 type, ret); 1359 1360 return ret; 1361 } 1362 1363 static void hclgevf_flr_done(struct hnae3_ae_dev *ae_dev) 1364 { 1365 struct hclgevf_dev *hdev = ae_dev->priv; 1366 1367 set_bit(HNAE3_FLR_DONE, &hdev->flr_state); 1368 } 1369 1370 static int hclgevf_flr_poll_timeout(struct hclgevf_dev *hdev, 1371 unsigned long delay_us, 1372 unsigned long wait_cnt) 1373 { 1374 unsigned long cnt = 0; 1375 1376 while (!test_bit(HNAE3_FLR_DONE, &hdev->flr_state) && 1377 cnt++ < wait_cnt) 1378 usleep_range(delay_us, delay_us * 2); 1379 1380 if (!test_bit(HNAE3_FLR_DONE, &hdev->flr_state)) { 1381 dev_err(&hdev->pdev->dev, 1382 "flr wait timeout\n"); 1383 return -ETIMEDOUT; 1384 } 1385 1386 return 0; 1387 } 1388 1389 static int hclgevf_reset_wait(struct hclgevf_dev *hdev) 1390 { 1391 #define HCLGEVF_RESET_WAIT_US 20000 1392 #define HCLGEVF_RESET_WAIT_CNT 2000 1393 #define HCLGEVF_RESET_WAIT_TIMEOUT_US \ 1394 (HCLGEVF_RESET_WAIT_US * HCLGEVF_RESET_WAIT_CNT) 1395 1396 u32 val; 1397 int ret; 1398 1399 /* wait to check the hardware reset completion status */ 1400 val = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 1401 dev_info(&hdev->pdev->dev, "checking vf resetting status: %x\n", val); 1402 1403 if (hdev->reset_type == HNAE3_FLR_RESET) 1404 return hclgevf_flr_poll_timeout(hdev, 1405 HCLGEVF_RESET_WAIT_US, 1406 HCLGEVF_RESET_WAIT_CNT); 1407 1408 ret = readl_poll_timeout(hdev->hw.io_base + HCLGEVF_RST_ING, val, 1409 !(val & HCLGEVF_RST_ING_BITS), 1410 HCLGEVF_RESET_WAIT_US, 1411 HCLGEVF_RESET_WAIT_TIMEOUT_US); 1412 1413 /* hardware completion status should be available by this time */ 1414 if (ret) { 1415 dev_err(&hdev->pdev->dev, 1416 "could'nt get reset done status from h/w, timeout!\n"); 1417 return ret; 1418 } 1419 1420 /* we will wait a bit more to let reset of the stack to complete. This 1421 * might happen in case reset assertion was made by PF. Yes, this also 1422 * means we might end up waiting bit more even for VF reset. 1423 */ 1424 msleep(5000); 1425 1426 return 0; 1427 } 1428 1429 static void hclgevf_reset_handshake(struct hclgevf_dev *hdev, bool enable) 1430 { 1431 u32 reg_val; 1432 1433 reg_val = hclgevf_read_dev(&hdev->hw, HCLGEVF_NIC_CSQ_DEPTH_REG); 1434 if (enable) 1435 reg_val |= HCLGEVF_NIC_SW_RST_RDY; 1436 else 1437 reg_val &= ~HCLGEVF_NIC_SW_RST_RDY; 1438 1439 hclgevf_write_dev(&hdev->hw, HCLGEVF_NIC_CSQ_DEPTH_REG, 1440 reg_val); 1441 } 1442 1443 static int hclgevf_reset_stack(struct hclgevf_dev *hdev) 1444 { 1445 int ret; 1446 1447 /* uninitialize the nic client */ 1448 ret = hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT); 1449 if (ret) 1450 return ret; 1451 1452 /* re-initialize the hclge device */ 1453 ret = hclgevf_reset_hdev(hdev); 1454 if (ret) { 1455 dev_err(&hdev->pdev->dev, 1456 "hclge device re-init failed, VF is disabled!\n"); 1457 return ret; 1458 } 1459 1460 /* bring up the nic client again */ 1461 ret = hclgevf_notify_client(hdev, HNAE3_INIT_CLIENT); 1462 if (ret) 1463 return ret; 1464 1465 ret = hclgevf_notify_client(hdev, HNAE3_RESTORE_CLIENT); 1466 if (ret) 1467 return ret; 1468 1469 /* clear handshake status with IMP */ 1470 hclgevf_reset_handshake(hdev, false); 1471 1472 return 0; 1473 } 1474 1475 static int hclgevf_reset_prepare_wait(struct hclgevf_dev *hdev) 1476 { 1477 #define HCLGEVF_RESET_SYNC_TIME 100 1478 1479 int ret = 0; 1480 1481 switch (hdev->reset_type) { 1482 case HNAE3_VF_FUNC_RESET: 1483 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_RESET, 0, NULL, 1484 0, true, NULL, sizeof(u8)); 1485 hdev->rst_stats.vf_func_rst_cnt++; 1486 break; 1487 case HNAE3_FLR_RESET: 1488 set_bit(HNAE3_FLR_DOWN, &hdev->flr_state); 1489 hdev->rst_stats.flr_rst_cnt++; 1490 break; 1491 default: 1492 break; 1493 } 1494 1495 set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 1496 /* inform hardware that preparatory work is done */ 1497 msleep(HCLGEVF_RESET_SYNC_TIME); 1498 hclgevf_reset_handshake(hdev, true); 1499 dev_info(&hdev->pdev->dev, "prepare reset(%d) wait done, ret:%d\n", 1500 hdev->reset_type, ret); 1501 1502 return ret; 1503 } 1504 1505 static void hclgevf_reset_err_handle(struct hclgevf_dev *hdev) 1506 { 1507 /* recover handshake status with IMP when reset fail */ 1508 hclgevf_reset_handshake(hdev, true); 1509 hdev->rst_stats.rst_fail_cnt++; 1510 dev_err(&hdev->pdev->dev, "failed to reset VF(%d)\n", 1511 hdev->rst_stats.rst_fail_cnt); 1512 1513 if (hdev->rst_stats.rst_fail_cnt < HCLGEVF_RESET_MAX_FAIL_CNT) 1514 set_bit(hdev->reset_type, &hdev->reset_pending); 1515 1516 if (hclgevf_is_reset_pending(hdev)) { 1517 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1518 hclgevf_reset_task_schedule(hdev); 1519 } 1520 } 1521 1522 static int hclgevf_reset(struct hclgevf_dev *hdev) 1523 { 1524 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1525 int ret; 1526 1527 /* Initialize ae_dev reset status as well, in case enet layer wants to 1528 * know if device is undergoing reset 1529 */ 1530 ae_dev->reset_type = hdev->reset_type; 1531 hdev->rst_stats.rst_cnt++; 1532 rtnl_lock(); 1533 1534 /* bring down the nic to stop any ongoing TX/RX */ 1535 ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 1536 if (ret) 1537 goto err_reset_lock; 1538 1539 rtnl_unlock(); 1540 1541 ret = hclgevf_reset_prepare_wait(hdev); 1542 if (ret) 1543 goto err_reset; 1544 1545 /* check if VF could successfully fetch the hardware reset completion 1546 * status from the hardware 1547 */ 1548 ret = hclgevf_reset_wait(hdev); 1549 if (ret) { 1550 /* can't do much in this situation, will disable VF */ 1551 dev_err(&hdev->pdev->dev, 1552 "VF failed(=%d) to fetch H/W reset completion status\n", 1553 ret); 1554 goto err_reset; 1555 } 1556 1557 hdev->rst_stats.hw_rst_done_cnt++; 1558 1559 rtnl_lock(); 1560 1561 /* now, re-initialize the nic client and ae device*/ 1562 ret = hclgevf_reset_stack(hdev); 1563 if (ret) { 1564 dev_err(&hdev->pdev->dev, "failed to reset VF stack\n"); 1565 goto err_reset_lock; 1566 } 1567 1568 /* bring up the nic to enable TX/RX again */ 1569 ret = hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 1570 if (ret) 1571 goto err_reset_lock; 1572 1573 rtnl_unlock(); 1574 1575 hdev->last_reset_time = jiffies; 1576 ae_dev->reset_type = HNAE3_NONE_RESET; 1577 hdev->rst_stats.rst_done_cnt++; 1578 hdev->rst_stats.rst_fail_cnt = 0; 1579 1580 return ret; 1581 err_reset_lock: 1582 rtnl_unlock(); 1583 err_reset: 1584 hclgevf_reset_err_handle(hdev); 1585 1586 return ret; 1587 } 1588 1589 static enum hnae3_reset_type hclgevf_get_reset_level(struct hclgevf_dev *hdev, 1590 unsigned long *addr) 1591 { 1592 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; 1593 1594 /* return the highest priority reset level amongst all */ 1595 if (test_bit(HNAE3_VF_RESET, addr)) { 1596 rst_level = HNAE3_VF_RESET; 1597 clear_bit(HNAE3_VF_RESET, addr); 1598 clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1599 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1600 } else if (test_bit(HNAE3_VF_FULL_RESET, addr)) { 1601 rst_level = HNAE3_VF_FULL_RESET; 1602 clear_bit(HNAE3_VF_FULL_RESET, addr); 1603 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1604 } else if (test_bit(HNAE3_VF_PF_FUNC_RESET, addr)) { 1605 rst_level = HNAE3_VF_PF_FUNC_RESET; 1606 clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1607 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1608 } else if (test_bit(HNAE3_VF_FUNC_RESET, addr)) { 1609 rst_level = HNAE3_VF_FUNC_RESET; 1610 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1611 } else if (test_bit(HNAE3_FLR_RESET, addr)) { 1612 rst_level = HNAE3_FLR_RESET; 1613 clear_bit(HNAE3_FLR_RESET, addr); 1614 } 1615 1616 return rst_level; 1617 } 1618 1619 static void hclgevf_reset_event(struct pci_dev *pdev, 1620 struct hnae3_handle *handle) 1621 { 1622 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 1623 struct hclgevf_dev *hdev = ae_dev->priv; 1624 1625 dev_info(&hdev->pdev->dev, "received reset request from VF enet\n"); 1626 1627 if (hdev->default_reset_request) 1628 hdev->reset_level = 1629 hclgevf_get_reset_level(hdev, 1630 &hdev->default_reset_request); 1631 else 1632 hdev->reset_level = HNAE3_VF_FUNC_RESET; 1633 1634 /* reset of this VF requested */ 1635 set_bit(HCLGEVF_RESET_REQUESTED, &hdev->reset_state); 1636 hclgevf_reset_task_schedule(hdev); 1637 1638 hdev->last_reset_time = jiffies; 1639 } 1640 1641 static void hclgevf_set_def_reset_request(struct hnae3_ae_dev *ae_dev, 1642 enum hnae3_reset_type rst_type) 1643 { 1644 struct hclgevf_dev *hdev = ae_dev->priv; 1645 1646 set_bit(rst_type, &hdev->default_reset_request); 1647 } 1648 1649 static void hclgevf_flr_prepare(struct hnae3_ae_dev *ae_dev) 1650 { 1651 #define HCLGEVF_FLR_WAIT_MS 100 1652 #define HCLGEVF_FLR_WAIT_CNT 50 1653 struct hclgevf_dev *hdev = ae_dev->priv; 1654 int cnt = 0; 1655 1656 clear_bit(HNAE3_FLR_DOWN, &hdev->flr_state); 1657 clear_bit(HNAE3_FLR_DONE, &hdev->flr_state); 1658 set_bit(HNAE3_FLR_RESET, &hdev->default_reset_request); 1659 hclgevf_reset_event(hdev->pdev, NULL); 1660 1661 while (!test_bit(HNAE3_FLR_DOWN, &hdev->flr_state) && 1662 cnt++ < HCLGEVF_FLR_WAIT_CNT) 1663 msleep(HCLGEVF_FLR_WAIT_MS); 1664 1665 if (!test_bit(HNAE3_FLR_DOWN, &hdev->flr_state)) 1666 dev_err(&hdev->pdev->dev, 1667 "flr wait down timeout: %d\n", cnt); 1668 } 1669 1670 static u32 hclgevf_get_fw_version(struct hnae3_handle *handle) 1671 { 1672 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1673 1674 return hdev->fw_version; 1675 } 1676 1677 static void hclgevf_get_misc_vector(struct hclgevf_dev *hdev) 1678 { 1679 struct hclgevf_misc_vector *vector = &hdev->misc_vector; 1680 1681 vector->vector_irq = pci_irq_vector(hdev->pdev, 1682 HCLGEVF_MISC_VECTOR_NUM); 1683 vector->addr = hdev->hw.io_base + HCLGEVF_MISC_VECTOR_REG_BASE; 1684 /* vector status always valid for Vector 0 */ 1685 hdev->vector_status[HCLGEVF_MISC_VECTOR_NUM] = 0; 1686 hdev->vector_irq[HCLGEVF_MISC_VECTOR_NUM] = vector->vector_irq; 1687 1688 hdev->num_msi_left -= 1; 1689 hdev->num_msi_used += 1; 1690 } 1691 1692 void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev) 1693 { 1694 if (!test_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state) && 1695 !test_bit(HCLGEVF_STATE_REMOVING, &hdev->state)) { 1696 set_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state); 1697 schedule_work(&hdev->rst_service_task); 1698 } 1699 } 1700 1701 void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev) 1702 { 1703 if (!test_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state) && 1704 !test_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) { 1705 set_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 1706 schedule_work(&hdev->mbx_service_task); 1707 } 1708 } 1709 1710 static void hclgevf_task_schedule(struct hclgevf_dev *hdev) 1711 { 1712 if (!test_bit(HCLGEVF_STATE_DOWN, &hdev->state) && 1713 !test_and_set_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state)) 1714 schedule_work(&hdev->service_task); 1715 } 1716 1717 static void hclgevf_deferred_task_schedule(struct hclgevf_dev *hdev) 1718 { 1719 /* if we have any pending mailbox event then schedule the mbx task */ 1720 if (hdev->mbx_event_pending) 1721 hclgevf_mbx_task_schedule(hdev); 1722 1723 if (test_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state)) 1724 hclgevf_reset_task_schedule(hdev); 1725 } 1726 1727 static void hclgevf_service_timer(struct timer_list *t) 1728 { 1729 struct hclgevf_dev *hdev = from_timer(hdev, t, service_timer); 1730 1731 mod_timer(&hdev->service_timer, jiffies + 1732 HCLGEVF_GENERAL_TASK_INTERVAL * HZ); 1733 1734 hdev->stats_timer++; 1735 hclgevf_task_schedule(hdev); 1736 } 1737 1738 static void hclgevf_reset_service_task(struct work_struct *work) 1739 { 1740 struct hclgevf_dev *hdev = 1741 container_of(work, struct hclgevf_dev, rst_service_task); 1742 int ret; 1743 1744 if (test_and_set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 1745 return; 1746 1747 clear_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state); 1748 1749 if (test_and_clear_bit(HCLGEVF_RESET_PENDING, 1750 &hdev->reset_state)) { 1751 /* PF has initmated that it is about to reset the hardware. 1752 * We now have to poll & check if hardware has actually 1753 * completed the reset sequence. On hardware reset completion, 1754 * VF needs to reset the client and ae device. 1755 */ 1756 hdev->reset_attempts = 0; 1757 1758 hdev->last_reset_time = jiffies; 1759 while ((hdev->reset_type = 1760 hclgevf_get_reset_level(hdev, &hdev->reset_pending)) 1761 != HNAE3_NONE_RESET) { 1762 ret = hclgevf_reset(hdev); 1763 if (ret) 1764 dev_err(&hdev->pdev->dev, 1765 "VF stack reset failed %d.\n", ret); 1766 } 1767 } else if (test_and_clear_bit(HCLGEVF_RESET_REQUESTED, 1768 &hdev->reset_state)) { 1769 /* we could be here when either of below happens: 1770 * 1. reset was initiated due to watchdog timeout caused by 1771 * a. IMP was earlier reset and our TX got choked down and 1772 * which resulted in watchdog reacting and inducing VF 1773 * reset. This also means our cmdq would be unreliable. 1774 * b. problem in TX due to other lower layer(example link 1775 * layer not functioning properly etc.) 1776 * 2. VF reset might have been initiated due to some config 1777 * change. 1778 * 1779 * NOTE: Theres no clear way to detect above cases than to react 1780 * to the response of PF for this reset request. PF will ack the 1781 * 1b and 2. cases but we will not get any intimation about 1a 1782 * from PF as cmdq would be in unreliable state i.e. mailbox 1783 * communication between PF and VF would be broken. 1784 */ 1785 1786 /* if we are never geting into pending state it means either: 1787 * 1. PF is not receiving our request which could be due to IMP 1788 * reset 1789 * 2. PF is screwed 1790 * We cannot do much for 2. but to check first we can try reset 1791 * our PCIe + stack and see if it alleviates the problem. 1792 */ 1793 if (hdev->reset_attempts > 3) { 1794 /* prepare for full reset of stack + pcie interface */ 1795 set_bit(HNAE3_VF_FULL_RESET, &hdev->reset_pending); 1796 1797 /* "defer" schedule the reset task again */ 1798 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1799 } else { 1800 hdev->reset_attempts++; 1801 1802 set_bit(hdev->reset_level, &hdev->reset_pending); 1803 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1804 } 1805 hclgevf_reset_task_schedule(hdev); 1806 } 1807 1808 clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 1809 } 1810 1811 static void hclgevf_mailbox_service_task(struct work_struct *work) 1812 { 1813 struct hclgevf_dev *hdev; 1814 1815 hdev = container_of(work, struct hclgevf_dev, mbx_service_task); 1816 1817 if (test_and_set_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) 1818 return; 1819 1820 clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 1821 1822 hclgevf_mbx_async_handler(hdev); 1823 1824 clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 1825 } 1826 1827 static void hclgevf_keep_alive_timer(struct timer_list *t) 1828 { 1829 struct hclgevf_dev *hdev = from_timer(hdev, t, keep_alive_timer); 1830 1831 schedule_work(&hdev->keep_alive_task); 1832 mod_timer(&hdev->keep_alive_timer, jiffies + 1833 HCLGEVF_KEEP_ALIVE_TASK_INTERVAL * HZ); 1834 } 1835 1836 static void hclgevf_keep_alive_task(struct work_struct *work) 1837 { 1838 struct hclgevf_dev *hdev; 1839 u8 respmsg; 1840 int ret; 1841 1842 hdev = container_of(work, struct hclgevf_dev, keep_alive_task); 1843 1844 if (test_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state)) 1845 return; 1846 1847 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_KEEP_ALIVE, 0, NULL, 1848 0, false, &respmsg, sizeof(respmsg)); 1849 if (ret) 1850 dev_err(&hdev->pdev->dev, 1851 "VF sends keep alive cmd failed(=%d)\n", ret); 1852 } 1853 1854 static void hclgevf_service_task(struct work_struct *work) 1855 { 1856 struct hnae3_handle *handle; 1857 struct hclgevf_dev *hdev; 1858 1859 hdev = container_of(work, struct hclgevf_dev, service_task); 1860 handle = &hdev->nic; 1861 1862 if (hdev->stats_timer >= HCLGEVF_STATS_TIMER_INTERVAL) { 1863 hclgevf_tqps_update_stats(handle); 1864 hdev->stats_timer = 0; 1865 } 1866 1867 /* request the link status from the PF. PF would be able to tell VF 1868 * about such updates in future so we might remove this later 1869 */ 1870 hclgevf_request_link_info(hdev); 1871 1872 hclgevf_update_link_mode(hdev); 1873 1874 hclgevf_sync_vlan_filter(hdev); 1875 1876 hclgevf_deferred_task_schedule(hdev); 1877 1878 clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 1879 } 1880 1881 static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regclr) 1882 { 1883 hclgevf_write_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_SRC_REG, regclr); 1884 } 1885 1886 static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev, 1887 u32 *clearval) 1888 { 1889 u32 cmdq_src_reg, rst_ing_reg; 1890 1891 /* fetch the events from their corresponding regs */ 1892 cmdq_src_reg = hclgevf_read_dev(&hdev->hw, 1893 HCLGEVF_VECTOR0_CMDQ_SRC_REG); 1894 1895 if (BIT(HCLGEVF_VECTOR0_RST_INT_B) & cmdq_src_reg) { 1896 rst_ing_reg = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 1897 dev_info(&hdev->pdev->dev, 1898 "receive reset interrupt 0x%x!\n", rst_ing_reg); 1899 set_bit(HNAE3_VF_RESET, &hdev->reset_pending); 1900 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1901 set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 1902 cmdq_src_reg &= ~BIT(HCLGEVF_VECTOR0_RST_INT_B); 1903 *clearval = cmdq_src_reg; 1904 hdev->rst_stats.vf_rst_cnt++; 1905 return HCLGEVF_VECTOR0_EVENT_RST; 1906 } 1907 1908 /* check for vector0 mailbox(=CMDQ RX) event source */ 1909 if (BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) { 1910 cmdq_src_reg &= ~BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 1911 *clearval = cmdq_src_reg; 1912 return HCLGEVF_VECTOR0_EVENT_MBX; 1913 } 1914 1915 dev_dbg(&hdev->pdev->dev, "vector 0 interrupt from unknown source\n"); 1916 1917 return HCLGEVF_VECTOR0_EVENT_OTHER; 1918 } 1919 1920 static void hclgevf_enable_vector(struct hclgevf_misc_vector *vector, bool en) 1921 { 1922 writel(en ? 1 : 0, vector->addr); 1923 } 1924 1925 static irqreturn_t hclgevf_misc_irq_handle(int irq, void *data) 1926 { 1927 enum hclgevf_evt_cause event_cause; 1928 struct hclgevf_dev *hdev = data; 1929 u32 clearval; 1930 1931 hclgevf_enable_vector(&hdev->misc_vector, false); 1932 event_cause = hclgevf_check_evt_cause(hdev, &clearval); 1933 1934 switch (event_cause) { 1935 case HCLGEVF_VECTOR0_EVENT_RST: 1936 hclgevf_reset_task_schedule(hdev); 1937 break; 1938 case HCLGEVF_VECTOR0_EVENT_MBX: 1939 hclgevf_mbx_handler(hdev); 1940 break; 1941 default: 1942 break; 1943 } 1944 1945 if (event_cause != HCLGEVF_VECTOR0_EVENT_OTHER) { 1946 hclgevf_clear_event_cause(hdev, clearval); 1947 hclgevf_enable_vector(&hdev->misc_vector, true); 1948 } 1949 1950 return IRQ_HANDLED; 1951 } 1952 1953 static int hclgevf_configure(struct hclgevf_dev *hdev) 1954 { 1955 int ret; 1956 1957 /* get current port based vlan state from PF */ 1958 ret = hclgevf_get_port_base_vlan_filter_state(hdev); 1959 if (ret) 1960 return ret; 1961 1962 /* get queue configuration from PF */ 1963 ret = hclgevf_get_queue_info(hdev); 1964 if (ret) 1965 return ret; 1966 1967 /* get queue depth info from PF */ 1968 ret = hclgevf_get_queue_depth(hdev); 1969 if (ret) 1970 return ret; 1971 1972 ret = hclgevf_get_pf_media_type(hdev); 1973 if (ret) 1974 return ret; 1975 1976 /* get tc configuration from PF */ 1977 return hclgevf_get_tc_info(hdev); 1978 } 1979 1980 static int hclgevf_alloc_hdev(struct hnae3_ae_dev *ae_dev) 1981 { 1982 struct pci_dev *pdev = ae_dev->pdev; 1983 struct hclgevf_dev *hdev; 1984 1985 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 1986 if (!hdev) 1987 return -ENOMEM; 1988 1989 hdev->pdev = pdev; 1990 hdev->ae_dev = ae_dev; 1991 ae_dev->priv = hdev; 1992 1993 return 0; 1994 } 1995 1996 static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev) 1997 { 1998 struct hnae3_handle *roce = &hdev->roce; 1999 struct hnae3_handle *nic = &hdev->nic; 2000 2001 roce->rinfo.num_vectors = hdev->num_roce_msix; 2002 2003 if (hdev->num_msi_left < roce->rinfo.num_vectors || 2004 hdev->num_msi_left == 0) 2005 return -EINVAL; 2006 2007 roce->rinfo.base_vector = hdev->roce_base_vector; 2008 2009 roce->rinfo.netdev = nic->kinfo.netdev; 2010 roce->rinfo.roce_io_base = hdev->hw.io_base; 2011 2012 roce->pdev = nic->pdev; 2013 roce->ae_algo = nic->ae_algo; 2014 roce->numa_node_mask = nic->numa_node_mask; 2015 2016 return 0; 2017 } 2018 2019 static int hclgevf_config_gro(struct hclgevf_dev *hdev, bool en) 2020 { 2021 struct hclgevf_cfg_gro_status_cmd *req; 2022 struct hclgevf_desc desc; 2023 int ret; 2024 2025 if (!hnae3_dev_gro_supported(hdev)) 2026 return 0; 2027 2028 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_GRO_GENERIC_CONFIG, 2029 false); 2030 req = (struct hclgevf_cfg_gro_status_cmd *)desc.data; 2031 2032 req->gro_en = cpu_to_le16(en ? 1 : 0); 2033 2034 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 2035 if (ret) 2036 dev_err(&hdev->pdev->dev, 2037 "VF GRO hardware config cmd failed, ret = %d.\n", ret); 2038 2039 return ret; 2040 } 2041 2042 static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev) 2043 { 2044 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 2045 int i, ret; 2046 2047 rss_cfg->rss_size = hdev->rss_size_max; 2048 2049 if (hdev->pdev->revision >= 0x21) { 2050 rss_cfg->hash_algo = HCLGEVF_RSS_HASH_ALGO_SIMPLE; 2051 memcpy(rss_cfg->rss_hash_key, hclgevf_hash_key, 2052 HCLGEVF_RSS_KEY_SIZE); 2053 2054 ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 2055 rss_cfg->rss_hash_key); 2056 if (ret) 2057 return ret; 2058 2059 rss_cfg->rss_tuple_sets.ipv4_tcp_en = 2060 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2061 rss_cfg->rss_tuple_sets.ipv4_udp_en = 2062 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2063 rss_cfg->rss_tuple_sets.ipv4_sctp_en = 2064 HCLGEVF_RSS_INPUT_TUPLE_SCTP; 2065 rss_cfg->rss_tuple_sets.ipv4_fragment_en = 2066 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2067 rss_cfg->rss_tuple_sets.ipv6_tcp_en = 2068 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2069 rss_cfg->rss_tuple_sets.ipv6_udp_en = 2070 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2071 rss_cfg->rss_tuple_sets.ipv6_sctp_en = 2072 HCLGEVF_RSS_INPUT_TUPLE_SCTP; 2073 rss_cfg->rss_tuple_sets.ipv6_fragment_en = 2074 HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2075 2076 ret = hclgevf_set_rss_input_tuple(hdev, rss_cfg); 2077 if (ret) 2078 return ret; 2079 2080 } 2081 2082 /* Initialize RSS indirect table */ 2083 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++) 2084 rss_cfg->rss_indirection_tbl[i] = i % hdev->rss_size_max; 2085 2086 ret = hclgevf_set_rss_indir_table(hdev); 2087 if (ret) 2088 return ret; 2089 2090 return hclgevf_set_rss_tc_mode(hdev, hdev->rss_size_max); 2091 } 2092 2093 static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev) 2094 { 2095 return hclgevf_set_vlan_filter(&hdev->nic, htons(ETH_P_8021Q), 0, 2096 false); 2097 } 2098 2099 static void hclgevf_set_timer_task(struct hnae3_handle *handle, bool enable) 2100 { 2101 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2102 2103 if (enable) { 2104 mod_timer(&hdev->service_timer, jiffies + HZ); 2105 } else { 2106 del_timer_sync(&hdev->service_timer); 2107 cancel_work_sync(&hdev->service_task); 2108 clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 2109 } 2110 } 2111 2112 static int hclgevf_ae_start(struct hnae3_handle *handle) 2113 { 2114 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2115 2116 hclgevf_reset_tqp_stats(handle); 2117 2118 hclgevf_request_link_info(hdev); 2119 2120 hclgevf_update_link_mode(hdev); 2121 2122 clear_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2123 2124 return 0; 2125 } 2126 2127 static void hclgevf_ae_stop(struct hnae3_handle *handle) 2128 { 2129 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2130 int i; 2131 2132 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2133 2134 if (hdev->reset_type != HNAE3_VF_RESET) 2135 for (i = 0; i < handle->kinfo.num_tqps; i++) 2136 if (hclgevf_reset_tqp(handle, i)) 2137 break; 2138 2139 hclgevf_reset_tqp_stats(handle); 2140 hclgevf_update_link_status(hdev, 0); 2141 } 2142 2143 static int hclgevf_set_alive(struct hnae3_handle *handle, bool alive) 2144 { 2145 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2146 u8 msg_data; 2147 2148 msg_data = alive ? 1 : 0; 2149 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_ALIVE, 2150 0, &msg_data, 1, false, NULL, 0); 2151 } 2152 2153 static int hclgevf_client_start(struct hnae3_handle *handle) 2154 { 2155 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2156 int ret; 2157 2158 ret = hclgevf_set_alive(handle, true); 2159 if (ret) 2160 return ret; 2161 2162 mod_timer(&hdev->keep_alive_timer, jiffies + 2163 HCLGEVF_KEEP_ALIVE_TASK_INTERVAL * HZ); 2164 2165 return 0; 2166 } 2167 2168 static void hclgevf_client_stop(struct hnae3_handle *handle) 2169 { 2170 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2171 int ret; 2172 2173 ret = hclgevf_set_alive(handle, false); 2174 if (ret) 2175 dev_warn(&hdev->pdev->dev, 2176 "%s failed %d\n", __func__, ret); 2177 2178 del_timer_sync(&hdev->keep_alive_timer); 2179 cancel_work_sync(&hdev->keep_alive_task); 2180 } 2181 2182 static void hclgevf_state_init(struct hclgevf_dev *hdev) 2183 { 2184 /* setup tasks for the MBX */ 2185 INIT_WORK(&hdev->mbx_service_task, hclgevf_mailbox_service_task); 2186 clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 2187 clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 2188 2189 /* setup tasks for service timer */ 2190 timer_setup(&hdev->service_timer, hclgevf_service_timer, 0); 2191 2192 INIT_WORK(&hdev->service_task, hclgevf_service_task); 2193 clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state); 2194 2195 INIT_WORK(&hdev->rst_service_task, hclgevf_reset_service_task); 2196 2197 mutex_init(&hdev->mbx_resp.mbx_mutex); 2198 2199 /* bring the device down */ 2200 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2201 } 2202 2203 static void hclgevf_state_uninit(struct hclgevf_dev *hdev) 2204 { 2205 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2206 set_bit(HCLGEVF_STATE_REMOVING, &hdev->state); 2207 2208 if (hdev->keep_alive_timer.function) 2209 del_timer_sync(&hdev->keep_alive_timer); 2210 if (hdev->keep_alive_task.func) 2211 cancel_work_sync(&hdev->keep_alive_task); 2212 if (hdev->service_timer.function) 2213 del_timer_sync(&hdev->service_timer); 2214 if (hdev->service_task.func) 2215 cancel_work_sync(&hdev->service_task); 2216 if (hdev->mbx_service_task.func) 2217 cancel_work_sync(&hdev->mbx_service_task); 2218 if (hdev->rst_service_task.func) 2219 cancel_work_sync(&hdev->rst_service_task); 2220 2221 mutex_destroy(&hdev->mbx_resp.mbx_mutex); 2222 } 2223 2224 static int hclgevf_init_msi(struct hclgevf_dev *hdev) 2225 { 2226 struct pci_dev *pdev = hdev->pdev; 2227 int vectors; 2228 int i; 2229 2230 if (hnae3_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B)) 2231 vectors = pci_alloc_irq_vectors(pdev, 2232 hdev->roce_base_msix_offset + 1, 2233 hdev->num_msi, 2234 PCI_IRQ_MSIX); 2235 else 2236 vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi, 2237 PCI_IRQ_MSI | PCI_IRQ_MSIX); 2238 2239 if (vectors < 0) { 2240 dev_err(&pdev->dev, 2241 "failed(%d) to allocate MSI/MSI-X vectors\n", 2242 vectors); 2243 return vectors; 2244 } 2245 if (vectors < hdev->num_msi) 2246 dev_warn(&hdev->pdev->dev, 2247 "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n", 2248 hdev->num_msi, vectors); 2249 2250 hdev->num_msi = vectors; 2251 hdev->num_msi_left = vectors; 2252 hdev->base_msi_vector = pdev->irq; 2253 hdev->roce_base_vector = pdev->irq + hdev->roce_base_msix_offset; 2254 2255 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 2256 sizeof(u16), GFP_KERNEL); 2257 if (!hdev->vector_status) { 2258 pci_free_irq_vectors(pdev); 2259 return -ENOMEM; 2260 } 2261 2262 for (i = 0; i < hdev->num_msi; i++) 2263 hdev->vector_status[i] = HCLGEVF_INVALID_VPORT; 2264 2265 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 2266 sizeof(int), GFP_KERNEL); 2267 if (!hdev->vector_irq) { 2268 devm_kfree(&pdev->dev, hdev->vector_status); 2269 pci_free_irq_vectors(pdev); 2270 return -ENOMEM; 2271 } 2272 2273 return 0; 2274 } 2275 2276 static void hclgevf_uninit_msi(struct hclgevf_dev *hdev) 2277 { 2278 struct pci_dev *pdev = hdev->pdev; 2279 2280 devm_kfree(&pdev->dev, hdev->vector_status); 2281 devm_kfree(&pdev->dev, hdev->vector_irq); 2282 pci_free_irq_vectors(pdev); 2283 } 2284 2285 static int hclgevf_misc_irq_init(struct hclgevf_dev *hdev) 2286 { 2287 int ret = 0; 2288 2289 hclgevf_get_misc_vector(hdev); 2290 2291 ret = request_irq(hdev->misc_vector.vector_irq, hclgevf_misc_irq_handle, 2292 0, "hclgevf_cmd", hdev); 2293 if (ret) { 2294 dev_err(&hdev->pdev->dev, "VF failed to request misc irq(%d)\n", 2295 hdev->misc_vector.vector_irq); 2296 return ret; 2297 } 2298 2299 hclgevf_clear_event_cause(hdev, 0); 2300 2301 /* enable misc. vector(vector 0) */ 2302 hclgevf_enable_vector(&hdev->misc_vector, true); 2303 2304 return ret; 2305 } 2306 2307 static void hclgevf_misc_irq_uninit(struct hclgevf_dev *hdev) 2308 { 2309 /* disable misc vector(vector 0) */ 2310 hclgevf_enable_vector(&hdev->misc_vector, false); 2311 synchronize_irq(hdev->misc_vector.vector_irq); 2312 free_irq(hdev->misc_vector.vector_irq, hdev); 2313 hclgevf_free_vector(hdev, 0); 2314 } 2315 2316 static void hclgevf_info_show(struct hclgevf_dev *hdev) 2317 { 2318 struct device *dev = &hdev->pdev->dev; 2319 2320 dev_info(dev, "VF info begin:\n"); 2321 2322 dev_info(dev, "Task queue pairs numbers: %d\n", hdev->num_tqps); 2323 dev_info(dev, "Desc num per TX queue: %d\n", hdev->num_tx_desc); 2324 dev_info(dev, "Desc num per RX queue: %d\n", hdev->num_rx_desc); 2325 dev_info(dev, "Numbers of vports: %d\n", hdev->num_alloc_vport); 2326 dev_info(dev, "HW tc map: %d\n", hdev->hw_tc_map); 2327 dev_info(dev, "PF media type of this VF: %d\n", 2328 hdev->hw.mac.media_type); 2329 2330 dev_info(dev, "VF info end.\n"); 2331 } 2332 2333 static int hclgevf_init_nic_client_instance(struct hnae3_ae_dev *ae_dev, 2334 struct hnae3_client *client) 2335 { 2336 struct hclgevf_dev *hdev = ae_dev->priv; 2337 int ret; 2338 2339 ret = client->ops->init_instance(&hdev->nic); 2340 if (ret) 2341 return ret; 2342 2343 set_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 2344 hnae3_set_client_init_flag(client, ae_dev, 1); 2345 2346 if (netif_msg_drv(&hdev->nic)) 2347 hclgevf_info_show(hdev); 2348 2349 return 0; 2350 } 2351 2352 static int hclgevf_init_roce_client_instance(struct hnae3_ae_dev *ae_dev, 2353 struct hnae3_client *client) 2354 { 2355 struct hclgevf_dev *hdev = ae_dev->priv; 2356 int ret; 2357 2358 if (!hnae3_dev_roce_supported(hdev) || !hdev->roce_client || 2359 !hdev->nic_client) 2360 return 0; 2361 2362 ret = hclgevf_init_roce_base_info(hdev); 2363 if (ret) 2364 return ret; 2365 2366 ret = client->ops->init_instance(&hdev->roce); 2367 if (ret) 2368 return ret; 2369 2370 hnae3_set_client_init_flag(client, ae_dev, 1); 2371 2372 return 0; 2373 } 2374 2375 static int hclgevf_init_client_instance(struct hnae3_client *client, 2376 struct hnae3_ae_dev *ae_dev) 2377 { 2378 struct hclgevf_dev *hdev = ae_dev->priv; 2379 int ret; 2380 2381 switch (client->type) { 2382 case HNAE3_CLIENT_KNIC: 2383 hdev->nic_client = client; 2384 hdev->nic.client = client; 2385 2386 ret = hclgevf_init_nic_client_instance(ae_dev, client); 2387 if (ret) 2388 goto clear_nic; 2389 2390 ret = hclgevf_init_roce_client_instance(ae_dev, 2391 hdev->roce_client); 2392 if (ret) 2393 goto clear_roce; 2394 2395 break; 2396 case HNAE3_CLIENT_ROCE: 2397 if (hnae3_dev_roce_supported(hdev)) { 2398 hdev->roce_client = client; 2399 hdev->roce.client = client; 2400 } 2401 2402 ret = hclgevf_init_roce_client_instance(ae_dev, client); 2403 if (ret) 2404 goto clear_roce; 2405 2406 break; 2407 default: 2408 return -EINVAL; 2409 } 2410 2411 return 0; 2412 2413 clear_nic: 2414 hdev->nic_client = NULL; 2415 hdev->nic.client = NULL; 2416 return ret; 2417 clear_roce: 2418 hdev->roce_client = NULL; 2419 hdev->roce.client = NULL; 2420 return ret; 2421 } 2422 2423 static void hclgevf_uninit_client_instance(struct hnae3_client *client, 2424 struct hnae3_ae_dev *ae_dev) 2425 { 2426 struct hclgevf_dev *hdev = ae_dev->priv; 2427 2428 /* un-init roce, if it exists */ 2429 if (hdev->roce_client) { 2430 hdev->roce_client->ops->uninit_instance(&hdev->roce, 0); 2431 hdev->roce_client = NULL; 2432 hdev->roce.client = NULL; 2433 } 2434 2435 /* un-init nic/unic, if this was not called by roce client */ 2436 if (client->ops->uninit_instance && hdev->nic_client && 2437 client->type != HNAE3_CLIENT_ROCE) { 2438 clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 2439 2440 client->ops->uninit_instance(&hdev->nic, 0); 2441 hdev->nic_client = NULL; 2442 hdev->nic.client = NULL; 2443 } 2444 } 2445 2446 static int hclgevf_pci_init(struct hclgevf_dev *hdev) 2447 { 2448 struct pci_dev *pdev = hdev->pdev; 2449 struct hclgevf_hw *hw; 2450 int ret; 2451 2452 ret = pci_enable_device(pdev); 2453 if (ret) { 2454 dev_err(&pdev->dev, "failed to enable PCI device\n"); 2455 return ret; 2456 } 2457 2458 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 2459 if (ret) { 2460 dev_err(&pdev->dev, "can't set consistent PCI DMA, exiting"); 2461 goto err_disable_device; 2462 } 2463 2464 ret = pci_request_regions(pdev, HCLGEVF_DRIVER_NAME); 2465 if (ret) { 2466 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 2467 goto err_disable_device; 2468 } 2469 2470 pci_set_master(pdev); 2471 hw = &hdev->hw; 2472 hw->hdev = hdev; 2473 hw->io_base = pci_iomap(pdev, 2, 0); 2474 if (!hw->io_base) { 2475 dev_err(&pdev->dev, "can't map configuration register space\n"); 2476 ret = -ENOMEM; 2477 goto err_clr_master; 2478 } 2479 2480 return 0; 2481 2482 err_clr_master: 2483 pci_clear_master(pdev); 2484 pci_release_regions(pdev); 2485 err_disable_device: 2486 pci_disable_device(pdev); 2487 2488 return ret; 2489 } 2490 2491 static void hclgevf_pci_uninit(struct hclgevf_dev *hdev) 2492 { 2493 struct pci_dev *pdev = hdev->pdev; 2494 2495 pci_iounmap(pdev, hdev->hw.io_base); 2496 pci_clear_master(pdev); 2497 pci_release_regions(pdev); 2498 pci_disable_device(pdev); 2499 } 2500 2501 static int hclgevf_query_vf_resource(struct hclgevf_dev *hdev) 2502 { 2503 struct hclgevf_query_res_cmd *req; 2504 struct hclgevf_desc desc; 2505 int ret; 2506 2507 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_VF_RSRC, true); 2508 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 2509 if (ret) { 2510 dev_err(&hdev->pdev->dev, 2511 "query vf resource failed, ret = %d.\n", ret); 2512 return ret; 2513 } 2514 2515 req = (struct hclgevf_query_res_cmd *)desc.data; 2516 2517 if (hnae3_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B)) { 2518 hdev->roce_base_msix_offset = 2519 hnae3_get_field(__le16_to_cpu(req->msixcap_localid_ba_rocee), 2520 HCLGEVF_MSIX_OFT_ROCEE_M, 2521 HCLGEVF_MSIX_OFT_ROCEE_S); 2522 hdev->num_roce_msix = 2523 hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number), 2524 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 2525 2526 /* VF should have NIC vectors and Roce vectors, NIC vectors 2527 * are queued before Roce vectors. The offset is fixed to 64. 2528 */ 2529 hdev->num_msi = hdev->num_roce_msix + 2530 hdev->roce_base_msix_offset; 2531 } else { 2532 hdev->num_msi = 2533 hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number), 2534 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 2535 } 2536 2537 return 0; 2538 } 2539 2540 static int hclgevf_pci_reset(struct hclgevf_dev *hdev) 2541 { 2542 struct pci_dev *pdev = hdev->pdev; 2543 int ret = 0; 2544 2545 if (hdev->reset_type == HNAE3_VF_FULL_RESET && 2546 test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2547 hclgevf_misc_irq_uninit(hdev); 2548 hclgevf_uninit_msi(hdev); 2549 clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2550 } 2551 2552 if (!test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2553 pci_set_master(pdev); 2554 ret = hclgevf_init_msi(hdev); 2555 if (ret) { 2556 dev_err(&pdev->dev, 2557 "failed(%d) to init MSI/MSI-X\n", ret); 2558 return ret; 2559 } 2560 2561 ret = hclgevf_misc_irq_init(hdev); 2562 if (ret) { 2563 hclgevf_uninit_msi(hdev); 2564 dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 2565 ret); 2566 return ret; 2567 } 2568 2569 set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2570 } 2571 2572 return ret; 2573 } 2574 2575 static int hclgevf_reset_hdev(struct hclgevf_dev *hdev) 2576 { 2577 struct pci_dev *pdev = hdev->pdev; 2578 int ret; 2579 2580 ret = hclgevf_pci_reset(hdev); 2581 if (ret) { 2582 dev_err(&pdev->dev, "pci reset failed %d\n", ret); 2583 return ret; 2584 } 2585 2586 ret = hclgevf_cmd_init(hdev); 2587 if (ret) { 2588 dev_err(&pdev->dev, "cmd failed %d\n", ret); 2589 return ret; 2590 } 2591 2592 ret = hclgevf_rss_init_hw(hdev); 2593 if (ret) { 2594 dev_err(&hdev->pdev->dev, 2595 "failed(%d) to initialize RSS\n", ret); 2596 return ret; 2597 } 2598 2599 ret = hclgevf_config_gro(hdev, true); 2600 if (ret) 2601 return ret; 2602 2603 ret = hclgevf_init_vlan_config(hdev); 2604 if (ret) { 2605 dev_err(&hdev->pdev->dev, 2606 "failed(%d) to initialize VLAN config\n", ret); 2607 return ret; 2608 } 2609 2610 if (pdev->revision >= 0x21) { 2611 ret = hclgevf_set_promisc_mode(hdev, true); 2612 if (ret) 2613 return ret; 2614 } 2615 2616 dev_info(&hdev->pdev->dev, "Reset done\n"); 2617 2618 return 0; 2619 } 2620 2621 static int hclgevf_init_hdev(struct hclgevf_dev *hdev) 2622 { 2623 struct pci_dev *pdev = hdev->pdev; 2624 int ret; 2625 2626 ret = hclgevf_pci_init(hdev); 2627 if (ret) { 2628 dev_err(&pdev->dev, "PCI initialization failed\n"); 2629 return ret; 2630 } 2631 2632 ret = hclgevf_cmd_queue_init(hdev); 2633 if (ret) { 2634 dev_err(&pdev->dev, "Cmd queue init failed: %d\n", ret); 2635 goto err_cmd_queue_init; 2636 } 2637 2638 ret = hclgevf_cmd_init(hdev); 2639 if (ret) 2640 goto err_cmd_init; 2641 2642 /* Get vf resource */ 2643 ret = hclgevf_query_vf_resource(hdev); 2644 if (ret) { 2645 dev_err(&hdev->pdev->dev, 2646 "Query vf status error, ret = %d.\n", ret); 2647 goto err_cmd_init; 2648 } 2649 2650 ret = hclgevf_init_msi(hdev); 2651 if (ret) { 2652 dev_err(&pdev->dev, "failed(%d) to init MSI/MSI-X\n", ret); 2653 goto err_cmd_init; 2654 } 2655 2656 hclgevf_state_init(hdev); 2657 hdev->reset_level = HNAE3_VF_FUNC_RESET; 2658 2659 ret = hclgevf_misc_irq_init(hdev); 2660 if (ret) { 2661 dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 2662 ret); 2663 goto err_misc_irq_init; 2664 } 2665 2666 set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2667 2668 ret = hclgevf_configure(hdev); 2669 if (ret) { 2670 dev_err(&pdev->dev, "failed(%d) to fetch configuration\n", ret); 2671 goto err_config; 2672 } 2673 2674 ret = hclgevf_alloc_tqps(hdev); 2675 if (ret) { 2676 dev_err(&pdev->dev, "failed(%d) to allocate TQPs\n", ret); 2677 goto err_config; 2678 } 2679 2680 ret = hclgevf_set_handle_info(hdev); 2681 if (ret) { 2682 dev_err(&pdev->dev, "failed(%d) to set handle info\n", ret); 2683 goto err_config; 2684 } 2685 2686 ret = hclgevf_config_gro(hdev, true); 2687 if (ret) 2688 goto err_config; 2689 2690 /* vf is not allowed to enable unicast/multicast promisc mode. 2691 * For revision 0x20, default to disable broadcast promisc mode, 2692 * firmware makes sure broadcast packets can be accepted. 2693 * For revision 0x21, default to enable broadcast promisc mode. 2694 */ 2695 if (pdev->revision >= 0x21) { 2696 ret = hclgevf_set_promisc_mode(hdev, true); 2697 if (ret) 2698 goto err_config; 2699 } 2700 2701 /* Initialize RSS for this VF */ 2702 ret = hclgevf_rss_init_hw(hdev); 2703 if (ret) { 2704 dev_err(&hdev->pdev->dev, 2705 "failed(%d) to initialize RSS\n", ret); 2706 goto err_config; 2707 } 2708 2709 ret = hclgevf_init_vlan_config(hdev); 2710 if (ret) { 2711 dev_err(&hdev->pdev->dev, 2712 "failed(%d) to initialize VLAN config\n", ret); 2713 goto err_config; 2714 } 2715 2716 hdev->last_reset_time = jiffies; 2717 dev_info(&hdev->pdev->dev, "finished initializing %s driver\n", 2718 HCLGEVF_DRIVER_NAME); 2719 2720 return 0; 2721 2722 err_config: 2723 hclgevf_misc_irq_uninit(hdev); 2724 err_misc_irq_init: 2725 hclgevf_state_uninit(hdev); 2726 hclgevf_uninit_msi(hdev); 2727 err_cmd_init: 2728 hclgevf_cmd_uninit(hdev); 2729 err_cmd_queue_init: 2730 hclgevf_pci_uninit(hdev); 2731 clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 2732 return ret; 2733 } 2734 2735 static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev) 2736 { 2737 hclgevf_state_uninit(hdev); 2738 2739 if (test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 2740 hclgevf_misc_irq_uninit(hdev); 2741 hclgevf_uninit_msi(hdev); 2742 } 2743 2744 hclgevf_pci_uninit(hdev); 2745 hclgevf_cmd_uninit(hdev); 2746 } 2747 2748 static int hclgevf_init_ae_dev(struct hnae3_ae_dev *ae_dev) 2749 { 2750 struct pci_dev *pdev = ae_dev->pdev; 2751 struct hclgevf_dev *hdev; 2752 int ret; 2753 2754 ret = hclgevf_alloc_hdev(ae_dev); 2755 if (ret) { 2756 dev_err(&pdev->dev, "hclge device allocation failed\n"); 2757 return ret; 2758 } 2759 2760 ret = hclgevf_init_hdev(ae_dev->priv); 2761 if (ret) { 2762 dev_err(&pdev->dev, "hclge device initialization failed\n"); 2763 return ret; 2764 } 2765 2766 hdev = ae_dev->priv; 2767 timer_setup(&hdev->keep_alive_timer, hclgevf_keep_alive_timer, 0); 2768 INIT_WORK(&hdev->keep_alive_task, hclgevf_keep_alive_task); 2769 2770 return 0; 2771 } 2772 2773 static void hclgevf_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 2774 { 2775 struct hclgevf_dev *hdev = ae_dev->priv; 2776 2777 hclgevf_uninit_hdev(hdev); 2778 ae_dev->priv = NULL; 2779 } 2780 2781 static u32 hclgevf_get_max_channels(struct hclgevf_dev *hdev) 2782 { 2783 struct hnae3_handle *nic = &hdev->nic; 2784 struct hnae3_knic_private_info *kinfo = &nic->kinfo; 2785 2786 return min_t(u32, hdev->rss_size_max, 2787 hdev->num_tqps / kinfo->num_tc); 2788 } 2789 2790 /** 2791 * hclgevf_get_channels - Get the current channels enabled and max supported. 2792 * @handle: hardware information for network interface 2793 * @ch: ethtool channels structure 2794 * 2795 * We don't support separate tx and rx queues as channels. The other count 2796 * represents how many queues are being used for control. max_combined counts 2797 * how many queue pairs we can support. They may not be mapped 1 to 1 with 2798 * q_vectors since we support a lot more queue pairs than q_vectors. 2799 **/ 2800 static void hclgevf_get_channels(struct hnae3_handle *handle, 2801 struct ethtool_channels *ch) 2802 { 2803 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2804 2805 ch->max_combined = hclgevf_get_max_channels(hdev); 2806 ch->other_count = 0; 2807 ch->max_other = 0; 2808 ch->combined_count = handle->kinfo.rss_size; 2809 } 2810 2811 static void hclgevf_get_tqps_and_rss_info(struct hnae3_handle *handle, 2812 u16 *alloc_tqps, u16 *max_rss_size) 2813 { 2814 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2815 2816 *alloc_tqps = hdev->num_tqps; 2817 *max_rss_size = hdev->rss_size_max; 2818 } 2819 2820 static int hclgevf_get_status(struct hnae3_handle *handle) 2821 { 2822 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2823 2824 return hdev->hw.mac.link; 2825 } 2826 2827 static void hclgevf_get_ksettings_an_result(struct hnae3_handle *handle, 2828 u8 *auto_neg, u32 *speed, 2829 u8 *duplex) 2830 { 2831 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2832 2833 if (speed) 2834 *speed = hdev->hw.mac.speed; 2835 if (duplex) 2836 *duplex = hdev->hw.mac.duplex; 2837 if (auto_neg) 2838 *auto_neg = AUTONEG_DISABLE; 2839 } 2840 2841 void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed, 2842 u8 duplex) 2843 { 2844 hdev->hw.mac.speed = speed; 2845 hdev->hw.mac.duplex = duplex; 2846 } 2847 2848 static int hclgevf_gro_en(struct hnae3_handle *handle, bool enable) 2849 { 2850 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2851 2852 return hclgevf_config_gro(hdev, enable); 2853 } 2854 2855 static void hclgevf_get_media_type(struct hnae3_handle *handle, u8 *media_type, 2856 u8 *module_type) 2857 { 2858 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2859 2860 if (media_type) 2861 *media_type = hdev->hw.mac.media_type; 2862 2863 if (module_type) 2864 *module_type = hdev->hw.mac.module_type; 2865 } 2866 2867 static bool hclgevf_get_hw_reset_stat(struct hnae3_handle *handle) 2868 { 2869 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2870 2871 return !!hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 2872 } 2873 2874 static bool hclgevf_ae_dev_resetting(struct hnae3_handle *handle) 2875 { 2876 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2877 2878 return test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 2879 } 2880 2881 static unsigned long hclgevf_ae_dev_reset_cnt(struct hnae3_handle *handle) 2882 { 2883 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2884 2885 return hdev->rst_stats.hw_rst_done_cnt; 2886 } 2887 2888 static void hclgevf_get_link_mode(struct hnae3_handle *handle, 2889 unsigned long *supported, 2890 unsigned long *advertising) 2891 { 2892 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2893 2894 *supported = hdev->hw.mac.supported; 2895 *advertising = hdev->hw.mac.advertising; 2896 } 2897 2898 #define MAX_SEPARATE_NUM 4 2899 #define SEPARATOR_VALUE 0xFFFFFFFF 2900 #define REG_NUM_PER_LINE 4 2901 #define REG_LEN_PER_LINE (REG_NUM_PER_LINE * sizeof(u32)) 2902 2903 static int hclgevf_get_regs_len(struct hnae3_handle *handle) 2904 { 2905 int cmdq_lines, common_lines, ring_lines, tqp_intr_lines; 2906 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2907 2908 cmdq_lines = sizeof(cmdq_reg_addr_list) / REG_LEN_PER_LINE + 1; 2909 common_lines = sizeof(common_reg_addr_list) / REG_LEN_PER_LINE + 1; 2910 ring_lines = sizeof(ring_reg_addr_list) / REG_LEN_PER_LINE + 1; 2911 tqp_intr_lines = sizeof(tqp_intr_reg_addr_list) / REG_LEN_PER_LINE + 1; 2912 2913 return (cmdq_lines + common_lines + ring_lines * hdev->num_tqps + 2914 tqp_intr_lines * (hdev->num_msi_used - 1)) * REG_LEN_PER_LINE; 2915 } 2916 2917 static void hclgevf_get_regs(struct hnae3_handle *handle, u32 *version, 2918 void *data) 2919 { 2920 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2921 int i, j, reg_um, separator_num; 2922 u32 *reg = data; 2923 2924 *version = hdev->fw_version; 2925 2926 /* fetching per-VF registers values from VF PCIe register space */ 2927 reg_um = sizeof(cmdq_reg_addr_list) / sizeof(u32); 2928 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 2929 for (i = 0; i < reg_um; i++) 2930 *reg++ = hclgevf_read_dev(&hdev->hw, cmdq_reg_addr_list[i]); 2931 for (i = 0; i < separator_num; i++) 2932 *reg++ = SEPARATOR_VALUE; 2933 2934 reg_um = sizeof(common_reg_addr_list) / sizeof(u32); 2935 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 2936 for (i = 0; i < reg_um; i++) 2937 *reg++ = hclgevf_read_dev(&hdev->hw, common_reg_addr_list[i]); 2938 for (i = 0; i < separator_num; i++) 2939 *reg++ = SEPARATOR_VALUE; 2940 2941 reg_um = sizeof(ring_reg_addr_list) / sizeof(u32); 2942 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 2943 for (j = 0; j < hdev->num_tqps; j++) { 2944 for (i = 0; i < reg_um; i++) 2945 *reg++ = hclgevf_read_dev(&hdev->hw, 2946 ring_reg_addr_list[i] + 2947 0x200 * j); 2948 for (i = 0; i < separator_num; i++) 2949 *reg++ = SEPARATOR_VALUE; 2950 } 2951 2952 reg_um = sizeof(tqp_intr_reg_addr_list) / sizeof(u32); 2953 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 2954 for (j = 0; j < hdev->num_msi_used - 1; j++) { 2955 for (i = 0; i < reg_um; i++) 2956 *reg++ = hclgevf_read_dev(&hdev->hw, 2957 tqp_intr_reg_addr_list[i] + 2958 4 * j); 2959 for (i = 0; i < separator_num; i++) 2960 *reg++ = SEPARATOR_VALUE; 2961 } 2962 } 2963 2964 void hclgevf_update_port_base_vlan_info(struct hclgevf_dev *hdev, u16 state, 2965 u8 *port_base_vlan_info, u8 data_size) 2966 { 2967 struct hnae3_handle *nic = &hdev->nic; 2968 2969 rtnl_lock(); 2970 hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 2971 rtnl_unlock(); 2972 2973 /* send msg to PF and wait update port based vlan info */ 2974 hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN, 2975 HCLGE_MBX_PORT_BASE_VLAN_CFG, 2976 port_base_vlan_info, data_size, 2977 false, NULL, 0); 2978 2979 if (state == HNAE3_PORT_BASE_VLAN_DISABLE) 2980 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_DISABLE; 2981 else 2982 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_ENABLE; 2983 2984 rtnl_lock(); 2985 hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 2986 rtnl_unlock(); 2987 } 2988 2989 static const struct hnae3_ae_ops hclgevf_ops = { 2990 .init_ae_dev = hclgevf_init_ae_dev, 2991 .uninit_ae_dev = hclgevf_uninit_ae_dev, 2992 .flr_prepare = hclgevf_flr_prepare, 2993 .flr_done = hclgevf_flr_done, 2994 .init_client_instance = hclgevf_init_client_instance, 2995 .uninit_client_instance = hclgevf_uninit_client_instance, 2996 .start = hclgevf_ae_start, 2997 .stop = hclgevf_ae_stop, 2998 .client_start = hclgevf_client_start, 2999 .client_stop = hclgevf_client_stop, 3000 .map_ring_to_vector = hclgevf_map_ring_to_vector, 3001 .unmap_ring_from_vector = hclgevf_unmap_ring_from_vector, 3002 .get_vector = hclgevf_get_vector, 3003 .put_vector = hclgevf_put_vector, 3004 .reset_queue = hclgevf_reset_tqp, 3005 .get_mac_addr = hclgevf_get_mac_addr, 3006 .set_mac_addr = hclgevf_set_mac_addr, 3007 .add_uc_addr = hclgevf_add_uc_addr, 3008 .rm_uc_addr = hclgevf_rm_uc_addr, 3009 .add_mc_addr = hclgevf_add_mc_addr, 3010 .rm_mc_addr = hclgevf_rm_mc_addr, 3011 .get_stats = hclgevf_get_stats, 3012 .update_stats = hclgevf_update_stats, 3013 .get_strings = hclgevf_get_strings, 3014 .get_sset_count = hclgevf_get_sset_count, 3015 .get_rss_key_size = hclgevf_get_rss_key_size, 3016 .get_rss_indir_size = hclgevf_get_rss_indir_size, 3017 .get_rss = hclgevf_get_rss, 3018 .set_rss = hclgevf_set_rss, 3019 .get_rss_tuple = hclgevf_get_rss_tuple, 3020 .set_rss_tuple = hclgevf_set_rss_tuple, 3021 .get_tc_size = hclgevf_get_tc_size, 3022 .get_fw_version = hclgevf_get_fw_version, 3023 .set_vlan_filter = hclgevf_set_vlan_filter, 3024 .enable_hw_strip_rxvtag = hclgevf_en_hw_strip_rxvtag, 3025 .reset_event = hclgevf_reset_event, 3026 .set_default_reset_request = hclgevf_set_def_reset_request, 3027 .get_channels = hclgevf_get_channels, 3028 .get_tqps_and_rss_info = hclgevf_get_tqps_and_rss_info, 3029 .get_regs_len = hclgevf_get_regs_len, 3030 .get_regs = hclgevf_get_regs, 3031 .get_status = hclgevf_get_status, 3032 .get_ksettings_an_result = hclgevf_get_ksettings_an_result, 3033 .get_media_type = hclgevf_get_media_type, 3034 .get_hw_reset_stat = hclgevf_get_hw_reset_stat, 3035 .ae_dev_resetting = hclgevf_ae_dev_resetting, 3036 .ae_dev_reset_cnt = hclgevf_ae_dev_reset_cnt, 3037 .set_gro_en = hclgevf_gro_en, 3038 .set_mtu = hclgevf_set_mtu, 3039 .get_global_queue_id = hclgevf_get_qid_global, 3040 .set_timer_task = hclgevf_set_timer_task, 3041 .get_link_mode = hclgevf_get_link_mode, 3042 }; 3043 3044 static struct hnae3_ae_algo ae_algovf = { 3045 .ops = &hclgevf_ops, 3046 .pdev_id_table = ae_algovf_pci_tbl, 3047 }; 3048 3049 static int hclgevf_init(void) 3050 { 3051 pr_info("%s is initializing\n", HCLGEVF_NAME); 3052 3053 hnae3_register_ae_algo(&ae_algovf); 3054 3055 return 0; 3056 } 3057 3058 static void hclgevf_exit(void) 3059 { 3060 hnae3_unregister_ae_algo(&ae_algovf); 3061 } 3062 module_init(hclgevf_init); 3063 module_exit(hclgevf_exit); 3064 3065 MODULE_LICENSE("GPL"); 3066 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 3067 MODULE_DESCRIPTION("HCLGEVF Driver"); 3068 MODULE_VERSION(HCLGEVF_MOD_VERSION); 3069