1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/etherdevice.h> 5 #include <linux/iopoll.h> 6 #include <net/rtnetlink.h> 7 #include "hclgevf_cmd.h" 8 #include "hclgevf_main.h" 9 #include "hclge_mbx.h" 10 #include "hnae3.h" 11 12 #define HCLGEVF_NAME "hclgevf" 13 14 #define HCLGEVF_RESET_MAX_FAIL_CNT 5 15 16 static int hclgevf_reset_hdev(struct hclgevf_dev *hdev); 17 static void hclgevf_task_schedule(struct hclgevf_dev *hdev, 18 unsigned long delay); 19 20 static struct hnae3_ae_algo ae_algovf; 21 22 static struct workqueue_struct *hclgevf_wq; 23 24 static const struct pci_device_id ae_algovf_pci_tbl[] = { 25 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_VF), 0}, 26 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF), 27 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 28 /* required last entry */ 29 {0, } 30 }; 31 32 static const u8 hclgevf_hash_key[] = { 33 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2, 34 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0, 35 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4, 36 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C, 37 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA 38 }; 39 40 MODULE_DEVICE_TABLE(pci, ae_algovf_pci_tbl); 41 42 static const u32 cmdq_reg_addr_list[] = {HCLGEVF_CMDQ_TX_ADDR_L_REG, 43 HCLGEVF_CMDQ_TX_ADDR_H_REG, 44 HCLGEVF_CMDQ_TX_DEPTH_REG, 45 HCLGEVF_CMDQ_TX_TAIL_REG, 46 HCLGEVF_CMDQ_TX_HEAD_REG, 47 HCLGEVF_CMDQ_RX_ADDR_L_REG, 48 HCLGEVF_CMDQ_RX_ADDR_H_REG, 49 HCLGEVF_CMDQ_RX_DEPTH_REG, 50 HCLGEVF_CMDQ_RX_TAIL_REG, 51 HCLGEVF_CMDQ_RX_HEAD_REG, 52 HCLGEVF_VECTOR0_CMDQ_SRC_REG, 53 HCLGEVF_VECTOR0_CMDQ_STATE_REG, 54 HCLGEVF_CMDQ_INTR_EN_REG, 55 HCLGEVF_CMDQ_INTR_GEN_REG}; 56 57 static const u32 common_reg_addr_list[] = {HCLGEVF_MISC_VECTOR_REG_BASE, 58 HCLGEVF_RST_ING, 59 HCLGEVF_GRO_EN_REG}; 60 61 static const u32 ring_reg_addr_list[] = {HCLGEVF_RING_RX_ADDR_L_REG, 62 HCLGEVF_RING_RX_ADDR_H_REG, 63 HCLGEVF_RING_RX_BD_NUM_REG, 64 HCLGEVF_RING_RX_BD_LENGTH_REG, 65 HCLGEVF_RING_RX_MERGE_EN_REG, 66 HCLGEVF_RING_RX_TAIL_REG, 67 HCLGEVF_RING_RX_HEAD_REG, 68 HCLGEVF_RING_RX_FBD_NUM_REG, 69 HCLGEVF_RING_RX_OFFSET_REG, 70 HCLGEVF_RING_RX_FBD_OFFSET_REG, 71 HCLGEVF_RING_RX_STASH_REG, 72 HCLGEVF_RING_RX_BD_ERR_REG, 73 HCLGEVF_RING_TX_ADDR_L_REG, 74 HCLGEVF_RING_TX_ADDR_H_REG, 75 HCLGEVF_RING_TX_BD_NUM_REG, 76 HCLGEVF_RING_TX_PRIORITY_REG, 77 HCLGEVF_RING_TX_TC_REG, 78 HCLGEVF_RING_TX_MERGE_EN_REG, 79 HCLGEVF_RING_TX_TAIL_REG, 80 HCLGEVF_RING_TX_HEAD_REG, 81 HCLGEVF_RING_TX_FBD_NUM_REG, 82 HCLGEVF_RING_TX_OFFSET_REG, 83 HCLGEVF_RING_TX_EBD_NUM_REG, 84 HCLGEVF_RING_TX_EBD_OFFSET_REG, 85 HCLGEVF_RING_TX_BD_ERR_REG, 86 HCLGEVF_RING_EN_REG}; 87 88 static const u32 tqp_intr_reg_addr_list[] = {HCLGEVF_TQP_INTR_CTRL_REG, 89 HCLGEVF_TQP_INTR_GL0_REG, 90 HCLGEVF_TQP_INTR_GL1_REG, 91 HCLGEVF_TQP_INTR_GL2_REG, 92 HCLGEVF_TQP_INTR_RL_REG}; 93 94 static struct hclgevf_dev *hclgevf_ae_get_hdev(struct hnae3_handle *handle) 95 { 96 if (!handle->client) 97 return container_of(handle, struct hclgevf_dev, nic); 98 else if (handle->client->type == HNAE3_CLIENT_ROCE) 99 return container_of(handle, struct hclgevf_dev, roce); 100 else 101 return container_of(handle, struct hclgevf_dev, nic); 102 } 103 104 static int hclgevf_tqps_update_stats(struct hnae3_handle *handle) 105 { 106 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 107 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 108 struct hclgevf_desc desc; 109 struct hclgevf_tqp *tqp; 110 int status; 111 int i; 112 113 for (i = 0; i < kinfo->num_tqps; i++) { 114 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 115 hclgevf_cmd_setup_basic_desc(&desc, 116 HCLGEVF_OPC_QUERY_RX_STATUS, 117 true); 118 119 desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 120 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 121 if (status) { 122 dev_err(&hdev->pdev->dev, 123 "Query tqp stat fail, status = %d,queue = %d\n", 124 status, i); 125 return status; 126 } 127 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd += 128 le32_to_cpu(desc.data[1]); 129 130 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_TX_STATUS, 131 true); 132 133 desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); 134 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 135 if (status) { 136 dev_err(&hdev->pdev->dev, 137 "Query tqp stat fail, status = %d,queue = %d\n", 138 status, i); 139 return status; 140 } 141 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd += 142 le32_to_cpu(desc.data[1]); 143 } 144 145 return 0; 146 } 147 148 static u64 *hclgevf_tqps_get_stats(struct hnae3_handle *handle, u64 *data) 149 { 150 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 151 struct hclgevf_tqp *tqp; 152 u64 *buff = data; 153 int i; 154 155 for (i = 0; i < kinfo->num_tqps; i++) { 156 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 157 *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd; 158 } 159 for (i = 0; i < kinfo->num_tqps; i++) { 160 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 161 *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd; 162 } 163 164 return buff; 165 } 166 167 static int hclgevf_tqps_get_sset_count(struct hnae3_handle *handle, int strset) 168 { 169 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 170 171 return kinfo->num_tqps * 2; 172 } 173 174 static u8 *hclgevf_tqps_get_strings(struct hnae3_handle *handle, u8 *data) 175 { 176 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 177 u8 *buff = data; 178 int i; 179 180 for (i = 0; i < kinfo->num_tqps; i++) { 181 struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 182 struct hclgevf_tqp, q); 183 snprintf(buff, ETH_GSTRING_LEN, "txq%u_pktnum_rcd", 184 tqp->index); 185 buff += ETH_GSTRING_LEN; 186 } 187 188 for (i = 0; i < kinfo->num_tqps; i++) { 189 struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i], 190 struct hclgevf_tqp, q); 191 snprintf(buff, ETH_GSTRING_LEN, "rxq%u_pktnum_rcd", 192 tqp->index); 193 buff += ETH_GSTRING_LEN; 194 } 195 196 return buff; 197 } 198 199 static void hclgevf_update_stats(struct hnae3_handle *handle, 200 struct net_device_stats *net_stats) 201 { 202 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 203 int status; 204 205 status = hclgevf_tqps_update_stats(handle); 206 if (status) 207 dev_err(&hdev->pdev->dev, 208 "VF update of TQPS stats fail, status = %d.\n", 209 status); 210 } 211 212 static int hclgevf_get_sset_count(struct hnae3_handle *handle, int strset) 213 { 214 if (strset == ETH_SS_TEST) 215 return -EOPNOTSUPP; 216 else if (strset == ETH_SS_STATS) 217 return hclgevf_tqps_get_sset_count(handle, strset); 218 219 return 0; 220 } 221 222 static void hclgevf_get_strings(struct hnae3_handle *handle, u32 strset, 223 u8 *data) 224 { 225 u8 *p = (char *)data; 226 227 if (strset == ETH_SS_STATS) 228 p = hclgevf_tqps_get_strings(handle, p); 229 } 230 231 static void hclgevf_get_stats(struct hnae3_handle *handle, u64 *data) 232 { 233 hclgevf_tqps_get_stats(handle, data); 234 } 235 236 static void hclgevf_build_send_msg(struct hclge_vf_to_pf_msg *msg, u8 code, 237 u8 subcode) 238 { 239 if (msg) { 240 memset(msg, 0, sizeof(struct hclge_vf_to_pf_msg)); 241 msg->code = code; 242 msg->subcode = subcode; 243 } 244 } 245 246 static int hclgevf_get_tc_info(struct hclgevf_dev *hdev) 247 { 248 struct hclge_vf_to_pf_msg send_msg; 249 u8 resp_msg; 250 int status; 251 252 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_TCINFO, 0); 253 status = hclgevf_send_mbx_msg(hdev, &send_msg, true, &resp_msg, 254 sizeof(resp_msg)); 255 if (status) { 256 dev_err(&hdev->pdev->dev, 257 "VF request to get TC info from PF failed %d", 258 status); 259 return status; 260 } 261 262 hdev->hw_tc_map = resp_msg; 263 264 return 0; 265 } 266 267 static int hclgevf_get_port_base_vlan_filter_state(struct hclgevf_dev *hdev) 268 { 269 struct hnae3_handle *nic = &hdev->nic; 270 struct hclge_vf_to_pf_msg send_msg; 271 u8 resp_msg; 272 int ret; 273 274 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 275 HCLGE_MBX_GET_PORT_BASE_VLAN_STATE); 276 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, &resp_msg, 277 sizeof(u8)); 278 if (ret) { 279 dev_err(&hdev->pdev->dev, 280 "VF request to get port based vlan state failed %d", 281 ret); 282 return ret; 283 } 284 285 nic->port_base_vlan_state = resp_msg; 286 287 return 0; 288 } 289 290 static int hclgevf_get_queue_info(struct hclgevf_dev *hdev) 291 { 292 #define HCLGEVF_TQPS_RSS_INFO_LEN 6 293 #define HCLGEVF_TQPS_ALLOC_OFFSET 0 294 #define HCLGEVF_TQPS_RSS_SIZE_OFFSET 2 295 #define HCLGEVF_TQPS_RX_BUFFER_LEN_OFFSET 4 296 297 u8 resp_msg[HCLGEVF_TQPS_RSS_INFO_LEN]; 298 struct hclge_vf_to_pf_msg send_msg; 299 int status; 300 301 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QINFO, 0); 302 status = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 303 HCLGEVF_TQPS_RSS_INFO_LEN); 304 if (status) { 305 dev_err(&hdev->pdev->dev, 306 "VF request to get tqp info from PF failed %d", 307 status); 308 return status; 309 } 310 311 memcpy(&hdev->num_tqps, &resp_msg[HCLGEVF_TQPS_ALLOC_OFFSET], 312 sizeof(u16)); 313 memcpy(&hdev->rss_size_max, &resp_msg[HCLGEVF_TQPS_RSS_SIZE_OFFSET], 314 sizeof(u16)); 315 memcpy(&hdev->rx_buf_len, &resp_msg[HCLGEVF_TQPS_RX_BUFFER_LEN_OFFSET], 316 sizeof(u16)); 317 318 return 0; 319 } 320 321 static int hclgevf_get_queue_depth(struct hclgevf_dev *hdev) 322 { 323 #define HCLGEVF_TQPS_DEPTH_INFO_LEN 4 324 #define HCLGEVF_TQPS_NUM_TX_DESC_OFFSET 0 325 #define HCLGEVF_TQPS_NUM_RX_DESC_OFFSET 2 326 327 u8 resp_msg[HCLGEVF_TQPS_DEPTH_INFO_LEN]; 328 struct hclge_vf_to_pf_msg send_msg; 329 int ret; 330 331 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QDEPTH, 0); 332 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 333 HCLGEVF_TQPS_DEPTH_INFO_LEN); 334 if (ret) { 335 dev_err(&hdev->pdev->dev, 336 "VF request to get tqp depth info from PF failed %d", 337 ret); 338 return ret; 339 } 340 341 memcpy(&hdev->num_tx_desc, &resp_msg[HCLGEVF_TQPS_NUM_TX_DESC_OFFSET], 342 sizeof(u16)); 343 memcpy(&hdev->num_rx_desc, &resp_msg[HCLGEVF_TQPS_NUM_RX_DESC_OFFSET], 344 sizeof(u16)); 345 346 return 0; 347 } 348 349 static u16 hclgevf_get_qid_global(struct hnae3_handle *handle, u16 queue_id) 350 { 351 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 352 struct hclge_vf_to_pf_msg send_msg; 353 u16 qid_in_pf = 0; 354 u8 resp_data[2]; 355 int ret; 356 357 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QID_IN_PF, 0); 358 memcpy(send_msg.data, &queue_id, sizeof(queue_id)); 359 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_data, 360 sizeof(resp_data)); 361 if (!ret) 362 qid_in_pf = *(u16 *)resp_data; 363 364 return qid_in_pf; 365 } 366 367 static int hclgevf_get_pf_media_type(struct hclgevf_dev *hdev) 368 { 369 struct hclge_vf_to_pf_msg send_msg; 370 u8 resp_msg[2]; 371 int ret; 372 373 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_MEDIA_TYPE, 0); 374 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 375 sizeof(resp_msg)); 376 if (ret) { 377 dev_err(&hdev->pdev->dev, 378 "VF request to get the pf port media type failed %d", 379 ret); 380 return ret; 381 } 382 383 hdev->hw.mac.media_type = resp_msg[0]; 384 hdev->hw.mac.module_type = resp_msg[1]; 385 386 return 0; 387 } 388 389 static int hclgevf_alloc_tqps(struct hclgevf_dev *hdev) 390 { 391 struct hclgevf_tqp *tqp; 392 int i; 393 394 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 395 sizeof(struct hclgevf_tqp), GFP_KERNEL); 396 if (!hdev->htqp) 397 return -ENOMEM; 398 399 tqp = hdev->htqp; 400 401 for (i = 0; i < hdev->num_tqps; i++) { 402 tqp->dev = &hdev->pdev->dev; 403 tqp->index = i; 404 405 tqp->q.ae_algo = &ae_algovf; 406 tqp->q.buf_size = hdev->rx_buf_len; 407 tqp->q.tx_desc_num = hdev->num_tx_desc; 408 tqp->q.rx_desc_num = hdev->num_rx_desc; 409 410 /* need an extended offset to configure queues >= 411 * HCLGEVF_TQP_MAX_SIZE_DEV_V2. 412 */ 413 if (i < HCLGEVF_TQP_MAX_SIZE_DEV_V2) 414 tqp->q.io_base = hdev->hw.io_base + 415 HCLGEVF_TQP_REG_OFFSET + 416 i * HCLGEVF_TQP_REG_SIZE; 417 else 418 tqp->q.io_base = hdev->hw.io_base + 419 HCLGEVF_TQP_REG_OFFSET + 420 HCLGEVF_TQP_EXT_REG_OFFSET + 421 (i - HCLGEVF_TQP_MAX_SIZE_DEV_V2) * 422 HCLGEVF_TQP_REG_SIZE; 423 424 tqp++; 425 } 426 427 return 0; 428 } 429 430 static int hclgevf_knic_setup(struct hclgevf_dev *hdev) 431 { 432 struct hnae3_handle *nic = &hdev->nic; 433 struct hnae3_knic_private_info *kinfo; 434 u16 new_tqps = hdev->num_tqps; 435 unsigned int i; 436 u8 num_tc = 0; 437 438 kinfo = &nic->kinfo; 439 kinfo->num_tx_desc = hdev->num_tx_desc; 440 kinfo->num_rx_desc = hdev->num_rx_desc; 441 kinfo->rx_buf_len = hdev->rx_buf_len; 442 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) 443 if (hdev->hw_tc_map & BIT(i)) 444 num_tc++; 445 446 num_tc = num_tc ? num_tc : 1; 447 kinfo->tc_info.num_tc = num_tc; 448 kinfo->rss_size = min_t(u16, hdev->rss_size_max, new_tqps / num_tc); 449 new_tqps = kinfo->rss_size * num_tc; 450 kinfo->num_tqps = min(new_tqps, hdev->num_tqps); 451 452 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps, 453 sizeof(struct hnae3_queue *), GFP_KERNEL); 454 if (!kinfo->tqp) 455 return -ENOMEM; 456 457 for (i = 0; i < kinfo->num_tqps; i++) { 458 hdev->htqp[i].q.handle = &hdev->nic; 459 hdev->htqp[i].q.tqp_index = i; 460 kinfo->tqp[i] = &hdev->htqp[i].q; 461 } 462 463 /* after init the max rss_size and tqps, adjust the default tqp numbers 464 * and rss size with the actual vector numbers 465 */ 466 kinfo->num_tqps = min_t(u16, hdev->num_nic_msix - 1, kinfo->num_tqps); 467 kinfo->rss_size = min_t(u16, kinfo->num_tqps / num_tc, 468 kinfo->rss_size); 469 470 return 0; 471 } 472 473 static void hclgevf_request_link_info(struct hclgevf_dev *hdev) 474 { 475 struct hclge_vf_to_pf_msg send_msg; 476 int status; 477 478 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_LINK_STATUS, 0); 479 status = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 480 if (status) 481 dev_err(&hdev->pdev->dev, 482 "VF failed to fetch link status(%d) from PF", status); 483 } 484 485 void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state) 486 { 487 struct hnae3_handle *rhandle = &hdev->roce; 488 struct hnae3_handle *handle = &hdev->nic; 489 struct hnae3_client *rclient; 490 struct hnae3_client *client; 491 492 if (test_and_set_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state)) 493 return; 494 495 client = handle->client; 496 rclient = hdev->roce_client; 497 498 link_state = 499 test_bit(HCLGEVF_STATE_DOWN, &hdev->state) ? 0 : link_state; 500 501 if (link_state != hdev->hw.mac.link) { 502 client->ops->link_status_change(handle, !!link_state); 503 if (rclient && rclient->ops->link_status_change) 504 rclient->ops->link_status_change(rhandle, !!link_state); 505 hdev->hw.mac.link = link_state; 506 } 507 508 clear_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state); 509 } 510 511 static void hclgevf_update_link_mode(struct hclgevf_dev *hdev) 512 { 513 #define HCLGEVF_ADVERTISING 0 514 #define HCLGEVF_SUPPORTED 1 515 516 struct hclge_vf_to_pf_msg send_msg; 517 518 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_LINK_MODE, 0); 519 send_msg.data[0] = HCLGEVF_ADVERTISING; 520 hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 521 send_msg.data[0] = HCLGEVF_SUPPORTED; 522 hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 523 } 524 525 static int hclgevf_set_handle_info(struct hclgevf_dev *hdev) 526 { 527 struct hnae3_handle *nic = &hdev->nic; 528 int ret; 529 530 nic->ae_algo = &ae_algovf; 531 nic->pdev = hdev->pdev; 532 nic->numa_node_mask = hdev->numa_node_mask; 533 nic->flags |= HNAE3_SUPPORT_VF; 534 535 ret = hclgevf_knic_setup(hdev); 536 if (ret) 537 dev_err(&hdev->pdev->dev, "VF knic setup failed %d\n", 538 ret); 539 return ret; 540 } 541 542 static void hclgevf_free_vector(struct hclgevf_dev *hdev, int vector_id) 543 { 544 if (hdev->vector_status[vector_id] == HCLGEVF_INVALID_VPORT) { 545 dev_warn(&hdev->pdev->dev, 546 "vector(vector_id %d) has been freed.\n", vector_id); 547 return; 548 } 549 550 hdev->vector_status[vector_id] = HCLGEVF_INVALID_VPORT; 551 hdev->num_msi_left += 1; 552 hdev->num_msi_used -= 1; 553 } 554 555 static int hclgevf_get_vector(struct hnae3_handle *handle, u16 vector_num, 556 struct hnae3_vector_info *vector_info) 557 { 558 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 559 struct hnae3_vector_info *vector = vector_info; 560 int alloc = 0; 561 int i, j; 562 563 vector_num = min_t(u16, hdev->num_nic_msix - 1, vector_num); 564 vector_num = min(hdev->num_msi_left, vector_num); 565 566 for (j = 0; j < vector_num; j++) { 567 for (i = HCLGEVF_MISC_VECTOR_NUM + 1; i < hdev->num_msi; i++) { 568 if (hdev->vector_status[i] == HCLGEVF_INVALID_VPORT) { 569 vector->vector = pci_irq_vector(hdev->pdev, i); 570 vector->io_addr = hdev->hw.io_base + 571 HCLGEVF_VECTOR_REG_BASE + 572 (i - 1) * HCLGEVF_VECTOR_REG_OFFSET; 573 hdev->vector_status[i] = 0; 574 hdev->vector_irq[i] = vector->vector; 575 576 vector++; 577 alloc++; 578 579 break; 580 } 581 } 582 } 583 hdev->num_msi_left -= alloc; 584 hdev->num_msi_used += alloc; 585 586 return alloc; 587 } 588 589 static int hclgevf_get_vector_index(struct hclgevf_dev *hdev, int vector) 590 { 591 int i; 592 593 for (i = 0; i < hdev->num_msi; i++) 594 if (vector == hdev->vector_irq[i]) 595 return i; 596 597 return -EINVAL; 598 } 599 600 static int hclgevf_set_rss_algo_key(struct hclgevf_dev *hdev, 601 const u8 hfunc, const u8 *key) 602 { 603 struct hclgevf_rss_config_cmd *req; 604 unsigned int key_offset = 0; 605 struct hclgevf_desc desc; 606 int key_counts; 607 int key_size; 608 int ret; 609 610 key_counts = HCLGEVF_RSS_KEY_SIZE; 611 req = (struct hclgevf_rss_config_cmd *)desc.data; 612 613 while (key_counts) { 614 hclgevf_cmd_setup_basic_desc(&desc, 615 HCLGEVF_OPC_RSS_GENERIC_CONFIG, 616 false); 617 618 req->hash_config |= (hfunc & HCLGEVF_RSS_HASH_ALGO_MASK); 619 req->hash_config |= 620 (key_offset << HCLGEVF_RSS_HASH_KEY_OFFSET_B); 621 622 key_size = min(HCLGEVF_RSS_HASH_KEY_NUM, key_counts); 623 memcpy(req->hash_key, 624 key + key_offset * HCLGEVF_RSS_HASH_KEY_NUM, key_size); 625 626 key_counts -= key_size; 627 key_offset++; 628 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 629 if (ret) { 630 dev_err(&hdev->pdev->dev, 631 "Configure RSS config fail, status = %d\n", 632 ret); 633 return ret; 634 } 635 } 636 637 return 0; 638 } 639 640 static u32 hclgevf_get_rss_key_size(struct hnae3_handle *handle) 641 { 642 return HCLGEVF_RSS_KEY_SIZE; 643 } 644 645 static int hclgevf_set_rss_indir_table(struct hclgevf_dev *hdev) 646 { 647 const u8 *indir = hdev->rss_cfg.rss_indirection_tbl; 648 struct hclgevf_rss_indirection_table_cmd *req; 649 struct hclgevf_desc desc; 650 int rss_cfg_tbl_num; 651 int status; 652 int i, j; 653 654 req = (struct hclgevf_rss_indirection_table_cmd *)desc.data; 655 rss_cfg_tbl_num = hdev->ae_dev->dev_specs.rss_ind_tbl_size / 656 HCLGEVF_RSS_CFG_TBL_SIZE; 657 658 for (i = 0; i < rss_cfg_tbl_num; i++) { 659 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INDIR_TABLE, 660 false); 661 req->start_table_index = 662 cpu_to_le16(i * HCLGEVF_RSS_CFG_TBL_SIZE); 663 req->rss_set_bitmap = cpu_to_le16(HCLGEVF_RSS_SET_BITMAP_MSK); 664 for (j = 0; j < HCLGEVF_RSS_CFG_TBL_SIZE; j++) 665 req->rss_result[j] = 666 indir[i * HCLGEVF_RSS_CFG_TBL_SIZE + j]; 667 668 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 669 if (status) { 670 dev_err(&hdev->pdev->dev, 671 "VF failed(=%d) to set RSS indirection table\n", 672 status); 673 return status; 674 } 675 } 676 677 return 0; 678 } 679 680 static int hclgevf_set_rss_tc_mode(struct hclgevf_dev *hdev, u16 rss_size) 681 { 682 struct hclgevf_rss_tc_mode_cmd *req; 683 u16 tc_offset[HCLGEVF_MAX_TC_NUM]; 684 u16 tc_valid[HCLGEVF_MAX_TC_NUM]; 685 u16 tc_size[HCLGEVF_MAX_TC_NUM]; 686 struct hclgevf_desc desc; 687 u16 roundup_size; 688 unsigned int i; 689 int status; 690 691 req = (struct hclgevf_rss_tc_mode_cmd *)desc.data; 692 693 roundup_size = roundup_pow_of_two(rss_size); 694 roundup_size = ilog2(roundup_size); 695 696 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 697 tc_valid[i] = !!(hdev->hw_tc_map & BIT(i)); 698 tc_size[i] = roundup_size; 699 tc_offset[i] = rss_size * i; 700 } 701 702 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_TC_MODE, false); 703 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) { 704 u16 mode = 0; 705 706 hnae3_set_bit(mode, HCLGEVF_RSS_TC_VALID_B, 707 (tc_valid[i] & 0x1)); 708 hnae3_set_field(mode, HCLGEVF_RSS_TC_SIZE_M, 709 HCLGEVF_RSS_TC_SIZE_S, tc_size[i]); 710 hnae3_set_field(mode, HCLGEVF_RSS_TC_OFFSET_M, 711 HCLGEVF_RSS_TC_OFFSET_S, tc_offset[i]); 712 713 req->rss_tc_mode[i] = cpu_to_le16(mode); 714 } 715 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 716 if (status) 717 dev_err(&hdev->pdev->dev, 718 "VF failed(=%d) to set rss tc mode\n", status); 719 720 return status; 721 } 722 723 /* for revision 0x20, vf shared the same rss config with pf */ 724 static int hclgevf_get_rss_hash_key(struct hclgevf_dev *hdev) 725 { 726 #define HCLGEVF_RSS_MBX_RESP_LEN 8 727 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 728 u8 resp_msg[HCLGEVF_RSS_MBX_RESP_LEN]; 729 struct hclge_vf_to_pf_msg send_msg; 730 u16 msg_num, hash_key_index; 731 u8 index; 732 int ret; 733 734 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_RSS_KEY, 0); 735 msg_num = (HCLGEVF_RSS_KEY_SIZE + HCLGEVF_RSS_MBX_RESP_LEN - 1) / 736 HCLGEVF_RSS_MBX_RESP_LEN; 737 for (index = 0; index < msg_num; index++) { 738 send_msg.data[0] = index; 739 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg, 740 HCLGEVF_RSS_MBX_RESP_LEN); 741 if (ret) { 742 dev_err(&hdev->pdev->dev, 743 "VF get rss hash key from PF failed, ret=%d", 744 ret); 745 return ret; 746 } 747 748 hash_key_index = HCLGEVF_RSS_MBX_RESP_LEN * index; 749 if (index == msg_num - 1) 750 memcpy(&rss_cfg->rss_hash_key[hash_key_index], 751 &resp_msg[0], 752 HCLGEVF_RSS_KEY_SIZE - hash_key_index); 753 else 754 memcpy(&rss_cfg->rss_hash_key[hash_key_index], 755 &resp_msg[0], HCLGEVF_RSS_MBX_RESP_LEN); 756 } 757 758 return 0; 759 } 760 761 static int hclgevf_get_rss(struct hnae3_handle *handle, u32 *indir, u8 *key, 762 u8 *hfunc) 763 { 764 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 765 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 766 int i, ret; 767 768 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 769 /* Get hash algorithm */ 770 if (hfunc) { 771 switch (rss_cfg->hash_algo) { 772 case HCLGEVF_RSS_HASH_ALGO_TOEPLITZ: 773 *hfunc = ETH_RSS_HASH_TOP; 774 break; 775 case HCLGEVF_RSS_HASH_ALGO_SIMPLE: 776 *hfunc = ETH_RSS_HASH_XOR; 777 break; 778 default: 779 *hfunc = ETH_RSS_HASH_UNKNOWN; 780 break; 781 } 782 } 783 784 /* Get the RSS Key required by the user */ 785 if (key) 786 memcpy(key, rss_cfg->rss_hash_key, 787 HCLGEVF_RSS_KEY_SIZE); 788 } else { 789 if (hfunc) 790 *hfunc = ETH_RSS_HASH_TOP; 791 if (key) { 792 ret = hclgevf_get_rss_hash_key(hdev); 793 if (ret) 794 return ret; 795 memcpy(key, rss_cfg->rss_hash_key, 796 HCLGEVF_RSS_KEY_SIZE); 797 } 798 } 799 800 if (indir) 801 for (i = 0; i < hdev->ae_dev->dev_specs.rss_ind_tbl_size; i++) 802 indir[i] = rss_cfg->rss_indirection_tbl[i]; 803 804 return 0; 805 } 806 807 static int hclgevf_set_rss(struct hnae3_handle *handle, const u32 *indir, 808 const u8 *key, const u8 hfunc) 809 { 810 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 811 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 812 int ret, i; 813 814 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 815 /* Set the RSS Hash Key if specififed by the user */ 816 if (key) { 817 switch (hfunc) { 818 case ETH_RSS_HASH_TOP: 819 rss_cfg->hash_algo = 820 HCLGEVF_RSS_HASH_ALGO_TOEPLITZ; 821 break; 822 case ETH_RSS_HASH_XOR: 823 rss_cfg->hash_algo = 824 HCLGEVF_RSS_HASH_ALGO_SIMPLE; 825 break; 826 case ETH_RSS_HASH_NO_CHANGE: 827 break; 828 default: 829 return -EINVAL; 830 } 831 832 ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 833 key); 834 if (ret) 835 return ret; 836 837 /* Update the shadow RSS key with user specified qids */ 838 memcpy(rss_cfg->rss_hash_key, key, 839 HCLGEVF_RSS_KEY_SIZE); 840 } 841 } 842 843 /* update the shadow RSS table with user specified qids */ 844 for (i = 0; i < hdev->ae_dev->dev_specs.rss_ind_tbl_size; i++) 845 rss_cfg->rss_indirection_tbl[i] = indir[i]; 846 847 /* update the hardware */ 848 return hclgevf_set_rss_indir_table(hdev); 849 } 850 851 static u8 hclgevf_get_rss_hash_bits(struct ethtool_rxnfc *nfc) 852 { 853 u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGEVF_S_PORT_BIT : 0; 854 855 if (nfc->data & RXH_L4_B_2_3) 856 hash_sets |= HCLGEVF_D_PORT_BIT; 857 else 858 hash_sets &= ~HCLGEVF_D_PORT_BIT; 859 860 if (nfc->data & RXH_IP_SRC) 861 hash_sets |= HCLGEVF_S_IP_BIT; 862 else 863 hash_sets &= ~HCLGEVF_S_IP_BIT; 864 865 if (nfc->data & RXH_IP_DST) 866 hash_sets |= HCLGEVF_D_IP_BIT; 867 else 868 hash_sets &= ~HCLGEVF_D_IP_BIT; 869 870 if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW) 871 hash_sets |= HCLGEVF_V_TAG_BIT; 872 873 return hash_sets; 874 } 875 876 static int hclgevf_set_rss_tuple(struct hnae3_handle *handle, 877 struct ethtool_rxnfc *nfc) 878 { 879 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 880 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 881 struct hclgevf_rss_input_tuple_cmd *req; 882 struct hclgevf_desc desc; 883 u8 tuple_sets; 884 int ret; 885 886 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 887 return -EOPNOTSUPP; 888 889 if (nfc->data & 890 ~(RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3)) 891 return -EINVAL; 892 893 req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 894 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 895 896 req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 897 req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 898 req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 899 req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 900 req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 901 req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 902 req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 903 req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 904 905 tuple_sets = hclgevf_get_rss_hash_bits(nfc); 906 switch (nfc->flow_type) { 907 case TCP_V4_FLOW: 908 req->ipv4_tcp_en = tuple_sets; 909 break; 910 case TCP_V6_FLOW: 911 req->ipv6_tcp_en = tuple_sets; 912 break; 913 case UDP_V4_FLOW: 914 req->ipv4_udp_en = tuple_sets; 915 break; 916 case UDP_V6_FLOW: 917 req->ipv6_udp_en = tuple_sets; 918 break; 919 case SCTP_V4_FLOW: 920 req->ipv4_sctp_en = tuple_sets; 921 break; 922 case SCTP_V6_FLOW: 923 if (hdev->ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2 && 924 (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3))) 925 return -EINVAL; 926 927 req->ipv6_sctp_en = tuple_sets; 928 break; 929 case IPV4_FLOW: 930 req->ipv4_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 931 break; 932 case IPV6_FLOW: 933 req->ipv6_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 934 break; 935 default: 936 return -EINVAL; 937 } 938 939 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 940 if (ret) { 941 dev_err(&hdev->pdev->dev, 942 "Set rss tuple fail, status = %d\n", ret); 943 return ret; 944 } 945 946 rss_cfg->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en; 947 rss_cfg->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en; 948 rss_cfg->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en; 949 rss_cfg->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en; 950 rss_cfg->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en; 951 rss_cfg->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en; 952 rss_cfg->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en; 953 rss_cfg->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en; 954 return 0; 955 } 956 957 static int hclgevf_get_rss_tuple(struct hnae3_handle *handle, 958 struct ethtool_rxnfc *nfc) 959 { 960 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 961 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 962 u8 tuple_sets; 963 964 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 965 return -EOPNOTSUPP; 966 967 nfc->data = 0; 968 969 switch (nfc->flow_type) { 970 case TCP_V4_FLOW: 971 tuple_sets = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 972 break; 973 case UDP_V4_FLOW: 974 tuple_sets = rss_cfg->rss_tuple_sets.ipv4_udp_en; 975 break; 976 case TCP_V6_FLOW: 977 tuple_sets = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 978 break; 979 case UDP_V6_FLOW: 980 tuple_sets = rss_cfg->rss_tuple_sets.ipv6_udp_en; 981 break; 982 case SCTP_V4_FLOW: 983 tuple_sets = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 984 break; 985 case SCTP_V6_FLOW: 986 tuple_sets = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 987 break; 988 case IPV4_FLOW: 989 case IPV6_FLOW: 990 tuple_sets = HCLGEVF_S_IP_BIT | HCLGEVF_D_IP_BIT; 991 break; 992 default: 993 return -EINVAL; 994 } 995 996 if (!tuple_sets) 997 return 0; 998 999 if (tuple_sets & HCLGEVF_D_PORT_BIT) 1000 nfc->data |= RXH_L4_B_2_3; 1001 if (tuple_sets & HCLGEVF_S_PORT_BIT) 1002 nfc->data |= RXH_L4_B_0_1; 1003 if (tuple_sets & HCLGEVF_D_IP_BIT) 1004 nfc->data |= RXH_IP_DST; 1005 if (tuple_sets & HCLGEVF_S_IP_BIT) 1006 nfc->data |= RXH_IP_SRC; 1007 1008 return 0; 1009 } 1010 1011 static int hclgevf_set_rss_input_tuple(struct hclgevf_dev *hdev, 1012 struct hclgevf_rss_cfg *rss_cfg) 1013 { 1014 struct hclgevf_rss_input_tuple_cmd *req; 1015 struct hclgevf_desc desc; 1016 int ret; 1017 1018 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false); 1019 1020 req = (struct hclgevf_rss_input_tuple_cmd *)desc.data; 1021 1022 req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en; 1023 req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en; 1024 req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en; 1025 req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en; 1026 req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en; 1027 req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en; 1028 req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en; 1029 req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en; 1030 1031 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1032 if (ret) 1033 dev_err(&hdev->pdev->dev, 1034 "Configure rss input fail, status = %d\n", ret); 1035 return ret; 1036 } 1037 1038 static int hclgevf_get_tc_size(struct hnae3_handle *handle) 1039 { 1040 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1041 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 1042 1043 return rss_cfg->rss_size; 1044 } 1045 1046 static int hclgevf_bind_ring_to_vector(struct hnae3_handle *handle, bool en, 1047 int vector_id, 1048 struct hnae3_ring_chain_node *ring_chain) 1049 { 1050 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1051 struct hclge_vf_to_pf_msg send_msg; 1052 struct hnae3_ring_chain_node *node; 1053 int status; 1054 int i = 0; 1055 1056 memset(&send_msg, 0, sizeof(send_msg)); 1057 send_msg.code = en ? HCLGE_MBX_MAP_RING_TO_VECTOR : 1058 HCLGE_MBX_UNMAP_RING_TO_VECTOR; 1059 send_msg.vector_id = vector_id; 1060 1061 for (node = ring_chain; node; node = node->next) { 1062 send_msg.param[i].ring_type = 1063 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B); 1064 1065 send_msg.param[i].tqp_index = node->tqp_index; 1066 send_msg.param[i].int_gl_index = 1067 hnae3_get_field(node->int_gl_idx, 1068 HNAE3_RING_GL_IDX_M, 1069 HNAE3_RING_GL_IDX_S); 1070 1071 i++; 1072 if (i == HCLGE_MBX_MAX_RING_CHAIN_PARAM_NUM || !node->next) { 1073 send_msg.ring_num = i; 1074 1075 status = hclgevf_send_mbx_msg(hdev, &send_msg, false, 1076 NULL, 0); 1077 if (status) { 1078 dev_err(&hdev->pdev->dev, 1079 "Map TQP fail, status is %d.\n", 1080 status); 1081 return status; 1082 } 1083 i = 0; 1084 } 1085 } 1086 1087 return 0; 1088 } 1089 1090 static int hclgevf_map_ring_to_vector(struct hnae3_handle *handle, int vector, 1091 struct hnae3_ring_chain_node *ring_chain) 1092 { 1093 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1094 int vector_id; 1095 1096 vector_id = hclgevf_get_vector_index(hdev, vector); 1097 if (vector_id < 0) { 1098 dev_err(&handle->pdev->dev, 1099 "Get vector index fail. ret =%d\n", vector_id); 1100 return vector_id; 1101 } 1102 1103 return hclgevf_bind_ring_to_vector(handle, true, vector_id, ring_chain); 1104 } 1105 1106 static int hclgevf_unmap_ring_from_vector( 1107 struct hnae3_handle *handle, 1108 int vector, 1109 struct hnae3_ring_chain_node *ring_chain) 1110 { 1111 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1112 int ret, vector_id; 1113 1114 if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) 1115 return 0; 1116 1117 vector_id = hclgevf_get_vector_index(hdev, vector); 1118 if (vector_id < 0) { 1119 dev_err(&handle->pdev->dev, 1120 "Get vector index fail. ret =%d\n", vector_id); 1121 return vector_id; 1122 } 1123 1124 ret = hclgevf_bind_ring_to_vector(handle, false, vector_id, ring_chain); 1125 if (ret) 1126 dev_err(&handle->pdev->dev, 1127 "Unmap ring from vector fail. vector=%d, ret =%d\n", 1128 vector_id, 1129 ret); 1130 1131 return ret; 1132 } 1133 1134 static int hclgevf_put_vector(struct hnae3_handle *handle, int vector) 1135 { 1136 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1137 int vector_id; 1138 1139 vector_id = hclgevf_get_vector_index(hdev, vector); 1140 if (vector_id < 0) { 1141 dev_err(&handle->pdev->dev, 1142 "hclgevf_put_vector get vector index fail. ret =%d\n", 1143 vector_id); 1144 return vector_id; 1145 } 1146 1147 hclgevf_free_vector(hdev, vector_id); 1148 1149 return 0; 1150 } 1151 1152 static int hclgevf_cmd_set_promisc_mode(struct hclgevf_dev *hdev, 1153 bool en_uc_pmc, bool en_mc_pmc, 1154 bool en_bc_pmc) 1155 { 1156 struct hnae3_handle *handle = &hdev->nic; 1157 struct hclge_vf_to_pf_msg send_msg; 1158 int ret; 1159 1160 memset(&send_msg, 0, sizeof(send_msg)); 1161 send_msg.code = HCLGE_MBX_SET_PROMISC_MODE; 1162 send_msg.en_bc = en_bc_pmc ? 1 : 0; 1163 send_msg.en_uc = en_uc_pmc ? 1 : 0; 1164 send_msg.en_mc = en_mc_pmc ? 1 : 0; 1165 send_msg.en_limit_promisc = test_bit(HNAE3_PFLAG_LIMIT_PROMISC, 1166 &handle->priv_flags) ? 1 : 0; 1167 1168 ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 1169 if (ret) 1170 dev_err(&hdev->pdev->dev, 1171 "Set promisc mode fail, status is %d.\n", ret); 1172 1173 return ret; 1174 } 1175 1176 static int hclgevf_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc, 1177 bool en_mc_pmc) 1178 { 1179 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1180 bool en_bc_pmc; 1181 1182 en_bc_pmc = hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2; 1183 1184 return hclgevf_cmd_set_promisc_mode(hdev, en_uc_pmc, en_mc_pmc, 1185 en_bc_pmc); 1186 } 1187 1188 static void hclgevf_request_update_promisc_mode(struct hnae3_handle *handle) 1189 { 1190 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1191 1192 set_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state); 1193 hclgevf_task_schedule(hdev, 0); 1194 } 1195 1196 static void hclgevf_sync_promisc_mode(struct hclgevf_dev *hdev) 1197 { 1198 struct hnae3_handle *handle = &hdev->nic; 1199 bool en_uc_pmc = handle->netdev_flags & HNAE3_UPE; 1200 bool en_mc_pmc = handle->netdev_flags & HNAE3_MPE; 1201 int ret; 1202 1203 if (test_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state)) { 1204 ret = hclgevf_set_promisc_mode(handle, en_uc_pmc, en_mc_pmc); 1205 if (!ret) 1206 clear_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state); 1207 } 1208 } 1209 1210 static int hclgevf_tqp_enable(struct hclgevf_dev *hdev, unsigned int tqp_id, 1211 int stream_id, bool enable) 1212 { 1213 struct hclgevf_cfg_com_tqp_queue_cmd *req; 1214 struct hclgevf_desc desc; 1215 int status; 1216 1217 req = (struct hclgevf_cfg_com_tqp_queue_cmd *)desc.data; 1218 1219 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_CFG_COM_TQP_QUEUE, 1220 false); 1221 req->tqp_id = cpu_to_le16(tqp_id & HCLGEVF_RING_ID_MASK); 1222 req->stream_id = cpu_to_le16(stream_id); 1223 if (enable) 1224 req->enable |= 1U << HCLGEVF_TQP_ENABLE_B; 1225 1226 status = hclgevf_cmd_send(&hdev->hw, &desc, 1); 1227 if (status) 1228 dev_err(&hdev->pdev->dev, 1229 "TQP enable fail, status =%d.\n", status); 1230 1231 return status; 1232 } 1233 1234 static void hclgevf_reset_tqp_stats(struct hnae3_handle *handle) 1235 { 1236 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 1237 struct hclgevf_tqp *tqp; 1238 int i; 1239 1240 for (i = 0; i < kinfo->num_tqps; i++) { 1241 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q); 1242 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats)); 1243 } 1244 } 1245 1246 static int hclgevf_get_host_mac_addr(struct hclgevf_dev *hdev, u8 *p) 1247 { 1248 struct hclge_vf_to_pf_msg send_msg; 1249 u8 host_mac[ETH_ALEN]; 1250 int status; 1251 1252 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_MAC_ADDR, 0); 1253 status = hclgevf_send_mbx_msg(hdev, &send_msg, true, host_mac, 1254 ETH_ALEN); 1255 if (status) { 1256 dev_err(&hdev->pdev->dev, 1257 "fail to get VF MAC from host %d", status); 1258 return status; 1259 } 1260 1261 ether_addr_copy(p, host_mac); 1262 1263 return 0; 1264 } 1265 1266 static void hclgevf_get_mac_addr(struct hnae3_handle *handle, u8 *p) 1267 { 1268 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1269 u8 host_mac_addr[ETH_ALEN]; 1270 1271 if (hclgevf_get_host_mac_addr(hdev, host_mac_addr)) 1272 return; 1273 1274 hdev->has_pf_mac = !is_zero_ether_addr(host_mac_addr); 1275 if (hdev->has_pf_mac) 1276 ether_addr_copy(p, host_mac_addr); 1277 else 1278 ether_addr_copy(p, hdev->hw.mac.mac_addr); 1279 } 1280 1281 static int hclgevf_set_mac_addr(struct hnae3_handle *handle, void *p, 1282 bool is_first) 1283 { 1284 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1285 u8 *old_mac_addr = (u8 *)hdev->hw.mac.mac_addr; 1286 struct hclge_vf_to_pf_msg send_msg; 1287 u8 *new_mac_addr = (u8 *)p; 1288 int status; 1289 1290 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_UNICAST, 0); 1291 send_msg.subcode = HCLGE_MBX_MAC_VLAN_UC_MODIFY; 1292 ether_addr_copy(send_msg.data, new_mac_addr); 1293 if (is_first && !hdev->has_pf_mac) 1294 eth_zero_addr(&send_msg.data[ETH_ALEN]); 1295 else 1296 ether_addr_copy(&send_msg.data[ETH_ALEN], old_mac_addr); 1297 status = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1298 if (!status) 1299 ether_addr_copy(hdev->hw.mac.mac_addr, new_mac_addr); 1300 1301 return status; 1302 } 1303 1304 static struct hclgevf_mac_addr_node * 1305 hclgevf_find_mac_node(struct list_head *list, const u8 *mac_addr) 1306 { 1307 struct hclgevf_mac_addr_node *mac_node, *tmp; 1308 1309 list_for_each_entry_safe(mac_node, tmp, list, node) 1310 if (ether_addr_equal(mac_addr, mac_node->mac_addr)) 1311 return mac_node; 1312 1313 return NULL; 1314 } 1315 1316 static void hclgevf_update_mac_node(struct hclgevf_mac_addr_node *mac_node, 1317 enum HCLGEVF_MAC_NODE_STATE state) 1318 { 1319 switch (state) { 1320 /* from set_rx_mode or tmp_add_list */ 1321 case HCLGEVF_MAC_TO_ADD: 1322 if (mac_node->state == HCLGEVF_MAC_TO_DEL) 1323 mac_node->state = HCLGEVF_MAC_ACTIVE; 1324 break; 1325 /* only from set_rx_mode */ 1326 case HCLGEVF_MAC_TO_DEL: 1327 if (mac_node->state == HCLGEVF_MAC_TO_ADD) { 1328 list_del(&mac_node->node); 1329 kfree(mac_node); 1330 } else { 1331 mac_node->state = HCLGEVF_MAC_TO_DEL; 1332 } 1333 break; 1334 /* only from tmp_add_list, the mac_node->state won't be 1335 * HCLGEVF_MAC_ACTIVE 1336 */ 1337 case HCLGEVF_MAC_ACTIVE: 1338 if (mac_node->state == HCLGEVF_MAC_TO_ADD) 1339 mac_node->state = HCLGEVF_MAC_ACTIVE; 1340 break; 1341 } 1342 } 1343 1344 static int hclgevf_update_mac_list(struct hnae3_handle *handle, 1345 enum HCLGEVF_MAC_NODE_STATE state, 1346 enum HCLGEVF_MAC_ADDR_TYPE mac_type, 1347 const unsigned char *addr) 1348 { 1349 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1350 struct hclgevf_mac_addr_node *mac_node; 1351 struct list_head *list; 1352 1353 list = (mac_type == HCLGEVF_MAC_ADDR_UC) ? 1354 &hdev->mac_table.uc_mac_list : &hdev->mac_table.mc_mac_list; 1355 1356 spin_lock_bh(&hdev->mac_table.mac_list_lock); 1357 1358 /* if the mac addr is already in the mac list, no need to add a new 1359 * one into it, just check the mac addr state, convert it to a new 1360 * new state, or just remove it, or do nothing. 1361 */ 1362 mac_node = hclgevf_find_mac_node(list, addr); 1363 if (mac_node) { 1364 hclgevf_update_mac_node(mac_node, state); 1365 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1366 return 0; 1367 } 1368 /* if this address is never added, unnecessary to delete */ 1369 if (state == HCLGEVF_MAC_TO_DEL) { 1370 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1371 return -ENOENT; 1372 } 1373 1374 mac_node = kzalloc(sizeof(*mac_node), GFP_ATOMIC); 1375 if (!mac_node) { 1376 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1377 return -ENOMEM; 1378 } 1379 1380 mac_node->state = state; 1381 ether_addr_copy(mac_node->mac_addr, addr); 1382 list_add_tail(&mac_node->node, list); 1383 1384 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1385 return 0; 1386 } 1387 1388 static int hclgevf_add_uc_addr(struct hnae3_handle *handle, 1389 const unsigned char *addr) 1390 { 1391 return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_ADD, 1392 HCLGEVF_MAC_ADDR_UC, addr); 1393 } 1394 1395 static int hclgevf_rm_uc_addr(struct hnae3_handle *handle, 1396 const unsigned char *addr) 1397 { 1398 return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_DEL, 1399 HCLGEVF_MAC_ADDR_UC, addr); 1400 } 1401 1402 static int hclgevf_add_mc_addr(struct hnae3_handle *handle, 1403 const unsigned char *addr) 1404 { 1405 return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_ADD, 1406 HCLGEVF_MAC_ADDR_MC, addr); 1407 } 1408 1409 static int hclgevf_rm_mc_addr(struct hnae3_handle *handle, 1410 const unsigned char *addr) 1411 { 1412 return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_DEL, 1413 HCLGEVF_MAC_ADDR_MC, addr); 1414 } 1415 1416 static int hclgevf_add_del_mac_addr(struct hclgevf_dev *hdev, 1417 struct hclgevf_mac_addr_node *mac_node, 1418 enum HCLGEVF_MAC_ADDR_TYPE mac_type) 1419 { 1420 struct hclge_vf_to_pf_msg send_msg; 1421 u8 code, subcode; 1422 1423 if (mac_type == HCLGEVF_MAC_ADDR_UC) { 1424 code = HCLGE_MBX_SET_UNICAST; 1425 if (mac_node->state == HCLGEVF_MAC_TO_ADD) 1426 subcode = HCLGE_MBX_MAC_VLAN_UC_ADD; 1427 else 1428 subcode = HCLGE_MBX_MAC_VLAN_UC_REMOVE; 1429 } else { 1430 code = HCLGE_MBX_SET_MULTICAST; 1431 if (mac_node->state == HCLGEVF_MAC_TO_ADD) 1432 subcode = HCLGE_MBX_MAC_VLAN_MC_ADD; 1433 else 1434 subcode = HCLGE_MBX_MAC_VLAN_MC_REMOVE; 1435 } 1436 1437 hclgevf_build_send_msg(&send_msg, code, subcode); 1438 ether_addr_copy(send_msg.data, mac_node->mac_addr); 1439 return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 1440 } 1441 1442 static void hclgevf_config_mac_list(struct hclgevf_dev *hdev, 1443 struct list_head *list, 1444 enum HCLGEVF_MAC_ADDR_TYPE mac_type) 1445 { 1446 struct hclgevf_mac_addr_node *mac_node, *tmp; 1447 int ret; 1448 1449 list_for_each_entry_safe(mac_node, tmp, list, node) { 1450 ret = hclgevf_add_del_mac_addr(hdev, mac_node, mac_type); 1451 if (ret) { 1452 dev_err(&hdev->pdev->dev, 1453 "failed to configure mac %pM, state = %d, ret = %d\n", 1454 mac_node->mac_addr, mac_node->state, ret); 1455 return; 1456 } 1457 if (mac_node->state == HCLGEVF_MAC_TO_ADD) { 1458 mac_node->state = HCLGEVF_MAC_ACTIVE; 1459 } else { 1460 list_del(&mac_node->node); 1461 kfree(mac_node); 1462 } 1463 } 1464 } 1465 1466 static void hclgevf_sync_from_add_list(struct list_head *add_list, 1467 struct list_head *mac_list) 1468 { 1469 struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node; 1470 1471 list_for_each_entry_safe(mac_node, tmp, add_list, node) { 1472 /* if the mac address from tmp_add_list is not in the 1473 * uc/mc_mac_list, it means have received a TO_DEL request 1474 * during the time window of sending mac config request to PF 1475 * If mac_node state is ACTIVE, then change its state to TO_DEL, 1476 * then it will be removed at next time. If is TO_ADD, it means 1477 * send TO_ADD request failed, so just remove the mac node. 1478 */ 1479 new_node = hclgevf_find_mac_node(mac_list, mac_node->mac_addr); 1480 if (new_node) { 1481 hclgevf_update_mac_node(new_node, mac_node->state); 1482 list_del(&mac_node->node); 1483 kfree(mac_node); 1484 } else if (mac_node->state == HCLGEVF_MAC_ACTIVE) { 1485 mac_node->state = HCLGEVF_MAC_TO_DEL; 1486 list_del(&mac_node->node); 1487 list_add_tail(&mac_node->node, mac_list); 1488 } else { 1489 list_del(&mac_node->node); 1490 kfree(mac_node); 1491 } 1492 } 1493 } 1494 1495 static void hclgevf_sync_from_del_list(struct list_head *del_list, 1496 struct list_head *mac_list) 1497 { 1498 struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node; 1499 1500 list_for_each_entry_safe(mac_node, tmp, del_list, node) { 1501 new_node = hclgevf_find_mac_node(mac_list, mac_node->mac_addr); 1502 if (new_node) { 1503 /* If the mac addr is exist in the mac list, it means 1504 * received a new request TO_ADD during the time window 1505 * of sending mac addr configurrequest to PF, so just 1506 * change the mac state to ACTIVE. 1507 */ 1508 new_node->state = HCLGEVF_MAC_ACTIVE; 1509 list_del(&mac_node->node); 1510 kfree(mac_node); 1511 } else { 1512 list_del(&mac_node->node); 1513 list_add_tail(&mac_node->node, mac_list); 1514 } 1515 } 1516 } 1517 1518 static void hclgevf_clear_list(struct list_head *list) 1519 { 1520 struct hclgevf_mac_addr_node *mac_node, *tmp; 1521 1522 list_for_each_entry_safe(mac_node, tmp, list, node) { 1523 list_del(&mac_node->node); 1524 kfree(mac_node); 1525 } 1526 } 1527 1528 static void hclgevf_sync_mac_list(struct hclgevf_dev *hdev, 1529 enum HCLGEVF_MAC_ADDR_TYPE mac_type) 1530 { 1531 struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node; 1532 struct list_head tmp_add_list, tmp_del_list; 1533 struct list_head *list; 1534 1535 INIT_LIST_HEAD(&tmp_add_list); 1536 INIT_LIST_HEAD(&tmp_del_list); 1537 1538 /* move the mac addr to the tmp_add_list and tmp_del_list, then 1539 * we can add/delete these mac addr outside the spin lock 1540 */ 1541 list = (mac_type == HCLGEVF_MAC_ADDR_UC) ? 1542 &hdev->mac_table.uc_mac_list : &hdev->mac_table.mc_mac_list; 1543 1544 spin_lock_bh(&hdev->mac_table.mac_list_lock); 1545 1546 list_for_each_entry_safe(mac_node, tmp, list, node) { 1547 switch (mac_node->state) { 1548 case HCLGEVF_MAC_TO_DEL: 1549 list_del(&mac_node->node); 1550 list_add_tail(&mac_node->node, &tmp_del_list); 1551 break; 1552 case HCLGEVF_MAC_TO_ADD: 1553 new_node = kzalloc(sizeof(*new_node), GFP_ATOMIC); 1554 if (!new_node) 1555 goto stop_traverse; 1556 1557 ether_addr_copy(new_node->mac_addr, mac_node->mac_addr); 1558 new_node->state = mac_node->state; 1559 list_add_tail(&new_node->node, &tmp_add_list); 1560 break; 1561 default: 1562 break; 1563 } 1564 } 1565 1566 stop_traverse: 1567 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1568 1569 /* delete first, in order to get max mac table space for adding */ 1570 hclgevf_config_mac_list(hdev, &tmp_del_list, mac_type); 1571 hclgevf_config_mac_list(hdev, &tmp_add_list, mac_type); 1572 1573 /* if some mac addresses were added/deleted fail, move back to the 1574 * mac_list, and retry at next time. 1575 */ 1576 spin_lock_bh(&hdev->mac_table.mac_list_lock); 1577 1578 hclgevf_sync_from_del_list(&tmp_del_list, list); 1579 hclgevf_sync_from_add_list(&tmp_add_list, list); 1580 1581 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1582 } 1583 1584 static void hclgevf_sync_mac_table(struct hclgevf_dev *hdev) 1585 { 1586 hclgevf_sync_mac_list(hdev, HCLGEVF_MAC_ADDR_UC); 1587 hclgevf_sync_mac_list(hdev, HCLGEVF_MAC_ADDR_MC); 1588 } 1589 1590 static void hclgevf_uninit_mac_list(struct hclgevf_dev *hdev) 1591 { 1592 spin_lock_bh(&hdev->mac_table.mac_list_lock); 1593 1594 hclgevf_clear_list(&hdev->mac_table.uc_mac_list); 1595 hclgevf_clear_list(&hdev->mac_table.mc_mac_list); 1596 1597 spin_unlock_bh(&hdev->mac_table.mac_list_lock); 1598 } 1599 1600 static int hclgevf_set_vlan_filter(struct hnae3_handle *handle, 1601 __be16 proto, u16 vlan_id, 1602 bool is_kill) 1603 { 1604 #define HCLGEVF_VLAN_MBX_IS_KILL_OFFSET 0 1605 #define HCLGEVF_VLAN_MBX_VLAN_ID_OFFSET 1 1606 #define HCLGEVF_VLAN_MBX_PROTO_OFFSET 3 1607 1608 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1609 struct hclge_vf_to_pf_msg send_msg; 1610 int ret; 1611 1612 if (vlan_id > HCLGEVF_MAX_VLAN_ID) 1613 return -EINVAL; 1614 1615 if (proto != htons(ETH_P_8021Q)) 1616 return -EPROTONOSUPPORT; 1617 1618 /* When device is resetting or reset failed, firmware is unable to 1619 * handle mailbox. Just record the vlan id, and remove it after 1620 * reset finished. 1621 */ 1622 if ((test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) || 1623 test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) && is_kill) { 1624 set_bit(vlan_id, hdev->vlan_del_fail_bmap); 1625 return -EBUSY; 1626 } 1627 1628 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 1629 HCLGE_MBX_VLAN_FILTER); 1630 send_msg.data[HCLGEVF_VLAN_MBX_IS_KILL_OFFSET] = is_kill; 1631 memcpy(&send_msg.data[HCLGEVF_VLAN_MBX_VLAN_ID_OFFSET], &vlan_id, 1632 sizeof(vlan_id)); 1633 memcpy(&send_msg.data[HCLGEVF_VLAN_MBX_PROTO_OFFSET], &proto, 1634 sizeof(proto)); 1635 /* when remove hw vlan filter failed, record the vlan id, 1636 * and try to remove it from hw later, to be consistence 1637 * with stack. 1638 */ 1639 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1640 if (is_kill && ret) 1641 set_bit(vlan_id, hdev->vlan_del_fail_bmap); 1642 1643 return ret; 1644 } 1645 1646 static void hclgevf_sync_vlan_filter(struct hclgevf_dev *hdev) 1647 { 1648 #define HCLGEVF_MAX_SYNC_COUNT 60 1649 struct hnae3_handle *handle = &hdev->nic; 1650 int ret, sync_cnt = 0; 1651 u16 vlan_id; 1652 1653 vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID); 1654 while (vlan_id != VLAN_N_VID) { 1655 ret = hclgevf_set_vlan_filter(handle, htons(ETH_P_8021Q), 1656 vlan_id, true); 1657 if (ret) 1658 return; 1659 1660 clear_bit(vlan_id, hdev->vlan_del_fail_bmap); 1661 sync_cnt++; 1662 if (sync_cnt >= HCLGEVF_MAX_SYNC_COUNT) 1663 return; 1664 1665 vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID); 1666 } 1667 } 1668 1669 static int hclgevf_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) 1670 { 1671 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1672 struct hclge_vf_to_pf_msg send_msg; 1673 1674 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 1675 HCLGE_MBX_VLAN_RX_OFF_CFG); 1676 send_msg.data[0] = enable ? 1 : 0; 1677 return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 1678 } 1679 1680 static int hclgevf_reset_tqp(struct hnae3_handle *handle, u16 queue_id) 1681 { 1682 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1683 struct hclge_vf_to_pf_msg send_msg; 1684 int ret; 1685 1686 /* disable vf queue before send queue reset msg to PF */ 1687 ret = hclgevf_tqp_enable(hdev, queue_id, 0, false); 1688 if (ret) 1689 return ret; 1690 1691 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_QUEUE_RESET, 0); 1692 memcpy(send_msg.data, &queue_id, sizeof(queue_id)); 1693 return hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1694 } 1695 1696 static int hclgevf_set_mtu(struct hnae3_handle *handle, int new_mtu) 1697 { 1698 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 1699 struct hclge_vf_to_pf_msg send_msg; 1700 1701 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_MTU, 0); 1702 memcpy(send_msg.data, &new_mtu, sizeof(new_mtu)); 1703 return hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1704 } 1705 1706 static int hclgevf_notify_client(struct hclgevf_dev *hdev, 1707 enum hnae3_reset_notify_type type) 1708 { 1709 struct hnae3_client *client = hdev->nic_client; 1710 struct hnae3_handle *handle = &hdev->nic; 1711 int ret; 1712 1713 if (!test_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state) || 1714 !client) 1715 return 0; 1716 1717 if (!client->ops->reset_notify) 1718 return -EOPNOTSUPP; 1719 1720 ret = client->ops->reset_notify(handle, type); 1721 if (ret) 1722 dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n", 1723 type, ret); 1724 1725 return ret; 1726 } 1727 1728 static int hclgevf_notify_roce_client(struct hclgevf_dev *hdev, 1729 enum hnae3_reset_notify_type type) 1730 { 1731 struct hnae3_client *client = hdev->roce_client; 1732 struct hnae3_handle *handle = &hdev->roce; 1733 int ret; 1734 1735 if (!test_bit(HCLGEVF_STATE_ROCE_REGISTERED, &hdev->state) || !client) 1736 return 0; 1737 1738 if (!client->ops->reset_notify) 1739 return -EOPNOTSUPP; 1740 1741 ret = client->ops->reset_notify(handle, type); 1742 if (ret) 1743 dev_err(&hdev->pdev->dev, "notify roce client failed %d(%d)", 1744 type, ret); 1745 return ret; 1746 } 1747 1748 static int hclgevf_reset_wait(struct hclgevf_dev *hdev) 1749 { 1750 #define HCLGEVF_RESET_WAIT_US 20000 1751 #define HCLGEVF_RESET_WAIT_CNT 2000 1752 #define HCLGEVF_RESET_WAIT_TIMEOUT_US \ 1753 (HCLGEVF_RESET_WAIT_US * HCLGEVF_RESET_WAIT_CNT) 1754 1755 u32 val; 1756 int ret; 1757 1758 if (hdev->reset_type == HNAE3_VF_RESET) 1759 ret = readl_poll_timeout(hdev->hw.io_base + 1760 HCLGEVF_VF_RST_ING, val, 1761 !(val & HCLGEVF_VF_RST_ING_BIT), 1762 HCLGEVF_RESET_WAIT_US, 1763 HCLGEVF_RESET_WAIT_TIMEOUT_US); 1764 else 1765 ret = readl_poll_timeout(hdev->hw.io_base + 1766 HCLGEVF_RST_ING, val, 1767 !(val & HCLGEVF_RST_ING_BITS), 1768 HCLGEVF_RESET_WAIT_US, 1769 HCLGEVF_RESET_WAIT_TIMEOUT_US); 1770 1771 /* hardware completion status should be available by this time */ 1772 if (ret) { 1773 dev_err(&hdev->pdev->dev, 1774 "couldn't get reset done status from h/w, timeout!\n"); 1775 return ret; 1776 } 1777 1778 /* we will wait a bit more to let reset of the stack to complete. This 1779 * might happen in case reset assertion was made by PF. Yes, this also 1780 * means we might end up waiting bit more even for VF reset. 1781 */ 1782 msleep(5000); 1783 1784 return 0; 1785 } 1786 1787 static void hclgevf_reset_handshake(struct hclgevf_dev *hdev, bool enable) 1788 { 1789 u32 reg_val; 1790 1791 reg_val = hclgevf_read_dev(&hdev->hw, HCLGEVF_NIC_CSQ_DEPTH_REG); 1792 if (enable) 1793 reg_val |= HCLGEVF_NIC_SW_RST_RDY; 1794 else 1795 reg_val &= ~HCLGEVF_NIC_SW_RST_RDY; 1796 1797 hclgevf_write_dev(&hdev->hw, HCLGEVF_NIC_CSQ_DEPTH_REG, 1798 reg_val); 1799 } 1800 1801 static int hclgevf_reset_stack(struct hclgevf_dev *hdev) 1802 { 1803 int ret; 1804 1805 /* uninitialize the nic client */ 1806 ret = hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT); 1807 if (ret) 1808 return ret; 1809 1810 /* re-initialize the hclge device */ 1811 ret = hclgevf_reset_hdev(hdev); 1812 if (ret) { 1813 dev_err(&hdev->pdev->dev, 1814 "hclge device re-init failed, VF is disabled!\n"); 1815 return ret; 1816 } 1817 1818 /* bring up the nic client again */ 1819 ret = hclgevf_notify_client(hdev, HNAE3_INIT_CLIENT); 1820 if (ret) 1821 return ret; 1822 1823 /* clear handshake status with IMP */ 1824 hclgevf_reset_handshake(hdev, false); 1825 1826 /* bring up the nic to enable TX/RX again */ 1827 return hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 1828 } 1829 1830 static int hclgevf_reset_prepare_wait(struct hclgevf_dev *hdev) 1831 { 1832 #define HCLGEVF_RESET_SYNC_TIME 100 1833 1834 if (hdev->reset_type == HNAE3_VF_FUNC_RESET) { 1835 struct hclge_vf_to_pf_msg send_msg; 1836 int ret; 1837 1838 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_RESET, 0); 1839 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0); 1840 if (ret) { 1841 dev_err(&hdev->pdev->dev, 1842 "failed to assert VF reset, ret = %d\n", ret); 1843 return ret; 1844 } 1845 hdev->rst_stats.vf_func_rst_cnt++; 1846 } 1847 1848 set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 1849 /* inform hardware that preparatory work is done */ 1850 msleep(HCLGEVF_RESET_SYNC_TIME); 1851 hclgevf_reset_handshake(hdev, true); 1852 dev_info(&hdev->pdev->dev, "prepare reset(%d) wait done\n", 1853 hdev->reset_type); 1854 1855 return 0; 1856 } 1857 1858 static void hclgevf_dump_rst_info(struct hclgevf_dev *hdev) 1859 { 1860 dev_info(&hdev->pdev->dev, "VF function reset count: %u\n", 1861 hdev->rst_stats.vf_func_rst_cnt); 1862 dev_info(&hdev->pdev->dev, "FLR reset count: %u\n", 1863 hdev->rst_stats.flr_rst_cnt); 1864 dev_info(&hdev->pdev->dev, "VF reset count: %u\n", 1865 hdev->rst_stats.vf_rst_cnt); 1866 dev_info(&hdev->pdev->dev, "reset done count: %u\n", 1867 hdev->rst_stats.rst_done_cnt); 1868 dev_info(&hdev->pdev->dev, "HW reset done count: %u\n", 1869 hdev->rst_stats.hw_rst_done_cnt); 1870 dev_info(&hdev->pdev->dev, "reset count: %u\n", 1871 hdev->rst_stats.rst_cnt); 1872 dev_info(&hdev->pdev->dev, "reset fail count: %u\n", 1873 hdev->rst_stats.rst_fail_cnt); 1874 dev_info(&hdev->pdev->dev, "vector0 interrupt enable status: 0x%x\n", 1875 hclgevf_read_dev(&hdev->hw, HCLGEVF_MISC_VECTOR_REG_BASE)); 1876 dev_info(&hdev->pdev->dev, "vector0 interrupt status: 0x%x\n", 1877 hclgevf_read_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_STATE_REG)); 1878 dev_info(&hdev->pdev->dev, "handshake status: 0x%x\n", 1879 hclgevf_read_dev(&hdev->hw, HCLGEVF_CMDQ_TX_DEPTH_REG)); 1880 dev_info(&hdev->pdev->dev, "function reset status: 0x%x\n", 1881 hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING)); 1882 dev_info(&hdev->pdev->dev, "hdev state: 0x%lx\n", hdev->state); 1883 } 1884 1885 static void hclgevf_reset_err_handle(struct hclgevf_dev *hdev) 1886 { 1887 /* recover handshake status with IMP when reset fail */ 1888 hclgevf_reset_handshake(hdev, true); 1889 hdev->rst_stats.rst_fail_cnt++; 1890 dev_err(&hdev->pdev->dev, "failed to reset VF(%u)\n", 1891 hdev->rst_stats.rst_fail_cnt); 1892 1893 if (hdev->rst_stats.rst_fail_cnt < HCLGEVF_RESET_MAX_FAIL_CNT) 1894 set_bit(hdev->reset_type, &hdev->reset_pending); 1895 1896 if (hclgevf_is_reset_pending(hdev)) { 1897 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 1898 hclgevf_reset_task_schedule(hdev); 1899 } else { 1900 set_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state); 1901 hclgevf_dump_rst_info(hdev); 1902 } 1903 } 1904 1905 static int hclgevf_reset_prepare(struct hclgevf_dev *hdev) 1906 { 1907 int ret; 1908 1909 hdev->rst_stats.rst_cnt++; 1910 1911 /* perform reset of the stack & ae device for a client */ 1912 ret = hclgevf_notify_roce_client(hdev, HNAE3_DOWN_CLIENT); 1913 if (ret) 1914 return ret; 1915 1916 rtnl_lock(); 1917 /* bring down the nic to stop any ongoing TX/RX */ 1918 ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 1919 rtnl_unlock(); 1920 if (ret) 1921 return ret; 1922 1923 return hclgevf_reset_prepare_wait(hdev); 1924 } 1925 1926 static int hclgevf_reset_rebuild(struct hclgevf_dev *hdev) 1927 { 1928 int ret; 1929 1930 hdev->rst_stats.hw_rst_done_cnt++; 1931 ret = hclgevf_notify_roce_client(hdev, HNAE3_UNINIT_CLIENT); 1932 if (ret) 1933 return ret; 1934 1935 rtnl_lock(); 1936 /* now, re-initialize the nic client and ae device */ 1937 ret = hclgevf_reset_stack(hdev); 1938 rtnl_unlock(); 1939 if (ret) { 1940 dev_err(&hdev->pdev->dev, "failed to reset VF stack\n"); 1941 return ret; 1942 } 1943 1944 ret = hclgevf_notify_roce_client(hdev, HNAE3_INIT_CLIENT); 1945 /* ignore RoCE notify error if it fails HCLGEVF_RESET_MAX_FAIL_CNT - 1 1946 * times 1947 */ 1948 if (ret && 1949 hdev->rst_stats.rst_fail_cnt < HCLGEVF_RESET_MAX_FAIL_CNT - 1) 1950 return ret; 1951 1952 ret = hclgevf_notify_roce_client(hdev, HNAE3_UP_CLIENT); 1953 if (ret) 1954 return ret; 1955 1956 hdev->last_reset_time = jiffies; 1957 hdev->rst_stats.rst_done_cnt++; 1958 hdev->rst_stats.rst_fail_cnt = 0; 1959 clear_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state); 1960 1961 return 0; 1962 } 1963 1964 static void hclgevf_reset(struct hclgevf_dev *hdev) 1965 { 1966 if (hclgevf_reset_prepare(hdev)) 1967 goto err_reset; 1968 1969 /* check if VF could successfully fetch the hardware reset completion 1970 * status from the hardware 1971 */ 1972 if (hclgevf_reset_wait(hdev)) { 1973 /* can't do much in this situation, will disable VF */ 1974 dev_err(&hdev->pdev->dev, 1975 "failed to fetch H/W reset completion status\n"); 1976 goto err_reset; 1977 } 1978 1979 if (hclgevf_reset_rebuild(hdev)) 1980 goto err_reset; 1981 1982 return; 1983 1984 err_reset: 1985 hclgevf_reset_err_handle(hdev); 1986 } 1987 1988 static enum hnae3_reset_type hclgevf_get_reset_level(struct hclgevf_dev *hdev, 1989 unsigned long *addr) 1990 { 1991 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; 1992 1993 /* return the highest priority reset level amongst all */ 1994 if (test_bit(HNAE3_VF_RESET, addr)) { 1995 rst_level = HNAE3_VF_RESET; 1996 clear_bit(HNAE3_VF_RESET, addr); 1997 clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 1998 clear_bit(HNAE3_VF_FUNC_RESET, addr); 1999 } else if (test_bit(HNAE3_VF_FULL_RESET, addr)) { 2000 rst_level = HNAE3_VF_FULL_RESET; 2001 clear_bit(HNAE3_VF_FULL_RESET, addr); 2002 clear_bit(HNAE3_VF_FUNC_RESET, addr); 2003 } else if (test_bit(HNAE3_VF_PF_FUNC_RESET, addr)) { 2004 rst_level = HNAE3_VF_PF_FUNC_RESET; 2005 clear_bit(HNAE3_VF_PF_FUNC_RESET, addr); 2006 clear_bit(HNAE3_VF_FUNC_RESET, addr); 2007 } else if (test_bit(HNAE3_VF_FUNC_RESET, addr)) { 2008 rst_level = HNAE3_VF_FUNC_RESET; 2009 clear_bit(HNAE3_VF_FUNC_RESET, addr); 2010 } else if (test_bit(HNAE3_FLR_RESET, addr)) { 2011 rst_level = HNAE3_FLR_RESET; 2012 clear_bit(HNAE3_FLR_RESET, addr); 2013 } 2014 2015 return rst_level; 2016 } 2017 2018 static void hclgevf_reset_event(struct pci_dev *pdev, 2019 struct hnae3_handle *handle) 2020 { 2021 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2022 struct hclgevf_dev *hdev = ae_dev->priv; 2023 2024 dev_info(&hdev->pdev->dev, "received reset request from VF enet\n"); 2025 2026 if (hdev->default_reset_request) 2027 hdev->reset_level = 2028 hclgevf_get_reset_level(hdev, 2029 &hdev->default_reset_request); 2030 else 2031 hdev->reset_level = HNAE3_VF_FUNC_RESET; 2032 2033 /* reset of this VF requested */ 2034 set_bit(HCLGEVF_RESET_REQUESTED, &hdev->reset_state); 2035 hclgevf_reset_task_schedule(hdev); 2036 2037 hdev->last_reset_time = jiffies; 2038 } 2039 2040 static void hclgevf_set_def_reset_request(struct hnae3_ae_dev *ae_dev, 2041 enum hnae3_reset_type rst_type) 2042 { 2043 struct hclgevf_dev *hdev = ae_dev->priv; 2044 2045 set_bit(rst_type, &hdev->default_reset_request); 2046 } 2047 2048 static void hclgevf_enable_vector(struct hclgevf_misc_vector *vector, bool en) 2049 { 2050 writel(en ? 1 : 0, vector->addr); 2051 } 2052 2053 static void hclgevf_flr_prepare(struct hnae3_ae_dev *ae_dev) 2054 { 2055 #define HCLGEVF_FLR_RETRY_WAIT_MS 500 2056 #define HCLGEVF_FLR_RETRY_CNT 5 2057 2058 struct hclgevf_dev *hdev = ae_dev->priv; 2059 int retry_cnt = 0; 2060 int ret; 2061 2062 retry: 2063 down(&hdev->reset_sem); 2064 set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 2065 hdev->reset_type = HNAE3_FLR_RESET; 2066 ret = hclgevf_reset_prepare(hdev); 2067 if (ret) { 2068 dev_err(&hdev->pdev->dev, "fail to prepare FLR, ret=%d\n", 2069 ret); 2070 if (hdev->reset_pending || 2071 retry_cnt++ < HCLGEVF_FLR_RETRY_CNT) { 2072 dev_err(&hdev->pdev->dev, 2073 "reset_pending:0x%lx, retry_cnt:%d\n", 2074 hdev->reset_pending, retry_cnt); 2075 clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 2076 up(&hdev->reset_sem); 2077 msleep(HCLGEVF_FLR_RETRY_WAIT_MS); 2078 goto retry; 2079 } 2080 } 2081 2082 /* disable misc vector before FLR done */ 2083 hclgevf_enable_vector(&hdev->misc_vector, false); 2084 hdev->rst_stats.flr_rst_cnt++; 2085 } 2086 2087 static void hclgevf_flr_done(struct hnae3_ae_dev *ae_dev) 2088 { 2089 struct hclgevf_dev *hdev = ae_dev->priv; 2090 int ret; 2091 2092 hclgevf_enable_vector(&hdev->misc_vector, true); 2093 2094 ret = hclgevf_reset_rebuild(hdev); 2095 if (ret) 2096 dev_warn(&hdev->pdev->dev, "fail to rebuild, ret=%d\n", 2097 ret); 2098 2099 hdev->reset_type = HNAE3_NONE_RESET; 2100 clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 2101 up(&hdev->reset_sem); 2102 } 2103 2104 static u32 hclgevf_get_fw_version(struct hnae3_handle *handle) 2105 { 2106 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2107 2108 return hdev->fw_version; 2109 } 2110 2111 static void hclgevf_get_misc_vector(struct hclgevf_dev *hdev) 2112 { 2113 struct hclgevf_misc_vector *vector = &hdev->misc_vector; 2114 2115 vector->vector_irq = pci_irq_vector(hdev->pdev, 2116 HCLGEVF_MISC_VECTOR_NUM); 2117 vector->addr = hdev->hw.io_base + HCLGEVF_MISC_VECTOR_REG_BASE; 2118 /* vector status always valid for Vector 0 */ 2119 hdev->vector_status[HCLGEVF_MISC_VECTOR_NUM] = 0; 2120 hdev->vector_irq[HCLGEVF_MISC_VECTOR_NUM] = vector->vector_irq; 2121 2122 hdev->num_msi_left -= 1; 2123 hdev->num_msi_used += 1; 2124 } 2125 2126 void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev) 2127 { 2128 if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) && 2129 !test_and_set_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, 2130 &hdev->state)) 2131 mod_delayed_work(hclgevf_wq, &hdev->service_task, 0); 2132 } 2133 2134 void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev) 2135 { 2136 if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) && 2137 !test_and_set_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, 2138 &hdev->state)) 2139 mod_delayed_work(hclgevf_wq, &hdev->service_task, 0); 2140 } 2141 2142 static void hclgevf_task_schedule(struct hclgevf_dev *hdev, 2143 unsigned long delay) 2144 { 2145 if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) && 2146 !test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) 2147 mod_delayed_work(hclgevf_wq, &hdev->service_task, delay); 2148 } 2149 2150 static void hclgevf_reset_service_task(struct hclgevf_dev *hdev) 2151 { 2152 #define HCLGEVF_MAX_RESET_ATTEMPTS_CNT 3 2153 2154 if (!test_and_clear_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state)) 2155 return; 2156 2157 down(&hdev->reset_sem); 2158 set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 2159 2160 if (test_and_clear_bit(HCLGEVF_RESET_PENDING, 2161 &hdev->reset_state)) { 2162 /* PF has initmated that it is about to reset the hardware. 2163 * We now have to poll & check if hardware has actually 2164 * completed the reset sequence. On hardware reset completion, 2165 * VF needs to reset the client and ae device. 2166 */ 2167 hdev->reset_attempts = 0; 2168 2169 hdev->last_reset_time = jiffies; 2170 while ((hdev->reset_type = 2171 hclgevf_get_reset_level(hdev, &hdev->reset_pending)) 2172 != HNAE3_NONE_RESET) 2173 hclgevf_reset(hdev); 2174 } else if (test_and_clear_bit(HCLGEVF_RESET_REQUESTED, 2175 &hdev->reset_state)) { 2176 /* we could be here when either of below happens: 2177 * 1. reset was initiated due to watchdog timeout caused by 2178 * a. IMP was earlier reset and our TX got choked down and 2179 * which resulted in watchdog reacting and inducing VF 2180 * reset. This also means our cmdq would be unreliable. 2181 * b. problem in TX due to other lower layer(example link 2182 * layer not functioning properly etc.) 2183 * 2. VF reset might have been initiated due to some config 2184 * change. 2185 * 2186 * NOTE: Theres no clear way to detect above cases than to react 2187 * to the response of PF for this reset request. PF will ack the 2188 * 1b and 2. cases but we will not get any intimation about 1a 2189 * from PF as cmdq would be in unreliable state i.e. mailbox 2190 * communication between PF and VF would be broken. 2191 * 2192 * if we are never geting into pending state it means either: 2193 * 1. PF is not receiving our request which could be due to IMP 2194 * reset 2195 * 2. PF is screwed 2196 * We cannot do much for 2. but to check first we can try reset 2197 * our PCIe + stack and see if it alleviates the problem. 2198 */ 2199 if (hdev->reset_attempts > HCLGEVF_MAX_RESET_ATTEMPTS_CNT) { 2200 /* prepare for full reset of stack + pcie interface */ 2201 set_bit(HNAE3_VF_FULL_RESET, &hdev->reset_pending); 2202 2203 /* "defer" schedule the reset task again */ 2204 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 2205 } else { 2206 hdev->reset_attempts++; 2207 2208 set_bit(hdev->reset_level, &hdev->reset_pending); 2209 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 2210 } 2211 hclgevf_reset_task_schedule(hdev); 2212 } 2213 2214 hdev->reset_type = HNAE3_NONE_RESET; 2215 clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 2216 up(&hdev->reset_sem); 2217 } 2218 2219 static void hclgevf_mailbox_service_task(struct hclgevf_dev *hdev) 2220 { 2221 if (!test_and_clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state)) 2222 return; 2223 2224 if (test_and_set_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) 2225 return; 2226 2227 hclgevf_mbx_async_handler(hdev); 2228 2229 clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 2230 } 2231 2232 static void hclgevf_keep_alive(struct hclgevf_dev *hdev) 2233 { 2234 struct hclge_vf_to_pf_msg send_msg; 2235 int ret; 2236 2237 if (test_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state)) 2238 return; 2239 2240 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_KEEP_ALIVE, 0); 2241 ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 2242 if (ret) 2243 dev_err(&hdev->pdev->dev, 2244 "VF sends keep alive cmd failed(=%d)\n", ret); 2245 } 2246 2247 static void hclgevf_periodic_service_task(struct hclgevf_dev *hdev) 2248 { 2249 unsigned long delta = round_jiffies_relative(HZ); 2250 struct hnae3_handle *handle = &hdev->nic; 2251 2252 if (test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) 2253 return; 2254 2255 if (time_is_after_jiffies(hdev->last_serv_processed + HZ)) { 2256 delta = jiffies - hdev->last_serv_processed; 2257 2258 if (delta < round_jiffies_relative(HZ)) { 2259 delta = round_jiffies_relative(HZ) - delta; 2260 goto out; 2261 } 2262 } 2263 2264 hdev->serv_processed_cnt++; 2265 if (!(hdev->serv_processed_cnt % HCLGEVF_KEEP_ALIVE_TASK_INTERVAL)) 2266 hclgevf_keep_alive(hdev); 2267 2268 if (test_bit(HCLGEVF_STATE_DOWN, &hdev->state)) { 2269 hdev->last_serv_processed = jiffies; 2270 goto out; 2271 } 2272 2273 if (!(hdev->serv_processed_cnt % HCLGEVF_STATS_TIMER_INTERVAL)) 2274 hclgevf_tqps_update_stats(handle); 2275 2276 /* request the link status from the PF. PF would be able to tell VF 2277 * about such updates in future so we might remove this later 2278 */ 2279 hclgevf_request_link_info(hdev); 2280 2281 hclgevf_update_link_mode(hdev); 2282 2283 hclgevf_sync_vlan_filter(hdev); 2284 2285 hclgevf_sync_mac_table(hdev); 2286 2287 hclgevf_sync_promisc_mode(hdev); 2288 2289 hdev->last_serv_processed = jiffies; 2290 2291 out: 2292 hclgevf_task_schedule(hdev, delta); 2293 } 2294 2295 static void hclgevf_service_task(struct work_struct *work) 2296 { 2297 struct hclgevf_dev *hdev = container_of(work, struct hclgevf_dev, 2298 service_task.work); 2299 2300 hclgevf_reset_service_task(hdev); 2301 hclgevf_mailbox_service_task(hdev); 2302 hclgevf_periodic_service_task(hdev); 2303 2304 /* Handle reset and mbx again in case periodical task delays the 2305 * handling by calling hclgevf_task_schedule() in 2306 * hclgevf_periodic_service_task() 2307 */ 2308 hclgevf_reset_service_task(hdev); 2309 hclgevf_mailbox_service_task(hdev); 2310 } 2311 2312 static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regclr) 2313 { 2314 hclgevf_write_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_SRC_REG, regclr); 2315 } 2316 2317 static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev, 2318 u32 *clearval) 2319 { 2320 u32 val, cmdq_stat_reg, rst_ing_reg; 2321 2322 /* fetch the events from their corresponding regs */ 2323 cmdq_stat_reg = hclgevf_read_dev(&hdev->hw, 2324 HCLGEVF_VECTOR0_CMDQ_STATE_REG); 2325 2326 if (BIT(HCLGEVF_VECTOR0_RST_INT_B) & cmdq_stat_reg) { 2327 rst_ing_reg = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 2328 dev_info(&hdev->pdev->dev, 2329 "receive reset interrupt 0x%x!\n", rst_ing_reg); 2330 set_bit(HNAE3_VF_RESET, &hdev->reset_pending); 2331 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); 2332 set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 2333 *clearval = ~(1U << HCLGEVF_VECTOR0_RST_INT_B); 2334 hdev->rst_stats.vf_rst_cnt++; 2335 /* set up VF hardware reset status, its PF will clear 2336 * this status when PF has initialized done. 2337 */ 2338 val = hclgevf_read_dev(&hdev->hw, HCLGEVF_VF_RST_ING); 2339 hclgevf_write_dev(&hdev->hw, HCLGEVF_VF_RST_ING, 2340 val | HCLGEVF_VF_RST_ING_BIT); 2341 return HCLGEVF_VECTOR0_EVENT_RST; 2342 } 2343 2344 /* check for vector0 mailbox(=CMDQ RX) event source */ 2345 if (BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) { 2346 /* for revision 0x21, clearing interrupt is writing bit 0 2347 * to the clear register, writing bit 1 means to keep the 2348 * old value. 2349 * for revision 0x20, the clear register is a read & write 2350 * register, so we should just write 0 to the bit we are 2351 * handling, and keep other bits as cmdq_stat_reg. 2352 */ 2353 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) 2354 *clearval = ~(1U << HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 2355 else 2356 *clearval = cmdq_stat_reg & 2357 ~BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B); 2358 2359 return HCLGEVF_VECTOR0_EVENT_MBX; 2360 } 2361 2362 /* print other vector0 event source */ 2363 dev_info(&hdev->pdev->dev, 2364 "vector 0 interrupt from unknown source, cmdq_src = %#x\n", 2365 cmdq_stat_reg); 2366 2367 return HCLGEVF_VECTOR0_EVENT_OTHER; 2368 } 2369 2370 static irqreturn_t hclgevf_misc_irq_handle(int irq, void *data) 2371 { 2372 enum hclgevf_evt_cause event_cause; 2373 struct hclgevf_dev *hdev = data; 2374 u32 clearval; 2375 2376 hclgevf_enable_vector(&hdev->misc_vector, false); 2377 event_cause = hclgevf_check_evt_cause(hdev, &clearval); 2378 2379 switch (event_cause) { 2380 case HCLGEVF_VECTOR0_EVENT_RST: 2381 hclgevf_reset_task_schedule(hdev); 2382 break; 2383 case HCLGEVF_VECTOR0_EVENT_MBX: 2384 hclgevf_mbx_handler(hdev); 2385 break; 2386 default: 2387 break; 2388 } 2389 2390 if (event_cause != HCLGEVF_VECTOR0_EVENT_OTHER) { 2391 hclgevf_clear_event_cause(hdev, clearval); 2392 hclgevf_enable_vector(&hdev->misc_vector, true); 2393 } 2394 2395 return IRQ_HANDLED; 2396 } 2397 2398 static int hclgevf_configure(struct hclgevf_dev *hdev) 2399 { 2400 int ret; 2401 2402 /* get current port based vlan state from PF */ 2403 ret = hclgevf_get_port_base_vlan_filter_state(hdev); 2404 if (ret) 2405 return ret; 2406 2407 /* get queue configuration from PF */ 2408 ret = hclgevf_get_queue_info(hdev); 2409 if (ret) 2410 return ret; 2411 2412 /* get queue depth info from PF */ 2413 ret = hclgevf_get_queue_depth(hdev); 2414 if (ret) 2415 return ret; 2416 2417 ret = hclgevf_get_pf_media_type(hdev); 2418 if (ret) 2419 return ret; 2420 2421 /* get tc configuration from PF */ 2422 return hclgevf_get_tc_info(hdev); 2423 } 2424 2425 static int hclgevf_alloc_hdev(struct hnae3_ae_dev *ae_dev) 2426 { 2427 struct pci_dev *pdev = ae_dev->pdev; 2428 struct hclgevf_dev *hdev; 2429 2430 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 2431 if (!hdev) 2432 return -ENOMEM; 2433 2434 hdev->pdev = pdev; 2435 hdev->ae_dev = ae_dev; 2436 ae_dev->priv = hdev; 2437 2438 return 0; 2439 } 2440 2441 static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev) 2442 { 2443 struct hnae3_handle *roce = &hdev->roce; 2444 struct hnae3_handle *nic = &hdev->nic; 2445 2446 roce->rinfo.num_vectors = hdev->num_roce_msix; 2447 2448 if (hdev->num_msi_left < roce->rinfo.num_vectors || 2449 hdev->num_msi_left == 0) 2450 return -EINVAL; 2451 2452 roce->rinfo.base_vector = hdev->roce_base_vector; 2453 2454 roce->rinfo.netdev = nic->kinfo.netdev; 2455 roce->rinfo.roce_io_base = hdev->hw.io_base; 2456 roce->rinfo.roce_mem_base = hdev->hw.mem_base; 2457 2458 roce->pdev = nic->pdev; 2459 roce->ae_algo = nic->ae_algo; 2460 roce->numa_node_mask = nic->numa_node_mask; 2461 2462 return 0; 2463 } 2464 2465 static int hclgevf_config_gro(struct hclgevf_dev *hdev, bool en) 2466 { 2467 struct hclgevf_cfg_gro_status_cmd *req; 2468 struct hclgevf_desc desc; 2469 int ret; 2470 2471 if (!hnae3_dev_gro_supported(hdev)) 2472 return 0; 2473 2474 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_GRO_GENERIC_CONFIG, 2475 false); 2476 req = (struct hclgevf_cfg_gro_status_cmd *)desc.data; 2477 2478 req->gro_en = en ? 1 : 0; 2479 2480 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 2481 if (ret) 2482 dev_err(&hdev->pdev->dev, 2483 "VF GRO hardware config cmd failed, ret = %d.\n", ret); 2484 2485 return ret; 2486 } 2487 2488 static int hclgevf_rss_init_cfg(struct hclgevf_dev *hdev) 2489 { 2490 u16 rss_ind_tbl_size = hdev->ae_dev->dev_specs.rss_ind_tbl_size; 2491 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 2492 struct hclgevf_rss_tuple_cfg *tuple_sets; 2493 u32 i; 2494 2495 rss_cfg->hash_algo = HCLGEVF_RSS_HASH_ALGO_TOEPLITZ; 2496 rss_cfg->rss_size = hdev->nic.kinfo.rss_size; 2497 tuple_sets = &rss_cfg->rss_tuple_sets; 2498 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 2499 u8 *rss_ind_tbl; 2500 2501 rss_cfg->hash_algo = HCLGEVF_RSS_HASH_ALGO_SIMPLE; 2502 2503 rss_ind_tbl = devm_kcalloc(&hdev->pdev->dev, rss_ind_tbl_size, 2504 sizeof(*rss_ind_tbl), GFP_KERNEL); 2505 if (!rss_ind_tbl) 2506 return -ENOMEM; 2507 2508 rss_cfg->rss_indirection_tbl = rss_ind_tbl; 2509 memcpy(rss_cfg->rss_hash_key, hclgevf_hash_key, 2510 HCLGEVF_RSS_KEY_SIZE); 2511 2512 tuple_sets->ipv4_tcp_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2513 tuple_sets->ipv4_udp_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2514 tuple_sets->ipv4_sctp_en = HCLGEVF_RSS_INPUT_TUPLE_SCTP; 2515 tuple_sets->ipv4_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2516 tuple_sets->ipv6_tcp_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2517 tuple_sets->ipv6_udp_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2518 tuple_sets->ipv6_sctp_en = 2519 hdev->ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2 ? 2520 HCLGEVF_RSS_INPUT_TUPLE_SCTP_NO_PORT : 2521 HCLGEVF_RSS_INPUT_TUPLE_SCTP; 2522 tuple_sets->ipv6_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER; 2523 } 2524 2525 /* Initialize RSS indirect table */ 2526 for (i = 0; i < rss_ind_tbl_size; i++) 2527 rss_cfg->rss_indirection_tbl[i] = i % rss_cfg->rss_size; 2528 2529 return 0; 2530 } 2531 2532 static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev) 2533 { 2534 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg; 2535 int ret; 2536 2537 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 2538 ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo, 2539 rss_cfg->rss_hash_key); 2540 if (ret) 2541 return ret; 2542 2543 ret = hclgevf_set_rss_input_tuple(hdev, rss_cfg); 2544 if (ret) 2545 return ret; 2546 } 2547 2548 ret = hclgevf_set_rss_indir_table(hdev); 2549 if (ret) 2550 return ret; 2551 2552 return hclgevf_set_rss_tc_mode(hdev, rss_cfg->rss_size); 2553 } 2554 2555 static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev) 2556 { 2557 return hclgevf_set_vlan_filter(&hdev->nic, htons(ETH_P_8021Q), 0, 2558 false); 2559 } 2560 2561 static void hclgevf_flush_link_update(struct hclgevf_dev *hdev) 2562 { 2563 #define HCLGEVF_FLUSH_LINK_TIMEOUT 100000 2564 2565 unsigned long last = hdev->serv_processed_cnt; 2566 int i = 0; 2567 2568 while (test_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state) && 2569 i++ < HCLGEVF_FLUSH_LINK_TIMEOUT && 2570 last == hdev->serv_processed_cnt) 2571 usleep_range(1, 1); 2572 } 2573 2574 static void hclgevf_set_timer_task(struct hnae3_handle *handle, bool enable) 2575 { 2576 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2577 2578 if (enable) { 2579 hclgevf_task_schedule(hdev, 0); 2580 } else { 2581 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2582 2583 /* flush memory to make sure DOWN is seen by service task */ 2584 smp_mb__before_atomic(); 2585 hclgevf_flush_link_update(hdev); 2586 } 2587 } 2588 2589 static int hclgevf_ae_start(struct hnae3_handle *handle) 2590 { 2591 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2592 2593 hclgevf_reset_tqp_stats(handle); 2594 2595 hclgevf_request_link_info(hdev); 2596 2597 hclgevf_update_link_mode(hdev); 2598 2599 clear_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2600 2601 return 0; 2602 } 2603 2604 static void hclgevf_ae_stop(struct hnae3_handle *handle) 2605 { 2606 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2607 int i; 2608 2609 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2610 2611 if (hdev->reset_type != HNAE3_VF_RESET) 2612 for (i = 0; i < handle->kinfo.num_tqps; i++) 2613 if (hclgevf_reset_tqp(handle, i)) 2614 break; 2615 2616 hclgevf_reset_tqp_stats(handle); 2617 hclgevf_update_link_status(hdev, 0); 2618 } 2619 2620 static int hclgevf_set_alive(struct hnae3_handle *handle, bool alive) 2621 { 2622 #define HCLGEVF_STATE_ALIVE 1 2623 #define HCLGEVF_STATE_NOT_ALIVE 0 2624 2625 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2626 struct hclge_vf_to_pf_msg send_msg; 2627 2628 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_ALIVE, 0); 2629 send_msg.data[0] = alive ? HCLGEVF_STATE_ALIVE : 2630 HCLGEVF_STATE_NOT_ALIVE; 2631 return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 2632 } 2633 2634 static int hclgevf_client_start(struct hnae3_handle *handle) 2635 { 2636 return hclgevf_set_alive(handle, true); 2637 } 2638 2639 static void hclgevf_client_stop(struct hnae3_handle *handle) 2640 { 2641 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 2642 int ret; 2643 2644 ret = hclgevf_set_alive(handle, false); 2645 if (ret) 2646 dev_warn(&hdev->pdev->dev, 2647 "%s failed %d\n", __func__, ret); 2648 } 2649 2650 static void hclgevf_state_init(struct hclgevf_dev *hdev) 2651 { 2652 clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state); 2653 clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state); 2654 clear_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state); 2655 2656 INIT_DELAYED_WORK(&hdev->service_task, hclgevf_service_task); 2657 2658 mutex_init(&hdev->mbx_resp.mbx_mutex); 2659 sema_init(&hdev->reset_sem, 1); 2660 2661 spin_lock_init(&hdev->mac_table.mac_list_lock); 2662 INIT_LIST_HEAD(&hdev->mac_table.uc_mac_list); 2663 INIT_LIST_HEAD(&hdev->mac_table.mc_mac_list); 2664 2665 /* bring the device down */ 2666 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2667 } 2668 2669 static void hclgevf_state_uninit(struct hclgevf_dev *hdev) 2670 { 2671 set_bit(HCLGEVF_STATE_DOWN, &hdev->state); 2672 set_bit(HCLGEVF_STATE_REMOVING, &hdev->state); 2673 2674 if (hdev->service_task.work.func) 2675 cancel_delayed_work_sync(&hdev->service_task); 2676 2677 mutex_destroy(&hdev->mbx_resp.mbx_mutex); 2678 } 2679 2680 static int hclgevf_init_msi(struct hclgevf_dev *hdev) 2681 { 2682 struct pci_dev *pdev = hdev->pdev; 2683 int vectors; 2684 int i; 2685 2686 if (hnae3_dev_roce_supported(hdev)) 2687 vectors = pci_alloc_irq_vectors(pdev, 2688 hdev->roce_base_msix_offset + 1, 2689 hdev->num_msi, 2690 PCI_IRQ_MSIX); 2691 else 2692 vectors = pci_alloc_irq_vectors(pdev, HNAE3_MIN_VECTOR_NUM, 2693 hdev->num_msi, 2694 PCI_IRQ_MSI | PCI_IRQ_MSIX); 2695 2696 if (vectors < 0) { 2697 dev_err(&pdev->dev, 2698 "failed(%d) to allocate MSI/MSI-X vectors\n", 2699 vectors); 2700 return vectors; 2701 } 2702 if (vectors < hdev->num_msi) 2703 dev_warn(&hdev->pdev->dev, 2704 "requested %u MSI/MSI-X, but allocated %d MSI/MSI-X\n", 2705 hdev->num_msi, vectors); 2706 2707 hdev->num_msi = vectors; 2708 hdev->num_msi_left = vectors; 2709 2710 hdev->base_msi_vector = pdev->irq; 2711 hdev->roce_base_vector = pdev->irq + hdev->roce_base_msix_offset; 2712 2713 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 2714 sizeof(u16), GFP_KERNEL); 2715 if (!hdev->vector_status) { 2716 pci_free_irq_vectors(pdev); 2717 return -ENOMEM; 2718 } 2719 2720 for (i = 0; i < hdev->num_msi; i++) 2721 hdev->vector_status[i] = HCLGEVF_INVALID_VPORT; 2722 2723 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 2724 sizeof(int), GFP_KERNEL); 2725 if (!hdev->vector_irq) { 2726 devm_kfree(&pdev->dev, hdev->vector_status); 2727 pci_free_irq_vectors(pdev); 2728 return -ENOMEM; 2729 } 2730 2731 return 0; 2732 } 2733 2734 static void hclgevf_uninit_msi(struct hclgevf_dev *hdev) 2735 { 2736 struct pci_dev *pdev = hdev->pdev; 2737 2738 devm_kfree(&pdev->dev, hdev->vector_status); 2739 devm_kfree(&pdev->dev, hdev->vector_irq); 2740 pci_free_irq_vectors(pdev); 2741 } 2742 2743 static int hclgevf_misc_irq_init(struct hclgevf_dev *hdev) 2744 { 2745 int ret; 2746 2747 hclgevf_get_misc_vector(hdev); 2748 2749 snprintf(hdev->misc_vector.name, HNAE3_INT_NAME_LEN, "%s-misc-%s", 2750 HCLGEVF_NAME, pci_name(hdev->pdev)); 2751 ret = request_irq(hdev->misc_vector.vector_irq, hclgevf_misc_irq_handle, 2752 0, hdev->misc_vector.name, hdev); 2753 if (ret) { 2754 dev_err(&hdev->pdev->dev, "VF failed to request misc irq(%d)\n", 2755 hdev->misc_vector.vector_irq); 2756 return ret; 2757 } 2758 2759 hclgevf_clear_event_cause(hdev, 0); 2760 2761 /* enable misc. vector(vector 0) */ 2762 hclgevf_enable_vector(&hdev->misc_vector, true); 2763 2764 return ret; 2765 } 2766 2767 static void hclgevf_misc_irq_uninit(struct hclgevf_dev *hdev) 2768 { 2769 /* disable misc vector(vector 0) */ 2770 hclgevf_enable_vector(&hdev->misc_vector, false); 2771 synchronize_irq(hdev->misc_vector.vector_irq); 2772 free_irq(hdev->misc_vector.vector_irq, hdev); 2773 hclgevf_free_vector(hdev, 0); 2774 } 2775 2776 static void hclgevf_info_show(struct hclgevf_dev *hdev) 2777 { 2778 struct device *dev = &hdev->pdev->dev; 2779 2780 dev_info(dev, "VF info begin:\n"); 2781 2782 dev_info(dev, "Task queue pairs numbers: %u\n", hdev->num_tqps); 2783 dev_info(dev, "Desc num per TX queue: %u\n", hdev->num_tx_desc); 2784 dev_info(dev, "Desc num per RX queue: %u\n", hdev->num_rx_desc); 2785 dev_info(dev, "Numbers of vports: %u\n", hdev->num_alloc_vport); 2786 dev_info(dev, "HW tc map: 0x%x\n", hdev->hw_tc_map); 2787 dev_info(dev, "PF media type of this VF: %u\n", 2788 hdev->hw.mac.media_type); 2789 2790 dev_info(dev, "VF info end.\n"); 2791 } 2792 2793 static int hclgevf_init_nic_client_instance(struct hnae3_ae_dev *ae_dev, 2794 struct hnae3_client *client) 2795 { 2796 struct hclgevf_dev *hdev = ae_dev->priv; 2797 int rst_cnt = hdev->rst_stats.rst_cnt; 2798 int ret; 2799 2800 ret = client->ops->init_instance(&hdev->nic); 2801 if (ret) 2802 return ret; 2803 2804 set_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 2805 if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) || 2806 rst_cnt != hdev->rst_stats.rst_cnt) { 2807 clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 2808 2809 client->ops->uninit_instance(&hdev->nic, 0); 2810 return -EBUSY; 2811 } 2812 2813 hnae3_set_client_init_flag(client, ae_dev, 1); 2814 2815 if (netif_msg_drv(&hdev->nic)) 2816 hclgevf_info_show(hdev); 2817 2818 return 0; 2819 } 2820 2821 static int hclgevf_init_roce_client_instance(struct hnae3_ae_dev *ae_dev, 2822 struct hnae3_client *client) 2823 { 2824 struct hclgevf_dev *hdev = ae_dev->priv; 2825 int ret; 2826 2827 if (!hnae3_dev_roce_supported(hdev) || !hdev->roce_client || 2828 !hdev->nic_client) 2829 return 0; 2830 2831 ret = hclgevf_init_roce_base_info(hdev); 2832 if (ret) 2833 return ret; 2834 2835 ret = client->ops->init_instance(&hdev->roce); 2836 if (ret) 2837 return ret; 2838 2839 set_bit(HCLGEVF_STATE_ROCE_REGISTERED, &hdev->state); 2840 hnae3_set_client_init_flag(client, ae_dev, 1); 2841 2842 return 0; 2843 } 2844 2845 static int hclgevf_init_client_instance(struct hnae3_client *client, 2846 struct hnae3_ae_dev *ae_dev) 2847 { 2848 struct hclgevf_dev *hdev = ae_dev->priv; 2849 int ret; 2850 2851 switch (client->type) { 2852 case HNAE3_CLIENT_KNIC: 2853 hdev->nic_client = client; 2854 hdev->nic.client = client; 2855 2856 ret = hclgevf_init_nic_client_instance(ae_dev, client); 2857 if (ret) 2858 goto clear_nic; 2859 2860 ret = hclgevf_init_roce_client_instance(ae_dev, 2861 hdev->roce_client); 2862 if (ret) 2863 goto clear_roce; 2864 2865 break; 2866 case HNAE3_CLIENT_ROCE: 2867 if (hnae3_dev_roce_supported(hdev)) { 2868 hdev->roce_client = client; 2869 hdev->roce.client = client; 2870 } 2871 2872 ret = hclgevf_init_roce_client_instance(ae_dev, client); 2873 if (ret) 2874 goto clear_roce; 2875 2876 break; 2877 default: 2878 return -EINVAL; 2879 } 2880 2881 return 0; 2882 2883 clear_nic: 2884 hdev->nic_client = NULL; 2885 hdev->nic.client = NULL; 2886 return ret; 2887 clear_roce: 2888 hdev->roce_client = NULL; 2889 hdev->roce.client = NULL; 2890 return ret; 2891 } 2892 2893 static void hclgevf_uninit_client_instance(struct hnae3_client *client, 2894 struct hnae3_ae_dev *ae_dev) 2895 { 2896 struct hclgevf_dev *hdev = ae_dev->priv; 2897 2898 /* un-init roce, if it exists */ 2899 if (hdev->roce_client) { 2900 clear_bit(HCLGEVF_STATE_ROCE_REGISTERED, &hdev->state); 2901 hdev->roce_client->ops->uninit_instance(&hdev->roce, 0); 2902 hdev->roce_client = NULL; 2903 hdev->roce.client = NULL; 2904 } 2905 2906 /* un-init nic/unic, if this was not called by roce client */ 2907 if (client->ops->uninit_instance && hdev->nic_client && 2908 client->type != HNAE3_CLIENT_ROCE) { 2909 clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state); 2910 2911 client->ops->uninit_instance(&hdev->nic, 0); 2912 hdev->nic_client = NULL; 2913 hdev->nic.client = NULL; 2914 } 2915 } 2916 2917 static int hclgevf_dev_mem_map(struct hclgevf_dev *hdev) 2918 { 2919 #define HCLGEVF_MEM_BAR 4 2920 2921 struct pci_dev *pdev = hdev->pdev; 2922 struct hclgevf_hw *hw = &hdev->hw; 2923 2924 /* for device does not have device memory, return directly */ 2925 if (!(pci_select_bars(pdev, IORESOURCE_MEM) & BIT(HCLGEVF_MEM_BAR))) 2926 return 0; 2927 2928 hw->mem_base = devm_ioremap_wc(&pdev->dev, 2929 pci_resource_start(pdev, 2930 HCLGEVF_MEM_BAR), 2931 pci_resource_len(pdev, HCLGEVF_MEM_BAR)); 2932 if (!hw->mem_base) { 2933 dev_err(&pdev->dev, "failed to map device memory\n"); 2934 return -EFAULT; 2935 } 2936 2937 return 0; 2938 } 2939 2940 static int hclgevf_pci_init(struct hclgevf_dev *hdev) 2941 { 2942 struct pci_dev *pdev = hdev->pdev; 2943 struct hclgevf_hw *hw; 2944 int ret; 2945 2946 ret = pci_enable_device(pdev); 2947 if (ret) { 2948 dev_err(&pdev->dev, "failed to enable PCI device\n"); 2949 return ret; 2950 } 2951 2952 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 2953 if (ret) { 2954 dev_err(&pdev->dev, "can't set consistent PCI DMA, exiting"); 2955 goto err_disable_device; 2956 } 2957 2958 ret = pci_request_regions(pdev, HCLGEVF_DRIVER_NAME); 2959 if (ret) { 2960 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 2961 goto err_disable_device; 2962 } 2963 2964 pci_set_master(pdev); 2965 hw = &hdev->hw; 2966 hw->hdev = hdev; 2967 hw->io_base = pci_iomap(pdev, 2, 0); 2968 if (!hw->io_base) { 2969 dev_err(&pdev->dev, "can't map configuration register space\n"); 2970 ret = -ENOMEM; 2971 goto err_clr_master; 2972 } 2973 2974 ret = hclgevf_dev_mem_map(hdev); 2975 if (ret) 2976 goto err_unmap_io_base; 2977 2978 return 0; 2979 2980 err_unmap_io_base: 2981 pci_iounmap(pdev, hdev->hw.io_base); 2982 err_clr_master: 2983 pci_clear_master(pdev); 2984 pci_release_regions(pdev); 2985 err_disable_device: 2986 pci_disable_device(pdev); 2987 2988 return ret; 2989 } 2990 2991 static void hclgevf_pci_uninit(struct hclgevf_dev *hdev) 2992 { 2993 struct pci_dev *pdev = hdev->pdev; 2994 2995 if (hdev->hw.mem_base) 2996 devm_iounmap(&pdev->dev, hdev->hw.mem_base); 2997 2998 pci_iounmap(pdev, hdev->hw.io_base); 2999 pci_clear_master(pdev); 3000 pci_release_regions(pdev); 3001 pci_disable_device(pdev); 3002 } 3003 3004 static int hclgevf_query_vf_resource(struct hclgevf_dev *hdev) 3005 { 3006 struct hclgevf_query_res_cmd *req; 3007 struct hclgevf_desc desc; 3008 int ret; 3009 3010 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_VF_RSRC, true); 3011 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1); 3012 if (ret) { 3013 dev_err(&hdev->pdev->dev, 3014 "query vf resource failed, ret = %d.\n", ret); 3015 return ret; 3016 } 3017 3018 req = (struct hclgevf_query_res_cmd *)desc.data; 3019 3020 if (hnae3_dev_roce_supported(hdev)) { 3021 hdev->roce_base_msix_offset = 3022 hnae3_get_field(le16_to_cpu(req->msixcap_localid_ba_rocee), 3023 HCLGEVF_MSIX_OFT_ROCEE_M, 3024 HCLGEVF_MSIX_OFT_ROCEE_S); 3025 hdev->num_roce_msix = 3026 hnae3_get_field(le16_to_cpu(req->vf_intr_vector_number), 3027 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 3028 3029 /* nic's msix numbers is always equals to the roce's. */ 3030 hdev->num_nic_msix = hdev->num_roce_msix; 3031 3032 /* VF should have NIC vectors and Roce vectors, NIC vectors 3033 * are queued before Roce vectors. The offset is fixed to 64. 3034 */ 3035 hdev->num_msi = hdev->num_roce_msix + 3036 hdev->roce_base_msix_offset; 3037 } else { 3038 hdev->num_msi = 3039 hnae3_get_field(le16_to_cpu(req->vf_intr_vector_number), 3040 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S); 3041 3042 hdev->num_nic_msix = hdev->num_msi; 3043 } 3044 3045 if (hdev->num_nic_msix < HNAE3_MIN_VECTOR_NUM) { 3046 dev_err(&hdev->pdev->dev, 3047 "Just %u msi resources, not enough for vf(min:2).\n", 3048 hdev->num_nic_msix); 3049 return -EINVAL; 3050 } 3051 3052 return 0; 3053 } 3054 3055 static void hclgevf_set_default_dev_specs(struct hclgevf_dev *hdev) 3056 { 3057 #define HCLGEVF_MAX_NON_TSO_BD_NUM 8U 3058 3059 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 3060 3061 ae_dev->dev_specs.max_non_tso_bd_num = 3062 HCLGEVF_MAX_NON_TSO_BD_NUM; 3063 ae_dev->dev_specs.rss_ind_tbl_size = HCLGEVF_RSS_IND_TBL_SIZE; 3064 ae_dev->dev_specs.rss_key_size = HCLGEVF_RSS_KEY_SIZE; 3065 ae_dev->dev_specs.max_int_gl = HCLGEVF_DEF_MAX_INT_GL; 3066 ae_dev->dev_specs.max_frm_size = HCLGEVF_MAC_MAX_FRAME; 3067 } 3068 3069 static void hclgevf_parse_dev_specs(struct hclgevf_dev *hdev, 3070 struct hclgevf_desc *desc) 3071 { 3072 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 3073 struct hclgevf_dev_specs_0_cmd *req0; 3074 struct hclgevf_dev_specs_1_cmd *req1; 3075 3076 req0 = (struct hclgevf_dev_specs_0_cmd *)desc[0].data; 3077 req1 = (struct hclgevf_dev_specs_1_cmd *)desc[1].data; 3078 3079 ae_dev->dev_specs.max_non_tso_bd_num = req0->max_non_tso_bd_num; 3080 ae_dev->dev_specs.rss_ind_tbl_size = 3081 le16_to_cpu(req0->rss_ind_tbl_size); 3082 ae_dev->dev_specs.int_ql_max = le16_to_cpu(req0->int_ql_max); 3083 ae_dev->dev_specs.rss_key_size = le16_to_cpu(req0->rss_key_size); 3084 ae_dev->dev_specs.max_int_gl = le16_to_cpu(req1->max_int_gl); 3085 ae_dev->dev_specs.max_frm_size = le16_to_cpu(req1->max_frm_size); 3086 } 3087 3088 static void hclgevf_check_dev_specs(struct hclgevf_dev *hdev) 3089 { 3090 struct hnae3_dev_specs *dev_specs = &hdev->ae_dev->dev_specs; 3091 3092 if (!dev_specs->max_non_tso_bd_num) 3093 dev_specs->max_non_tso_bd_num = HCLGEVF_MAX_NON_TSO_BD_NUM; 3094 if (!dev_specs->rss_ind_tbl_size) 3095 dev_specs->rss_ind_tbl_size = HCLGEVF_RSS_IND_TBL_SIZE; 3096 if (!dev_specs->rss_key_size) 3097 dev_specs->rss_key_size = HCLGEVF_RSS_KEY_SIZE; 3098 if (!dev_specs->max_int_gl) 3099 dev_specs->max_int_gl = HCLGEVF_DEF_MAX_INT_GL; 3100 if (!dev_specs->max_frm_size) 3101 dev_specs->max_frm_size = HCLGEVF_MAC_MAX_FRAME; 3102 } 3103 3104 static int hclgevf_query_dev_specs(struct hclgevf_dev *hdev) 3105 { 3106 struct hclgevf_desc desc[HCLGEVF_QUERY_DEV_SPECS_BD_NUM]; 3107 int ret; 3108 int i; 3109 3110 /* set default specifications as devices lower than version V3 do not 3111 * support querying specifications from firmware. 3112 */ 3113 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3) { 3114 hclgevf_set_default_dev_specs(hdev); 3115 return 0; 3116 } 3117 3118 for (i = 0; i < HCLGEVF_QUERY_DEV_SPECS_BD_NUM - 1; i++) { 3119 hclgevf_cmd_setup_basic_desc(&desc[i], 3120 HCLGEVF_OPC_QUERY_DEV_SPECS, true); 3121 desc[i].flag |= cpu_to_le16(HCLGEVF_CMD_FLAG_NEXT); 3122 } 3123 hclgevf_cmd_setup_basic_desc(&desc[i], HCLGEVF_OPC_QUERY_DEV_SPECS, 3124 true); 3125 3126 ret = hclgevf_cmd_send(&hdev->hw, desc, HCLGEVF_QUERY_DEV_SPECS_BD_NUM); 3127 if (ret) 3128 return ret; 3129 3130 hclgevf_parse_dev_specs(hdev, desc); 3131 hclgevf_check_dev_specs(hdev); 3132 3133 return 0; 3134 } 3135 3136 static int hclgevf_pci_reset(struct hclgevf_dev *hdev) 3137 { 3138 struct pci_dev *pdev = hdev->pdev; 3139 int ret = 0; 3140 3141 if (hdev->reset_type == HNAE3_VF_FULL_RESET && 3142 test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 3143 hclgevf_misc_irq_uninit(hdev); 3144 hclgevf_uninit_msi(hdev); 3145 clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 3146 } 3147 3148 if (!test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 3149 pci_set_master(pdev); 3150 ret = hclgevf_init_msi(hdev); 3151 if (ret) { 3152 dev_err(&pdev->dev, 3153 "failed(%d) to init MSI/MSI-X\n", ret); 3154 return ret; 3155 } 3156 3157 ret = hclgevf_misc_irq_init(hdev); 3158 if (ret) { 3159 hclgevf_uninit_msi(hdev); 3160 dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n", 3161 ret); 3162 return ret; 3163 } 3164 3165 set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 3166 } 3167 3168 return ret; 3169 } 3170 3171 static int hclgevf_clear_vport_list(struct hclgevf_dev *hdev) 3172 { 3173 struct hclge_vf_to_pf_msg send_msg; 3174 3175 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_HANDLE_VF_TBL, 3176 HCLGE_MBX_VPORT_LIST_CLEAR); 3177 return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 3178 } 3179 3180 static int hclgevf_reset_hdev(struct hclgevf_dev *hdev) 3181 { 3182 struct pci_dev *pdev = hdev->pdev; 3183 int ret; 3184 3185 ret = hclgevf_pci_reset(hdev); 3186 if (ret) { 3187 dev_err(&pdev->dev, "pci reset failed %d\n", ret); 3188 return ret; 3189 } 3190 3191 ret = hclgevf_cmd_init(hdev); 3192 if (ret) { 3193 dev_err(&pdev->dev, "cmd failed %d\n", ret); 3194 return ret; 3195 } 3196 3197 ret = hclgevf_rss_init_hw(hdev); 3198 if (ret) { 3199 dev_err(&hdev->pdev->dev, 3200 "failed(%d) to initialize RSS\n", ret); 3201 return ret; 3202 } 3203 3204 ret = hclgevf_config_gro(hdev, true); 3205 if (ret) 3206 return ret; 3207 3208 ret = hclgevf_init_vlan_config(hdev); 3209 if (ret) { 3210 dev_err(&hdev->pdev->dev, 3211 "failed(%d) to initialize VLAN config\n", ret); 3212 return ret; 3213 } 3214 3215 set_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state); 3216 3217 dev_info(&hdev->pdev->dev, "Reset done\n"); 3218 3219 return 0; 3220 } 3221 3222 static int hclgevf_init_hdev(struct hclgevf_dev *hdev) 3223 { 3224 struct pci_dev *pdev = hdev->pdev; 3225 int ret; 3226 3227 ret = hclgevf_pci_init(hdev); 3228 if (ret) 3229 return ret; 3230 3231 ret = hclgevf_cmd_queue_init(hdev); 3232 if (ret) 3233 goto err_cmd_queue_init; 3234 3235 ret = hclgevf_cmd_init(hdev); 3236 if (ret) 3237 goto err_cmd_init; 3238 3239 /* Get vf resource */ 3240 ret = hclgevf_query_vf_resource(hdev); 3241 if (ret) 3242 goto err_cmd_init; 3243 3244 ret = hclgevf_query_dev_specs(hdev); 3245 if (ret) { 3246 dev_err(&pdev->dev, 3247 "failed to query dev specifications, ret = %d\n", ret); 3248 goto err_cmd_init; 3249 } 3250 3251 ret = hclgevf_init_msi(hdev); 3252 if (ret) { 3253 dev_err(&pdev->dev, "failed(%d) to init MSI/MSI-X\n", ret); 3254 goto err_cmd_init; 3255 } 3256 3257 hclgevf_state_init(hdev); 3258 hdev->reset_level = HNAE3_VF_FUNC_RESET; 3259 hdev->reset_type = HNAE3_NONE_RESET; 3260 3261 ret = hclgevf_misc_irq_init(hdev); 3262 if (ret) 3263 goto err_misc_irq_init; 3264 3265 set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 3266 3267 ret = hclgevf_configure(hdev); 3268 if (ret) { 3269 dev_err(&pdev->dev, "failed(%d) to fetch configuration\n", ret); 3270 goto err_config; 3271 } 3272 3273 ret = hclgevf_alloc_tqps(hdev); 3274 if (ret) { 3275 dev_err(&pdev->dev, "failed(%d) to allocate TQPs\n", ret); 3276 goto err_config; 3277 } 3278 3279 ret = hclgevf_set_handle_info(hdev); 3280 if (ret) 3281 goto err_config; 3282 3283 ret = hclgevf_config_gro(hdev, true); 3284 if (ret) 3285 goto err_config; 3286 3287 /* Initialize RSS for this VF */ 3288 ret = hclgevf_rss_init_cfg(hdev); 3289 if (ret) { 3290 dev_err(&pdev->dev, "failed to init rss cfg, ret = %d\n", ret); 3291 goto err_config; 3292 } 3293 3294 ret = hclgevf_rss_init_hw(hdev); 3295 if (ret) { 3296 dev_err(&hdev->pdev->dev, 3297 "failed(%d) to initialize RSS\n", ret); 3298 goto err_config; 3299 } 3300 3301 /* ensure vf tbl list as empty before init*/ 3302 ret = hclgevf_clear_vport_list(hdev); 3303 if (ret) { 3304 dev_err(&pdev->dev, 3305 "failed to clear tbl list configuration, ret = %d.\n", 3306 ret); 3307 goto err_config; 3308 } 3309 3310 ret = hclgevf_init_vlan_config(hdev); 3311 if (ret) { 3312 dev_err(&hdev->pdev->dev, 3313 "failed(%d) to initialize VLAN config\n", ret); 3314 goto err_config; 3315 } 3316 3317 hdev->last_reset_time = jiffies; 3318 dev_info(&hdev->pdev->dev, "finished initializing %s driver\n", 3319 HCLGEVF_DRIVER_NAME); 3320 3321 hclgevf_task_schedule(hdev, round_jiffies_relative(HZ)); 3322 3323 return 0; 3324 3325 err_config: 3326 hclgevf_misc_irq_uninit(hdev); 3327 err_misc_irq_init: 3328 hclgevf_state_uninit(hdev); 3329 hclgevf_uninit_msi(hdev); 3330 err_cmd_init: 3331 hclgevf_cmd_uninit(hdev); 3332 err_cmd_queue_init: 3333 hclgevf_pci_uninit(hdev); 3334 clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); 3335 return ret; 3336 } 3337 3338 static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev) 3339 { 3340 struct hclge_vf_to_pf_msg send_msg; 3341 3342 hclgevf_state_uninit(hdev); 3343 3344 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_VF_UNINIT, 0); 3345 hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 3346 3347 if (test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) { 3348 hclgevf_misc_irq_uninit(hdev); 3349 hclgevf_uninit_msi(hdev); 3350 } 3351 3352 hclgevf_cmd_uninit(hdev); 3353 hclgevf_pci_uninit(hdev); 3354 hclgevf_uninit_mac_list(hdev); 3355 } 3356 3357 static int hclgevf_init_ae_dev(struct hnae3_ae_dev *ae_dev) 3358 { 3359 struct pci_dev *pdev = ae_dev->pdev; 3360 int ret; 3361 3362 ret = hclgevf_alloc_hdev(ae_dev); 3363 if (ret) { 3364 dev_err(&pdev->dev, "hclge device allocation failed\n"); 3365 return ret; 3366 } 3367 3368 ret = hclgevf_init_hdev(ae_dev->priv); 3369 if (ret) { 3370 dev_err(&pdev->dev, "hclge device initialization failed\n"); 3371 return ret; 3372 } 3373 3374 return 0; 3375 } 3376 3377 static void hclgevf_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 3378 { 3379 struct hclgevf_dev *hdev = ae_dev->priv; 3380 3381 hclgevf_uninit_hdev(hdev); 3382 ae_dev->priv = NULL; 3383 } 3384 3385 static u32 hclgevf_get_max_channels(struct hclgevf_dev *hdev) 3386 { 3387 struct hnae3_handle *nic = &hdev->nic; 3388 struct hnae3_knic_private_info *kinfo = &nic->kinfo; 3389 3390 return min_t(u32, hdev->rss_size_max, 3391 hdev->num_tqps / kinfo->tc_info.num_tc); 3392 } 3393 3394 /** 3395 * hclgevf_get_channels - Get the current channels enabled and max supported. 3396 * @handle: hardware information for network interface 3397 * @ch: ethtool channels structure 3398 * 3399 * We don't support separate tx and rx queues as channels. The other count 3400 * represents how many queues are being used for control. max_combined counts 3401 * how many queue pairs we can support. They may not be mapped 1 to 1 with 3402 * q_vectors since we support a lot more queue pairs than q_vectors. 3403 **/ 3404 static void hclgevf_get_channels(struct hnae3_handle *handle, 3405 struct ethtool_channels *ch) 3406 { 3407 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3408 3409 ch->max_combined = hclgevf_get_max_channels(hdev); 3410 ch->other_count = 0; 3411 ch->max_other = 0; 3412 ch->combined_count = handle->kinfo.rss_size; 3413 } 3414 3415 static void hclgevf_get_tqps_and_rss_info(struct hnae3_handle *handle, 3416 u16 *alloc_tqps, u16 *max_rss_size) 3417 { 3418 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3419 3420 *alloc_tqps = hdev->num_tqps; 3421 *max_rss_size = hdev->rss_size_max; 3422 } 3423 3424 static void hclgevf_update_rss_size(struct hnae3_handle *handle, 3425 u32 new_tqps_num) 3426 { 3427 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 3428 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3429 u16 max_rss_size; 3430 3431 kinfo->req_rss_size = new_tqps_num; 3432 3433 max_rss_size = min_t(u16, hdev->rss_size_max, 3434 hdev->num_tqps / kinfo->tc_info.num_tc); 3435 3436 /* Use the user's configuration when it is not larger than 3437 * max_rss_size, otherwise, use the maximum specification value. 3438 */ 3439 if (kinfo->req_rss_size != kinfo->rss_size && kinfo->req_rss_size && 3440 kinfo->req_rss_size <= max_rss_size) 3441 kinfo->rss_size = kinfo->req_rss_size; 3442 else if (kinfo->rss_size > max_rss_size || 3443 (!kinfo->req_rss_size && kinfo->rss_size < max_rss_size)) 3444 kinfo->rss_size = max_rss_size; 3445 3446 kinfo->num_tqps = kinfo->tc_info.num_tc * kinfo->rss_size; 3447 } 3448 3449 static int hclgevf_set_channels(struct hnae3_handle *handle, u32 new_tqps_num, 3450 bool rxfh_configured) 3451 { 3452 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3453 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 3454 u16 cur_rss_size = kinfo->rss_size; 3455 u16 cur_tqps = kinfo->num_tqps; 3456 u32 *rss_indir; 3457 unsigned int i; 3458 int ret; 3459 3460 hclgevf_update_rss_size(handle, new_tqps_num); 3461 3462 ret = hclgevf_set_rss_tc_mode(hdev, kinfo->rss_size); 3463 if (ret) 3464 return ret; 3465 3466 /* RSS indirection table has been configuared by user */ 3467 if (rxfh_configured) 3468 goto out; 3469 3470 /* Reinitializes the rss indirect table according to the new RSS size */ 3471 rss_indir = kcalloc(hdev->ae_dev->dev_specs.rss_ind_tbl_size, 3472 sizeof(u32), GFP_KERNEL); 3473 if (!rss_indir) 3474 return -ENOMEM; 3475 3476 for (i = 0; i < hdev->ae_dev->dev_specs.rss_ind_tbl_size; i++) 3477 rss_indir[i] = i % kinfo->rss_size; 3478 3479 hdev->rss_cfg.rss_size = kinfo->rss_size; 3480 3481 ret = hclgevf_set_rss(handle, rss_indir, NULL, 0); 3482 if (ret) 3483 dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n", 3484 ret); 3485 3486 kfree(rss_indir); 3487 3488 out: 3489 if (!ret) 3490 dev_info(&hdev->pdev->dev, 3491 "Channels changed, rss_size from %u to %u, tqps from %u to %u", 3492 cur_rss_size, kinfo->rss_size, 3493 cur_tqps, kinfo->rss_size * kinfo->tc_info.num_tc); 3494 3495 return ret; 3496 } 3497 3498 static int hclgevf_get_status(struct hnae3_handle *handle) 3499 { 3500 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3501 3502 return hdev->hw.mac.link; 3503 } 3504 3505 static void hclgevf_get_ksettings_an_result(struct hnae3_handle *handle, 3506 u8 *auto_neg, u32 *speed, 3507 u8 *duplex) 3508 { 3509 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3510 3511 if (speed) 3512 *speed = hdev->hw.mac.speed; 3513 if (duplex) 3514 *duplex = hdev->hw.mac.duplex; 3515 if (auto_neg) 3516 *auto_neg = AUTONEG_DISABLE; 3517 } 3518 3519 void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed, 3520 u8 duplex) 3521 { 3522 hdev->hw.mac.speed = speed; 3523 hdev->hw.mac.duplex = duplex; 3524 } 3525 3526 static int hclgevf_gro_en(struct hnae3_handle *handle, bool enable) 3527 { 3528 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3529 3530 return hclgevf_config_gro(hdev, enable); 3531 } 3532 3533 static void hclgevf_get_media_type(struct hnae3_handle *handle, u8 *media_type, 3534 u8 *module_type) 3535 { 3536 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3537 3538 if (media_type) 3539 *media_type = hdev->hw.mac.media_type; 3540 3541 if (module_type) 3542 *module_type = hdev->hw.mac.module_type; 3543 } 3544 3545 static bool hclgevf_get_hw_reset_stat(struct hnae3_handle *handle) 3546 { 3547 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3548 3549 return !!hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); 3550 } 3551 3552 static bool hclgevf_get_cmdq_stat(struct hnae3_handle *handle) 3553 { 3554 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3555 3556 return test_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state); 3557 } 3558 3559 static bool hclgevf_ae_dev_resetting(struct hnae3_handle *handle) 3560 { 3561 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3562 3563 return test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); 3564 } 3565 3566 static unsigned long hclgevf_ae_dev_reset_cnt(struct hnae3_handle *handle) 3567 { 3568 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3569 3570 return hdev->rst_stats.hw_rst_done_cnt; 3571 } 3572 3573 static void hclgevf_get_link_mode(struct hnae3_handle *handle, 3574 unsigned long *supported, 3575 unsigned long *advertising) 3576 { 3577 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3578 3579 *supported = hdev->hw.mac.supported; 3580 *advertising = hdev->hw.mac.advertising; 3581 } 3582 3583 #define MAX_SEPARATE_NUM 4 3584 #define SEPARATOR_VALUE 0xFFFFFFFF 3585 #define REG_NUM_PER_LINE 4 3586 #define REG_LEN_PER_LINE (REG_NUM_PER_LINE * sizeof(u32)) 3587 3588 static int hclgevf_get_regs_len(struct hnae3_handle *handle) 3589 { 3590 int cmdq_lines, common_lines, ring_lines, tqp_intr_lines; 3591 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3592 3593 cmdq_lines = sizeof(cmdq_reg_addr_list) / REG_LEN_PER_LINE + 1; 3594 common_lines = sizeof(common_reg_addr_list) / REG_LEN_PER_LINE + 1; 3595 ring_lines = sizeof(ring_reg_addr_list) / REG_LEN_PER_LINE + 1; 3596 tqp_intr_lines = sizeof(tqp_intr_reg_addr_list) / REG_LEN_PER_LINE + 1; 3597 3598 return (cmdq_lines + common_lines + ring_lines * hdev->num_tqps + 3599 tqp_intr_lines * (hdev->num_msi_used - 1)) * REG_LEN_PER_LINE; 3600 } 3601 3602 static void hclgevf_get_regs(struct hnae3_handle *handle, u32 *version, 3603 void *data) 3604 { 3605 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); 3606 int i, j, reg_um, separator_num; 3607 u32 *reg = data; 3608 3609 *version = hdev->fw_version; 3610 3611 /* fetching per-VF registers values from VF PCIe register space */ 3612 reg_um = sizeof(cmdq_reg_addr_list) / sizeof(u32); 3613 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 3614 for (i = 0; i < reg_um; i++) 3615 *reg++ = hclgevf_read_dev(&hdev->hw, cmdq_reg_addr_list[i]); 3616 for (i = 0; i < separator_num; i++) 3617 *reg++ = SEPARATOR_VALUE; 3618 3619 reg_um = sizeof(common_reg_addr_list) / sizeof(u32); 3620 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 3621 for (i = 0; i < reg_um; i++) 3622 *reg++ = hclgevf_read_dev(&hdev->hw, common_reg_addr_list[i]); 3623 for (i = 0; i < separator_num; i++) 3624 *reg++ = SEPARATOR_VALUE; 3625 3626 reg_um = sizeof(ring_reg_addr_list) / sizeof(u32); 3627 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 3628 for (j = 0; j < hdev->num_tqps; j++) { 3629 for (i = 0; i < reg_um; i++) 3630 *reg++ = hclgevf_read_dev(&hdev->hw, 3631 ring_reg_addr_list[i] + 3632 0x200 * j); 3633 for (i = 0; i < separator_num; i++) 3634 *reg++ = SEPARATOR_VALUE; 3635 } 3636 3637 reg_um = sizeof(tqp_intr_reg_addr_list) / sizeof(u32); 3638 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; 3639 for (j = 0; j < hdev->num_msi_used - 1; j++) { 3640 for (i = 0; i < reg_um; i++) 3641 *reg++ = hclgevf_read_dev(&hdev->hw, 3642 tqp_intr_reg_addr_list[i] + 3643 4 * j); 3644 for (i = 0; i < separator_num; i++) 3645 *reg++ = SEPARATOR_VALUE; 3646 } 3647 } 3648 3649 void hclgevf_update_port_base_vlan_info(struct hclgevf_dev *hdev, u16 state, 3650 u8 *port_base_vlan_info, u8 data_size) 3651 { 3652 struct hnae3_handle *nic = &hdev->nic; 3653 struct hclge_vf_to_pf_msg send_msg; 3654 int ret; 3655 3656 rtnl_lock(); 3657 3658 if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) || 3659 test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) { 3660 dev_warn(&hdev->pdev->dev, 3661 "is resetting when updating port based vlan info\n"); 3662 rtnl_unlock(); 3663 return; 3664 } 3665 3666 ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT); 3667 if (ret) { 3668 rtnl_unlock(); 3669 return; 3670 } 3671 3672 /* send msg to PF and wait update port based vlan info */ 3673 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, 3674 HCLGE_MBX_PORT_BASE_VLAN_CFG); 3675 memcpy(send_msg.data, port_base_vlan_info, data_size); 3676 ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); 3677 if (!ret) { 3678 if (state == HNAE3_PORT_BASE_VLAN_DISABLE) 3679 nic->port_base_vlan_state = state; 3680 else 3681 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_ENABLE; 3682 } 3683 3684 hclgevf_notify_client(hdev, HNAE3_UP_CLIENT); 3685 rtnl_unlock(); 3686 } 3687 3688 static const struct hnae3_ae_ops hclgevf_ops = { 3689 .init_ae_dev = hclgevf_init_ae_dev, 3690 .uninit_ae_dev = hclgevf_uninit_ae_dev, 3691 .flr_prepare = hclgevf_flr_prepare, 3692 .flr_done = hclgevf_flr_done, 3693 .init_client_instance = hclgevf_init_client_instance, 3694 .uninit_client_instance = hclgevf_uninit_client_instance, 3695 .start = hclgevf_ae_start, 3696 .stop = hclgevf_ae_stop, 3697 .client_start = hclgevf_client_start, 3698 .client_stop = hclgevf_client_stop, 3699 .map_ring_to_vector = hclgevf_map_ring_to_vector, 3700 .unmap_ring_from_vector = hclgevf_unmap_ring_from_vector, 3701 .get_vector = hclgevf_get_vector, 3702 .put_vector = hclgevf_put_vector, 3703 .reset_queue = hclgevf_reset_tqp, 3704 .get_mac_addr = hclgevf_get_mac_addr, 3705 .set_mac_addr = hclgevf_set_mac_addr, 3706 .add_uc_addr = hclgevf_add_uc_addr, 3707 .rm_uc_addr = hclgevf_rm_uc_addr, 3708 .add_mc_addr = hclgevf_add_mc_addr, 3709 .rm_mc_addr = hclgevf_rm_mc_addr, 3710 .get_stats = hclgevf_get_stats, 3711 .update_stats = hclgevf_update_stats, 3712 .get_strings = hclgevf_get_strings, 3713 .get_sset_count = hclgevf_get_sset_count, 3714 .get_rss_key_size = hclgevf_get_rss_key_size, 3715 .get_rss = hclgevf_get_rss, 3716 .set_rss = hclgevf_set_rss, 3717 .get_rss_tuple = hclgevf_get_rss_tuple, 3718 .set_rss_tuple = hclgevf_set_rss_tuple, 3719 .get_tc_size = hclgevf_get_tc_size, 3720 .get_fw_version = hclgevf_get_fw_version, 3721 .set_vlan_filter = hclgevf_set_vlan_filter, 3722 .enable_hw_strip_rxvtag = hclgevf_en_hw_strip_rxvtag, 3723 .reset_event = hclgevf_reset_event, 3724 .set_default_reset_request = hclgevf_set_def_reset_request, 3725 .set_channels = hclgevf_set_channels, 3726 .get_channels = hclgevf_get_channels, 3727 .get_tqps_and_rss_info = hclgevf_get_tqps_and_rss_info, 3728 .get_regs_len = hclgevf_get_regs_len, 3729 .get_regs = hclgevf_get_regs, 3730 .get_status = hclgevf_get_status, 3731 .get_ksettings_an_result = hclgevf_get_ksettings_an_result, 3732 .get_media_type = hclgevf_get_media_type, 3733 .get_hw_reset_stat = hclgevf_get_hw_reset_stat, 3734 .ae_dev_resetting = hclgevf_ae_dev_resetting, 3735 .ae_dev_reset_cnt = hclgevf_ae_dev_reset_cnt, 3736 .set_gro_en = hclgevf_gro_en, 3737 .set_mtu = hclgevf_set_mtu, 3738 .get_global_queue_id = hclgevf_get_qid_global, 3739 .set_timer_task = hclgevf_set_timer_task, 3740 .get_link_mode = hclgevf_get_link_mode, 3741 .set_promisc_mode = hclgevf_set_promisc_mode, 3742 .request_update_promisc_mode = hclgevf_request_update_promisc_mode, 3743 .get_cmdq_stat = hclgevf_get_cmdq_stat, 3744 }; 3745 3746 static struct hnae3_ae_algo ae_algovf = { 3747 .ops = &hclgevf_ops, 3748 .pdev_id_table = ae_algovf_pci_tbl, 3749 }; 3750 3751 static int hclgevf_init(void) 3752 { 3753 pr_info("%s is initializing\n", HCLGEVF_NAME); 3754 3755 hclgevf_wq = alloc_workqueue("%s", 0, 0, HCLGEVF_NAME); 3756 if (!hclgevf_wq) { 3757 pr_err("%s: failed to create workqueue\n", HCLGEVF_NAME); 3758 return -ENOMEM; 3759 } 3760 3761 hnae3_register_ae_algo(&ae_algovf); 3762 3763 return 0; 3764 } 3765 3766 static void hclgevf_exit(void) 3767 { 3768 hnae3_unregister_ae_algo(&ae_algovf); 3769 destroy_workqueue(hclgevf_wq); 3770 } 3771 module_init(hclgevf_init); 3772 module_exit(hclgevf_exit); 3773 3774 MODULE_LICENSE("GPL"); 3775 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 3776 MODULE_DESCRIPTION("HCLGEVF Driver"); 3777 MODULE_VERSION(HCLGEVF_MOD_VERSION); 3778