1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright (c) 2016-2017 Hisilicon Limited.
3 
4 #include <linux/etherdevice.h>
5 #include <linux/iopoll.h>
6 #include <net/rtnetlink.h>
7 #include "hclgevf_cmd.h"
8 #include "hclgevf_main.h"
9 #include "hclge_mbx.h"
10 #include "hnae3.h"
11 
12 #define HCLGEVF_NAME	"hclgevf"
13 
14 #define HCLGEVF_RESET_MAX_FAIL_CNT	5
15 
16 static int hclgevf_reset_hdev(struct hclgevf_dev *hdev);
17 static void hclgevf_task_schedule(struct hclgevf_dev *hdev,
18 				  unsigned long delay);
19 
20 static struct hnae3_ae_algo ae_algovf;
21 
22 static struct workqueue_struct *hclgevf_wq;
23 
24 static const struct pci_device_id ae_algovf_pci_tbl[] = {
25 	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_VF), 0},
26 	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF),
27 	 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
28 	/* required last entry */
29 	{0, }
30 };
31 
32 static const u8 hclgevf_hash_key[] = {
33 	0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2,
34 	0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0,
35 	0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4,
36 	0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C,
37 	0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA
38 };
39 
40 MODULE_DEVICE_TABLE(pci, ae_algovf_pci_tbl);
41 
42 static const u32 cmdq_reg_addr_list[] = {HCLGEVF_CMDQ_TX_ADDR_L_REG,
43 					 HCLGEVF_CMDQ_TX_ADDR_H_REG,
44 					 HCLGEVF_CMDQ_TX_DEPTH_REG,
45 					 HCLGEVF_CMDQ_TX_TAIL_REG,
46 					 HCLGEVF_CMDQ_TX_HEAD_REG,
47 					 HCLGEVF_CMDQ_RX_ADDR_L_REG,
48 					 HCLGEVF_CMDQ_RX_ADDR_H_REG,
49 					 HCLGEVF_CMDQ_RX_DEPTH_REG,
50 					 HCLGEVF_CMDQ_RX_TAIL_REG,
51 					 HCLGEVF_CMDQ_RX_HEAD_REG,
52 					 HCLGEVF_VECTOR0_CMDQ_SRC_REG,
53 					 HCLGEVF_VECTOR0_CMDQ_STATE_REG,
54 					 HCLGEVF_CMDQ_INTR_EN_REG,
55 					 HCLGEVF_CMDQ_INTR_GEN_REG};
56 
57 static const u32 common_reg_addr_list[] = {HCLGEVF_MISC_VECTOR_REG_BASE,
58 					   HCLGEVF_RST_ING,
59 					   HCLGEVF_GRO_EN_REG};
60 
61 static const u32 ring_reg_addr_list[] = {HCLGEVF_RING_RX_ADDR_L_REG,
62 					 HCLGEVF_RING_RX_ADDR_H_REG,
63 					 HCLGEVF_RING_RX_BD_NUM_REG,
64 					 HCLGEVF_RING_RX_BD_LENGTH_REG,
65 					 HCLGEVF_RING_RX_MERGE_EN_REG,
66 					 HCLGEVF_RING_RX_TAIL_REG,
67 					 HCLGEVF_RING_RX_HEAD_REG,
68 					 HCLGEVF_RING_RX_FBD_NUM_REG,
69 					 HCLGEVF_RING_RX_OFFSET_REG,
70 					 HCLGEVF_RING_RX_FBD_OFFSET_REG,
71 					 HCLGEVF_RING_RX_STASH_REG,
72 					 HCLGEVF_RING_RX_BD_ERR_REG,
73 					 HCLGEVF_RING_TX_ADDR_L_REG,
74 					 HCLGEVF_RING_TX_ADDR_H_REG,
75 					 HCLGEVF_RING_TX_BD_NUM_REG,
76 					 HCLGEVF_RING_TX_PRIORITY_REG,
77 					 HCLGEVF_RING_TX_TC_REG,
78 					 HCLGEVF_RING_TX_MERGE_EN_REG,
79 					 HCLGEVF_RING_TX_TAIL_REG,
80 					 HCLGEVF_RING_TX_HEAD_REG,
81 					 HCLGEVF_RING_TX_FBD_NUM_REG,
82 					 HCLGEVF_RING_TX_OFFSET_REG,
83 					 HCLGEVF_RING_TX_EBD_NUM_REG,
84 					 HCLGEVF_RING_TX_EBD_OFFSET_REG,
85 					 HCLGEVF_RING_TX_BD_ERR_REG,
86 					 HCLGEVF_RING_EN_REG};
87 
88 static const u32 tqp_intr_reg_addr_list[] = {HCLGEVF_TQP_INTR_CTRL_REG,
89 					     HCLGEVF_TQP_INTR_GL0_REG,
90 					     HCLGEVF_TQP_INTR_GL1_REG,
91 					     HCLGEVF_TQP_INTR_GL2_REG,
92 					     HCLGEVF_TQP_INTR_RL_REG};
93 
94 static struct hclgevf_dev *hclgevf_ae_get_hdev(struct hnae3_handle *handle)
95 {
96 	if (!handle->client)
97 		return container_of(handle, struct hclgevf_dev, nic);
98 	else if (handle->client->type == HNAE3_CLIENT_ROCE)
99 		return container_of(handle, struct hclgevf_dev, roce);
100 	else
101 		return container_of(handle, struct hclgevf_dev, nic);
102 }
103 
104 static int hclgevf_tqps_update_stats(struct hnae3_handle *handle)
105 {
106 	struct hnae3_knic_private_info *kinfo = &handle->kinfo;
107 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
108 	struct hclgevf_desc desc;
109 	struct hclgevf_tqp *tqp;
110 	int status;
111 	int i;
112 
113 	for (i = 0; i < kinfo->num_tqps; i++) {
114 		tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q);
115 		hclgevf_cmd_setup_basic_desc(&desc,
116 					     HCLGEVF_OPC_QUERY_RX_STATUS,
117 					     true);
118 
119 		desc.data[0] = cpu_to_le32(tqp->index & 0x1ff);
120 		status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
121 		if (status) {
122 			dev_err(&hdev->pdev->dev,
123 				"Query tqp stat fail, status = %d,queue = %d\n",
124 				status,	i);
125 			return status;
126 		}
127 		tqp->tqp_stats.rcb_rx_ring_pktnum_rcd +=
128 			le32_to_cpu(desc.data[1]);
129 
130 		hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_TX_STATUS,
131 					     true);
132 
133 		desc.data[0] = cpu_to_le32(tqp->index & 0x1ff);
134 		status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
135 		if (status) {
136 			dev_err(&hdev->pdev->dev,
137 				"Query tqp stat fail, status = %d,queue = %d\n",
138 				status, i);
139 			return status;
140 		}
141 		tqp->tqp_stats.rcb_tx_ring_pktnum_rcd +=
142 			le32_to_cpu(desc.data[1]);
143 	}
144 
145 	return 0;
146 }
147 
148 static u64 *hclgevf_tqps_get_stats(struct hnae3_handle *handle, u64 *data)
149 {
150 	struct hnae3_knic_private_info *kinfo = &handle->kinfo;
151 	struct hclgevf_tqp *tqp;
152 	u64 *buff = data;
153 	int i;
154 
155 	for (i = 0; i < kinfo->num_tqps; i++) {
156 		tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q);
157 		*buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd;
158 	}
159 	for (i = 0; i < kinfo->num_tqps; i++) {
160 		tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q);
161 		*buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd;
162 	}
163 
164 	return buff;
165 }
166 
167 static int hclgevf_tqps_get_sset_count(struct hnae3_handle *handle, int strset)
168 {
169 	struct hnae3_knic_private_info *kinfo = &handle->kinfo;
170 
171 	return kinfo->num_tqps * 2;
172 }
173 
174 static u8 *hclgevf_tqps_get_strings(struct hnae3_handle *handle, u8 *data)
175 {
176 	struct hnae3_knic_private_info *kinfo = &handle->kinfo;
177 	u8 *buff = data;
178 	int i;
179 
180 	for (i = 0; i < kinfo->num_tqps; i++) {
181 		struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i],
182 						       struct hclgevf_tqp, q);
183 		snprintf(buff, ETH_GSTRING_LEN, "txq%u_pktnum_rcd",
184 			 tqp->index);
185 		buff += ETH_GSTRING_LEN;
186 	}
187 
188 	for (i = 0; i < kinfo->num_tqps; i++) {
189 		struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i],
190 						       struct hclgevf_tqp, q);
191 		snprintf(buff, ETH_GSTRING_LEN, "rxq%u_pktnum_rcd",
192 			 tqp->index);
193 		buff += ETH_GSTRING_LEN;
194 	}
195 
196 	return buff;
197 }
198 
199 static void hclgevf_update_stats(struct hnae3_handle *handle,
200 				 struct net_device_stats *net_stats)
201 {
202 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
203 	int status;
204 
205 	status = hclgevf_tqps_update_stats(handle);
206 	if (status)
207 		dev_err(&hdev->pdev->dev,
208 			"VF update of TQPS stats fail, status = %d.\n",
209 			status);
210 }
211 
212 static int hclgevf_get_sset_count(struct hnae3_handle *handle, int strset)
213 {
214 	if (strset == ETH_SS_TEST)
215 		return -EOPNOTSUPP;
216 	else if (strset == ETH_SS_STATS)
217 		return hclgevf_tqps_get_sset_count(handle, strset);
218 
219 	return 0;
220 }
221 
222 static void hclgevf_get_strings(struct hnae3_handle *handle, u32 strset,
223 				u8 *data)
224 {
225 	u8 *p = (char *)data;
226 
227 	if (strset == ETH_SS_STATS)
228 		p = hclgevf_tqps_get_strings(handle, p);
229 }
230 
231 static void hclgevf_get_stats(struct hnae3_handle *handle, u64 *data)
232 {
233 	hclgevf_tqps_get_stats(handle, data);
234 }
235 
236 static void hclgevf_build_send_msg(struct hclge_vf_to_pf_msg *msg, u8 code,
237 				   u8 subcode)
238 {
239 	if (msg) {
240 		memset(msg, 0, sizeof(struct hclge_vf_to_pf_msg));
241 		msg->code = code;
242 		msg->subcode = subcode;
243 	}
244 }
245 
246 static int hclgevf_get_basic_info(struct hclgevf_dev *hdev)
247 {
248 	struct hnae3_ae_dev *ae_dev = hdev->ae_dev;
249 	u8 resp_msg[HCLGE_MBX_MAX_RESP_DATA_SIZE];
250 	struct hclge_basic_info *basic_info;
251 	struct hclge_vf_to_pf_msg send_msg;
252 	unsigned long caps;
253 	int status;
254 
255 	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_BASIC_INFO, 0);
256 	status = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg,
257 				      sizeof(resp_msg));
258 	if (status) {
259 		dev_err(&hdev->pdev->dev,
260 			"failed to get basic info from pf, ret = %d", status);
261 		return status;
262 	}
263 
264 	basic_info = (struct hclge_basic_info *)resp_msg;
265 
266 	hdev->hw_tc_map = basic_info->hw_tc_map;
267 	hdev->mbx_api_version = basic_info->mbx_api_version;
268 	caps = basic_info->pf_caps;
269 	if (test_bit(HNAE3_PF_SUPPORT_VLAN_FLTR_MDF_B, &caps))
270 		set_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps);
271 
272 	return 0;
273 }
274 
275 static int hclgevf_get_port_base_vlan_filter_state(struct hclgevf_dev *hdev)
276 {
277 	struct hnae3_handle *nic = &hdev->nic;
278 	struct hclge_vf_to_pf_msg send_msg;
279 	u8 resp_msg;
280 	int ret;
281 
282 	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN,
283 			       HCLGE_MBX_GET_PORT_BASE_VLAN_STATE);
284 	ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, &resp_msg,
285 				   sizeof(u8));
286 	if (ret) {
287 		dev_err(&hdev->pdev->dev,
288 			"VF request to get port based vlan state failed %d",
289 			ret);
290 		return ret;
291 	}
292 
293 	nic->port_base_vlan_state = resp_msg;
294 
295 	return 0;
296 }
297 
298 static int hclgevf_get_queue_info(struct hclgevf_dev *hdev)
299 {
300 #define HCLGEVF_TQPS_RSS_INFO_LEN	6
301 #define HCLGEVF_TQPS_ALLOC_OFFSET	0
302 #define HCLGEVF_TQPS_RSS_SIZE_OFFSET	2
303 #define HCLGEVF_TQPS_RX_BUFFER_LEN_OFFSET	4
304 
305 	u8 resp_msg[HCLGEVF_TQPS_RSS_INFO_LEN];
306 	struct hclge_vf_to_pf_msg send_msg;
307 	int status;
308 
309 	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QINFO, 0);
310 	status = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg,
311 				      HCLGEVF_TQPS_RSS_INFO_LEN);
312 	if (status) {
313 		dev_err(&hdev->pdev->dev,
314 			"VF request to get tqp info from PF failed %d",
315 			status);
316 		return status;
317 	}
318 
319 	memcpy(&hdev->num_tqps, &resp_msg[HCLGEVF_TQPS_ALLOC_OFFSET],
320 	       sizeof(u16));
321 	memcpy(&hdev->rss_size_max, &resp_msg[HCLGEVF_TQPS_RSS_SIZE_OFFSET],
322 	       sizeof(u16));
323 	memcpy(&hdev->rx_buf_len, &resp_msg[HCLGEVF_TQPS_RX_BUFFER_LEN_OFFSET],
324 	       sizeof(u16));
325 
326 	return 0;
327 }
328 
329 static int hclgevf_get_queue_depth(struct hclgevf_dev *hdev)
330 {
331 #define HCLGEVF_TQPS_DEPTH_INFO_LEN	4
332 #define HCLGEVF_TQPS_NUM_TX_DESC_OFFSET	0
333 #define HCLGEVF_TQPS_NUM_RX_DESC_OFFSET	2
334 
335 	u8 resp_msg[HCLGEVF_TQPS_DEPTH_INFO_LEN];
336 	struct hclge_vf_to_pf_msg send_msg;
337 	int ret;
338 
339 	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QDEPTH, 0);
340 	ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg,
341 				   HCLGEVF_TQPS_DEPTH_INFO_LEN);
342 	if (ret) {
343 		dev_err(&hdev->pdev->dev,
344 			"VF request to get tqp depth info from PF failed %d",
345 			ret);
346 		return ret;
347 	}
348 
349 	memcpy(&hdev->num_tx_desc, &resp_msg[HCLGEVF_TQPS_NUM_TX_DESC_OFFSET],
350 	       sizeof(u16));
351 	memcpy(&hdev->num_rx_desc, &resp_msg[HCLGEVF_TQPS_NUM_RX_DESC_OFFSET],
352 	       sizeof(u16));
353 
354 	return 0;
355 }
356 
357 static u16 hclgevf_get_qid_global(struct hnae3_handle *handle, u16 queue_id)
358 {
359 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
360 	struct hclge_vf_to_pf_msg send_msg;
361 	u16 qid_in_pf = 0;
362 	u8 resp_data[2];
363 	int ret;
364 
365 	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QID_IN_PF, 0);
366 	memcpy(send_msg.data, &queue_id, sizeof(queue_id));
367 	ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_data,
368 				   sizeof(resp_data));
369 	if (!ret)
370 		qid_in_pf = *(u16 *)resp_data;
371 
372 	return qid_in_pf;
373 }
374 
375 static int hclgevf_get_pf_media_type(struct hclgevf_dev *hdev)
376 {
377 	struct hclge_vf_to_pf_msg send_msg;
378 	u8 resp_msg[2];
379 	int ret;
380 
381 	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_MEDIA_TYPE, 0);
382 	ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg,
383 				   sizeof(resp_msg));
384 	if (ret) {
385 		dev_err(&hdev->pdev->dev,
386 			"VF request to get the pf port media type failed %d",
387 			ret);
388 		return ret;
389 	}
390 
391 	hdev->hw.mac.media_type = resp_msg[0];
392 	hdev->hw.mac.module_type = resp_msg[1];
393 
394 	return 0;
395 }
396 
397 static int hclgevf_alloc_tqps(struct hclgevf_dev *hdev)
398 {
399 	struct hclgevf_tqp *tqp;
400 	int i;
401 
402 	hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps,
403 				  sizeof(struct hclgevf_tqp), GFP_KERNEL);
404 	if (!hdev->htqp)
405 		return -ENOMEM;
406 
407 	tqp = hdev->htqp;
408 
409 	for (i = 0; i < hdev->num_tqps; i++) {
410 		tqp->dev = &hdev->pdev->dev;
411 		tqp->index = i;
412 
413 		tqp->q.ae_algo = &ae_algovf;
414 		tqp->q.buf_size = hdev->rx_buf_len;
415 		tqp->q.tx_desc_num = hdev->num_tx_desc;
416 		tqp->q.rx_desc_num = hdev->num_rx_desc;
417 
418 		/* need an extended offset to configure queues >=
419 		 * HCLGEVF_TQP_MAX_SIZE_DEV_V2.
420 		 */
421 		if (i < HCLGEVF_TQP_MAX_SIZE_DEV_V2)
422 			tqp->q.io_base = hdev->hw.io_base +
423 					 HCLGEVF_TQP_REG_OFFSET +
424 					 i * HCLGEVF_TQP_REG_SIZE;
425 		else
426 			tqp->q.io_base = hdev->hw.io_base +
427 					 HCLGEVF_TQP_REG_OFFSET +
428 					 HCLGEVF_TQP_EXT_REG_OFFSET +
429 					 (i - HCLGEVF_TQP_MAX_SIZE_DEV_V2) *
430 					 HCLGEVF_TQP_REG_SIZE;
431 
432 		tqp++;
433 	}
434 
435 	return 0;
436 }
437 
438 static int hclgevf_knic_setup(struct hclgevf_dev *hdev)
439 {
440 	struct hnae3_handle *nic = &hdev->nic;
441 	struct hnae3_knic_private_info *kinfo;
442 	u16 new_tqps = hdev->num_tqps;
443 	unsigned int i;
444 	u8 num_tc = 0;
445 
446 	kinfo = &nic->kinfo;
447 	kinfo->num_tx_desc = hdev->num_tx_desc;
448 	kinfo->num_rx_desc = hdev->num_rx_desc;
449 	kinfo->rx_buf_len = hdev->rx_buf_len;
450 	for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++)
451 		if (hdev->hw_tc_map & BIT(i))
452 			num_tc++;
453 
454 	num_tc = num_tc ? num_tc : 1;
455 	kinfo->tc_info.num_tc = num_tc;
456 	kinfo->rss_size = min_t(u16, hdev->rss_size_max, new_tqps / num_tc);
457 	new_tqps = kinfo->rss_size * num_tc;
458 	kinfo->num_tqps = min(new_tqps, hdev->num_tqps);
459 
460 	kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps,
461 				  sizeof(struct hnae3_queue *), GFP_KERNEL);
462 	if (!kinfo->tqp)
463 		return -ENOMEM;
464 
465 	for (i = 0; i < kinfo->num_tqps; i++) {
466 		hdev->htqp[i].q.handle = &hdev->nic;
467 		hdev->htqp[i].q.tqp_index = i;
468 		kinfo->tqp[i] = &hdev->htqp[i].q;
469 	}
470 
471 	/* after init the max rss_size and tqps, adjust the default tqp numbers
472 	 * and rss size with the actual vector numbers
473 	 */
474 	kinfo->num_tqps = min_t(u16, hdev->num_nic_msix - 1, kinfo->num_tqps);
475 	kinfo->rss_size = min_t(u16, kinfo->num_tqps / num_tc,
476 				kinfo->rss_size);
477 
478 	return 0;
479 }
480 
481 static void hclgevf_request_link_info(struct hclgevf_dev *hdev)
482 {
483 	struct hclge_vf_to_pf_msg send_msg;
484 	int status;
485 
486 	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_LINK_STATUS, 0);
487 	status = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
488 	if (status)
489 		dev_err(&hdev->pdev->dev,
490 			"VF failed to fetch link status(%d) from PF", status);
491 }
492 
493 void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state)
494 {
495 	struct hnae3_handle *rhandle = &hdev->roce;
496 	struct hnae3_handle *handle = &hdev->nic;
497 	struct hnae3_client *rclient;
498 	struct hnae3_client *client;
499 
500 	if (test_and_set_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state))
501 		return;
502 
503 	client = handle->client;
504 	rclient = hdev->roce_client;
505 
506 	link_state =
507 		test_bit(HCLGEVF_STATE_DOWN, &hdev->state) ? 0 : link_state;
508 	if (link_state != hdev->hw.mac.link) {
509 		client->ops->link_status_change(handle, !!link_state);
510 		if (rclient && rclient->ops->link_status_change)
511 			rclient->ops->link_status_change(rhandle, !!link_state);
512 		hdev->hw.mac.link = link_state;
513 	}
514 
515 	clear_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state);
516 }
517 
518 static void hclgevf_update_link_mode(struct hclgevf_dev *hdev)
519 {
520 #define HCLGEVF_ADVERTISING	0
521 #define HCLGEVF_SUPPORTED	1
522 
523 	struct hclge_vf_to_pf_msg send_msg;
524 
525 	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_LINK_MODE, 0);
526 	send_msg.data[0] = HCLGEVF_ADVERTISING;
527 	hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
528 	send_msg.data[0] = HCLGEVF_SUPPORTED;
529 	hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
530 }
531 
532 static int hclgevf_set_handle_info(struct hclgevf_dev *hdev)
533 {
534 	struct hnae3_handle *nic = &hdev->nic;
535 	int ret;
536 
537 	nic->ae_algo = &ae_algovf;
538 	nic->pdev = hdev->pdev;
539 	nic->numa_node_mask = hdev->numa_node_mask;
540 	nic->flags |= HNAE3_SUPPORT_VF;
541 
542 	ret = hclgevf_knic_setup(hdev);
543 	if (ret)
544 		dev_err(&hdev->pdev->dev, "VF knic setup failed %d\n",
545 			ret);
546 	return ret;
547 }
548 
549 static void hclgevf_free_vector(struct hclgevf_dev *hdev, int vector_id)
550 {
551 	if (hdev->vector_status[vector_id] == HCLGEVF_INVALID_VPORT) {
552 		dev_warn(&hdev->pdev->dev,
553 			 "vector(vector_id %d) has been freed.\n", vector_id);
554 		return;
555 	}
556 
557 	hdev->vector_status[vector_id] = HCLGEVF_INVALID_VPORT;
558 	hdev->num_msi_left += 1;
559 	hdev->num_msi_used -= 1;
560 }
561 
562 static int hclgevf_get_vector(struct hnae3_handle *handle, u16 vector_num,
563 			      struct hnae3_vector_info *vector_info)
564 {
565 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
566 	struct hnae3_vector_info *vector = vector_info;
567 	int alloc = 0;
568 	int i, j;
569 
570 	vector_num = min_t(u16, hdev->num_nic_msix - 1, vector_num);
571 	vector_num = min(hdev->num_msi_left, vector_num);
572 
573 	for (j = 0; j < vector_num; j++) {
574 		for (i = HCLGEVF_MISC_VECTOR_NUM + 1; i < hdev->num_msi; i++) {
575 			if (hdev->vector_status[i] == HCLGEVF_INVALID_VPORT) {
576 				vector->vector = pci_irq_vector(hdev->pdev, i);
577 				vector->io_addr = hdev->hw.io_base +
578 					HCLGEVF_VECTOR_REG_BASE +
579 					(i - 1) * HCLGEVF_VECTOR_REG_OFFSET;
580 				hdev->vector_status[i] = 0;
581 				hdev->vector_irq[i] = vector->vector;
582 
583 				vector++;
584 				alloc++;
585 
586 				break;
587 			}
588 		}
589 	}
590 	hdev->num_msi_left -= alloc;
591 	hdev->num_msi_used += alloc;
592 
593 	return alloc;
594 }
595 
596 static int hclgevf_get_vector_index(struct hclgevf_dev *hdev, int vector)
597 {
598 	int i;
599 
600 	for (i = 0; i < hdev->num_msi; i++)
601 		if (vector == hdev->vector_irq[i])
602 			return i;
603 
604 	return -EINVAL;
605 }
606 
607 static int hclgevf_set_rss_algo_key(struct hclgevf_dev *hdev,
608 				    const u8 hfunc, const u8 *key)
609 {
610 	struct hclgevf_rss_config_cmd *req;
611 	unsigned int key_offset = 0;
612 	struct hclgevf_desc desc;
613 	int key_counts;
614 	int key_size;
615 	int ret;
616 
617 	key_counts = HCLGEVF_RSS_KEY_SIZE;
618 	req = (struct hclgevf_rss_config_cmd *)desc.data;
619 
620 	while (key_counts) {
621 		hclgevf_cmd_setup_basic_desc(&desc,
622 					     HCLGEVF_OPC_RSS_GENERIC_CONFIG,
623 					     false);
624 
625 		req->hash_config |= (hfunc & HCLGEVF_RSS_HASH_ALGO_MASK);
626 		req->hash_config |=
627 			(key_offset << HCLGEVF_RSS_HASH_KEY_OFFSET_B);
628 
629 		key_size = min(HCLGEVF_RSS_HASH_KEY_NUM, key_counts);
630 		memcpy(req->hash_key,
631 		       key + key_offset * HCLGEVF_RSS_HASH_KEY_NUM, key_size);
632 
633 		key_counts -= key_size;
634 		key_offset++;
635 		ret = hclgevf_cmd_send(&hdev->hw, &desc, 1);
636 		if (ret) {
637 			dev_err(&hdev->pdev->dev,
638 				"Configure RSS config fail, status = %d\n",
639 				ret);
640 			return ret;
641 		}
642 	}
643 
644 	return 0;
645 }
646 
647 static u32 hclgevf_get_rss_key_size(struct hnae3_handle *handle)
648 {
649 	return HCLGEVF_RSS_KEY_SIZE;
650 }
651 
652 static int hclgevf_set_rss_indir_table(struct hclgevf_dev *hdev)
653 {
654 	const u8 *indir = hdev->rss_cfg.rss_indirection_tbl;
655 	struct hclgevf_rss_indirection_table_cmd *req;
656 	struct hclgevf_desc desc;
657 	int rss_cfg_tbl_num;
658 	int status;
659 	int i, j;
660 
661 	req = (struct hclgevf_rss_indirection_table_cmd *)desc.data;
662 	rss_cfg_tbl_num = hdev->ae_dev->dev_specs.rss_ind_tbl_size /
663 			  HCLGEVF_RSS_CFG_TBL_SIZE;
664 
665 	for (i = 0; i < rss_cfg_tbl_num; i++) {
666 		hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INDIR_TABLE,
667 					     false);
668 		req->start_table_index =
669 			cpu_to_le16(i * HCLGEVF_RSS_CFG_TBL_SIZE);
670 		req->rss_set_bitmap = cpu_to_le16(HCLGEVF_RSS_SET_BITMAP_MSK);
671 		for (j = 0; j < HCLGEVF_RSS_CFG_TBL_SIZE; j++)
672 			req->rss_result[j] =
673 				indir[i * HCLGEVF_RSS_CFG_TBL_SIZE + j];
674 
675 		status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
676 		if (status) {
677 			dev_err(&hdev->pdev->dev,
678 				"VF failed(=%d) to set RSS indirection table\n",
679 				status);
680 			return status;
681 		}
682 	}
683 
684 	return 0;
685 }
686 
687 static int hclgevf_set_rss_tc_mode(struct hclgevf_dev *hdev,  u16 rss_size)
688 {
689 	struct hclgevf_rss_tc_mode_cmd *req;
690 	u16 tc_offset[HCLGEVF_MAX_TC_NUM];
691 	u16 tc_valid[HCLGEVF_MAX_TC_NUM];
692 	u16 tc_size[HCLGEVF_MAX_TC_NUM];
693 	struct hclgevf_desc desc;
694 	u16 roundup_size;
695 	unsigned int i;
696 	int status;
697 
698 	req = (struct hclgevf_rss_tc_mode_cmd *)desc.data;
699 
700 	roundup_size = roundup_pow_of_two(rss_size);
701 	roundup_size = ilog2(roundup_size);
702 
703 	for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) {
704 		tc_valid[i] = !!(hdev->hw_tc_map & BIT(i));
705 		tc_size[i] = roundup_size;
706 		tc_offset[i] = rss_size * i;
707 	}
708 
709 	hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_TC_MODE, false);
710 	for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) {
711 		u16 mode = 0;
712 
713 		hnae3_set_bit(mode, HCLGEVF_RSS_TC_VALID_B,
714 			      (tc_valid[i] & 0x1));
715 		hnae3_set_field(mode, HCLGEVF_RSS_TC_SIZE_M,
716 				HCLGEVF_RSS_TC_SIZE_S, tc_size[i]);
717 		hnae3_set_bit(mode, HCLGEVF_RSS_TC_SIZE_MSB_B,
718 			      tc_size[i] >> HCLGEVF_RSS_TC_SIZE_MSB_OFFSET &
719 			      0x1);
720 		hnae3_set_field(mode, HCLGEVF_RSS_TC_OFFSET_M,
721 				HCLGEVF_RSS_TC_OFFSET_S, tc_offset[i]);
722 
723 		req->rss_tc_mode[i] = cpu_to_le16(mode);
724 	}
725 	status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
726 	if (status)
727 		dev_err(&hdev->pdev->dev,
728 			"VF failed(=%d) to set rss tc mode\n", status);
729 
730 	return status;
731 }
732 
733 /* for revision 0x20, vf shared the same rss config with pf */
734 static int hclgevf_get_rss_hash_key(struct hclgevf_dev *hdev)
735 {
736 #define HCLGEVF_RSS_MBX_RESP_LEN	8
737 	struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
738 	u8 resp_msg[HCLGEVF_RSS_MBX_RESP_LEN];
739 	struct hclge_vf_to_pf_msg send_msg;
740 	u16 msg_num, hash_key_index;
741 	u8 index;
742 	int ret;
743 
744 	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_RSS_KEY, 0);
745 	msg_num = (HCLGEVF_RSS_KEY_SIZE + HCLGEVF_RSS_MBX_RESP_LEN - 1) /
746 			HCLGEVF_RSS_MBX_RESP_LEN;
747 	for (index = 0; index < msg_num; index++) {
748 		send_msg.data[0] = index;
749 		ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg,
750 					   HCLGEVF_RSS_MBX_RESP_LEN);
751 		if (ret) {
752 			dev_err(&hdev->pdev->dev,
753 				"VF get rss hash key from PF failed, ret=%d",
754 				ret);
755 			return ret;
756 		}
757 
758 		hash_key_index = HCLGEVF_RSS_MBX_RESP_LEN * index;
759 		if (index == msg_num - 1)
760 			memcpy(&rss_cfg->rss_hash_key[hash_key_index],
761 			       &resp_msg[0],
762 			       HCLGEVF_RSS_KEY_SIZE - hash_key_index);
763 		else
764 			memcpy(&rss_cfg->rss_hash_key[hash_key_index],
765 			       &resp_msg[0], HCLGEVF_RSS_MBX_RESP_LEN);
766 	}
767 
768 	return 0;
769 }
770 
771 static int hclgevf_get_rss(struct hnae3_handle *handle, u32 *indir, u8 *key,
772 			   u8 *hfunc)
773 {
774 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
775 	struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
776 	int i, ret;
777 
778 	if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) {
779 		/* Get hash algorithm */
780 		if (hfunc) {
781 			switch (rss_cfg->hash_algo) {
782 			case HCLGEVF_RSS_HASH_ALGO_TOEPLITZ:
783 				*hfunc = ETH_RSS_HASH_TOP;
784 				break;
785 			case HCLGEVF_RSS_HASH_ALGO_SIMPLE:
786 				*hfunc = ETH_RSS_HASH_XOR;
787 				break;
788 			default:
789 				*hfunc = ETH_RSS_HASH_UNKNOWN;
790 				break;
791 			}
792 		}
793 
794 		/* Get the RSS Key required by the user */
795 		if (key)
796 			memcpy(key, rss_cfg->rss_hash_key,
797 			       HCLGEVF_RSS_KEY_SIZE);
798 	} else {
799 		if (hfunc)
800 			*hfunc = ETH_RSS_HASH_TOP;
801 		if (key) {
802 			ret = hclgevf_get_rss_hash_key(hdev);
803 			if (ret)
804 				return ret;
805 			memcpy(key, rss_cfg->rss_hash_key,
806 			       HCLGEVF_RSS_KEY_SIZE);
807 		}
808 	}
809 
810 	if (indir)
811 		for (i = 0; i < hdev->ae_dev->dev_specs.rss_ind_tbl_size; i++)
812 			indir[i] = rss_cfg->rss_indirection_tbl[i];
813 
814 	return 0;
815 }
816 
817 static int hclgevf_set_rss(struct hnae3_handle *handle, const u32 *indir,
818 			   const u8 *key, const u8 hfunc)
819 {
820 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
821 	struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
822 	int ret, i;
823 
824 	if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) {
825 		/* Set the RSS Hash Key if specififed by the user */
826 		if (key) {
827 			switch (hfunc) {
828 			case ETH_RSS_HASH_TOP:
829 				rss_cfg->hash_algo =
830 					HCLGEVF_RSS_HASH_ALGO_TOEPLITZ;
831 				break;
832 			case ETH_RSS_HASH_XOR:
833 				rss_cfg->hash_algo =
834 					HCLGEVF_RSS_HASH_ALGO_SIMPLE;
835 				break;
836 			case ETH_RSS_HASH_NO_CHANGE:
837 				break;
838 			default:
839 				return -EINVAL;
840 			}
841 
842 			ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo,
843 						       key);
844 			if (ret)
845 				return ret;
846 
847 			/* Update the shadow RSS key with user specified qids */
848 			memcpy(rss_cfg->rss_hash_key, key,
849 			       HCLGEVF_RSS_KEY_SIZE);
850 		}
851 	}
852 
853 	/* update the shadow RSS table with user specified qids */
854 	for (i = 0; i < hdev->ae_dev->dev_specs.rss_ind_tbl_size; i++)
855 		rss_cfg->rss_indirection_tbl[i] = indir[i];
856 
857 	/* update the hardware */
858 	return hclgevf_set_rss_indir_table(hdev);
859 }
860 
861 static u8 hclgevf_get_rss_hash_bits(struct ethtool_rxnfc *nfc)
862 {
863 	u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGEVF_S_PORT_BIT : 0;
864 
865 	if (nfc->data & RXH_L4_B_2_3)
866 		hash_sets |= HCLGEVF_D_PORT_BIT;
867 	else
868 		hash_sets &= ~HCLGEVF_D_PORT_BIT;
869 
870 	if (nfc->data & RXH_IP_SRC)
871 		hash_sets |= HCLGEVF_S_IP_BIT;
872 	else
873 		hash_sets &= ~HCLGEVF_S_IP_BIT;
874 
875 	if (nfc->data & RXH_IP_DST)
876 		hash_sets |= HCLGEVF_D_IP_BIT;
877 	else
878 		hash_sets &= ~HCLGEVF_D_IP_BIT;
879 
880 	if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW)
881 		hash_sets |= HCLGEVF_V_TAG_BIT;
882 
883 	return hash_sets;
884 }
885 
886 static int hclgevf_init_rss_tuple_cmd(struct hnae3_handle *handle,
887 				      struct ethtool_rxnfc *nfc,
888 				      struct hclgevf_rss_input_tuple_cmd *req)
889 {
890 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
891 	struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
892 	u8 tuple_sets;
893 
894 	req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en;
895 	req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en;
896 	req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en;
897 	req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en;
898 	req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en;
899 	req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en;
900 	req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en;
901 	req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en;
902 
903 	tuple_sets = hclgevf_get_rss_hash_bits(nfc);
904 	switch (nfc->flow_type) {
905 	case TCP_V4_FLOW:
906 		req->ipv4_tcp_en = tuple_sets;
907 		break;
908 	case TCP_V6_FLOW:
909 		req->ipv6_tcp_en = tuple_sets;
910 		break;
911 	case UDP_V4_FLOW:
912 		req->ipv4_udp_en = tuple_sets;
913 		break;
914 	case UDP_V6_FLOW:
915 		req->ipv6_udp_en = tuple_sets;
916 		break;
917 	case SCTP_V4_FLOW:
918 		req->ipv4_sctp_en = tuple_sets;
919 		break;
920 	case SCTP_V6_FLOW:
921 		if (hdev->ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2 &&
922 		    (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)))
923 			return -EINVAL;
924 
925 		req->ipv6_sctp_en = tuple_sets;
926 		break;
927 	case IPV4_FLOW:
928 		req->ipv4_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER;
929 		break;
930 	case IPV6_FLOW:
931 		req->ipv6_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER;
932 		break;
933 	default:
934 		return -EINVAL;
935 	}
936 
937 	return 0;
938 }
939 
940 static int hclgevf_set_rss_tuple(struct hnae3_handle *handle,
941 				 struct ethtool_rxnfc *nfc)
942 {
943 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
944 	struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
945 	struct hclgevf_rss_input_tuple_cmd *req;
946 	struct hclgevf_desc desc;
947 	int ret;
948 
949 	if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)
950 		return -EOPNOTSUPP;
951 
952 	if (nfc->data &
953 	    ~(RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3))
954 		return -EINVAL;
955 
956 	req = (struct hclgevf_rss_input_tuple_cmd *)desc.data;
957 	hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false);
958 
959 	ret = hclgevf_init_rss_tuple_cmd(handle, nfc, req);
960 	if (ret) {
961 		dev_err(&hdev->pdev->dev,
962 			"failed to init rss tuple cmd, ret = %d\n", ret);
963 		return ret;
964 	}
965 
966 	ret = hclgevf_cmd_send(&hdev->hw, &desc, 1);
967 	if (ret) {
968 		dev_err(&hdev->pdev->dev,
969 			"Set rss tuple fail, status = %d\n", ret);
970 		return ret;
971 	}
972 
973 	rss_cfg->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en;
974 	rss_cfg->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en;
975 	rss_cfg->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en;
976 	rss_cfg->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en;
977 	rss_cfg->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en;
978 	rss_cfg->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en;
979 	rss_cfg->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en;
980 	rss_cfg->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en;
981 	return 0;
982 }
983 
984 static int hclgevf_get_rss_tuple_by_flow_type(struct hclgevf_dev *hdev,
985 					      int flow_type, u8 *tuple_sets)
986 {
987 	switch (flow_type) {
988 	case TCP_V4_FLOW:
989 		*tuple_sets = hdev->rss_cfg.rss_tuple_sets.ipv4_tcp_en;
990 		break;
991 	case UDP_V4_FLOW:
992 		*tuple_sets = hdev->rss_cfg.rss_tuple_sets.ipv4_udp_en;
993 		break;
994 	case TCP_V6_FLOW:
995 		*tuple_sets = hdev->rss_cfg.rss_tuple_sets.ipv6_tcp_en;
996 		break;
997 	case UDP_V6_FLOW:
998 		*tuple_sets = hdev->rss_cfg.rss_tuple_sets.ipv6_udp_en;
999 		break;
1000 	case SCTP_V4_FLOW:
1001 		*tuple_sets = hdev->rss_cfg.rss_tuple_sets.ipv4_sctp_en;
1002 		break;
1003 	case SCTP_V6_FLOW:
1004 		*tuple_sets = hdev->rss_cfg.rss_tuple_sets.ipv6_sctp_en;
1005 		break;
1006 	case IPV4_FLOW:
1007 	case IPV6_FLOW:
1008 		*tuple_sets = HCLGEVF_S_IP_BIT | HCLGEVF_D_IP_BIT;
1009 		break;
1010 	default:
1011 		return -EINVAL;
1012 	}
1013 
1014 	return 0;
1015 }
1016 
1017 static u64 hclgevf_convert_rss_tuple(u8 tuple_sets)
1018 {
1019 	u64 tuple_data = 0;
1020 
1021 	if (tuple_sets & HCLGEVF_D_PORT_BIT)
1022 		tuple_data |= RXH_L4_B_2_3;
1023 	if (tuple_sets & HCLGEVF_S_PORT_BIT)
1024 		tuple_data |= RXH_L4_B_0_1;
1025 	if (tuple_sets & HCLGEVF_D_IP_BIT)
1026 		tuple_data |= RXH_IP_DST;
1027 	if (tuple_sets & HCLGEVF_S_IP_BIT)
1028 		tuple_data |= RXH_IP_SRC;
1029 
1030 	return tuple_data;
1031 }
1032 
1033 static int hclgevf_get_rss_tuple(struct hnae3_handle *handle,
1034 				 struct ethtool_rxnfc *nfc)
1035 {
1036 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1037 	u8 tuple_sets;
1038 	int ret;
1039 
1040 	if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)
1041 		return -EOPNOTSUPP;
1042 
1043 	nfc->data = 0;
1044 
1045 	ret = hclgevf_get_rss_tuple_by_flow_type(hdev, nfc->flow_type,
1046 						 &tuple_sets);
1047 	if (ret || !tuple_sets)
1048 		return ret;
1049 
1050 	nfc->data = hclgevf_convert_rss_tuple(tuple_sets);
1051 
1052 	return 0;
1053 }
1054 
1055 static int hclgevf_set_rss_input_tuple(struct hclgevf_dev *hdev,
1056 				       struct hclgevf_rss_cfg *rss_cfg)
1057 {
1058 	struct hclgevf_rss_input_tuple_cmd *req;
1059 	struct hclgevf_desc desc;
1060 	int ret;
1061 
1062 	hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false);
1063 
1064 	req = (struct hclgevf_rss_input_tuple_cmd *)desc.data;
1065 
1066 	req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en;
1067 	req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en;
1068 	req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en;
1069 	req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en;
1070 	req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en;
1071 	req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en;
1072 	req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en;
1073 	req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en;
1074 
1075 	ret = hclgevf_cmd_send(&hdev->hw, &desc, 1);
1076 	if (ret)
1077 		dev_err(&hdev->pdev->dev,
1078 			"Configure rss input fail, status = %d\n", ret);
1079 	return ret;
1080 }
1081 
1082 static int hclgevf_get_tc_size(struct hnae3_handle *handle)
1083 {
1084 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1085 	struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
1086 
1087 	return rss_cfg->rss_size;
1088 }
1089 
1090 static int hclgevf_bind_ring_to_vector(struct hnae3_handle *handle, bool en,
1091 				       int vector_id,
1092 				       struct hnae3_ring_chain_node *ring_chain)
1093 {
1094 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1095 	struct hclge_vf_to_pf_msg send_msg;
1096 	struct hnae3_ring_chain_node *node;
1097 	int status;
1098 	int i = 0;
1099 
1100 	memset(&send_msg, 0, sizeof(send_msg));
1101 	send_msg.code = en ? HCLGE_MBX_MAP_RING_TO_VECTOR :
1102 		HCLGE_MBX_UNMAP_RING_TO_VECTOR;
1103 	send_msg.vector_id = vector_id;
1104 
1105 	for (node = ring_chain; node; node = node->next) {
1106 		send_msg.param[i].ring_type =
1107 				hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B);
1108 
1109 		send_msg.param[i].tqp_index = node->tqp_index;
1110 		send_msg.param[i].int_gl_index =
1111 					hnae3_get_field(node->int_gl_idx,
1112 							HNAE3_RING_GL_IDX_M,
1113 							HNAE3_RING_GL_IDX_S);
1114 
1115 		i++;
1116 		if (i == HCLGE_MBX_MAX_RING_CHAIN_PARAM_NUM || !node->next) {
1117 			send_msg.ring_num = i;
1118 
1119 			status = hclgevf_send_mbx_msg(hdev, &send_msg, false,
1120 						      NULL, 0);
1121 			if (status) {
1122 				dev_err(&hdev->pdev->dev,
1123 					"Map TQP fail, status is %d.\n",
1124 					status);
1125 				return status;
1126 			}
1127 			i = 0;
1128 		}
1129 	}
1130 
1131 	return 0;
1132 }
1133 
1134 static int hclgevf_map_ring_to_vector(struct hnae3_handle *handle, int vector,
1135 				      struct hnae3_ring_chain_node *ring_chain)
1136 {
1137 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1138 	int vector_id;
1139 
1140 	vector_id = hclgevf_get_vector_index(hdev, vector);
1141 	if (vector_id < 0) {
1142 		dev_err(&handle->pdev->dev,
1143 			"Get vector index fail. ret =%d\n", vector_id);
1144 		return vector_id;
1145 	}
1146 
1147 	return hclgevf_bind_ring_to_vector(handle, true, vector_id, ring_chain);
1148 }
1149 
1150 static int hclgevf_unmap_ring_from_vector(
1151 				struct hnae3_handle *handle,
1152 				int vector,
1153 				struct hnae3_ring_chain_node *ring_chain)
1154 {
1155 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1156 	int ret, vector_id;
1157 
1158 	if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state))
1159 		return 0;
1160 
1161 	vector_id = hclgevf_get_vector_index(hdev, vector);
1162 	if (vector_id < 0) {
1163 		dev_err(&handle->pdev->dev,
1164 			"Get vector index fail. ret =%d\n", vector_id);
1165 		return vector_id;
1166 	}
1167 
1168 	ret = hclgevf_bind_ring_to_vector(handle, false, vector_id, ring_chain);
1169 	if (ret)
1170 		dev_err(&handle->pdev->dev,
1171 			"Unmap ring from vector fail. vector=%d, ret =%d\n",
1172 			vector_id,
1173 			ret);
1174 
1175 	return ret;
1176 }
1177 
1178 static int hclgevf_put_vector(struct hnae3_handle *handle, int vector)
1179 {
1180 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1181 	int vector_id;
1182 
1183 	vector_id = hclgevf_get_vector_index(hdev, vector);
1184 	if (vector_id < 0) {
1185 		dev_err(&handle->pdev->dev,
1186 			"hclgevf_put_vector get vector index fail. ret =%d\n",
1187 			vector_id);
1188 		return vector_id;
1189 	}
1190 
1191 	hclgevf_free_vector(hdev, vector_id);
1192 
1193 	return 0;
1194 }
1195 
1196 static int hclgevf_cmd_set_promisc_mode(struct hclgevf_dev *hdev,
1197 					bool en_uc_pmc, bool en_mc_pmc,
1198 					bool en_bc_pmc)
1199 {
1200 	struct hnae3_handle *handle = &hdev->nic;
1201 	struct hclge_vf_to_pf_msg send_msg;
1202 	int ret;
1203 
1204 	memset(&send_msg, 0, sizeof(send_msg));
1205 	send_msg.code = HCLGE_MBX_SET_PROMISC_MODE;
1206 	send_msg.en_bc = en_bc_pmc ? 1 : 0;
1207 	send_msg.en_uc = en_uc_pmc ? 1 : 0;
1208 	send_msg.en_mc = en_mc_pmc ? 1 : 0;
1209 	send_msg.en_limit_promisc = test_bit(HNAE3_PFLAG_LIMIT_PROMISC,
1210 					     &handle->priv_flags) ? 1 : 0;
1211 
1212 	ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
1213 	if (ret)
1214 		dev_err(&hdev->pdev->dev,
1215 			"Set promisc mode fail, status is %d.\n", ret);
1216 
1217 	return ret;
1218 }
1219 
1220 static int hclgevf_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc,
1221 				    bool en_mc_pmc)
1222 {
1223 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1224 	bool en_bc_pmc;
1225 
1226 	en_bc_pmc = hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2;
1227 
1228 	return hclgevf_cmd_set_promisc_mode(hdev, en_uc_pmc, en_mc_pmc,
1229 					    en_bc_pmc);
1230 }
1231 
1232 static void hclgevf_request_update_promisc_mode(struct hnae3_handle *handle)
1233 {
1234 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1235 
1236 	set_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state);
1237 	hclgevf_task_schedule(hdev, 0);
1238 }
1239 
1240 static void hclgevf_sync_promisc_mode(struct hclgevf_dev *hdev)
1241 {
1242 	struct hnae3_handle *handle = &hdev->nic;
1243 	bool en_uc_pmc = handle->netdev_flags & HNAE3_UPE;
1244 	bool en_mc_pmc = handle->netdev_flags & HNAE3_MPE;
1245 	int ret;
1246 
1247 	if (test_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state)) {
1248 		ret = hclgevf_set_promisc_mode(handle, en_uc_pmc, en_mc_pmc);
1249 		if (!ret)
1250 			clear_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state);
1251 	}
1252 }
1253 
1254 static int hclgevf_tqp_enable_cmd_send(struct hclgevf_dev *hdev, u16 tqp_id,
1255 				       u16 stream_id, bool enable)
1256 {
1257 	struct hclgevf_cfg_com_tqp_queue_cmd *req;
1258 	struct hclgevf_desc desc;
1259 
1260 	req = (struct hclgevf_cfg_com_tqp_queue_cmd *)desc.data;
1261 
1262 	hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_CFG_COM_TQP_QUEUE,
1263 				     false);
1264 	req->tqp_id = cpu_to_le16(tqp_id & HCLGEVF_RING_ID_MASK);
1265 	req->stream_id = cpu_to_le16(stream_id);
1266 	if (enable)
1267 		req->enable |= 1U << HCLGEVF_TQP_ENABLE_B;
1268 
1269 	return hclgevf_cmd_send(&hdev->hw, &desc, 1);
1270 }
1271 
1272 static int hclgevf_tqp_enable(struct hnae3_handle *handle, bool enable)
1273 {
1274 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1275 	int ret;
1276 	u16 i;
1277 
1278 	for (i = 0; i < handle->kinfo.num_tqps; i++) {
1279 		ret = hclgevf_tqp_enable_cmd_send(hdev, i, 0, enable);
1280 		if (ret)
1281 			return ret;
1282 	}
1283 
1284 	return 0;
1285 }
1286 
1287 static void hclgevf_reset_tqp_stats(struct hnae3_handle *handle)
1288 {
1289 	struct hnae3_knic_private_info *kinfo = &handle->kinfo;
1290 	struct hclgevf_tqp *tqp;
1291 	int i;
1292 
1293 	for (i = 0; i < kinfo->num_tqps; i++) {
1294 		tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q);
1295 		memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats));
1296 	}
1297 }
1298 
1299 static int hclgevf_get_host_mac_addr(struct hclgevf_dev *hdev, u8 *p)
1300 {
1301 	struct hclge_vf_to_pf_msg send_msg;
1302 	u8 host_mac[ETH_ALEN];
1303 	int status;
1304 
1305 	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_MAC_ADDR, 0);
1306 	status = hclgevf_send_mbx_msg(hdev, &send_msg, true, host_mac,
1307 				      ETH_ALEN);
1308 	if (status) {
1309 		dev_err(&hdev->pdev->dev,
1310 			"fail to get VF MAC from host %d", status);
1311 		return status;
1312 	}
1313 
1314 	ether_addr_copy(p, host_mac);
1315 
1316 	return 0;
1317 }
1318 
1319 static void hclgevf_get_mac_addr(struct hnae3_handle *handle, u8 *p)
1320 {
1321 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1322 	u8 host_mac_addr[ETH_ALEN];
1323 
1324 	if (hclgevf_get_host_mac_addr(hdev, host_mac_addr))
1325 		return;
1326 
1327 	hdev->has_pf_mac = !is_zero_ether_addr(host_mac_addr);
1328 	if (hdev->has_pf_mac)
1329 		ether_addr_copy(p, host_mac_addr);
1330 	else
1331 		ether_addr_copy(p, hdev->hw.mac.mac_addr);
1332 }
1333 
1334 static int hclgevf_set_mac_addr(struct hnae3_handle *handle, void *p,
1335 				bool is_first)
1336 {
1337 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1338 	u8 *old_mac_addr = (u8 *)hdev->hw.mac.mac_addr;
1339 	struct hclge_vf_to_pf_msg send_msg;
1340 	u8 *new_mac_addr = (u8 *)p;
1341 	int status;
1342 
1343 	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_UNICAST, 0);
1344 	send_msg.subcode = HCLGE_MBX_MAC_VLAN_UC_MODIFY;
1345 	ether_addr_copy(send_msg.data, new_mac_addr);
1346 	if (is_first && !hdev->has_pf_mac)
1347 		eth_zero_addr(&send_msg.data[ETH_ALEN]);
1348 	else
1349 		ether_addr_copy(&send_msg.data[ETH_ALEN], old_mac_addr);
1350 	status = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0);
1351 	if (!status)
1352 		ether_addr_copy(hdev->hw.mac.mac_addr, new_mac_addr);
1353 
1354 	return status;
1355 }
1356 
1357 static struct hclgevf_mac_addr_node *
1358 hclgevf_find_mac_node(struct list_head *list, const u8 *mac_addr)
1359 {
1360 	struct hclgevf_mac_addr_node *mac_node, *tmp;
1361 
1362 	list_for_each_entry_safe(mac_node, tmp, list, node)
1363 		if (ether_addr_equal(mac_addr, mac_node->mac_addr))
1364 			return mac_node;
1365 
1366 	return NULL;
1367 }
1368 
1369 static void hclgevf_update_mac_node(struct hclgevf_mac_addr_node *mac_node,
1370 				    enum HCLGEVF_MAC_NODE_STATE state)
1371 {
1372 	switch (state) {
1373 	/* from set_rx_mode or tmp_add_list */
1374 	case HCLGEVF_MAC_TO_ADD:
1375 		if (mac_node->state == HCLGEVF_MAC_TO_DEL)
1376 			mac_node->state = HCLGEVF_MAC_ACTIVE;
1377 		break;
1378 	/* only from set_rx_mode */
1379 	case HCLGEVF_MAC_TO_DEL:
1380 		if (mac_node->state == HCLGEVF_MAC_TO_ADD) {
1381 			list_del(&mac_node->node);
1382 			kfree(mac_node);
1383 		} else {
1384 			mac_node->state = HCLGEVF_MAC_TO_DEL;
1385 		}
1386 		break;
1387 	/* only from tmp_add_list, the mac_node->state won't be
1388 	 * HCLGEVF_MAC_ACTIVE
1389 	 */
1390 	case HCLGEVF_MAC_ACTIVE:
1391 		if (mac_node->state == HCLGEVF_MAC_TO_ADD)
1392 			mac_node->state = HCLGEVF_MAC_ACTIVE;
1393 		break;
1394 	}
1395 }
1396 
1397 static int hclgevf_update_mac_list(struct hnae3_handle *handle,
1398 				   enum HCLGEVF_MAC_NODE_STATE state,
1399 				   enum HCLGEVF_MAC_ADDR_TYPE mac_type,
1400 				   const unsigned char *addr)
1401 {
1402 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1403 	struct hclgevf_mac_addr_node *mac_node;
1404 	struct list_head *list;
1405 
1406 	list = (mac_type == HCLGEVF_MAC_ADDR_UC) ?
1407 	       &hdev->mac_table.uc_mac_list : &hdev->mac_table.mc_mac_list;
1408 
1409 	spin_lock_bh(&hdev->mac_table.mac_list_lock);
1410 
1411 	/* if the mac addr is already in the mac list, no need to add a new
1412 	 * one into it, just check the mac addr state, convert it to a new
1413 	 * new state, or just remove it, or do nothing.
1414 	 */
1415 	mac_node = hclgevf_find_mac_node(list, addr);
1416 	if (mac_node) {
1417 		hclgevf_update_mac_node(mac_node, state);
1418 		spin_unlock_bh(&hdev->mac_table.mac_list_lock);
1419 		return 0;
1420 	}
1421 	/* if this address is never added, unnecessary to delete */
1422 	if (state == HCLGEVF_MAC_TO_DEL) {
1423 		spin_unlock_bh(&hdev->mac_table.mac_list_lock);
1424 		return -ENOENT;
1425 	}
1426 
1427 	mac_node = kzalloc(sizeof(*mac_node), GFP_ATOMIC);
1428 	if (!mac_node) {
1429 		spin_unlock_bh(&hdev->mac_table.mac_list_lock);
1430 		return -ENOMEM;
1431 	}
1432 
1433 	mac_node->state = state;
1434 	ether_addr_copy(mac_node->mac_addr, addr);
1435 	list_add_tail(&mac_node->node, list);
1436 
1437 	spin_unlock_bh(&hdev->mac_table.mac_list_lock);
1438 	return 0;
1439 }
1440 
1441 static int hclgevf_add_uc_addr(struct hnae3_handle *handle,
1442 			       const unsigned char *addr)
1443 {
1444 	return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_ADD,
1445 				       HCLGEVF_MAC_ADDR_UC, addr);
1446 }
1447 
1448 static int hclgevf_rm_uc_addr(struct hnae3_handle *handle,
1449 			      const unsigned char *addr)
1450 {
1451 	return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_DEL,
1452 				       HCLGEVF_MAC_ADDR_UC, addr);
1453 }
1454 
1455 static int hclgevf_add_mc_addr(struct hnae3_handle *handle,
1456 			       const unsigned char *addr)
1457 {
1458 	return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_ADD,
1459 				       HCLGEVF_MAC_ADDR_MC, addr);
1460 }
1461 
1462 static int hclgevf_rm_mc_addr(struct hnae3_handle *handle,
1463 			      const unsigned char *addr)
1464 {
1465 	return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_DEL,
1466 				       HCLGEVF_MAC_ADDR_MC, addr);
1467 }
1468 
1469 static int hclgevf_add_del_mac_addr(struct hclgevf_dev *hdev,
1470 				    struct hclgevf_mac_addr_node *mac_node,
1471 				    enum HCLGEVF_MAC_ADDR_TYPE mac_type)
1472 {
1473 	struct hclge_vf_to_pf_msg send_msg;
1474 	u8 code, subcode;
1475 
1476 	if (mac_type == HCLGEVF_MAC_ADDR_UC) {
1477 		code = HCLGE_MBX_SET_UNICAST;
1478 		if (mac_node->state == HCLGEVF_MAC_TO_ADD)
1479 			subcode = HCLGE_MBX_MAC_VLAN_UC_ADD;
1480 		else
1481 			subcode = HCLGE_MBX_MAC_VLAN_UC_REMOVE;
1482 	} else {
1483 		code = HCLGE_MBX_SET_MULTICAST;
1484 		if (mac_node->state == HCLGEVF_MAC_TO_ADD)
1485 			subcode = HCLGE_MBX_MAC_VLAN_MC_ADD;
1486 		else
1487 			subcode = HCLGE_MBX_MAC_VLAN_MC_REMOVE;
1488 	}
1489 
1490 	hclgevf_build_send_msg(&send_msg, code, subcode);
1491 	ether_addr_copy(send_msg.data, mac_node->mac_addr);
1492 	return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
1493 }
1494 
1495 static void hclgevf_config_mac_list(struct hclgevf_dev *hdev,
1496 				    struct list_head *list,
1497 				    enum HCLGEVF_MAC_ADDR_TYPE mac_type)
1498 {
1499 	struct hclgevf_mac_addr_node *mac_node, *tmp;
1500 	int ret;
1501 
1502 	list_for_each_entry_safe(mac_node, tmp, list, node) {
1503 		ret = hclgevf_add_del_mac_addr(hdev, mac_node, mac_type);
1504 		if  (ret) {
1505 			dev_err(&hdev->pdev->dev,
1506 				"failed to configure mac %pM, state = %d, ret = %d\n",
1507 				mac_node->mac_addr, mac_node->state, ret);
1508 			return;
1509 		}
1510 		if (mac_node->state == HCLGEVF_MAC_TO_ADD) {
1511 			mac_node->state = HCLGEVF_MAC_ACTIVE;
1512 		} else {
1513 			list_del(&mac_node->node);
1514 			kfree(mac_node);
1515 		}
1516 	}
1517 }
1518 
1519 static void hclgevf_sync_from_add_list(struct list_head *add_list,
1520 				       struct list_head *mac_list)
1521 {
1522 	struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node;
1523 
1524 	list_for_each_entry_safe(mac_node, tmp, add_list, node) {
1525 		/* if the mac address from tmp_add_list is not in the
1526 		 * uc/mc_mac_list, it means have received a TO_DEL request
1527 		 * during the time window of sending mac config request to PF
1528 		 * If mac_node state is ACTIVE, then change its state to TO_DEL,
1529 		 * then it will be removed at next time. If is TO_ADD, it means
1530 		 * send TO_ADD request failed, so just remove the mac node.
1531 		 */
1532 		new_node = hclgevf_find_mac_node(mac_list, mac_node->mac_addr);
1533 		if (new_node) {
1534 			hclgevf_update_mac_node(new_node, mac_node->state);
1535 			list_del(&mac_node->node);
1536 			kfree(mac_node);
1537 		} else if (mac_node->state == HCLGEVF_MAC_ACTIVE) {
1538 			mac_node->state = HCLGEVF_MAC_TO_DEL;
1539 			list_move_tail(&mac_node->node, mac_list);
1540 		} else {
1541 			list_del(&mac_node->node);
1542 			kfree(mac_node);
1543 		}
1544 	}
1545 }
1546 
1547 static void hclgevf_sync_from_del_list(struct list_head *del_list,
1548 				       struct list_head *mac_list)
1549 {
1550 	struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node;
1551 
1552 	list_for_each_entry_safe(mac_node, tmp, del_list, node) {
1553 		new_node = hclgevf_find_mac_node(mac_list, mac_node->mac_addr);
1554 		if (new_node) {
1555 			/* If the mac addr is exist in the mac list, it means
1556 			 * received a new request TO_ADD during the time window
1557 			 * of sending mac addr configurrequest to PF, so just
1558 			 * change the mac state to ACTIVE.
1559 			 */
1560 			new_node->state = HCLGEVF_MAC_ACTIVE;
1561 			list_del(&mac_node->node);
1562 			kfree(mac_node);
1563 		} else {
1564 			list_move_tail(&mac_node->node, mac_list);
1565 		}
1566 	}
1567 }
1568 
1569 static void hclgevf_clear_list(struct list_head *list)
1570 {
1571 	struct hclgevf_mac_addr_node *mac_node, *tmp;
1572 
1573 	list_for_each_entry_safe(mac_node, tmp, list, node) {
1574 		list_del(&mac_node->node);
1575 		kfree(mac_node);
1576 	}
1577 }
1578 
1579 static void hclgevf_sync_mac_list(struct hclgevf_dev *hdev,
1580 				  enum HCLGEVF_MAC_ADDR_TYPE mac_type)
1581 {
1582 	struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node;
1583 	struct list_head tmp_add_list, tmp_del_list;
1584 	struct list_head *list;
1585 
1586 	INIT_LIST_HEAD(&tmp_add_list);
1587 	INIT_LIST_HEAD(&tmp_del_list);
1588 
1589 	/* move the mac addr to the tmp_add_list and tmp_del_list, then
1590 	 * we can add/delete these mac addr outside the spin lock
1591 	 */
1592 	list = (mac_type == HCLGEVF_MAC_ADDR_UC) ?
1593 		&hdev->mac_table.uc_mac_list : &hdev->mac_table.mc_mac_list;
1594 
1595 	spin_lock_bh(&hdev->mac_table.mac_list_lock);
1596 
1597 	list_for_each_entry_safe(mac_node, tmp, list, node) {
1598 		switch (mac_node->state) {
1599 		case HCLGEVF_MAC_TO_DEL:
1600 			list_move_tail(&mac_node->node, &tmp_del_list);
1601 			break;
1602 		case HCLGEVF_MAC_TO_ADD:
1603 			new_node = kzalloc(sizeof(*new_node), GFP_ATOMIC);
1604 			if (!new_node)
1605 				goto stop_traverse;
1606 
1607 			ether_addr_copy(new_node->mac_addr, mac_node->mac_addr);
1608 			new_node->state = mac_node->state;
1609 			list_add_tail(&new_node->node, &tmp_add_list);
1610 			break;
1611 		default:
1612 			break;
1613 		}
1614 	}
1615 
1616 stop_traverse:
1617 	spin_unlock_bh(&hdev->mac_table.mac_list_lock);
1618 
1619 	/* delete first, in order to get max mac table space for adding */
1620 	hclgevf_config_mac_list(hdev, &tmp_del_list, mac_type);
1621 	hclgevf_config_mac_list(hdev, &tmp_add_list, mac_type);
1622 
1623 	/* if some mac addresses were added/deleted fail, move back to the
1624 	 * mac_list, and retry at next time.
1625 	 */
1626 	spin_lock_bh(&hdev->mac_table.mac_list_lock);
1627 
1628 	hclgevf_sync_from_del_list(&tmp_del_list, list);
1629 	hclgevf_sync_from_add_list(&tmp_add_list, list);
1630 
1631 	spin_unlock_bh(&hdev->mac_table.mac_list_lock);
1632 }
1633 
1634 static void hclgevf_sync_mac_table(struct hclgevf_dev *hdev)
1635 {
1636 	hclgevf_sync_mac_list(hdev, HCLGEVF_MAC_ADDR_UC);
1637 	hclgevf_sync_mac_list(hdev, HCLGEVF_MAC_ADDR_MC);
1638 }
1639 
1640 static void hclgevf_uninit_mac_list(struct hclgevf_dev *hdev)
1641 {
1642 	spin_lock_bh(&hdev->mac_table.mac_list_lock);
1643 
1644 	hclgevf_clear_list(&hdev->mac_table.uc_mac_list);
1645 	hclgevf_clear_list(&hdev->mac_table.mc_mac_list);
1646 
1647 	spin_unlock_bh(&hdev->mac_table.mac_list_lock);
1648 }
1649 
1650 static int hclgevf_enable_vlan_filter(struct hnae3_handle *handle, bool enable)
1651 {
1652 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1653 	struct hnae3_ae_dev *ae_dev = hdev->ae_dev;
1654 	struct hclge_vf_to_pf_msg send_msg;
1655 
1656 	if (!test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps))
1657 		return -EOPNOTSUPP;
1658 
1659 	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN,
1660 			       HCLGE_MBX_ENABLE_VLAN_FILTER);
1661 	send_msg.data[0] = enable ? 1 : 0;
1662 
1663 	return hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0);
1664 }
1665 
1666 static int hclgevf_set_vlan_filter(struct hnae3_handle *handle,
1667 				   __be16 proto, u16 vlan_id,
1668 				   bool is_kill)
1669 {
1670 #define HCLGEVF_VLAN_MBX_IS_KILL_OFFSET	0
1671 #define HCLGEVF_VLAN_MBX_VLAN_ID_OFFSET	1
1672 #define HCLGEVF_VLAN_MBX_PROTO_OFFSET	3
1673 
1674 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1675 	struct hclge_vf_to_pf_msg send_msg;
1676 	int ret;
1677 
1678 	if (vlan_id > HCLGEVF_MAX_VLAN_ID)
1679 		return -EINVAL;
1680 
1681 	if (proto != htons(ETH_P_8021Q))
1682 		return -EPROTONOSUPPORT;
1683 
1684 	/* When device is resetting or reset failed, firmware is unable to
1685 	 * handle mailbox. Just record the vlan id, and remove it after
1686 	 * reset finished.
1687 	 */
1688 	if ((test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) ||
1689 	     test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) && is_kill) {
1690 		set_bit(vlan_id, hdev->vlan_del_fail_bmap);
1691 		return -EBUSY;
1692 	}
1693 
1694 	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN,
1695 			       HCLGE_MBX_VLAN_FILTER);
1696 	send_msg.data[HCLGEVF_VLAN_MBX_IS_KILL_OFFSET] = is_kill;
1697 	memcpy(&send_msg.data[HCLGEVF_VLAN_MBX_VLAN_ID_OFFSET], &vlan_id,
1698 	       sizeof(vlan_id));
1699 	memcpy(&send_msg.data[HCLGEVF_VLAN_MBX_PROTO_OFFSET], &proto,
1700 	       sizeof(proto));
1701 	/* when remove hw vlan filter failed, record the vlan id,
1702 	 * and try to remove it from hw later, to be consistence
1703 	 * with stack.
1704 	 */
1705 	ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0);
1706 	if (is_kill && ret)
1707 		set_bit(vlan_id, hdev->vlan_del_fail_bmap);
1708 
1709 	return ret;
1710 }
1711 
1712 static void hclgevf_sync_vlan_filter(struct hclgevf_dev *hdev)
1713 {
1714 #define HCLGEVF_MAX_SYNC_COUNT	60
1715 	struct hnae3_handle *handle = &hdev->nic;
1716 	int ret, sync_cnt = 0;
1717 	u16 vlan_id;
1718 
1719 	vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID);
1720 	while (vlan_id != VLAN_N_VID) {
1721 		ret = hclgevf_set_vlan_filter(handle, htons(ETH_P_8021Q),
1722 					      vlan_id, true);
1723 		if (ret)
1724 			return;
1725 
1726 		clear_bit(vlan_id, hdev->vlan_del_fail_bmap);
1727 		sync_cnt++;
1728 		if (sync_cnt >= HCLGEVF_MAX_SYNC_COUNT)
1729 			return;
1730 
1731 		vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID);
1732 	}
1733 }
1734 
1735 static int hclgevf_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable)
1736 {
1737 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1738 	struct hclge_vf_to_pf_msg send_msg;
1739 
1740 	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN,
1741 			       HCLGE_MBX_VLAN_RX_OFF_CFG);
1742 	send_msg.data[0] = enable ? 1 : 0;
1743 	return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
1744 }
1745 
1746 static int hclgevf_reset_tqp(struct hnae3_handle *handle)
1747 {
1748 #define HCLGEVF_RESET_ALL_QUEUE_DONE	1U
1749 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1750 	struct hclge_vf_to_pf_msg send_msg;
1751 	u8 return_status = 0;
1752 	int ret;
1753 	u16 i;
1754 
1755 	/* disable vf queue before send queue reset msg to PF */
1756 	ret = hclgevf_tqp_enable(handle, false);
1757 	if (ret) {
1758 		dev_err(&hdev->pdev->dev, "failed to disable tqp, ret = %d\n",
1759 			ret);
1760 		return ret;
1761 	}
1762 
1763 	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_QUEUE_RESET, 0);
1764 
1765 	ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, &return_status,
1766 				   sizeof(return_status));
1767 	if (ret || return_status == HCLGEVF_RESET_ALL_QUEUE_DONE)
1768 		return ret;
1769 
1770 	for (i = 1; i < handle->kinfo.num_tqps; i++) {
1771 		hclgevf_build_send_msg(&send_msg, HCLGE_MBX_QUEUE_RESET, 0);
1772 		memcpy(send_msg.data, &i, sizeof(i));
1773 		ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0);
1774 		if (ret)
1775 			return ret;
1776 	}
1777 
1778 	return 0;
1779 }
1780 
1781 static int hclgevf_set_mtu(struct hnae3_handle *handle, int new_mtu)
1782 {
1783 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1784 	struct hclge_vf_to_pf_msg send_msg;
1785 
1786 	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_MTU, 0);
1787 	memcpy(send_msg.data, &new_mtu, sizeof(new_mtu));
1788 	return hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0);
1789 }
1790 
1791 static int hclgevf_notify_client(struct hclgevf_dev *hdev,
1792 				 enum hnae3_reset_notify_type type)
1793 {
1794 	struct hnae3_client *client = hdev->nic_client;
1795 	struct hnae3_handle *handle = &hdev->nic;
1796 	int ret;
1797 
1798 	if (!test_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state) ||
1799 	    !client)
1800 		return 0;
1801 
1802 	if (!client->ops->reset_notify)
1803 		return -EOPNOTSUPP;
1804 
1805 	ret = client->ops->reset_notify(handle, type);
1806 	if (ret)
1807 		dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n",
1808 			type, ret);
1809 
1810 	return ret;
1811 }
1812 
1813 static int hclgevf_notify_roce_client(struct hclgevf_dev *hdev,
1814 				      enum hnae3_reset_notify_type type)
1815 {
1816 	struct hnae3_client *client = hdev->roce_client;
1817 	struct hnae3_handle *handle = &hdev->roce;
1818 	int ret;
1819 
1820 	if (!test_bit(HCLGEVF_STATE_ROCE_REGISTERED, &hdev->state) || !client)
1821 		return 0;
1822 
1823 	if (!client->ops->reset_notify)
1824 		return -EOPNOTSUPP;
1825 
1826 	ret = client->ops->reset_notify(handle, type);
1827 	if (ret)
1828 		dev_err(&hdev->pdev->dev, "notify roce client failed %d(%d)",
1829 			type, ret);
1830 	return ret;
1831 }
1832 
1833 static int hclgevf_reset_wait(struct hclgevf_dev *hdev)
1834 {
1835 #define HCLGEVF_RESET_WAIT_US	20000
1836 #define HCLGEVF_RESET_WAIT_CNT	2000
1837 #define HCLGEVF_RESET_WAIT_TIMEOUT_US	\
1838 	(HCLGEVF_RESET_WAIT_US * HCLGEVF_RESET_WAIT_CNT)
1839 
1840 	u32 val;
1841 	int ret;
1842 
1843 	if (hdev->reset_type == HNAE3_VF_RESET)
1844 		ret = readl_poll_timeout(hdev->hw.io_base +
1845 					 HCLGEVF_VF_RST_ING, val,
1846 					 !(val & HCLGEVF_VF_RST_ING_BIT),
1847 					 HCLGEVF_RESET_WAIT_US,
1848 					 HCLGEVF_RESET_WAIT_TIMEOUT_US);
1849 	else
1850 		ret = readl_poll_timeout(hdev->hw.io_base +
1851 					 HCLGEVF_RST_ING, val,
1852 					 !(val & HCLGEVF_RST_ING_BITS),
1853 					 HCLGEVF_RESET_WAIT_US,
1854 					 HCLGEVF_RESET_WAIT_TIMEOUT_US);
1855 
1856 	/* hardware completion status should be available by this time */
1857 	if (ret) {
1858 		dev_err(&hdev->pdev->dev,
1859 			"couldn't get reset done status from h/w, timeout!\n");
1860 		return ret;
1861 	}
1862 
1863 	/* we will wait a bit more to let reset of the stack to complete. This
1864 	 * might happen in case reset assertion was made by PF. Yes, this also
1865 	 * means we might end up waiting bit more even for VF reset.
1866 	 */
1867 	msleep(5000);
1868 
1869 	return 0;
1870 }
1871 
1872 static void hclgevf_reset_handshake(struct hclgevf_dev *hdev, bool enable)
1873 {
1874 	u32 reg_val;
1875 
1876 	reg_val = hclgevf_read_dev(&hdev->hw, HCLGEVF_NIC_CSQ_DEPTH_REG);
1877 	if (enable)
1878 		reg_val |= HCLGEVF_NIC_SW_RST_RDY;
1879 	else
1880 		reg_val &= ~HCLGEVF_NIC_SW_RST_RDY;
1881 
1882 	hclgevf_write_dev(&hdev->hw, HCLGEVF_NIC_CSQ_DEPTH_REG,
1883 			  reg_val);
1884 }
1885 
1886 static int hclgevf_reset_stack(struct hclgevf_dev *hdev)
1887 {
1888 	int ret;
1889 
1890 	/* uninitialize the nic client */
1891 	ret = hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT);
1892 	if (ret)
1893 		return ret;
1894 
1895 	/* re-initialize the hclge device */
1896 	ret = hclgevf_reset_hdev(hdev);
1897 	if (ret) {
1898 		dev_err(&hdev->pdev->dev,
1899 			"hclge device re-init failed, VF is disabled!\n");
1900 		return ret;
1901 	}
1902 
1903 	/* bring up the nic client again */
1904 	ret = hclgevf_notify_client(hdev, HNAE3_INIT_CLIENT);
1905 	if (ret)
1906 		return ret;
1907 
1908 	/* clear handshake status with IMP */
1909 	hclgevf_reset_handshake(hdev, false);
1910 
1911 	/* bring up the nic to enable TX/RX again */
1912 	return hclgevf_notify_client(hdev, HNAE3_UP_CLIENT);
1913 }
1914 
1915 static int hclgevf_reset_prepare_wait(struct hclgevf_dev *hdev)
1916 {
1917 #define HCLGEVF_RESET_SYNC_TIME 100
1918 
1919 	if (hdev->reset_type == HNAE3_VF_FUNC_RESET) {
1920 		struct hclge_vf_to_pf_msg send_msg;
1921 		int ret;
1922 
1923 		hclgevf_build_send_msg(&send_msg, HCLGE_MBX_RESET, 0);
1924 		ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0);
1925 		if (ret) {
1926 			dev_err(&hdev->pdev->dev,
1927 				"failed to assert VF reset, ret = %d\n", ret);
1928 			return ret;
1929 		}
1930 		hdev->rst_stats.vf_func_rst_cnt++;
1931 	}
1932 
1933 	set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state);
1934 	/* inform hardware that preparatory work is done */
1935 	msleep(HCLGEVF_RESET_SYNC_TIME);
1936 	hclgevf_reset_handshake(hdev, true);
1937 	dev_info(&hdev->pdev->dev, "prepare reset(%d) wait done\n",
1938 		 hdev->reset_type);
1939 
1940 	return 0;
1941 }
1942 
1943 static void hclgevf_dump_rst_info(struct hclgevf_dev *hdev)
1944 {
1945 	dev_info(&hdev->pdev->dev, "VF function reset count: %u\n",
1946 		 hdev->rst_stats.vf_func_rst_cnt);
1947 	dev_info(&hdev->pdev->dev, "FLR reset count: %u\n",
1948 		 hdev->rst_stats.flr_rst_cnt);
1949 	dev_info(&hdev->pdev->dev, "VF reset count: %u\n",
1950 		 hdev->rst_stats.vf_rst_cnt);
1951 	dev_info(&hdev->pdev->dev, "reset done count: %u\n",
1952 		 hdev->rst_stats.rst_done_cnt);
1953 	dev_info(&hdev->pdev->dev, "HW reset done count: %u\n",
1954 		 hdev->rst_stats.hw_rst_done_cnt);
1955 	dev_info(&hdev->pdev->dev, "reset count: %u\n",
1956 		 hdev->rst_stats.rst_cnt);
1957 	dev_info(&hdev->pdev->dev, "reset fail count: %u\n",
1958 		 hdev->rst_stats.rst_fail_cnt);
1959 	dev_info(&hdev->pdev->dev, "vector0 interrupt enable status: 0x%x\n",
1960 		 hclgevf_read_dev(&hdev->hw, HCLGEVF_MISC_VECTOR_REG_BASE));
1961 	dev_info(&hdev->pdev->dev, "vector0 interrupt status: 0x%x\n",
1962 		 hclgevf_read_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_STATE_REG));
1963 	dev_info(&hdev->pdev->dev, "handshake status: 0x%x\n",
1964 		 hclgevf_read_dev(&hdev->hw, HCLGEVF_CMDQ_TX_DEPTH_REG));
1965 	dev_info(&hdev->pdev->dev, "function reset status: 0x%x\n",
1966 		 hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING));
1967 	dev_info(&hdev->pdev->dev, "hdev state: 0x%lx\n", hdev->state);
1968 }
1969 
1970 static void hclgevf_reset_err_handle(struct hclgevf_dev *hdev)
1971 {
1972 	/* recover handshake status with IMP when reset fail */
1973 	hclgevf_reset_handshake(hdev, true);
1974 	hdev->rst_stats.rst_fail_cnt++;
1975 	dev_err(&hdev->pdev->dev, "failed to reset VF(%u)\n",
1976 		hdev->rst_stats.rst_fail_cnt);
1977 
1978 	if (hdev->rst_stats.rst_fail_cnt < HCLGEVF_RESET_MAX_FAIL_CNT)
1979 		set_bit(hdev->reset_type, &hdev->reset_pending);
1980 
1981 	if (hclgevf_is_reset_pending(hdev)) {
1982 		set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state);
1983 		hclgevf_reset_task_schedule(hdev);
1984 	} else {
1985 		set_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state);
1986 		hclgevf_dump_rst_info(hdev);
1987 	}
1988 }
1989 
1990 static int hclgevf_reset_prepare(struct hclgevf_dev *hdev)
1991 {
1992 	int ret;
1993 
1994 	hdev->rst_stats.rst_cnt++;
1995 
1996 	/* perform reset of the stack & ae device for a client */
1997 	ret = hclgevf_notify_roce_client(hdev, HNAE3_DOWN_CLIENT);
1998 	if (ret)
1999 		return ret;
2000 
2001 	rtnl_lock();
2002 	/* bring down the nic to stop any ongoing TX/RX */
2003 	ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT);
2004 	rtnl_unlock();
2005 	if (ret)
2006 		return ret;
2007 
2008 	return hclgevf_reset_prepare_wait(hdev);
2009 }
2010 
2011 static int hclgevf_reset_rebuild(struct hclgevf_dev *hdev)
2012 {
2013 	int ret;
2014 
2015 	hdev->rst_stats.hw_rst_done_cnt++;
2016 	ret = hclgevf_notify_roce_client(hdev, HNAE3_UNINIT_CLIENT);
2017 	if (ret)
2018 		return ret;
2019 
2020 	rtnl_lock();
2021 	/* now, re-initialize the nic client and ae device */
2022 	ret = hclgevf_reset_stack(hdev);
2023 	rtnl_unlock();
2024 	if (ret) {
2025 		dev_err(&hdev->pdev->dev, "failed to reset VF stack\n");
2026 		return ret;
2027 	}
2028 
2029 	ret = hclgevf_notify_roce_client(hdev, HNAE3_INIT_CLIENT);
2030 	/* ignore RoCE notify error if it fails HCLGEVF_RESET_MAX_FAIL_CNT - 1
2031 	 * times
2032 	 */
2033 	if (ret &&
2034 	    hdev->rst_stats.rst_fail_cnt < HCLGEVF_RESET_MAX_FAIL_CNT - 1)
2035 		return ret;
2036 
2037 	ret = hclgevf_notify_roce_client(hdev, HNAE3_UP_CLIENT);
2038 	if (ret)
2039 		return ret;
2040 
2041 	hdev->last_reset_time = jiffies;
2042 	hdev->rst_stats.rst_done_cnt++;
2043 	hdev->rst_stats.rst_fail_cnt = 0;
2044 	clear_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state);
2045 
2046 	return 0;
2047 }
2048 
2049 static void hclgevf_reset(struct hclgevf_dev *hdev)
2050 {
2051 	if (hclgevf_reset_prepare(hdev))
2052 		goto err_reset;
2053 
2054 	/* check if VF could successfully fetch the hardware reset completion
2055 	 * status from the hardware
2056 	 */
2057 	if (hclgevf_reset_wait(hdev)) {
2058 		/* can't do much in this situation, will disable VF */
2059 		dev_err(&hdev->pdev->dev,
2060 			"failed to fetch H/W reset completion status\n");
2061 		goto err_reset;
2062 	}
2063 
2064 	if (hclgevf_reset_rebuild(hdev))
2065 		goto err_reset;
2066 
2067 	return;
2068 
2069 err_reset:
2070 	hclgevf_reset_err_handle(hdev);
2071 }
2072 
2073 static enum hnae3_reset_type hclgevf_get_reset_level(struct hclgevf_dev *hdev,
2074 						     unsigned long *addr)
2075 {
2076 	enum hnae3_reset_type rst_level = HNAE3_NONE_RESET;
2077 
2078 	/* return the highest priority reset level amongst all */
2079 	if (test_bit(HNAE3_VF_RESET, addr)) {
2080 		rst_level = HNAE3_VF_RESET;
2081 		clear_bit(HNAE3_VF_RESET, addr);
2082 		clear_bit(HNAE3_VF_PF_FUNC_RESET, addr);
2083 		clear_bit(HNAE3_VF_FUNC_RESET, addr);
2084 	} else if (test_bit(HNAE3_VF_FULL_RESET, addr)) {
2085 		rst_level = HNAE3_VF_FULL_RESET;
2086 		clear_bit(HNAE3_VF_FULL_RESET, addr);
2087 		clear_bit(HNAE3_VF_FUNC_RESET, addr);
2088 	} else if (test_bit(HNAE3_VF_PF_FUNC_RESET, addr)) {
2089 		rst_level = HNAE3_VF_PF_FUNC_RESET;
2090 		clear_bit(HNAE3_VF_PF_FUNC_RESET, addr);
2091 		clear_bit(HNAE3_VF_FUNC_RESET, addr);
2092 	} else if (test_bit(HNAE3_VF_FUNC_RESET, addr)) {
2093 		rst_level = HNAE3_VF_FUNC_RESET;
2094 		clear_bit(HNAE3_VF_FUNC_RESET, addr);
2095 	} else if (test_bit(HNAE3_FLR_RESET, addr)) {
2096 		rst_level = HNAE3_FLR_RESET;
2097 		clear_bit(HNAE3_FLR_RESET, addr);
2098 	}
2099 
2100 	return rst_level;
2101 }
2102 
2103 static void hclgevf_reset_event(struct pci_dev *pdev,
2104 				struct hnae3_handle *handle)
2105 {
2106 	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2107 	struct hclgevf_dev *hdev = ae_dev->priv;
2108 
2109 	dev_info(&hdev->pdev->dev, "received reset request from VF enet\n");
2110 
2111 	if (hdev->default_reset_request)
2112 		hdev->reset_level =
2113 			hclgevf_get_reset_level(hdev,
2114 						&hdev->default_reset_request);
2115 	else
2116 		hdev->reset_level = HNAE3_VF_FUNC_RESET;
2117 
2118 	/* reset of this VF requested */
2119 	set_bit(HCLGEVF_RESET_REQUESTED, &hdev->reset_state);
2120 	hclgevf_reset_task_schedule(hdev);
2121 
2122 	hdev->last_reset_time = jiffies;
2123 }
2124 
2125 static void hclgevf_set_def_reset_request(struct hnae3_ae_dev *ae_dev,
2126 					  enum hnae3_reset_type rst_type)
2127 {
2128 	struct hclgevf_dev *hdev = ae_dev->priv;
2129 
2130 	set_bit(rst_type, &hdev->default_reset_request);
2131 }
2132 
2133 static void hclgevf_enable_vector(struct hclgevf_misc_vector *vector, bool en)
2134 {
2135 	writel(en ? 1 : 0, vector->addr);
2136 }
2137 
2138 static void hclgevf_reset_prepare_general(struct hnae3_ae_dev *ae_dev,
2139 					  enum hnae3_reset_type rst_type)
2140 {
2141 #define HCLGEVF_RESET_RETRY_WAIT_MS	500
2142 #define HCLGEVF_RESET_RETRY_CNT		5
2143 
2144 	struct hclgevf_dev *hdev = ae_dev->priv;
2145 	int retry_cnt = 0;
2146 	int ret;
2147 
2148 retry:
2149 	down(&hdev->reset_sem);
2150 	set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state);
2151 	hdev->reset_type = rst_type;
2152 	ret = hclgevf_reset_prepare(hdev);
2153 	if (ret) {
2154 		dev_err(&hdev->pdev->dev, "fail to prepare to reset, ret=%d\n",
2155 			ret);
2156 		if (hdev->reset_pending ||
2157 		    retry_cnt++ < HCLGEVF_RESET_RETRY_CNT) {
2158 			dev_err(&hdev->pdev->dev,
2159 				"reset_pending:0x%lx, retry_cnt:%d\n",
2160 				hdev->reset_pending, retry_cnt);
2161 			clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state);
2162 			up(&hdev->reset_sem);
2163 			msleep(HCLGEVF_RESET_RETRY_WAIT_MS);
2164 			goto retry;
2165 		}
2166 	}
2167 
2168 	/* disable misc vector before reset done */
2169 	hclgevf_enable_vector(&hdev->misc_vector, false);
2170 
2171 	if (hdev->reset_type == HNAE3_FLR_RESET)
2172 		hdev->rst_stats.flr_rst_cnt++;
2173 }
2174 
2175 static void hclgevf_reset_done(struct hnae3_ae_dev *ae_dev)
2176 {
2177 	struct hclgevf_dev *hdev = ae_dev->priv;
2178 	int ret;
2179 
2180 	hclgevf_enable_vector(&hdev->misc_vector, true);
2181 
2182 	ret = hclgevf_reset_rebuild(hdev);
2183 	if (ret)
2184 		dev_warn(&hdev->pdev->dev, "fail to rebuild, ret=%d\n",
2185 			 ret);
2186 
2187 	hdev->reset_type = HNAE3_NONE_RESET;
2188 	clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state);
2189 	up(&hdev->reset_sem);
2190 }
2191 
2192 static u32 hclgevf_get_fw_version(struct hnae3_handle *handle)
2193 {
2194 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2195 
2196 	return hdev->fw_version;
2197 }
2198 
2199 static void hclgevf_get_misc_vector(struct hclgevf_dev *hdev)
2200 {
2201 	struct hclgevf_misc_vector *vector = &hdev->misc_vector;
2202 
2203 	vector->vector_irq = pci_irq_vector(hdev->pdev,
2204 					    HCLGEVF_MISC_VECTOR_NUM);
2205 	vector->addr = hdev->hw.io_base + HCLGEVF_MISC_VECTOR_REG_BASE;
2206 	/* vector status always valid for Vector 0 */
2207 	hdev->vector_status[HCLGEVF_MISC_VECTOR_NUM] = 0;
2208 	hdev->vector_irq[HCLGEVF_MISC_VECTOR_NUM] = vector->vector_irq;
2209 
2210 	hdev->num_msi_left -= 1;
2211 	hdev->num_msi_used += 1;
2212 }
2213 
2214 void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev)
2215 {
2216 	if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) &&
2217 	    !test_and_set_bit(HCLGEVF_STATE_RST_SERVICE_SCHED,
2218 			      &hdev->state))
2219 		mod_delayed_work(hclgevf_wq, &hdev->service_task, 0);
2220 }
2221 
2222 void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev)
2223 {
2224 	if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) &&
2225 	    !test_and_set_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED,
2226 			      &hdev->state))
2227 		mod_delayed_work(hclgevf_wq, &hdev->service_task, 0);
2228 }
2229 
2230 static void hclgevf_task_schedule(struct hclgevf_dev *hdev,
2231 				  unsigned long delay)
2232 {
2233 	if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) &&
2234 	    !test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state))
2235 		mod_delayed_work(hclgevf_wq, &hdev->service_task, delay);
2236 }
2237 
2238 static void hclgevf_reset_service_task(struct hclgevf_dev *hdev)
2239 {
2240 #define	HCLGEVF_MAX_RESET_ATTEMPTS_CNT	3
2241 
2242 	if (!test_and_clear_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state))
2243 		return;
2244 
2245 	down(&hdev->reset_sem);
2246 	set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state);
2247 
2248 	if (test_and_clear_bit(HCLGEVF_RESET_PENDING,
2249 			       &hdev->reset_state)) {
2250 		/* PF has intimated that it is about to reset the hardware.
2251 		 * We now have to poll & check if hardware has actually
2252 		 * completed the reset sequence. On hardware reset completion,
2253 		 * VF needs to reset the client and ae device.
2254 		 */
2255 		hdev->reset_attempts = 0;
2256 
2257 		hdev->last_reset_time = jiffies;
2258 		while ((hdev->reset_type =
2259 			hclgevf_get_reset_level(hdev, &hdev->reset_pending))
2260 		       != HNAE3_NONE_RESET)
2261 			hclgevf_reset(hdev);
2262 	} else if (test_and_clear_bit(HCLGEVF_RESET_REQUESTED,
2263 				      &hdev->reset_state)) {
2264 		/* we could be here when either of below happens:
2265 		 * 1. reset was initiated due to watchdog timeout caused by
2266 		 *    a. IMP was earlier reset and our TX got choked down and
2267 		 *       which resulted in watchdog reacting and inducing VF
2268 		 *       reset. This also means our cmdq would be unreliable.
2269 		 *    b. problem in TX due to other lower layer(example link
2270 		 *       layer not functioning properly etc.)
2271 		 * 2. VF reset might have been initiated due to some config
2272 		 *    change.
2273 		 *
2274 		 * NOTE: Theres no clear way to detect above cases than to react
2275 		 * to the response of PF for this reset request. PF will ack the
2276 		 * 1b and 2. cases but we will not get any intimation about 1a
2277 		 * from PF as cmdq would be in unreliable state i.e. mailbox
2278 		 * communication between PF and VF would be broken.
2279 		 *
2280 		 * if we are never geting into pending state it means either:
2281 		 * 1. PF is not receiving our request which could be due to IMP
2282 		 *    reset
2283 		 * 2. PF is screwed
2284 		 * We cannot do much for 2. but to check first we can try reset
2285 		 * our PCIe + stack and see if it alleviates the problem.
2286 		 */
2287 		if (hdev->reset_attempts > HCLGEVF_MAX_RESET_ATTEMPTS_CNT) {
2288 			/* prepare for full reset of stack + pcie interface */
2289 			set_bit(HNAE3_VF_FULL_RESET, &hdev->reset_pending);
2290 
2291 			/* "defer" schedule the reset task again */
2292 			set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state);
2293 		} else {
2294 			hdev->reset_attempts++;
2295 
2296 			set_bit(hdev->reset_level, &hdev->reset_pending);
2297 			set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state);
2298 		}
2299 		hclgevf_reset_task_schedule(hdev);
2300 	}
2301 
2302 	hdev->reset_type = HNAE3_NONE_RESET;
2303 	clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state);
2304 	up(&hdev->reset_sem);
2305 }
2306 
2307 static void hclgevf_mailbox_service_task(struct hclgevf_dev *hdev)
2308 {
2309 	if (!test_and_clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state))
2310 		return;
2311 
2312 	if (test_and_set_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state))
2313 		return;
2314 
2315 	hclgevf_mbx_async_handler(hdev);
2316 
2317 	clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state);
2318 }
2319 
2320 static void hclgevf_keep_alive(struct hclgevf_dev *hdev)
2321 {
2322 	struct hclge_vf_to_pf_msg send_msg;
2323 	int ret;
2324 
2325 	if (test_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state))
2326 		return;
2327 
2328 	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_KEEP_ALIVE, 0);
2329 	ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
2330 	if (ret)
2331 		dev_err(&hdev->pdev->dev,
2332 			"VF sends keep alive cmd failed(=%d)\n", ret);
2333 }
2334 
2335 static void hclgevf_periodic_service_task(struct hclgevf_dev *hdev)
2336 {
2337 	unsigned long delta = round_jiffies_relative(HZ);
2338 	struct hnae3_handle *handle = &hdev->nic;
2339 
2340 	if (test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state))
2341 		return;
2342 
2343 	if (time_is_after_jiffies(hdev->last_serv_processed + HZ)) {
2344 		delta = jiffies - hdev->last_serv_processed;
2345 
2346 		if (delta < round_jiffies_relative(HZ)) {
2347 			delta = round_jiffies_relative(HZ) - delta;
2348 			goto out;
2349 		}
2350 	}
2351 
2352 	hdev->serv_processed_cnt++;
2353 	if (!(hdev->serv_processed_cnt % HCLGEVF_KEEP_ALIVE_TASK_INTERVAL))
2354 		hclgevf_keep_alive(hdev);
2355 
2356 	if (test_bit(HCLGEVF_STATE_DOWN, &hdev->state)) {
2357 		hdev->last_serv_processed = jiffies;
2358 		goto out;
2359 	}
2360 
2361 	if (!(hdev->serv_processed_cnt % HCLGEVF_STATS_TIMER_INTERVAL))
2362 		hclgevf_tqps_update_stats(handle);
2363 
2364 	/* VF does not need to request link status when this bit is set, because
2365 	 * PF will push its link status to VFs when link status changed.
2366 	 */
2367 	if (!test_bit(HCLGEVF_STATE_PF_PUSH_LINK_STATUS, &hdev->state))
2368 		hclgevf_request_link_info(hdev);
2369 
2370 	hclgevf_update_link_mode(hdev);
2371 
2372 	hclgevf_sync_vlan_filter(hdev);
2373 
2374 	hclgevf_sync_mac_table(hdev);
2375 
2376 	hclgevf_sync_promisc_mode(hdev);
2377 
2378 	hdev->last_serv_processed = jiffies;
2379 
2380 out:
2381 	hclgevf_task_schedule(hdev, delta);
2382 }
2383 
2384 static void hclgevf_service_task(struct work_struct *work)
2385 {
2386 	struct hclgevf_dev *hdev = container_of(work, struct hclgevf_dev,
2387 						service_task.work);
2388 
2389 	hclgevf_reset_service_task(hdev);
2390 	hclgevf_mailbox_service_task(hdev);
2391 	hclgevf_periodic_service_task(hdev);
2392 
2393 	/* Handle reset and mbx again in case periodical task delays the
2394 	 * handling by calling hclgevf_task_schedule() in
2395 	 * hclgevf_periodic_service_task()
2396 	 */
2397 	hclgevf_reset_service_task(hdev);
2398 	hclgevf_mailbox_service_task(hdev);
2399 }
2400 
2401 static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regclr)
2402 {
2403 	hclgevf_write_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_SRC_REG, regclr);
2404 }
2405 
2406 static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev,
2407 						      u32 *clearval)
2408 {
2409 	u32 val, cmdq_stat_reg, rst_ing_reg;
2410 
2411 	/* fetch the events from their corresponding regs */
2412 	cmdq_stat_reg = hclgevf_read_dev(&hdev->hw,
2413 					 HCLGEVF_VECTOR0_CMDQ_STATE_REG);
2414 	if (BIT(HCLGEVF_VECTOR0_RST_INT_B) & cmdq_stat_reg) {
2415 		rst_ing_reg = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING);
2416 		dev_info(&hdev->pdev->dev,
2417 			 "receive reset interrupt 0x%x!\n", rst_ing_reg);
2418 		set_bit(HNAE3_VF_RESET, &hdev->reset_pending);
2419 		set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state);
2420 		set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state);
2421 		*clearval = ~(1U << HCLGEVF_VECTOR0_RST_INT_B);
2422 		hdev->rst_stats.vf_rst_cnt++;
2423 		/* set up VF hardware reset status, its PF will clear
2424 		 * this status when PF has initialized done.
2425 		 */
2426 		val = hclgevf_read_dev(&hdev->hw, HCLGEVF_VF_RST_ING);
2427 		hclgevf_write_dev(&hdev->hw, HCLGEVF_VF_RST_ING,
2428 				  val | HCLGEVF_VF_RST_ING_BIT);
2429 		return HCLGEVF_VECTOR0_EVENT_RST;
2430 	}
2431 
2432 	/* check for vector0 mailbox(=CMDQ RX) event source */
2433 	if (BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) {
2434 		/* for revision 0x21, clearing interrupt is writing bit 0
2435 		 * to the clear register, writing bit 1 means to keep the
2436 		 * old value.
2437 		 * for revision 0x20, the clear register is a read & write
2438 		 * register, so we should just write 0 to the bit we are
2439 		 * handling, and keep other bits as cmdq_stat_reg.
2440 		 */
2441 		if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2)
2442 			*clearval = ~(1U << HCLGEVF_VECTOR0_RX_CMDQ_INT_B);
2443 		else
2444 			*clearval = cmdq_stat_reg &
2445 				    ~BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B);
2446 
2447 		return HCLGEVF_VECTOR0_EVENT_MBX;
2448 	}
2449 
2450 	/* print other vector0 event source */
2451 	dev_info(&hdev->pdev->dev,
2452 		 "vector 0 interrupt from unknown source, cmdq_src = %#x\n",
2453 		 cmdq_stat_reg);
2454 
2455 	return HCLGEVF_VECTOR0_EVENT_OTHER;
2456 }
2457 
2458 static irqreturn_t hclgevf_misc_irq_handle(int irq, void *data)
2459 {
2460 	enum hclgevf_evt_cause event_cause;
2461 	struct hclgevf_dev *hdev = data;
2462 	u32 clearval;
2463 
2464 	hclgevf_enable_vector(&hdev->misc_vector, false);
2465 	event_cause = hclgevf_check_evt_cause(hdev, &clearval);
2466 
2467 	switch (event_cause) {
2468 	case HCLGEVF_VECTOR0_EVENT_RST:
2469 		hclgevf_reset_task_schedule(hdev);
2470 		break;
2471 	case HCLGEVF_VECTOR0_EVENT_MBX:
2472 		hclgevf_mbx_handler(hdev);
2473 		break;
2474 	default:
2475 		break;
2476 	}
2477 
2478 	if (event_cause != HCLGEVF_VECTOR0_EVENT_OTHER) {
2479 		hclgevf_clear_event_cause(hdev, clearval);
2480 		hclgevf_enable_vector(&hdev->misc_vector, true);
2481 	}
2482 
2483 	return IRQ_HANDLED;
2484 }
2485 
2486 static int hclgevf_configure(struct hclgevf_dev *hdev)
2487 {
2488 	int ret;
2489 
2490 	ret = hclgevf_get_basic_info(hdev);
2491 	if (ret)
2492 		return ret;
2493 
2494 	/* get current port based vlan state from PF */
2495 	ret = hclgevf_get_port_base_vlan_filter_state(hdev);
2496 	if (ret)
2497 		return ret;
2498 
2499 	/* get queue configuration from PF */
2500 	ret = hclgevf_get_queue_info(hdev);
2501 	if (ret)
2502 		return ret;
2503 
2504 	/* get queue depth info from PF */
2505 	ret = hclgevf_get_queue_depth(hdev);
2506 	if (ret)
2507 		return ret;
2508 
2509 	return hclgevf_get_pf_media_type(hdev);
2510 }
2511 
2512 static int hclgevf_alloc_hdev(struct hnae3_ae_dev *ae_dev)
2513 {
2514 	struct pci_dev *pdev = ae_dev->pdev;
2515 	struct hclgevf_dev *hdev;
2516 
2517 	hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL);
2518 	if (!hdev)
2519 		return -ENOMEM;
2520 
2521 	hdev->pdev = pdev;
2522 	hdev->ae_dev = ae_dev;
2523 	ae_dev->priv = hdev;
2524 
2525 	return 0;
2526 }
2527 
2528 static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev)
2529 {
2530 	struct hnae3_handle *roce = &hdev->roce;
2531 	struct hnae3_handle *nic = &hdev->nic;
2532 
2533 	roce->rinfo.num_vectors = hdev->num_roce_msix;
2534 
2535 	if (hdev->num_msi_left < roce->rinfo.num_vectors ||
2536 	    hdev->num_msi_left == 0)
2537 		return -EINVAL;
2538 
2539 	roce->rinfo.base_vector = hdev->roce_base_vector;
2540 
2541 	roce->rinfo.netdev = nic->kinfo.netdev;
2542 	roce->rinfo.roce_io_base = hdev->hw.io_base;
2543 	roce->rinfo.roce_mem_base = hdev->hw.mem_base;
2544 
2545 	roce->pdev = nic->pdev;
2546 	roce->ae_algo = nic->ae_algo;
2547 	roce->numa_node_mask = nic->numa_node_mask;
2548 
2549 	return 0;
2550 }
2551 
2552 static int hclgevf_config_gro(struct hclgevf_dev *hdev, bool en)
2553 {
2554 	struct hclgevf_cfg_gro_status_cmd *req;
2555 	struct hclgevf_desc desc;
2556 	int ret;
2557 
2558 	if (!hnae3_dev_gro_supported(hdev))
2559 		return 0;
2560 
2561 	hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_GRO_GENERIC_CONFIG,
2562 				     false);
2563 	req = (struct hclgevf_cfg_gro_status_cmd *)desc.data;
2564 
2565 	req->gro_en = en ? 1 : 0;
2566 
2567 	ret = hclgevf_cmd_send(&hdev->hw, &desc, 1);
2568 	if (ret)
2569 		dev_err(&hdev->pdev->dev,
2570 			"VF GRO hardware config cmd failed, ret = %d.\n", ret);
2571 
2572 	return ret;
2573 }
2574 
2575 static int hclgevf_rss_init_cfg(struct hclgevf_dev *hdev)
2576 {
2577 	u16 rss_ind_tbl_size = hdev->ae_dev->dev_specs.rss_ind_tbl_size;
2578 	struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
2579 	struct hclgevf_rss_tuple_cfg *tuple_sets;
2580 	u32 i;
2581 
2582 	rss_cfg->hash_algo = HCLGEVF_RSS_HASH_ALGO_TOEPLITZ;
2583 	rss_cfg->rss_size = hdev->nic.kinfo.rss_size;
2584 	tuple_sets = &rss_cfg->rss_tuple_sets;
2585 	if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) {
2586 		u8 *rss_ind_tbl;
2587 
2588 		rss_cfg->hash_algo = HCLGEVF_RSS_HASH_ALGO_SIMPLE;
2589 
2590 		rss_ind_tbl = devm_kcalloc(&hdev->pdev->dev, rss_ind_tbl_size,
2591 					   sizeof(*rss_ind_tbl), GFP_KERNEL);
2592 		if (!rss_ind_tbl)
2593 			return -ENOMEM;
2594 
2595 		rss_cfg->rss_indirection_tbl = rss_ind_tbl;
2596 		memcpy(rss_cfg->rss_hash_key, hclgevf_hash_key,
2597 		       HCLGEVF_RSS_KEY_SIZE);
2598 
2599 		tuple_sets->ipv4_tcp_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER;
2600 		tuple_sets->ipv4_udp_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER;
2601 		tuple_sets->ipv4_sctp_en = HCLGEVF_RSS_INPUT_TUPLE_SCTP;
2602 		tuple_sets->ipv4_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER;
2603 		tuple_sets->ipv6_tcp_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER;
2604 		tuple_sets->ipv6_udp_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER;
2605 		tuple_sets->ipv6_sctp_en =
2606 			hdev->ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2 ?
2607 					HCLGEVF_RSS_INPUT_TUPLE_SCTP_NO_PORT :
2608 					HCLGEVF_RSS_INPUT_TUPLE_SCTP;
2609 		tuple_sets->ipv6_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER;
2610 	}
2611 
2612 	/* Initialize RSS indirect table */
2613 	for (i = 0; i < rss_ind_tbl_size; i++)
2614 		rss_cfg->rss_indirection_tbl[i] = i % rss_cfg->rss_size;
2615 
2616 	return 0;
2617 }
2618 
2619 static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev)
2620 {
2621 	struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
2622 	int ret;
2623 
2624 	if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) {
2625 		ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo,
2626 					       rss_cfg->rss_hash_key);
2627 		if (ret)
2628 			return ret;
2629 
2630 		ret = hclgevf_set_rss_input_tuple(hdev, rss_cfg);
2631 		if (ret)
2632 			return ret;
2633 	}
2634 
2635 	ret = hclgevf_set_rss_indir_table(hdev);
2636 	if (ret)
2637 		return ret;
2638 
2639 	return hclgevf_set_rss_tc_mode(hdev, rss_cfg->rss_size);
2640 }
2641 
2642 static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev)
2643 {
2644 	return hclgevf_set_vlan_filter(&hdev->nic, htons(ETH_P_8021Q), 0,
2645 				       false);
2646 }
2647 
2648 static void hclgevf_flush_link_update(struct hclgevf_dev *hdev)
2649 {
2650 #define HCLGEVF_FLUSH_LINK_TIMEOUT	100000
2651 
2652 	unsigned long last = hdev->serv_processed_cnt;
2653 	int i = 0;
2654 
2655 	while (test_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state) &&
2656 	       i++ < HCLGEVF_FLUSH_LINK_TIMEOUT &&
2657 	       last == hdev->serv_processed_cnt)
2658 		usleep_range(1, 1);
2659 }
2660 
2661 static void hclgevf_set_timer_task(struct hnae3_handle *handle, bool enable)
2662 {
2663 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2664 
2665 	if (enable) {
2666 		hclgevf_task_schedule(hdev, 0);
2667 	} else {
2668 		set_bit(HCLGEVF_STATE_DOWN, &hdev->state);
2669 
2670 		/* flush memory to make sure DOWN is seen by service task */
2671 		smp_mb__before_atomic();
2672 		hclgevf_flush_link_update(hdev);
2673 	}
2674 }
2675 
2676 static int hclgevf_ae_start(struct hnae3_handle *handle)
2677 {
2678 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2679 
2680 	clear_bit(HCLGEVF_STATE_DOWN, &hdev->state);
2681 	clear_bit(HCLGEVF_STATE_PF_PUSH_LINK_STATUS, &hdev->state);
2682 
2683 	hclgevf_reset_tqp_stats(handle);
2684 
2685 	hclgevf_request_link_info(hdev);
2686 
2687 	hclgevf_update_link_mode(hdev);
2688 
2689 	return 0;
2690 }
2691 
2692 static void hclgevf_ae_stop(struct hnae3_handle *handle)
2693 {
2694 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2695 
2696 	set_bit(HCLGEVF_STATE_DOWN, &hdev->state);
2697 
2698 	if (hdev->reset_type != HNAE3_VF_RESET)
2699 		hclgevf_reset_tqp(handle);
2700 
2701 	hclgevf_reset_tqp_stats(handle);
2702 	hclgevf_update_link_status(hdev, 0);
2703 }
2704 
2705 static int hclgevf_set_alive(struct hnae3_handle *handle, bool alive)
2706 {
2707 #define HCLGEVF_STATE_ALIVE	1
2708 #define HCLGEVF_STATE_NOT_ALIVE	0
2709 
2710 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2711 	struct hclge_vf_to_pf_msg send_msg;
2712 
2713 	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_ALIVE, 0);
2714 	send_msg.data[0] = alive ? HCLGEVF_STATE_ALIVE :
2715 				HCLGEVF_STATE_NOT_ALIVE;
2716 	return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
2717 }
2718 
2719 static int hclgevf_client_start(struct hnae3_handle *handle)
2720 {
2721 	return hclgevf_set_alive(handle, true);
2722 }
2723 
2724 static void hclgevf_client_stop(struct hnae3_handle *handle)
2725 {
2726 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2727 	int ret;
2728 
2729 	ret = hclgevf_set_alive(handle, false);
2730 	if (ret)
2731 		dev_warn(&hdev->pdev->dev,
2732 			 "%s failed %d\n", __func__, ret);
2733 }
2734 
2735 static void hclgevf_state_init(struct hclgevf_dev *hdev)
2736 {
2737 	clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state);
2738 	clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state);
2739 	clear_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state);
2740 
2741 	INIT_DELAYED_WORK(&hdev->service_task, hclgevf_service_task);
2742 
2743 	mutex_init(&hdev->mbx_resp.mbx_mutex);
2744 	sema_init(&hdev->reset_sem, 1);
2745 
2746 	spin_lock_init(&hdev->mac_table.mac_list_lock);
2747 	INIT_LIST_HEAD(&hdev->mac_table.uc_mac_list);
2748 	INIT_LIST_HEAD(&hdev->mac_table.mc_mac_list);
2749 
2750 	/* bring the device down */
2751 	set_bit(HCLGEVF_STATE_DOWN, &hdev->state);
2752 }
2753 
2754 static void hclgevf_state_uninit(struct hclgevf_dev *hdev)
2755 {
2756 	set_bit(HCLGEVF_STATE_DOWN, &hdev->state);
2757 	set_bit(HCLGEVF_STATE_REMOVING, &hdev->state);
2758 
2759 	if (hdev->service_task.work.func)
2760 		cancel_delayed_work_sync(&hdev->service_task);
2761 
2762 	mutex_destroy(&hdev->mbx_resp.mbx_mutex);
2763 }
2764 
2765 static int hclgevf_init_msi(struct hclgevf_dev *hdev)
2766 {
2767 	struct pci_dev *pdev = hdev->pdev;
2768 	int vectors;
2769 	int i;
2770 
2771 	if (hnae3_dev_roce_supported(hdev))
2772 		vectors = pci_alloc_irq_vectors(pdev,
2773 						hdev->roce_base_msix_offset + 1,
2774 						hdev->num_msi,
2775 						PCI_IRQ_MSIX);
2776 	else
2777 		vectors = pci_alloc_irq_vectors(pdev, HNAE3_MIN_VECTOR_NUM,
2778 						hdev->num_msi,
2779 						PCI_IRQ_MSI | PCI_IRQ_MSIX);
2780 
2781 	if (vectors < 0) {
2782 		dev_err(&pdev->dev,
2783 			"failed(%d) to allocate MSI/MSI-X vectors\n",
2784 			vectors);
2785 		return vectors;
2786 	}
2787 	if (vectors < hdev->num_msi)
2788 		dev_warn(&hdev->pdev->dev,
2789 			 "requested %u MSI/MSI-X, but allocated %d MSI/MSI-X\n",
2790 			 hdev->num_msi, vectors);
2791 
2792 	hdev->num_msi = vectors;
2793 	hdev->num_msi_left = vectors;
2794 
2795 	hdev->base_msi_vector = pdev->irq;
2796 	hdev->roce_base_vector = pdev->irq + hdev->roce_base_msix_offset;
2797 
2798 	hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
2799 					   sizeof(u16), GFP_KERNEL);
2800 	if (!hdev->vector_status) {
2801 		pci_free_irq_vectors(pdev);
2802 		return -ENOMEM;
2803 	}
2804 
2805 	for (i = 0; i < hdev->num_msi; i++)
2806 		hdev->vector_status[i] = HCLGEVF_INVALID_VPORT;
2807 
2808 	hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi,
2809 					sizeof(int), GFP_KERNEL);
2810 	if (!hdev->vector_irq) {
2811 		devm_kfree(&pdev->dev, hdev->vector_status);
2812 		pci_free_irq_vectors(pdev);
2813 		return -ENOMEM;
2814 	}
2815 
2816 	return 0;
2817 }
2818 
2819 static void hclgevf_uninit_msi(struct hclgevf_dev *hdev)
2820 {
2821 	struct pci_dev *pdev = hdev->pdev;
2822 
2823 	devm_kfree(&pdev->dev, hdev->vector_status);
2824 	devm_kfree(&pdev->dev, hdev->vector_irq);
2825 	pci_free_irq_vectors(pdev);
2826 }
2827 
2828 static int hclgevf_misc_irq_init(struct hclgevf_dev *hdev)
2829 {
2830 	int ret;
2831 
2832 	hclgevf_get_misc_vector(hdev);
2833 
2834 	snprintf(hdev->misc_vector.name, HNAE3_INT_NAME_LEN, "%s-misc-%s",
2835 		 HCLGEVF_NAME, pci_name(hdev->pdev));
2836 	ret = request_irq(hdev->misc_vector.vector_irq, hclgevf_misc_irq_handle,
2837 			  0, hdev->misc_vector.name, hdev);
2838 	if (ret) {
2839 		dev_err(&hdev->pdev->dev, "VF failed to request misc irq(%d)\n",
2840 			hdev->misc_vector.vector_irq);
2841 		return ret;
2842 	}
2843 
2844 	hclgevf_clear_event_cause(hdev, 0);
2845 
2846 	/* enable misc. vector(vector 0) */
2847 	hclgevf_enable_vector(&hdev->misc_vector, true);
2848 
2849 	return ret;
2850 }
2851 
2852 static void hclgevf_misc_irq_uninit(struct hclgevf_dev *hdev)
2853 {
2854 	/* disable misc vector(vector 0) */
2855 	hclgevf_enable_vector(&hdev->misc_vector, false);
2856 	synchronize_irq(hdev->misc_vector.vector_irq);
2857 	free_irq(hdev->misc_vector.vector_irq, hdev);
2858 	hclgevf_free_vector(hdev, 0);
2859 }
2860 
2861 static void hclgevf_info_show(struct hclgevf_dev *hdev)
2862 {
2863 	struct device *dev = &hdev->pdev->dev;
2864 
2865 	dev_info(dev, "VF info begin:\n");
2866 
2867 	dev_info(dev, "Task queue pairs numbers: %u\n", hdev->num_tqps);
2868 	dev_info(dev, "Desc num per TX queue: %u\n", hdev->num_tx_desc);
2869 	dev_info(dev, "Desc num per RX queue: %u\n", hdev->num_rx_desc);
2870 	dev_info(dev, "Numbers of vports: %u\n", hdev->num_alloc_vport);
2871 	dev_info(dev, "HW tc map: 0x%x\n", hdev->hw_tc_map);
2872 	dev_info(dev, "PF media type of this VF: %u\n",
2873 		 hdev->hw.mac.media_type);
2874 
2875 	dev_info(dev, "VF info end.\n");
2876 }
2877 
2878 static int hclgevf_init_nic_client_instance(struct hnae3_ae_dev *ae_dev,
2879 					    struct hnae3_client *client)
2880 {
2881 	struct hclgevf_dev *hdev = ae_dev->priv;
2882 	int rst_cnt = hdev->rst_stats.rst_cnt;
2883 	int ret;
2884 
2885 	ret = client->ops->init_instance(&hdev->nic);
2886 	if (ret)
2887 		return ret;
2888 
2889 	set_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state);
2890 	if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) ||
2891 	    rst_cnt != hdev->rst_stats.rst_cnt) {
2892 		clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state);
2893 
2894 		client->ops->uninit_instance(&hdev->nic, 0);
2895 		return -EBUSY;
2896 	}
2897 
2898 	hnae3_set_client_init_flag(client, ae_dev, 1);
2899 
2900 	if (netif_msg_drv(&hdev->nic))
2901 		hclgevf_info_show(hdev);
2902 
2903 	return 0;
2904 }
2905 
2906 static int hclgevf_init_roce_client_instance(struct hnae3_ae_dev *ae_dev,
2907 					     struct hnae3_client *client)
2908 {
2909 	struct hclgevf_dev *hdev = ae_dev->priv;
2910 	int ret;
2911 
2912 	if (!hnae3_dev_roce_supported(hdev) || !hdev->roce_client ||
2913 	    !hdev->nic_client)
2914 		return 0;
2915 
2916 	ret = hclgevf_init_roce_base_info(hdev);
2917 	if (ret)
2918 		return ret;
2919 
2920 	ret = client->ops->init_instance(&hdev->roce);
2921 	if (ret)
2922 		return ret;
2923 
2924 	set_bit(HCLGEVF_STATE_ROCE_REGISTERED, &hdev->state);
2925 	hnae3_set_client_init_flag(client, ae_dev, 1);
2926 
2927 	return 0;
2928 }
2929 
2930 static int hclgevf_init_client_instance(struct hnae3_client *client,
2931 					struct hnae3_ae_dev *ae_dev)
2932 {
2933 	struct hclgevf_dev *hdev = ae_dev->priv;
2934 	int ret;
2935 
2936 	switch (client->type) {
2937 	case HNAE3_CLIENT_KNIC:
2938 		hdev->nic_client = client;
2939 		hdev->nic.client = client;
2940 
2941 		ret = hclgevf_init_nic_client_instance(ae_dev, client);
2942 		if (ret)
2943 			goto clear_nic;
2944 
2945 		ret = hclgevf_init_roce_client_instance(ae_dev,
2946 							hdev->roce_client);
2947 		if (ret)
2948 			goto clear_roce;
2949 
2950 		break;
2951 	case HNAE3_CLIENT_ROCE:
2952 		if (hnae3_dev_roce_supported(hdev)) {
2953 			hdev->roce_client = client;
2954 			hdev->roce.client = client;
2955 		}
2956 
2957 		ret = hclgevf_init_roce_client_instance(ae_dev, client);
2958 		if (ret)
2959 			goto clear_roce;
2960 
2961 		break;
2962 	default:
2963 		return -EINVAL;
2964 	}
2965 
2966 	return 0;
2967 
2968 clear_nic:
2969 	hdev->nic_client = NULL;
2970 	hdev->nic.client = NULL;
2971 	return ret;
2972 clear_roce:
2973 	hdev->roce_client = NULL;
2974 	hdev->roce.client = NULL;
2975 	return ret;
2976 }
2977 
2978 static void hclgevf_uninit_client_instance(struct hnae3_client *client,
2979 					   struct hnae3_ae_dev *ae_dev)
2980 {
2981 	struct hclgevf_dev *hdev = ae_dev->priv;
2982 
2983 	/* un-init roce, if it exists */
2984 	if (hdev->roce_client) {
2985 		clear_bit(HCLGEVF_STATE_ROCE_REGISTERED, &hdev->state);
2986 		hdev->roce_client->ops->uninit_instance(&hdev->roce, 0);
2987 		hdev->roce_client = NULL;
2988 		hdev->roce.client = NULL;
2989 	}
2990 
2991 	/* un-init nic/unic, if this was not called by roce client */
2992 	if (client->ops->uninit_instance && hdev->nic_client &&
2993 	    client->type != HNAE3_CLIENT_ROCE) {
2994 		clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state);
2995 
2996 		client->ops->uninit_instance(&hdev->nic, 0);
2997 		hdev->nic_client = NULL;
2998 		hdev->nic.client = NULL;
2999 	}
3000 }
3001 
3002 static int hclgevf_dev_mem_map(struct hclgevf_dev *hdev)
3003 {
3004 #define HCLGEVF_MEM_BAR		4
3005 
3006 	struct pci_dev *pdev = hdev->pdev;
3007 	struct hclgevf_hw *hw = &hdev->hw;
3008 
3009 	/* for device does not have device memory, return directly */
3010 	if (!(pci_select_bars(pdev, IORESOURCE_MEM) & BIT(HCLGEVF_MEM_BAR)))
3011 		return 0;
3012 
3013 	hw->mem_base = devm_ioremap_wc(&pdev->dev,
3014 				       pci_resource_start(pdev,
3015 							  HCLGEVF_MEM_BAR),
3016 				       pci_resource_len(pdev, HCLGEVF_MEM_BAR));
3017 	if (!hw->mem_base) {
3018 		dev_err(&pdev->dev, "failed to map device memory\n");
3019 		return -EFAULT;
3020 	}
3021 
3022 	return 0;
3023 }
3024 
3025 static int hclgevf_pci_init(struct hclgevf_dev *hdev)
3026 {
3027 	struct pci_dev *pdev = hdev->pdev;
3028 	struct hclgevf_hw *hw;
3029 	int ret;
3030 
3031 	ret = pci_enable_device(pdev);
3032 	if (ret) {
3033 		dev_err(&pdev->dev, "failed to enable PCI device\n");
3034 		return ret;
3035 	}
3036 
3037 	ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
3038 	if (ret) {
3039 		dev_err(&pdev->dev, "can't set consistent PCI DMA, exiting");
3040 		goto err_disable_device;
3041 	}
3042 
3043 	ret = pci_request_regions(pdev, HCLGEVF_DRIVER_NAME);
3044 	if (ret) {
3045 		dev_err(&pdev->dev, "PCI request regions failed %d\n", ret);
3046 		goto err_disable_device;
3047 	}
3048 
3049 	pci_set_master(pdev);
3050 	hw = &hdev->hw;
3051 	hw->hdev = hdev;
3052 	hw->io_base = pci_iomap(pdev, 2, 0);
3053 	if (!hw->io_base) {
3054 		dev_err(&pdev->dev, "can't map configuration register space\n");
3055 		ret = -ENOMEM;
3056 		goto err_clr_master;
3057 	}
3058 
3059 	ret = hclgevf_dev_mem_map(hdev);
3060 	if (ret)
3061 		goto err_unmap_io_base;
3062 
3063 	return 0;
3064 
3065 err_unmap_io_base:
3066 	pci_iounmap(pdev, hdev->hw.io_base);
3067 err_clr_master:
3068 	pci_clear_master(pdev);
3069 	pci_release_regions(pdev);
3070 err_disable_device:
3071 	pci_disable_device(pdev);
3072 
3073 	return ret;
3074 }
3075 
3076 static void hclgevf_pci_uninit(struct hclgevf_dev *hdev)
3077 {
3078 	struct pci_dev *pdev = hdev->pdev;
3079 
3080 	if (hdev->hw.mem_base)
3081 		devm_iounmap(&pdev->dev, hdev->hw.mem_base);
3082 
3083 	pci_iounmap(pdev, hdev->hw.io_base);
3084 	pci_clear_master(pdev);
3085 	pci_release_regions(pdev);
3086 	pci_disable_device(pdev);
3087 }
3088 
3089 static int hclgevf_query_vf_resource(struct hclgevf_dev *hdev)
3090 {
3091 	struct hclgevf_query_res_cmd *req;
3092 	struct hclgevf_desc desc;
3093 	int ret;
3094 
3095 	hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_VF_RSRC, true);
3096 	ret = hclgevf_cmd_send(&hdev->hw, &desc, 1);
3097 	if (ret) {
3098 		dev_err(&hdev->pdev->dev,
3099 			"query vf resource failed, ret = %d.\n", ret);
3100 		return ret;
3101 	}
3102 
3103 	req = (struct hclgevf_query_res_cmd *)desc.data;
3104 
3105 	if (hnae3_dev_roce_supported(hdev)) {
3106 		hdev->roce_base_msix_offset =
3107 		hnae3_get_field(le16_to_cpu(req->msixcap_localid_ba_rocee),
3108 				HCLGEVF_MSIX_OFT_ROCEE_M,
3109 				HCLGEVF_MSIX_OFT_ROCEE_S);
3110 		hdev->num_roce_msix =
3111 		hnae3_get_field(le16_to_cpu(req->vf_intr_vector_number),
3112 				HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S);
3113 
3114 		/* nic's msix numbers is always equals to the roce's. */
3115 		hdev->num_nic_msix = hdev->num_roce_msix;
3116 
3117 		/* VF should have NIC vectors and Roce vectors, NIC vectors
3118 		 * are queued before Roce vectors. The offset is fixed to 64.
3119 		 */
3120 		hdev->num_msi = hdev->num_roce_msix +
3121 				hdev->roce_base_msix_offset;
3122 	} else {
3123 		hdev->num_msi =
3124 		hnae3_get_field(le16_to_cpu(req->vf_intr_vector_number),
3125 				HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S);
3126 
3127 		hdev->num_nic_msix = hdev->num_msi;
3128 	}
3129 
3130 	if (hdev->num_nic_msix < HNAE3_MIN_VECTOR_NUM) {
3131 		dev_err(&hdev->pdev->dev,
3132 			"Just %u msi resources, not enough for vf(min:2).\n",
3133 			hdev->num_nic_msix);
3134 		return -EINVAL;
3135 	}
3136 
3137 	return 0;
3138 }
3139 
3140 static void hclgevf_set_default_dev_specs(struct hclgevf_dev *hdev)
3141 {
3142 #define HCLGEVF_MAX_NON_TSO_BD_NUM			8U
3143 
3144 	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
3145 
3146 	ae_dev->dev_specs.max_non_tso_bd_num =
3147 					HCLGEVF_MAX_NON_TSO_BD_NUM;
3148 	ae_dev->dev_specs.rss_ind_tbl_size = HCLGEVF_RSS_IND_TBL_SIZE;
3149 	ae_dev->dev_specs.rss_key_size = HCLGEVF_RSS_KEY_SIZE;
3150 	ae_dev->dev_specs.max_int_gl = HCLGEVF_DEF_MAX_INT_GL;
3151 	ae_dev->dev_specs.max_frm_size = HCLGEVF_MAC_MAX_FRAME;
3152 }
3153 
3154 static void hclgevf_parse_dev_specs(struct hclgevf_dev *hdev,
3155 				    struct hclgevf_desc *desc)
3156 {
3157 	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
3158 	struct hclgevf_dev_specs_0_cmd *req0;
3159 	struct hclgevf_dev_specs_1_cmd *req1;
3160 
3161 	req0 = (struct hclgevf_dev_specs_0_cmd *)desc[0].data;
3162 	req1 = (struct hclgevf_dev_specs_1_cmd *)desc[1].data;
3163 
3164 	ae_dev->dev_specs.max_non_tso_bd_num = req0->max_non_tso_bd_num;
3165 	ae_dev->dev_specs.rss_ind_tbl_size =
3166 					le16_to_cpu(req0->rss_ind_tbl_size);
3167 	ae_dev->dev_specs.int_ql_max = le16_to_cpu(req0->int_ql_max);
3168 	ae_dev->dev_specs.rss_key_size = le16_to_cpu(req0->rss_key_size);
3169 	ae_dev->dev_specs.max_int_gl = le16_to_cpu(req1->max_int_gl);
3170 	ae_dev->dev_specs.max_frm_size = le16_to_cpu(req1->max_frm_size);
3171 }
3172 
3173 static void hclgevf_check_dev_specs(struct hclgevf_dev *hdev)
3174 {
3175 	struct hnae3_dev_specs *dev_specs = &hdev->ae_dev->dev_specs;
3176 
3177 	if (!dev_specs->max_non_tso_bd_num)
3178 		dev_specs->max_non_tso_bd_num = HCLGEVF_MAX_NON_TSO_BD_NUM;
3179 	if (!dev_specs->rss_ind_tbl_size)
3180 		dev_specs->rss_ind_tbl_size = HCLGEVF_RSS_IND_TBL_SIZE;
3181 	if (!dev_specs->rss_key_size)
3182 		dev_specs->rss_key_size = HCLGEVF_RSS_KEY_SIZE;
3183 	if (!dev_specs->max_int_gl)
3184 		dev_specs->max_int_gl = HCLGEVF_DEF_MAX_INT_GL;
3185 	if (!dev_specs->max_frm_size)
3186 		dev_specs->max_frm_size = HCLGEVF_MAC_MAX_FRAME;
3187 }
3188 
3189 static int hclgevf_query_dev_specs(struct hclgevf_dev *hdev)
3190 {
3191 	struct hclgevf_desc desc[HCLGEVF_QUERY_DEV_SPECS_BD_NUM];
3192 	int ret;
3193 	int i;
3194 
3195 	/* set default specifications as devices lower than version V3 do not
3196 	 * support querying specifications from firmware.
3197 	 */
3198 	if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3) {
3199 		hclgevf_set_default_dev_specs(hdev);
3200 		return 0;
3201 	}
3202 
3203 	for (i = 0; i < HCLGEVF_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
3204 		hclgevf_cmd_setup_basic_desc(&desc[i],
3205 					     HCLGEVF_OPC_QUERY_DEV_SPECS, true);
3206 		desc[i].flag |= cpu_to_le16(HCLGEVF_CMD_FLAG_NEXT);
3207 	}
3208 	hclgevf_cmd_setup_basic_desc(&desc[i], HCLGEVF_OPC_QUERY_DEV_SPECS,
3209 				     true);
3210 
3211 	ret = hclgevf_cmd_send(&hdev->hw, desc, HCLGEVF_QUERY_DEV_SPECS_BD_NUM);
3212 	if (ret)
3213 		return ret;
3214 
3215 	hclgevf_parse_dev_specs(hdev, desc);
3216 	hclgevf_check_dev_specs(hdev);
3217 
3218 	return 0;
3219 }
3220 
3221 static int hclgevf_pci_reset(struct hclgevf_dev *hdev)
3222 {
3223 	struct pci_dev *pdev = hdev->pdev;
3224 	int ret = 0;
3225 
3226 	if (hdev->reset_type == HNAE3_VF_FULL_RESET &&
3227 	    test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) {
3228 		hclgevf_misc_irq_uninit(hdev);
3229 		hclgevf_uninit_msi(hdev);
3230 		clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state);
3231 	}
3232 
3233 	if (!test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) {
3234 		pci_set_master(pdev);
3235 		ret = hclgevf_init_msi(hdev);
3236 		if (ret) {
3237 			dev_err(&pdev->dev,
3238 				"failed(%d) to init MSI/MSI-X\n", ret);
3239 			return ret;
3240 		}
3241 
3242 		ret = hclgevf_misc_irq_init(hdev);
3243 		if (ret) {
3244 			hclgevf_uninit_msi(hdev);
3245 			dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n",
3246 				ret);
3247 			return ret;
3248 		}
3249 
3250 		set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state);
3251 	}
3252 
3253 	return ret;
3254 }
3255 
3256 static int hclgevf_clear_vport_list(struct hclgevf_dev *hdev)
3257 {
3258 	struct hclge_vf_to_pf_msg send_msg;
3259 
3260 	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_HANDLE_VF_TBL,
3261 			       HCLGE_MBX_VPORT_LIST_CLEAR);
3262 	return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
3263 }
3264 
3265 static void hclgevf_init_rxd_adv_layout(struct hclgevf_dev *hdev)
3266 {
3267 	if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev))
3268 		hclgevf_write_dev(&hdev->hw, HCLGEVF_RXD_ADV_LAYOUT_EN_REG, 1);
3269 }
3270 
3271 static void hclgevf_uninit_rxd_adv_layout(struct hclgevf_dev *hdev)
3272 {
3273 	if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev))
3274 		hclgevf_write_dev(&hdev->hw, HCLGEVF_RXD_ADV_LAYOUT_EN_REG, 0);
3275 }
3276 
3277 static int hclgevf_reset_hdev(struct hclgevf_dev *hdev)
3278 {
3279 	struct pci_dev *pdev = hdev->pdev;
3280 	int ret;
3281 
3282 	ret = hclgevf_pci_reset(hdev);
3283 	if (ret) {
3284 		dev_err(&pdev->dev, "pci reset failed %d\n", ret);
3285 		return ret;
3286 	}
3287 
3288 	ret = hclgevf_cmd_init(hdev);
3289 	if (ret) {
3290 		dev_err(&pdev->dev, "cmd failed %d\n", ret);
3291 		return ret;
3292 	}
3293 
3294 	ret = hclgevf_rss_init_hw(hdev);
3295 	if (ret) {
3296 		dev_err(&hdev->pdev->dev,
3297 			"failed(%d) to initialize RSS\n", ret);
3298 		return ret;
3299 	}
3300 
3301 	ret = hclgevf_config_gro(hdev, true);
3302 	if (ret)
3303 		return ret;
3304 
3305 	ret = hclgevf_init_vlan_config(hdev);
3306 	if (ret) {
3307 		dev_err(&hdev->pdev->dev,
3308 			"failed(%d) to initialize VLAN config\n", ret);
3309 		return ret;
3310 	}
3311 
3312 	set_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state);
3313 
3314 	hclgevf_init_rxd_adv_layout(hdev);
3315 
3316 	dev_info(&hdev->pdev->dev, "Reset done\n");
3317 
3318 	return 0;
3319 }
3320 
3321 static int hclgevf_init_hdev(struct hclgevf_dev *hdev)
3322 {
3323 	struct pci_dev *pdev = hdev->pdev;
3324 	int ret;
3325 
3326 	ret = hclgevf_pci_init(hdev);
3327 	if (ret)
3328 		return ret;
3329 
3330 	ret = hclgevf_cmd_queue_init(hdev);
3331 	if (ret)
3332 		goto err_cmd_queue_init;
3333 
3334 	ret = hclgevf_cmd_init(hdev);
3335 	if (ret)
3336 		goto err_cmd_init;
3337 
3338 	/* Get vf resource */
3339 	ret = hclgevf_query_vf_resource(hdev);
3340 	if (ret)
3341 		goto err_cmd_init;
3342 
3343 	ret = hclgevf_query_dev_specs(hdev);
3344 	if (ret) {
3345 		dev_err(&pdev->dev,
3346 			"failed to query dev specifications, ret = %d\n", ret);
3347 		goto err_cmd_init;
3348 	}
3349 
3350 	ret = hclgevf_init_msi(hdev);
3351 	if (ret) {
3352 		dev_err(&pdev->dev, "failed(%d) to init MSI/MSI-X\n", ret);
3353 		goto err_cmd_init;
3354 	}
3355 
3356 	hclgevf_state_init(hdev);
3357 	hdev->reset_level = HNAE3_VF_FUNC_RESET;
3358 	hdev->reset_type = HNAE3_NONE_RESET;
3359 
3360 	ret = hclgevf_misc_irq_init(hdev);
3361 	if (ret)
3362 		goto err_misc_irq_init;
3363 
3364 	set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state);
3365 
3366 	ret = hclgevf_configure(hdev);
3367 	if (ret) {
3368 		dev_err(&pdev->dev, "failed(%d) to fetch configuration\n", ret);
3369 		goto err_config;
3370 	}
3371 
3372 	ret = hclgevf_alloc_tqps(hdev);
3373 	if (ret) {
3374 		dev_err(&pdev->dev, "failed(%d) to allocate TQPs\n", ret);
3375 		goto err_config;
3376 	}
3377 
3378 	ret = hclgevf_set_handle_info(hdev);
3379 	if (ret)
3380 		goto err_config;
3381 
3382 	ret = hclgevf_config_gro(hdev, true);
3383 	if (ret)
3384 		goto err_config;
3385 
3386 	/* Initialize RSS for this VF */
3387 	ret = hclgevf_rss_init_cfg(hdev);
3388 	if (ret) {
3389 		dev_err(&pdev->dev, "failed to init rss cfg, ret = %d\n", ret);
3390 		goto err_config;
3391 	}
3392 
3393 	ret = hclgevf_rss_init_hw(hdev);
3394 	if (ret) {
3395 		dev_err(&hdev->pdev->dev,
3396 			"failed(%d) to initialize RSS\n", ret);
3397 		goto err_config;
3398 	}
3399 
3400 	/* ensure vf tbl list as empty before init*/
3401 	ret = hclgevf_clear_vport_list(hdev);
3402 	if (ret) {
3403 		dev_err(&pdev->dev,
3404 			"failed to clear tbl list configuration, ret = %d.\n",
3405 			ret);
3406 		goto err_config;
3407 	}
3408 
3409 	ret = hclgevf_init_vlan_config(hdev);
3410 	if (ret) {
3411 		dev_err(&hdev->pdev->dev,
3412 			"failed(%d) to initialize VLAN config\n", ret);
3413 		goto err_config;
3414 	}
3415 
3416 	hclgevf_init_rxd_adv_layout(hdev);
3417 
3418 	hdev->last_reset_time = jiffies;
3419 	dev_info(&hdev->pdev->dev, "finished initializing %s driver\n",
3420 		 HCLGEVF_DRIVER_NAME);
3421 
3422 	hclgevf_task_schedule(hdev, round_jiffies_relative(HZ));
3423 
3424 	return 0;
3425 
3426 err_config:
3427 	hclgevf_misc_irq_uninit(hdev);
3428 err_misc_irq_init:
3429 	hclgevf_state_uninit(hdev);
3430 	hclgevf_uninit_msi(hdev);
3431 err_cmd_init:
3432 	hclgevf_cmd_uninit(hdev);
3433 err_cmd_queue_init:
3434 	hclgevf_pci_uninit(hdev);
3435 	clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state);
3436 	return ret;
3437 }
3438 
3439 static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev)
3440 {
3441 	struct hclge_vf_to_pf_msg send_msg;
3442 
3443 	hclgevf_state_uninit(hdev);
3444 	hclgevf_uninit_rxd_adv_layout(hdev);
3445 
3446 	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_VF_UNINIT, 0);
3447 	hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
3448 
3449 	if (test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) {
3450 		hclgevf_misc_irq_uninit(hdev);
3451 		hclgevf_uninit_msi(hdev);
3452 	}
3453 
3454 	hclgevf_cmd_uninit(hdev);
3455 	hclgevf_pci_uninit(hdev);
3456 	hclgevf_uninit_mac_list(hdev);
3457 }
3458 
3459 static int hclgevf_init_ae_dev(struct hnae3_ae_dev *ae_dev)
3460 {
3461 	struct pci_dev *pdev = ae_dev->pdev;
3462 	int ret;
3463 
3464 	ret = hclgevf_alloc_hdev(ae_dev);
3465 	if (ret) {
3466 		dev_err(&pdev->dev, "hclge device allocation failed\n");
3467 		return ret;
3468 	}
3469 
3470 	ret = hclgevf_init_hdev(ae_dev->priv);
3471 	if (ret) {
3472 		dev_err(&pdev->dev, "hclge device initialization failed\n");
3473 		return ret;
3474 	}
3475 
3476 	return 0;
3477 }
3478 
3479 static void hclgevf_uninit_ae_dev(struct hnae3_ae_dev *ae_dev)
3480 {
3481 	struct hclgevf_dev *hdev = ae_dev->priv;
3482 
3483 	hclgevf_uninit_hdev(hdev);
3484 	ae_dev->priv = NULL;
3485 }
3486 
3487 static u32 hclgevf_get_max_channels(struct hclgevf_dev *hdev)
3488 {
3489 	struct hnae3_handle *nic = &hdev->nic;
3490 	struct hnae3_knic_private_info *kinfo = &nic->kinfo;
3491 
3492 	return min_t(u32, hdev->rss_size_max,
3493 		     hdev->num_tqps / kinfo->tc_info.num_tc);
3494 }
3495 
3496 /**
3497  * hclgevf_get_channels - Get the current channels enabled and max supported.
3498  * @handle: hardware information for network interface
3499  * @ch: ethtool channels structure
3500  *
3501  * We don't support separate tx and rx queues as channels. The other count
3502  * represents how many queues are being used for control. max_combined counts
3503  * how many queue pairs we can support. They may not be mapped 1 to 1 with
3504  * q_vectors since we support a lot more queue pairs than q_vectors.
3505  **/
3506 static void hclgevf_get_channels(struct hnae3_handle *handle,
3507 				 struct ethtool_channels *ch)
3508 {
3509 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3510 
3511 	ch->max_combined = hclgevf_get_max_channels(hdev);
3512 	ch->other_count = 0;
3513 	ch->max_other = 0;
3514 	ch->combined_count = handle->kinfo.rss_size;
3515 }
3516 
3517 static void hclgevf_get_tqps_and_rss_info(struct hnae3_handle *handle,
3518 					  u16 *alloc_tqps, u16 *max_rss_size)
3519 {
3520 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3521 
3522 	*alloc_tqps = hdev->num_tqps;
3523 	*max_rss_size = hdev->rss_size_max;
3524 }
3525 
3526 static void hclgevf_update_rss_size(struct hnae3_handle *handle,
3527 				    u32 new_tqps_num)
3528 {
3529 	struct hnae3_knic_private_info *kinfo = &handle->kinfo;
3530 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3531 	u16 max_rss_size;
3532 
3533 	kinfo->req_rss_size = new_tqps_num;
3534 
3535 	max_rss_size = min_t(u16, hdev->rss_size_max,
3536 			     hdev->num_tqps / kinfo->tc_info.num_tc);
3537 
3538 	/* Use the user's configuration when it is not larger than
3539 	 * max_rss_size, otherwise, use the maximum specification value.
3540 	 */
3541 	if (kinfo->req_rss_size != kinfo->rss_size && kinfo->req_rss_size &&
3542 	    kinfo->req_rss_size <= max_rss_size)
3543 		kinfo->rss_size = kinfo->req_rss_size;
3544 	else if (kinfo->rss_size > max_rss_size ||
3545 		 (!kinfo->req_rss_size && kinfo->rss_size < max_rss_size))
3546 		kinfo->rss_size = max_rss_size;
3547 
3548 	kinfo->num_tqps = kinfo->tc_info.num_tc * kinfo->rss_size;
3549 }
3550 
3551 static int hclgevf_set_channels(struct hnae3_handle *handle, u32 new_tqps_num,
3552 				bool rxfh_configured)
3553 {
3554 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3555 	struct hnae3_knic_private_info *kinfo = &handle->kinfo;
3556 	u16 cur_rss_size = kinfo->rss_size;
3557 	u16 cur_tqps = kinfo->num_tqps;
3558 	u32 *rss_indir;
3559 	unsigned int i;
3560 	int ret;
3561 
3562 	hclgevf_update_rss_size(handle, new_tqps_num);
3563 
3564 	ret = hclgevf_set_rss_tc_mode(hdev, kinfo->rss_size);
3565 	if (ret)
3566 		return ret;
3567 
3568 	/* RSS indirection table has been configured by user */
3569 	if (rxfh_configured)
3570 		goto out;
3571 
3572 	/* Reinitializes the rss indirect table according to the new RSS size */
3573 	rss_indir = kcalloc(hdev->ae_dev->dev_specs.rss_ind_tbl_size,
3574 			    sizeof(u32), GFP_KERNEL);
3575 	if (!rss_indir)
3576 		return -ENOMEM;
3577 
3578 	for (i = 0; i < hdev->ae_dev->dev_specs.rss_ind_tbl_size; i++)
3579 		rss_indir[i] = i % kinfo->rss_size;
3580 
3581 	hdev->rss_cfg.rss_size = kinfo->rss_size;
3582 
3583 	ret = hclgevf_set_rss(handle, rss_indir, NULL, 0);
3584 	if (ret)
3585 		dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n",
3586 			ret);
3587 
3588 	kfree(rss_indir);
3589 
3590 out:
3591 	if (!ret)
3592 		dev_info(&hdev->pdev->dev,
3593 			 "Channels changed, rss_size from %u to %u, tqps from %u to %u",
3594 			 cur_rss_size, kinfo->rss_size,
3595 			 cur_tqps, kinfo->rss_size * kinfo->tc_info.num_tc);
3596 
3597 	return ret;
3598 }
3599 
3600 static int hclgevf_get_status(struct hnae3_handle *handle)
3601 {
3602 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3603 
3604 	return hdev->hw.mac.link;
3605 }
3606 
3607 static void hclgevf_get_ksettings_an_result(struct hnae3_handle *handle,
3608 					    u8 *auto_neg, u32 *speed,
3609 					    u8 *duplex)
3610 {
3611 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3612 
3613 	if (speed)
3614 		*speed = hdev->hw.mac.speed;
3615 	if (duplex)
3616 		*duplex = hdev->hw.mac.duplex;
3617 	if (auto_neg)
3618 		*auto_neg = AUTONEG_DISABLE;
3619 }
3620 
3621 void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed,
3622 				 u8 duplex)
3623 {
3624 	hdev->hw.mac.speed = speed;
3625 	hdev->hw.mac.duplex = duplex;
3626 }
3627 
3628 static int hclgevf_gro_en(struct hnae3_handle *handle, bool enable)
3629 {
3630 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3631 
3632 	return hclgevf_config_gro(hdev, enable);
3633 }
3634 
3635 static void hclgevf_get_media_type(struct hnae3_handle *handle, u8 *media_type,
3636 				   u8 *module_type)
3637 {
3638 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3639 
3640 	if (media_type)
3641 		*media_type = hdev->hw.mac.media_type;
3642 
3643 	if (module_type)
3644 		*module_type = hdev->hw.mac.module_type;
3645 }
3646 
3647 static bool hclgevf_get_hw_reset_stat(struct hnae3_handle *handle)
3648 {
3649 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3650 
3651 	return !!hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING);
3652 }
3653 
3654 static bool hclgevf_get_cmdq_stat(struct hnae3_handle *handle)
3655 {
3656 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3657 
3658 	return test_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state);
3659 }
3660 
3661 static bool hclgevf_ae_dev_resetting(struct hnae3_handle *handle)
3662 {
3663 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3664 
3665 	return test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state);
3666 }
3667 
3668 static unsigned long hclgevf_ae_dev_reset_cnt(struct hnae3_handle *handle)
3669 {
3670 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3671 
3672 	return hdev->rst_stats.hw_rst_done_cnt;
3673 }
3674 
3675 static void hclgevf_get_link_mode(struct hnae3_handle *handle,
3676 				  unsigned long *supported,
3677 				  unsigned long *advertising)
3678 {
3679 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3680 
3681 	*supported = hdev->hw.mac.supported;
3682 	*advertising = hdev->hw.mac.advertising;
3683 }
3684 
3685 #define MAX_SEPARATE_NUM	4
3686 #define SEPARATOR_VALUE		0xFDFCFBFA
3687 #define REG_NUM_PER_LINE	4
3688 #define REG_LEN_PER_LINE	(REG_NUM_PER_LINE * sizeof(u32))
3689 
3690 static int hclgevf_get_regs_len(struct hnae3_handle *handle)
3691 {
3692 	int cmdq_lines, common_lines, ring_lines, tqp_intr_lines;
3693 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3694 
3695 	cmdq_lines = sizeof(cmdq_reg_addr_list) / REG_LEN_PER_LINE + 1;
3696 	common_lines = sizeof(common_reg_addr_list) / REG_LEN_PER_LINE + 1;
3697 	ring_lines = sizeof(ring_reg_addr_list) / REG_LEN_PER_LINE + 1;
3698 	tqp_intr_lines = sizeof(tqp_intr_reg_addr_list) / REG_LEN_PER_LINE + 1;
3699 
3700 	return (cmdq_lines + common_lines + ring_lines * hdev->num_tqps +
3701 		tqp_intr_lines * (hdev->num_msi_used - 1)) * REG_LEN_PER_LINE;
3702 }
3703 
3704 static void hclgevf_get_regs(struct hnae3_handle *handle, u32 *version,
3705 			     void *data)
3706 {
3707 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3708 	int i, j, reg_um, separator_num;
3709 	u32 *reg = data;
3710 
3711 	*version = hdev->fw_version;
3712 
3713 	/* fetching per-VF registers values from VF PCIe register space */
3714 	reg_um = sizeof(cmdq_reg_addr_list) / sizeof(u32);
3715 	separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
3716 	for (i = 0; i < reg_um; i++)
3717 		*reg++ = hclgevf_read_dev(&hdev->hw, cmdq_reg_addr_list[i]);
3718 	for (i = 0; i < separator_num; i++)
3719 		*reg++ = SEPARATOR_VALUE;
3720 
3721 	reg_um = sizeof(common_reg_addr_list) / sizeof(u32);
3722 	separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
3723 	for (i = 0; i < reg_um; i++)
3724 		*reg++ = hclgevf_read_dev(&hdev->hw, common_reg_addr_list[i]);
3725 	for (i = 0; i < separator_num; i++)
3726 		*reg++ = SEPARATOR_VALUE;
3727 
3728 	reg_um = sizeof(ring_reg_addr_list) / sizeof(u32);
3729 	separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
3730 	for (j = 0; j < hdev->num_tqps; j++) {
3731 		for (i = 0; i < reg_um; i++)
3732 			*reg++ = hclgevf_read_dev(&hdev->hw,
3733 						  ring_reg_addr_list[i] +
3734 						  0x200 * j);
3735 		for (i = 0; i < separator_num; i++)
3736 			*reg++ = SEPARATOR_VALUE;
3737 	}
3738 
3739 	reg_um = sizeof(tqp_intr_reg_addr_list) / sizeof(u32);
3740 	separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
3741 	for (j = 0; j < hdev->num_msi_used - 1; j++) {
3742 		for (i = 0; i < reg_um; i++)
3743 			*reg++ = hclgevf_read_dev(&hdev->hw,
3744 						  tqp_intr_reg_addr_list[i] +
3745 						  4 * j);
3746 		for (i = 0; i < separator_num; i++)
3747 			*reg++ = SEPARATOR_VALUE;
3748 	}
3749 }
3750 
3751 void hclgevf_update_port_base_vlan_info(struct hclgevf_dev *hdev, u16 state,
3752 					u8 *port_base_vlan_info, u8 data_size)
3753 {
3754 	struct hnae3_handle *nic = &hdev->nic;
3755 	struct hclge_vf_to_pf_msg send_msg;
3756 	int ret;
3757 
3758 	rtnl_lock();
3759 
3760 	if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) ||
3761 	    test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) {
3762 		dev_warn(&hdev->pdev->dev,
3763 			 "is resetting when updating port based vlan info\n");
3764 		rtnl_unlock();
3765 		return;
3766 	}
3767 
3768 	ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT);
3769 	if (ret) {
3770 		rtnl_unlock();
3771 		return;
3772 	}
3773 
3774 	/* send msg to PF and wait update port based vlan info */
3775 	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN,
3776 			       HCLGE_MBX_PORT_BASE_VLAN_CFG);
3777 	memcpy(send_msg.data, port_base_vlan_info, data_size);
3778 	ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
3779 	if (!ret) {
3780 		if (state == HNAE3_PORT_BASE_VLAN_DISABLE)
3781 			nic->port_base_vlan_state = state;
3782 		else
3783 			nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_ENABLE;
3784 	}
3785 
3786 	hclgevf_notify_client(hdev, HNAE3_UP_CLIENT);
3787 	rtnl_unlock();
3788 }
3789 
3790 static const struct hnae3_ae_ops hclgevf_ops = {
3791 	.init_ae_dev = hclgevf_init_ae_dev,
3792 	.uninit_ae_dev = hclgevf_uninit_ae_dev,
3793 	.reset_prepare = hclgevf_reset_prepare_general,
3794 	.reset_done = hclgevf_reset_done,
3795 	.init_client_instance = hclgevf_init_client_instance,
3796 	.uninit_client_instance = hclgevf_uninit_client_instance,
3797 	.start = hclgevf_ae_start,
3798 	.stop = hclgevf_ae_stop,
3799 	.client_start = hclgevf_client_start,
3800 	.client_stop = hclgevf_client_stop,
3801 	.map_ring_to_vector = hclgevf_map_ring_to_vector,
3802 	.unmap_ring_from_vector = hclgevf_unmap_ring_from_vector,
3803 	.get_vector = hclgevf_get_vector,
3804 	.put_vector = hclgevf_put_vector,
3805 	.reset_queue = hclgevf_reset_tqp,
3806 	.get_mac_addr = hclgevf_get_mac_addr,
3807 	.set_mac_addr = hclgevf_set_mac_addr,
3808 	.add_uc_addr = hclgevf_add_uc_addr,
3809 	.rm_uc_addr = hclgevf_rm_uc_addr,
3810 	.add_mc_addr = hclgevf_add_mc_addr,
3811 	.rm_mc_addr = hclgevf_rm_mc_addr,
3812 	.get_stats = hclgevf_get_stats,
3813 	.update_stats = hclgevf_update_stats,
3814 	.get_strings = hclgevf_get_strings,
3815 	.get_sset_count = hclgevf_get_sset_count,
3816 	.get_rss_key_size = hclgevf_get_rss_key_size,
3817 	.get_rss = hclgevf_get_rss,
3818 	.set_rss = hclgevf_set_rss,
3819 	.get_rss_tuple = hclgevf_get_rss_tuple,
3820 	.set_rss_tuple = hclgevf_set_rss_tuple,
3821 	.get_tc_size = hclgevf_get_tc_size,
3822 	.get_fw_version = hclgevf_get_fw_version,
3823 	.set_vlan_filter = hclgevf_set_vlan_filter,
3824 	.enable_vlan_filter = hclgevf_enable_vlan_filter,
3825 	.enable_hw_strip_rxvtag = hclgevf_en_hw_strip_rxvtag,
3826 	.reset_event = hclgevf_reset_event,
3827 	.set_default_reset_request = hclgevf_set_def_reset_request,
3828 	.set_channels = hclgevf_set_channels,
3829 	.get_channels = hclgevf_get_channels,
3830 	.get_tqps_and_rss_info = hclgevf_get_tqps_and_rss_info,
3831 	.get_regs_len = hclgevf_get_regs_len,
3832 	.get_regs = hclgevf_get_regs,
3833 	.get_status = hclgevf_get_status,
3834 	.get_ksettings_an_result = hclgevf_get_ksettings_an_result,
3835 	.get_media_type = hclgevf_get_media_type,
3836 	.get_hw_reset_stat = hclgevf_get_hw_reset_stat,
3837 	.ae_dev_resetting = hclgevf_ae_dev_resetting,
3838 	.ae_dev_reset_cnt = hclgevf_ae_dev_reset_cnt,
3839 	.set_gro_en = hclgevf_gro_en,
3840 	.set_mtu = hclgevf_set_mtu,
3841 	.get_global_queue_id = hclgevf_get_qid_global,
3842 	.set_timer_task = hclgevf_set_timer_task,
3843 	.get_link_mode = hclgevf_get_link_mode,
3844 	.set_promisc_mode = hclgevf_set_promisc_mode,
3845 	.request_update_promisc_mode = hclgevf_request_update_promisc_mode,
3846 	.get_cmdq_stat = hclgevf_get_cmdq_stat,
3847 };
3848 
3849 static struct hnae3_ae_algo ae_algovf = {
3850 	.ops = &hclgevf_ops,
3851 	.pdev_id_table = ae_algovf_pci_tbl,
3852 };
3853 
3854 static int hclgevf_init(void)
3855 {
3856 	pr_info("%s is initializing\n", HCLGEVF_NAME);
3857 
3858 	hclgevf_wq = alloc_workqueue("%s", 0, 0, HCLGEVF_NAME);
3859 	if (!hclgevf_wq) {
3860 		pr_err("%s: failed to create workqueue\n", HCLGEVF_NAME);
3861 		return -ENOMEM;
3862 	}
3863 
3864 	hnae3_register_ae_algo(&ae_algovf);
3865 
3866 	return 0;
3867 }
3868 
3869 static void hclgevf_exit(void)
3870 {
3871 	hnae3_unregister_ae_algo(&ae_algovf);
3872 	destroy_workqueue(hclgevf_wq);
3873 }
3874 module_init(hclgevf_init);
3875 module_exit(hclgevf_exit);
3876 
3877 MODULE_LICENSE("GPL");
3878 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
3879 MODULE_DESCRIPTION("HCLGEVF Driver");
3880 MODULE_VERSION(HCLGEVF_MOD_VERSION);
3881